1 /* 2 * Copyright (c) 2016-2018 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 #include "hal_hw_headers.h" 19 #include "hal_internal.h" 20 #include "hal_api.h" 21 #include "target_type.h" 22 #include "wcss_version.h" 23 #include "qdf_module.h" 24 25 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_OFFSET \ 26 RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_OFFSET 27 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_MASK \ 28 RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_MASK 29 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_LSB \ 30 RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_LSB 31 #define UNIFIED_PHYRX_HT_SIG_0_HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS_OFFSET \ 32 PHYRX_HT_SIG_0_PHYRX_HT_SIG_INFO_DETAILS_MCS_OFFSET 33 #define UNIFIED_PHYRX_L_SIG_B_0_L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS_OFFSET \ 34 PHYRX_L_SIG_B_0_PHYRX_L_SIG_B_INFO_DETAILS_RATE_OFFSET 35 #define UNIFIED_PHYRX_L_SIG_A_0_L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS_OFFSET \ 36 PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_RATE_OFFSET 37 #define UNIFIED_PHYRX_VHT_SIG_A_0_VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS_OFFSET \ 38 PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_OFFSET 39 #define UNIFIED_PHYRX_HE_SIG_A_SU_0_HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS_OFFSET \ 40 PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_OFFSET 41 #define UNIFIED_PHYRX_HE_SIG_A_MU_DL_0_HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_OFFSET \ 42 PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_OFFSET 43 #define UNIFIED_PHYRX_HE_SIG_B1_MU_0_HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_OFFSET \ 44 PHYRX_HE_SIG_B1_MU_0_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_OFFSET 45 #define UNIFIED_PHYRX_HE_SIG_B2_MU_0_HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_OFFSET \ 46 PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_OFFSET 47 #define UNIFIED_PHYRX_HE_SIG_B2_OFDMA_0_HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_OFFSET \ 48 PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_OFFSET 49 #define UNIFIED_PHYRX_RSSI_LEGACY_3_RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS_OFFSET \ 50 PHYRX_RSSI_LEGACY_3_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 51 #define UNIFIED_RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET \ 52 RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 53 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 54 RX_MSDU_LINK_8_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 55 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ 56 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 57 #define UNIFIED_RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 58 RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 59 #define UNIFIED_REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 60 REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 61 #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER \ 62 STATUS_HEADER_REO_STATUS_NUMBER 63 #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC \ 64 STATUS_HEADER_TIMESTAMP 65 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ 66 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 67 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 68 RX_MSDU_LINK_8_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 69 #define UNIFIED_TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 70 TCL_DATA_CMD_0_BUF_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 71 #define UNIFIED_TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 72 TCL_DATA_CMD_1_BUF_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 73 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET \ 74 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET 75 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB \ 76 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB 77 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK \ 78 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK 79 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB \ 80 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB 81 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK \ 82 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK 83 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB \ 84 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB 85 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK \ 86 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK 87 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB \ 88 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB 89 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK \ 90 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK 91 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB \ 92 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB 93 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK \ 94 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK 95 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_MASK \ 96 WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MASK 97 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_OFFSET \ 98 WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_OFFSET 99 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_LSB \ 100 WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_LSB 101 #include "hal_8074v2_tx.h" 102 #include "hal_8074v2_rx.h" 103 #include <hal_generic_api.h> 104 #include <hal_wbm.h> 105 106 struct hal_hw_txrx_ops qca8074v2_hal_hw_txrx_ops = { 107 108 /* init and setup */ 109 hal_srng_dst_hw_init_generic, 110 hal_srng_src_hw_init_generic, 111 hal_reo_setup_generic, 112 hal_setup_link_idle_list_generic, 113 114 /* tx */ 115 hal_tx_desc_set_dscp_tid_table_id_8074v2, 116 hal_tx_set_dscp_tid_map_8074v2, 117 hal_tx_update_dscp_tid_8074v2, 118 hal_tx_desc_set_lmac_id_8074v2, 119 hal_tx_desc_set_buf_addr_generic, 120 hal_tx_comp_get_status_generic, 121 122 /* rx */ 123 hal_rx_msdu_start_nss_get_8074v2, 124 hal_rx_mon_hw_desc_get_mpdu_status_8074v2, 125 hal_rx_get_tlv_8074v2, 126 hal_rx_proc_phyrx_other_receive_info_tlv_8074v2, 127 hal_rx_dump_msdu_start_tlv_8074v2, 128 hal_rx_dump_msdu_end_tlv_8074v2, 129 hal_get_link_desc_size_8074v2, 130 hal_rx_mpdu_start_tid_get_8074v2, 131 hal_rx_msdu_start_reception_type_get_8074v2, 132 hal_rx_msdu_end_da_idx_get_8074v2, 133 hal_rx_msdu_desc_info_get_ptr_generic, 134 hal_rx_link_desc_msdu0_ptr_generic, 135 hal_reo_status_get_header_generic, 136 hal_rx_status_get_tlv_info_generic, 137 }; 138 139 struct hal_hw_srng_config hw_srng_table_8074v2[] = { 140 /* TODO: max_rings can populated by querying HW capabilities */ 141 { /* REO_DST */ 142 .start_ring_id = HAL_SRNG_REO2SW1, 143 .max_rings = 4, 144 .entry_size = sizeof(struct reo_destination_ring) >> 2, 145 .lmac_ring = FALSE, 146 .ring_dir = HAL_SRNG_DST_RING, 147 .reg_start = { 148 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR( 149 SEQ_WCSS_UMAC_REO_REG_OFFSET), 150 HWIO_REO_R2_REO2SW1_RING_HP_ADDR( 151 SEQ_WCSS_UMAC_REO_REG_OFFSET) 152 }, 153 .reg_size = { 154 HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(0) - 155 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(0), 156 HWIO_REO_R2_REO2SW2_RING_HP_ADDR(0) - 157 HWIO_REO_R2_REO2SW1_RING_HP_ADDR(0), 158 }, 159 .max_size = 160 HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_BMSK >> 161 HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_SHFT, 162 }, 163 { /* REO_EXCEPTION */ 164 /* Designating REO2TCL ring as exception ring. This ring is 165 * similar to other REO2SW rings though it is named as REO2TCL. 166 * Any of theREO2SW rings can be used as exception ring. 167 */ 168 .start_ring_id = HAL_SRNG_REO2TCL, 169 .max_rings = 1, 170 .entry_size = sizeof(struct reo_destination_ring) >> 2, 171 .lmac_ring = FALSE, 172 .ring_dir = HAL_SRNG_DST_RING, 173 .reg_start = { 174 HWIO_REO_R0_REO2TCL_RING_BASE_LSB_ADDR( 175 SEQ_WCSS_UMAC_REO_REG_OFFSET), 176 HWIO_REO_R2_REO2TCL_RING_HP_ADDR( 177 SEQ_WCSS_UMAC_REO_REG_OFFSET) 178 }, 179 /* Single ring - provide ring size if multiple rings of this 180 * type are supported 181 */ 182 .reg_size = {}, 183 .max_size = 184 HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_BMSK >> 185 HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_SHFT, 186 }, 187 { /* REO_REINJECT */ 188 .start_ring_id = HAL_SRNG_SW2REO, 189 .max_rings = 1, 190 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 191 .lmac_ring = FALSE, 192 .ring_dir = HAL_SRNG_SRC_RING, 193 .reg_start = { 194 HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR( 195 SEQ_WCSS_UMAC_REO_REG_OFFSET), 196 HWIO_REO_R2_SW2REO_RING_HP_ADDR( 197 SEQ_WCSS_UMAC_REO_REG_OFFSET) 198 }, 199 /* Single ring - provide ring size if multiple rings of this 200 * type are supported 201 */ 202 .reg_size = {}, 203 .max_size = HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_BMSK >> 204 HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_SHFT, 205 }, 206 { /* REO_CMD */ 207 .start_ring_id = HAL_SRNG_REO_CMD, 208 .max_rings = 1, 209 .entry_size = (sizeof(struct tlv_32_hdr) + 210 sizeof(struct reo_get_queue_stats)) >> 2, 211 .lmac_ring = FALSE, 212 .ring_dir = HAL_SRNG_SRC_RING, 213 .reg_start = { 214 HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR( 215 SEQ_WCSS_UMAC_REO_REG_OFFSET), 216 HWIO_REO_R2_REO_CMD_RING_HP_ADDR( 217 SEQ_WCSS_UMAC_REO_REG_OFFSET), 218 }, 219 /* Single ring - provide ring size if multiple rings of this 220 * type are supported 221 */ 222 .reg_size = {}, 223 .max_size = HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_BMSK >> 224 HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_SHFT, 225 }, 226 { /* REO_STATUS */ 227 .start_ring_id = HAL_SRNG_REO_STATUS, 228 .max_rings = 1, 229 .entry_size = (sizeof(struct tlv_32_hdr) + 230 sizeof(struct reo_get_queue_stats_status)) >> 2, 231 .lmac_ring = FALSE, 232 .ring_dir = HAL_SRNG_DST_RING, 233 .reg_start = { 234 HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR( 235 SEQ_WCSS_UMAC_REO_REG_OFFSET), 236 HWIO_REO_R2_REO_STATUS_RING_HP_ADDR( 237 SEQ_WCSS_UMAC_REO_REG_OFFSET), 238 }, 239 /* Single ring - provide ring size if multiple rings of this 240 * type are supported 241 */ 242 .reg_size = {}, 243 .max_size = 244 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> 245 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, 246 }, 247 { /* TCL_DATA */ 248 .start_ring_id = HAL_SRNG_SW2TCL1, 249 .max_rings = 3, 250 .entry_size = (sizeof(struct tlv_32_hdr) + 251 sizeof(struct tcl_data_cmd)) >> 2, 252 .lmac_ring = FALSE, 253 .ring_dir = HAL_SRNG_SRC_RING, 254 .reg_start = { 255 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR( 256 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 257 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR( 258 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 259 }, 260 .reg_size = { 261 HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(0) - 262 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(0), 263 HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(0) - 264 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(0), 265 }, 266 .max_size = 267 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK >> 268 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT, 269 }, 270 { /* TCL_CMD */ 271 .start_ring_id = HAL_SRNG_SW2TCL_CMD, 272 .max_rings = 1, 273 .entry_size = (sizeof(struct tlv_32_hdr) + 274 sizeof(struct tcl_gse_cmd)) >> 2, 275 .lmac_ring = FALSE, 276 .ring_dir = HAL_SRNG_SRC_RING, 277 .reg_start = { 278 HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_ADDR( 279 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 280 HWIO_TCL_R2_SW2TCL_CMD_RING_HP_ADDR( 281 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 282 }, 283 /* Single ring - provide ring size if multiple rings of this 284 * type are supported 285 */ 286 .reg_size = {}, 287 .max_size = 288 HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RING_SIZE_BMSK >> 289 HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RING_SIZE_SHFT, 290 }, 291 { /* TCL_STATUS */ 292 .start_ring_id = HAL_SRNG_TCL_STATUS, 293 .max_rings = 1, 294 .entry_size = (sizeof(struct tlv_32_hdr) + 295 sizeof(struct tcl_status_ring)) >> 2, 296 .lmac_ring = FALSE, 297 .ring_dir = HAL_SRNG_DST_RING, 298 .reg_start = { 299 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR( 300 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 301 HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR( 302 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 303 }, 304 /* Single ring - provide ring size if multiple rings of this 305 * type are supported 306 */ 307 .reg_size = {}, 308 .max_size = 309 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_BMSK >> 310 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_SHFT, 311 }, 312 { /* CE_SRC */ 313 .start_ring_id = HAL_SRNG_CE_0_SRC, 314 .max_rings = 12, 315 .entry_size = sizeof(struct ce_src_desc) >> 2, 316 .lmac_ring = FALSE, 317 .ring_dir = HAL_SRNG_SRC_RING, 318 .reg_start = { 319 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR( 320 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET), 321 HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR( 322 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET), 323 }, 324 .reg_size = { 325 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET - 326 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET, 327 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET - 328 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET, 329 }, 330 .max_size = 331 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >> 332 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT, 333 }, 334 { /* CE_DST */ 335 .start_ring_id = HAL_SRNG_CE_0_DST, 336 .max_rings = 12, 337 .entry_size = 8 >> 2, 338 /*TODO: entry_size above should actually be 339 * sizeof(struct ce_dst_desc) >> 2, but couldn't find definition 340 * of struct ce_dst_desc in HW header files 341 */ 342 .lmac_ring = FALSE, 343 .ring_dir = HAL_SRNG_SRC_RING, 344 .reg_start = { 345 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR( 346 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 347 HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR( 348 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 349 }, 350 .reg_size = { 351 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 352 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 353 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 354 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 355 }, 356 .max_size = 357 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >> 358 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT, 359 }, 360 { /* CE_DST_STATUS */ 361 .start_ring_id = HAL_SRNG_CE_0_DST_STATUS, 362 .max_rings = 12, 363 .entry_size = sizeof(struct ce_stat_desc) >> 2, 364 .lmac_ring = FALSE, 365 .ring_dir = HAL_SRNG_DST_RING, 366 .reg_start = { 367 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR( 368 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 369 HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR( 370 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 371 }, 372 /* TODO: check destination status ring registers */ 373 .reg_size = { 374 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 375 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 376 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 377 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 378 }, 379 .max_size = 380 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> 381 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, 382 }, 383 { /* WBM_IDLE_LINK */ 384 .start_ring_id = HAL_SRNG_WBM_IDLE_LINK, 385 .max_rings = 1, 386 .entry_size = sizeof(struct wbm_link_descriptor_ring) >> 2, 387 .lmac_ring = FALSE, 388 .ring_dir = HAL_SRNG_SRC_RING, 389 .reg_start = { 390 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 391 HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 392 }, 393 /* Single ring - provide ring size if multiple rings of this 394 * type are supported 395 */ 396 .reg_size = {}, 397 .max_size = 398 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_BMSK >> 399 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_SHFT, 400 }, 401 { /* SW2WBM_RELEASE */ 402 .start_ring_id = HAL_SRNG_WBM_SW_RELEASE, 403 .max_rings = 1, 404 .entry_size = sizeof(struct wbm_release_ring) >> 2, 405 .lmac_ring = FALSE, 406 .ring_dir = HAL_SRNG_SRC_RING, 407 .reg_start = { 408 HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 409 HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 410 }, 411 /* Single ring - provide ring size if multiple rings of this 412 * type are supported 413 */ 414 .reg_size = {}, 415 .max_size = 416 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> 417 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, 418 }, 419 { /* WBM2SW_RELEASE */ 420 .start_ring_id = HAL_SRNG_WBM2SW0_RELEASE, 421 .max_rings = 4, 422 .entry_size = sizeof(struct wbm_release_ring) >> 2, 423 .lmac_ring = FALSE, 424 .ring_dir = HAL_SRNG_DST_RING, 425 .reg_start = { 426 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 427 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 428 }, 429 .reg_size = { 430 HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) - 431 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 432 HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) - 433 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 434 }, 435 .max_size = 436 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> 437 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, 438 }, 439 { /* RXDMA_BUF */ 440 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA0_BUF0, 441 #ifdef IPA_OFFLOAD 442 .max_rings = 3, 443 #else 444 .max_rings = 2, 445 #endif 446 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 447 .lmac_ring = TRUE, 448 .ring_dir = HAL_SRNG_SRC_RING, 449 /* reg_start is not set because LMAC rings are not accessed 450 * from host 451 */ 452 .reg_start = {}, 453 .reg_size = {}, 454 .max_size = HAL_RXDMA_MAX_RING_SIZE, 455 }, 456 { /* RXDMA_DST */ 457 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW0, 458 .max_rings = 1, 459 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 460 .lmac_ring = TRUE, 461 .ring_dir = HAL_SRNG_DST_RING, 462 /* reg_start is not set because LMAC rings are not accessed 463 * from host 464 */ 465 .reg_start = {}, 466 .reg_size = {}, 467 .max_size = HAL_RXDMA_MAX_RING_SIZE, 468 }, 469 { /* RXDMA_MONITOR_BUF */ 470 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA2_BUF, 471 .max_rings = 1, 472 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 473 .lmac_ring = TRUE, 474 .ring_dir = HAL_SRNG_SRC_RING, 475 /* reg_start is not set because LMAC rings are not accessed 476 * from host 477 */ 478 .reg_start = {}, 479 .reg_size = {}, 480 .max_size = HAL_RXDMA_MAX_RING_SIZE, 481 }, 482 { /* RXDMA_MONITOR_STATUS */ 483 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_STATBUF, 484 .max_rings = 1, 485 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 486 .lmac_ring = TRUE, 487 .ring_dir = HAL_SRNG_SRC_RING, 488 /* reg_start is not set because LMAC rings are not accessed 489 * from host 490 */ 491 .reg_start = {}, 492 .reg_size = {}, 493 .max_size = HAL_RXDMA_MAX_RING_SIZE, 494 }, 495 { /* RXDMA_MONITOR_DST */ 496 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW1, 497 .max_rings = 1, 498 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 499 .lmac_ring = TRUE, 500 .ring_dir = HAL_SRNG_DST_RING, 501 /* reg_start is not set because LMAC rings are not accessed 502 * from host 503 */ 504 .reg_start = {}, 505 .reg_size = {}, 506 .max_size = HAL_RXDMA_MAX_RING_SIZE, 507 }, 508 { /* RXDMA_MONITOR_DESC */ 509 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_DESC, 510 .max_rings = 1, 511 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 512 .lmac_ring = TRUE, 513 .ring_dir = HAL_SRNG_SRC_RING, 514 /* reg_start is not set because LMAC rings are not accessed 515 * from host 516 */ 517 .reg_start = {}, 518 .reg_size = {}, 519 .max_size = HAL_RXDMA_MAX_RING_SIZE, 520 }, 521 { /* DIR_BUF_RX_DMA_SRC */ 522 .start_ring_id = HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING, 523 .max_rings = 1, 524 .entry_size = 2, 525 .lmac_ring = TRUE, 526 .ring_dir = HAL_SRNG_SRC_RING, 527 /* reg_start is not set because LMAC rings are not accessed 528 * from host 529 */ 530 .reg_start = {}, 531 .reg_size = {}, 532 .max_size = HAL_RXDMA_MAX_RING_SIZE, 533 }, 534 #ifdef WLAN_FEATURE_CIF_CFR 535 { /* WIFI_POS_SRC */ 536 .start_ring_id = HAL_SRNG_WIFI_POS_SRC_DMA_RING, 537 .max_rings = 1, 538 .entry_size = sizeof(wmi_oem_dma_buf_release_entry) >> 2, 539 .lmac_ring = TRUE, 540 .ring_dir = HAL_SRNG_SRC_RING, 541 /* reg_start is not set because LMAC rings are not accessed 542 * from host 543 */ 544 .reg_start = {}, 545 .reg_size = {}, 546 .max_size = HAL_RXDMA_MAX_RING_SIZE, 547 }, 548 #endif 549 }; 550 551 int32_t hal_hw_reg_offset_qca8074v2[] = { 552 /* dst */ 553 REG_OFFSET(DST, HP), 554 REG_OFFSET(DST, TP), 555 REG_OFFSET(DST, ID), 556 REG_OFFSET(DST, MISC), 557 REG_OFFSET(DST, HP_ADDR_LSB), 558 REG_OFFSET(DST, HP_ADDR_MSB), 559 REG_OFFSET(DST, MSI1_BASE_LSB), 560 REG_OFFSET(DST, MSI1_BASE_MSB), 561 REG_OFFSET(DST, MSI1_DATA), 562 REG_OFFSET(DST, BASE_LSB), 563 REG_OFFSET(DST, BASE_MSB), 564 REG_OFFSET(DST, PRODUCER_INT_SETUP), 565 /* src */ 566 REG_OFFSET(SRC, HP), 567 REG_OFFSET(SRC, TP), 568 REG_OFFSET(SRC, ID), 569 REG_OFFSET(SRC, MISC), 570 REG_OFFSET(SRC, TP_ADDR_LSB), 571 REG_OFFSET(SRC, TP_ADDR_MSB), 572 REG_OFFSET(SRC, MSI1_BASE_LSB), 573 REG_OFFSET(SRC, MSI1_BASE_MSB), 574 REG_OFFSET(SRC, MSI1_DATA), 575 REG_OFFSET(SRC, BASE_LSB), 576 REG_OFFSET(SRC, BASE_MSB), 577 REG_OFFSET(SRC, CONSUMER_INT_SETUP_IX0), 578 REG_OFFSET(SRC, CONSUMER_INT_SETUP_IX1), 579 }; 580 581 582 /** 583 * hal_qca8074v2_attach() - Attach 8074v2 target specific hal_soc ops, 584 * offset and srng table 585 */ 586 void hal_qca8074v2_attach(struct hal_soc *hal_soc) 587 { 588 hal_soc->hw_srng_table = hw_srng_table_8074v2; 589 hal_soc->hal_hw_reg_offset = hal_hw_reg_offset_qca8074v2; 590 hal_soc->ops = &qca8074v2_hal_hw_txrx_ops; 591 } 592 593 594 595