1 /* 2 * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 #include "hal_li_hw_headers.h" 19 #include "hal_internal.h" 20 #include "hal_api.h" 21 #include "target_type.h" 22 #include "wcss_version.h" 23 #include "qdf_module.h" 24 #include "hal_flow.h" 25 #include "rx_flow_search_entry.h" 26 #include "hal_rx_flow_info.h" 27 28 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_OFFSET \ 29 RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_OFFSET 30 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_MASK \ 31 RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_MASK 32 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_LSB \ 33 RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_LSB 34 #define UNIFIED_PHYRX_HT_SIG_0_HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS_OFFSET \ 35 PHYRX_HT_SIG_0_PHYRX_HT_SIG_INFO_DETAILS_MCS_OFFSET 36 #define UNIFIED_PHYRX_L_SIG_B_0_L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS_OFFSET \ 37 PHYRX_L_SIG_B_0_PHYRX_L_SIG_B_INFO_DETAILS_RATE_OFFSET 38 #define UNIFIED_PHYRX_L_SIG_A_0_L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS_OFFSET \ 39 PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_RATE_OFFSET 40 #define UNIFIED_PHYRX_VHT_SIG_A_0_VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS_OFFSET \ 41 PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_OFFSET 42 #define UNIFIED_PHYRX_HE_SIG_A_SU_0_HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS_OFFSET \ 43 PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_OFFSET 44 #define UNIFIED_PHYRX_HE_SIG_A_MU_DL_0_HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_OFFSET \ 45 PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_OFFSET 46 #define UNIFIED_PHYRX_HE_SIG_B1_MU_0_HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_OFFSET \ 47 PHYRX_HE_SIG_B1_MU_0_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_OFFSET 48 #define UNIFIED_PHYRX_HE_SIG_B2_MU_0_HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_OFFSET \ 49 PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_OFFSET 50 #define UNIFIED_PHYRX_HE_SIG_B2_OFDMA_0_HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_OFFSET \ 51 PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_OFFSET 52 #define UNIFIED_PHYRX_RSSI_LEGACY_3_RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS_OFFSET \ 53 PHYRX_RSSI_LEGACY_3_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 54 #define UNIFIED_PHYRX_RSSI_LEGACY_19_RECEIVE_RSSI_INFO_PREAMBLE_RSSI_INFO_DETAILS_OFFSET \ 55 PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 56 #define UNIFIED_RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET \ 57 RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 58 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 59 RX_MSDU_LINK_8_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 60 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ 61 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 62 #define UNIFIED_RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 63 RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 64 #define UNIFIED_REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 65 REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 66 #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER \ 67 STATUS_HEADER_REO_STATUS_NUMBER 68 #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC \ 69 STATUS_HEADER_TIMESTAMP 70 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ 71 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 72 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 73 RX_MSDU_LINK_8_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 74 #define UNIFIED_TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 75 TCL_DATA_CMD_0_BUF_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 76 #define UNIFIED_TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 77 TCL_DATA_CMD_1_BUF_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 78 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET \ 79 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET 80 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB \ 81 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB 82 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK \ 83 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK 84 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB \ 85 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB 86 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK \ 87 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK 88 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB \ 89 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB 90 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK \ 91 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK 92 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB \ 93 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB 94 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK \ 95 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK 96 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB \ 97 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB 98 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK \ 99 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK 100 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_MASK \ 101 WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MASK 102 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_OFFSET \ 103 WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_OFFSET 104 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_LSB \ 105 WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_LSB 106 107 #include "hal_8074v2_tx.h" 108 #include "hal_8074v2_rx.h" 109 #include <hal_generic_api.h> 110 #include "hal_li_rx.h" 111 #include "hal_li_api.h" 112 #include "hal_li_generic_api.h" 113 114 /** 115 * hal_rx_get_rx_fragment_number_8074v2(): Function to retrieve 116 * rx fragment number 117 * 118 * @nbuf: Network buffer 119 * Returns: rx fragment number 120 */ 121 static 122 uint8_t hal_rx_get_rx_fragment_number_8074v2(uint8_t *buf) 123 { 124 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 125 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 126 127 /* Return first 4 bits as fragment number */ 128 return HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info) & 129 DOT11_SEQ_FRAG_MASK; 130 } 131 132 /** 133 * hal_rx_msdu_end_da_is_mcbc_get_8074v2: API to check if pkt is MCBC 134 * from rx_msdu_end TLV 135 * 136 * @ buf: pointer to the start of RX PKT TLV headers 137 * Return: da_is_mcbc 138 */ 139 static uint8_t 140 hal_rx_msdu_end_da_is_mcbc_get_8074v2(uint8_t *buf) 141 { 142 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 143 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 144 145 return HAL_RX_MSDU_END_DA_IS_MCBC_GET(msdu_end); 146 } 147 148 /** 149 * hal_rx_msdu_end_sa_is_valid_get_8074v2(): API to get_8074v2 the 150 * sa_is_valid bit from rx_msdu_end TLV 151 * 152 * @ buf: pointer to the start of RX PKT TLV headers 153 * Return: sa_is_valid bit 154 */ 155 static uint8_t 156 hal_rx_msdu_end_sa_is_valid_get_8074v2(uint8_t *buf) 157 { 158 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 159 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 160 uint8_t sa_is_valid; 161 162 sa_is_valid = HAL_RX_MSDU_END_SA_IS_VALID_GET(msdu_end); 163 164 return sa_is_valid; 165 } 166 167 /** 168 * hal_rx_msdu_end_sa_idx_get_8074v2(): API to get_8074v2 the 169 * sa_idx from rx_msdu_end TLV 170 * 171 * @ buf: pointer to the start of RX PKT TLV headers 172 * Return: sa_idx (SA AST index) 173 */ 174 static uint16_t hal_rx_msdu_end_sa_idx_get_8074v2(uint8_t *buf) 175 { 176 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 177 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 178 uint16_t sa_idx; 179 180 sa_idx = HAL_RX_MSDU_END_SA_IDX_GET(msdu_end); 181 182 return sa_idx; 183 } 184 185 /** 186 * hal_rx_desc_is_first_msdu_8074v2() - Check if first msdu 187 * 188 * @hal_soc_hdl: hal_soc handle 189 * @hw_desc_addr: hardware descriptor address 190 * 191 * Return: 0 - success/ non-zero failure 192 */ 193 static uint32_t hal_rx_desc_is_first_msdu_8074v2(void *hw_desc_addr) 194 { 195 struct rx_pkt_tlvs *rx_tlvs = (struct rx_pkt_tlvs *)hw_desc_addr; 196 struct rx_msdu_end *msdu_end = &rx_tlvs->msdu_end_tlv.rx_msdu_end; 197 198 return HAL_RX_GET(msdu_end, RX_MSDU_END_5, FIRST_MSDU); 199 } 200 201 /** 202 * hal_rx_msdu_end_l3_hdr_padding_get_8074v2(): API to get_8074v2 the 203 * l3_header padding from rx_msdu_end TLV 204 * 205 * @ buf: pointer to the start of RX PKT TLV headers 206 * Return: number of l3 header padding bytes 207 */ 208 static uint32_t hal_rx_msdu_end_l3_hdr_padding_get_8074v2(uint8_t *buf) 209 { 210 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 211 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 212 uint32_t l3_header_padding; 213 214 l3_header_padding = HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(msdu_end); 215 216 return l3_header_padding; 217 } 218 219 /* 220 * @ hal_rx_encryption_info_valid_8074v2: Returns encryption type. 221 * 222 * @ buf: rx_tlv_hdr of the received packet 223 * @ Return: encryption type 224 */ 225 static uint32_t hal_rx_encryption_info_valid_8074v2(uint8_t *buf) 226 { 227 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 228 struct rx_mpdu_start *mpdu_start = 229 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 230 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 231 uint32_t encryption_info = HAL_RX_MPDU_ENCRYPTION_INFO_VALID(mpdu_info); 232 233 return encryption_info; 234 } 235 236 /* 237 * @ hal_rx_print_pn_8074v2: Prints the PN of rx packet. 238 * 239 * @ buf: rx_tlv_hdr of the received packet 240 * @ Return: void 241 */ 242 static void hal_rx_print_pn_8074v2(uint8_t *buf) 243 { 244 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 245 struct rx_mpdu_start *mpdu_start = 246 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 247 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 248 249 uint32_t pn_31_0 = HAL_RX_MPDU_PN_31_0_GET(mpdu_info); 250 uint32_t pn_63_32 = HAL_RX_MPDU_PN_63_32_GET(mpdu_info); 251 uint32_t pn_95_64 = HAL_RX_MPDU_PN_95_64_GET(mpdu_info); 252 uint32_t pn_127_96 = HAL_RX_MPDU_PN_127_96_GET(mpdu_info); 253 254 hal_debug("PN number pn_127_96 0x%x pn_95_64 0x%x pn_63_32 0x%x pn_31_0 0x%x ", 255 pn_127_96, pn_95_64, pn_63_32, pn_31_0); 256 } 257 258 /** 259 * hal_rx_msdu_end_first_msdu_get_8074v2: API to get first msdu status 260 * from rx_msdu_end TLV 261 * 262 * @ buf: pointer to the start of RX PKT TLV headers 263 * Return: first_msdu 264 */ 265 static uint8_t hal_rx_msdu_end_first_msdu_get_8074v2(uint8_t *buf) 266 { 267 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 268 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 269 uint8_t first_msdu; 270 271 first_msdu = HAL_RX_MSDU_END_FIRST_MSDU_GET(msdu_end); 272 273 return first_msdu; 274 } 275 276 /** 277 * hal_rx_msdu_end_da_is_valid_get_8074v2: API to check if da is valid 278 * from rx_msdu_end TLV 279 * 280 * @ buf: pointer to the start of RX PKT TLV headers 281 * Return: da_is_valid 282 */ 283 static uint8_t hal_rx_msdu_end_da_is_valid_get_8074v2(uint8_t *buf) 284 { 285 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 286 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 287 uint8_t da_is_valid; 288 289 da_is_valid = HAL_RX_MSDU_END_DA_IS_VALID_GET(msdu_end); 290 291 return da_is_valid; 292 } 293 294 /** 295 * hal_rx_msdu_end_last_msdu_get_8074v2: API to get last msdu status 296 * from rx_msdu_end TLV 297 * 298 * @ buf: pointer to the start of RX PKT TLV headers 299 * Return: last_msdu 300 */ 301 static uint8_t hal_rx_msdu_end_last_msdu_get_8074v2(uint8_t *buf) 302 { 303 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 304 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 305 uint8_t last_msdu; 306 307 last_msdu = HAL_RX_MSDU_END_LAST_MSDU_GET(msdu_end); 308 309 return last_msdu; 310 } 311 312 /* 313 * hal_rx_get_mpdu_mac_ad4_valid_8074v2(): Retrieves if mpdu 4th addr is valid 314 * 315 * @nbuf: Network buffer 316 * Returns: value of mpdu 4th address valid field 317 */ 318 static bool hal_rx_get_mpdu_mac_ad4_valid_8074v2(uint8_t *buf) 319 { 320 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 321 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 322 bool ad4_valid = 0; 323 324 ad4_valid = HAL_RX_MPDU_GET_MAC_AD4_VALID(rx_mpdu_info); 325 326 return ad4_valid; 327 } 328 329 /** 330 * hal_rx_mpdu_start_sw_peer_id_get_8074v2: Retrieve sw peer_id 331 * @buf: network buffer 332 * 333 * Return: sw peer_id 334 */ 335 static uint32_t hal_rx_mpdu_start_sw_peer_id_get_8074v2(uint8_t *buf) 336 { 337 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 338 struct rx_mpdu_start *mpdu_start = 339 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 340 341 return HAL_RX_MPDU_INFO_SW_PEER_ID_GET( 342 &mpdu_start->rx_mpdu_info_details); 343 } 344 345 /* 346 * hal_rx_mpdu_get_to_ds_8074v2(): API to get the tods info 347 * from rx_mpdu_start 348 * 349 * @buf: pointer to the start of RX PKT TLV header 350 * Return: uint32_t(to_ds) 351 */ 352 static uint32_t hal_rx_mpdu_get_to_ds_8074v2(uint8_t *buf) 353 { 354 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 355 struct rx_mpdu_start *mpdu_start = 356 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 357 358 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 359 360 return HAL_RX_MPDU_GET_TODS(mpdu_info); 361 } 362 363 /* 364 * hal_rx_mpdu_get_fr_ds_8074v2(): API to get the from ds info 365 * from rx_mpdu_start 366 * 367 * @buf: pointer to the start of RX PKT TLV header 368 * Return: uint32_t(fr_ds) 369 */ 370 static uint32_t hal_rx_mpdu_get_fr_ds_8074v2(uint8_t *buf) 371 { 372 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 373 struct rx_mpdu_start *mpdu_start = 374 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 375 376 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 377 378 return HAL_RX_MPDU_GET_FROMDS(mpdu_info); 379 } 380 381 /* 382 * hal_rx_get_mpdu_frame_control_valid_8074v2(): Retrieves mpdu 383 * frame control valid 384 * 385 * @nbuf: Network buffer 386 * Returns: value of frame control valid field 387 */ 388 static uint8_t hal_rx_get_mpdu_frame_control_valid_8074v2(uint8_t *buf) 389 { 390 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 391 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 392 393 return HAL_RX_MPDU_GET_FRAME_CONTROL_VALID(rx_mpdu_info); 394 } 395 396 /* 397 * hal_rx_mpdu_get_addr1_8074v2(): API to check get address1 of the mpdu 398 * 399 * @buf: pointer to the start of RX PKT TLV headera 400 * @mac_addr: pointer to mac address 401 * Return: success/failure 402 */ 403 static QDF_STATUS hal_rx_mpdu_get_addr1_8074v2(uint8_t *buf, uint8_t *mac_addr) 404 { 405 struct __attribute__((__packed__)) hal_addr1 { 406 uint32_t ad1_31_0; 407 uint16_t ad1_47_32; 408 }; 409 410 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 411 struct rx_mpdu_start *mpdu_start = 412 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 413 414 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 415 struct hal_addr1 *addr = (struct hal_addr1 *)mac_addr; 416 uint32_t mac_addr_ad1_valid; 417 418 mac_addr_ad1_valid = HAL_RX_MPDU_MAC_ADDR_AD1_VALID_GET(mpdu_info); 419 420 if (mac_addr_ad1_valid) { 421 addr->ad1_31_0 = HAL_RX_MPDU_AD1_31_0_GET(mpdu_info); 422 addr->ad1_47_32 = HAL_RX_MPDU_AD1_47_32_GET(mpdu_info); 423 return QDF_STATUS_SUCCESS; 424 } 425 426 return QDF_STATUS_E_FAILURE; 427 } 428 429 /* 430 * hal_rx_mpdu_get_addr2_8074v2(): API to check get address2 of the mpdu 431 * in the packet 432 * 433 * @buf: pointer to the start of RX PKT TLV header 434 * @mac_addr: pointer to mac address 435 * Return: success/failure 436 */ 437 static QDF_STATUS hal_rx_mpdu_get_addr2_8074v2(uint8_t *buf, uint8_t *mac_addr) 438 { 439 struct __attribute__((__packed__)) hal_addr2 { 440 uint16_t ad2_15_0; 441 uint32_t ad2_47_16; 442 }; 443 444 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 445 struct rx_mpdu_start *mpdu_start = 446 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 447 448 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 449 struct hal_addr2 *addr = (struct hal_addr2 *)mac_addr; 450 uint32_t mac_addr_ad2_valid; 451 452 mac_addr_ad2_valid = HAL_RX_MPDU_MAC_ADDR_AD2_VALID_GET(mpdu_info); 453 454 if (mac_addr_ad2_valid) { 455 addr->ad2_15_0 = HAL_RX_MPDU_AD2_15_0_GET(mpdu_info); 456 addr->ad2_47_16 = HAL_RX_MPDU_AD2_47_16_GET(mpdu_info); 457 return QDF_STATUS_SUCCESS; 458 } 459 460 return QDF_STATUS_E_FAILURE; 461 } 462 463 /* 464 * hal_rx_mpdu_get_addr3_8074v2(): API to get address3 of the mpdu 465 * in the packet 466 * 467 * @buf: pointer to the start of RX PKT TLV header 468 * @mac_addr: pointer to mac address 469 * Return: success/failure 470 */ 471 static QDF_STATUS hal_rx_mpdu_get_addr3_8074v2(uint8_t *buf, uint8_t *mac_addr) 472 { 473 struct __attribute__((__packed__)) hal_addr3 { 474 uint32_t ad3_31_0; 475 uint16_t ad3_47_32; 476 }; 477 478 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 479 struct rx_mpdu_start *mpdu_start = 480 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 481 482 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 483 struct hal_addr3 *addr = (struct hal_addr3 *)mac_addr; 484 uint32_t mac_addr_ad3_valid; 485 486 mac_addr_ad3_valid = HAL_RX_MPDU_MAC_ADDR_AD3_VALID_GET(mpdu_info); 487 488 if (mac_addr_ad3_valid) { 489 addr->ad3_31_0 = HAL_RX_MPDU_AD3_31_0_GET(mpdu_info); 490 addr->ad3_47_32 = HAL_RX_MPDU_AD3_47_32_GET(mpdu_info); 491 return QDF_STATUS_SUCCESS; 492 } 493 494 return QDF_STATUS_E_FAILURE; 495 } 496 497 /* 498 * hal_rx_mpdu_get_addr4_8074v2(): API to get address4 of the mpdu 499 * in the packet 500 * 501 * @buf: pointer to the start of RX PKT TLV header 502 * @mac_addr: pointer to mac address 503 * Return: success/failure 504 */ 505 static QDF_STATUS hal_rx_mpdu_get_addr4_8074v2(uint8_t *buf, uint8_t *mac_addr) 506 { 507 struct __attribute__((__packed__)) hal_addr4 { 508 uint32_t ad4_31_0; 509 uint16_t ad4_47_32; 510 }; 511 512 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 513 struct rx_mpdu_start *mpdu_start = 514 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 515 516 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 517 struct hal_addr4 *addr = (struct hal_addr4 *)mac_addr; 518 uint32_t mac_addr_ad4_valid; 519 520 mac_addr_ad4_valid = HAL_RX_MPDU_MAC_ADDR_AD4_VALID_GET(mpdu_info); 521 522 if (mac_addr_ad4_valid) { 523 addr->ad4_31_0 = HAL_RX_MPDU_AD4_31_0_GET(mpdu_info); 524 addr->ad4_47_32 = HAL_RX_MPDU_AD4_47_32_GET(mpdu_info); 525 return QDF_STATUS_SUCCESS; 526 } 527 528 return QDF_STATUS_E_FAILURE; 529 } 530 531 /* 532 * hal_rx_get_mpdu_sequence_control_valid_8074v2(): Get mpdu 533 * sequence control valid 534 * 535 * @nbuf: Network buffer 536 * Returns: value of sequence control valid field 537 */ 538 static uint8_t hal_rx_get_mpdu_sequence_control_valid_8074v2(uint8_t *buf) 539 { 540 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 541 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 542 543 return HAL_RX_MPDU_GET_SEQUENCE_CONTROL_VALID(rx_mpdu_info); 544 } 545 546 /** 547 * hal_rx_is_unicast_8074v2: check packet is unicast frame or not. 548 * 549 * @ buf: pointer to rx pkt TLV. 550 * 551 * Return: true on unicast. 552 */ 553 static bool hal_rx_is_unicast_8074v2(uint8_t *buf) 554 { 555 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 556 struct rx_mpdu_start *mpdu_start = 557 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 558 uint32_t grp_id; 559 uint8_t *rx_mpdu_info = (uint8_t *)&mpdu_start->rx_mpdu_info_details; 560 561 grp_id = (_HAL_MS((*_OFFSET_TO_WORD_PTR((rx_mpdu_info), 562 RX_MPDU_INFO_0_SW_FRAME_GROUP_ID_OFFSET)), 563 RX_MPDU_INFO_0_SW_FRAME_GROUP_ID_MASK, 564 RX_MPDU_INFO_0_SW_FRAME_GROUP_ID_LSB)); 565 566 return (HAL_MPDU_SW_FRAME_GROUP_UNICAST_DATA == grp_id) ? true : false; 567 } 568 569 /** 570 * hal_rx_tid_get_8074v2: get tid based on qos control valid. 571 * @hal_soc_hdl: hal soc handle 572 * @buf: pointer to rx pkt TLV. 573 * 574 * Return: tid 575 */ 576 static uint32_t hal_rx_tid_get_8074v2(hal_soc_handle_t hal_soc_hdl, 577 uint8_t *buf) 578 { 579 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 580 struct rx_mpdu_start *mpdu_start = 581 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 582 uint8_t *rx_mpdu_info = (uint8_t *)&mpdu_start->rx_mpdu_info_details; 583 uint8_t qos_control_valid = 584 (_HAL_MS((*_OFFSET_TO_WORD_PTR((rx_mpdu_info), 585 RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_OFFSET)), 586 RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_MASK, 587 RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_LSB)); 588 589 if (qos_control_valid) 590 return hal_rx_mpdu_start_tid_get_8074v2(buf); 591 592 return HAL_RX_NON_QOS_TID; 593 } 594 595 /** 596 * hal_rx_hw_desc_get_ppduid_get_8074v2(): retrieve ppdu id 597 * @rx_tlv_hdr: packtet rx tlv header 598 * @rxdma_dst_ring_desc: rxdma HW descriptor 599 * 600 * Return: ppdu id 601 */ 602 static uint32_t hal_rx_hw_desc_get_ppduid_get_8074v2(void *rx_tlv_hdr, 603 void *rxdma_dst_ring_desc) 604 { 605 struct rx_mpdu_info *rx_mpdu_info; 606 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)rx_tlv_hdr; 607 608 rx_mpdu_info = 609 &rx_desc->mpdu_start_tlv.rx_mpdu_start.rx_mpdu_info_details; 610 611 return HAL_RX_GET(rx_mpdu_info, RX_MPDU_INFO_0, PHY_PPDU_ID); 612 } 613 614 /** 615 * hal_reo_status_get_header_8074v2 - Process reo desc info 616 * @ring_desc: REO status ring descriptor 617 * @b - tlv type info 618 * @h1 - Pointer to hal_reo_status_header where info to be stored 619 * 620 * Return - none. 621 * 622 */ 623 static void hal_reo_status_get_header_8074v2(hal_ring_desc_t ring_desc, int b, 624 void *h1) 625 { 626 uint32_t *d = (uint32_t *)ring_desc; 627 uint32_t val1 = 0; 628 struct hal_reo_status_header *h = 629 (struct hal_reo_status_header *)h1; 630 631 /* Offsets of descriptor fields defined in HW headers start 632 * from the field after TLV header 633 */ 634 d += HAL_GET_NUM_DWORDS(sizeof(struct tlv_32_hdr)); 635 636 switch (b) { 637 case HAL_REO_QUEUE_STATS_STATUS_TLV: 638 val1 = d[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_0, 639 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 640 break; 641 case HAL_REO_FLUSH_QUEUE_STATUS_TLV: 642 val1 = d[HAL_OFFSET_DW(REO_FLUSH_QUEUE_STATUS_0, 643 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 644 break; 645 case HAL_REO_FLUSH_CACHE_STATUS_TLV: 646 val1 = d[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_0, 647 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 648 break; 649 case HAL_REO_UNBLK_CACHE_STATUS_TLV: 650 val1 = d[HAL_OFFSET_DW(REO_UNBLOCK_CACHE_STATUS_0, 651 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 652 break; 653 case HAL_REO_TIMOUT_LIST_STATUS_TLV: 654 val1 = d[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_0, 655 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 656 break; 657 case HAL_REO_DESC_THRES_STATUS_TLV: 658 val1 = 659 d[HAL_OFFSET_DW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0, 660 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 661 break; 662 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: 663 val1 = d[HAL_OFFSET_DW(REO_UPDATE_RX_REO_QUEUE_STATUS_0, 664 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 665 break; 666 default: 667 qdf_nofl_err("ERROR: Unknown tlv\n"); 668 break; 669 } 670 h->cmd_num = 671 HAL_GET_FIELD( 672 UNIFORM_REO_STATUS_HEADER_0, REO_STATUS_NUMBER, 673 val1); 674 h->exec_time = 675 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_0, 676 CMD_EXECUTION_TIME, val1); 677 h->status = 678 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_0, 679 REO_CMD_EXECUTION_STATUS, val1); 680 switch (b) { 681 case HAL_REO_QUEUE_STATS_STATUS_TLV: 682 val1 = d[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_1, 683 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 684 break; 685 case HAL_REO_FLUSH_QUEUE_STATUS_TLV: 686 val1 = d[HAL_OFFSET_DW(REO_FLUSH_QUEUE_STATUS_1, 687 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 688 break; 689 case HAL_REO_FLUSH_CACHE_STATUS_TLV: 690 val1 = d[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_1, 691 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 692 break; 693 case HAL_REO_UNBLK_CACHE_STATUS_TLV: 694 val1 = d[HAL_OFFSET_DW(REO_UNBLOCK_CACHE_STATUS_1, 695 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 696 break; 697 case HAL_REO_TIMOUT_LIST_STATUS_TLV: 698 val1 = d[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_1, 699 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 700 break; 701 case HAL_REO_DESC_THRES_STATUS_TLV: 702 val1 = 703 d[HAL_OFFSET_DW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_1, 704 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 705 break; 706 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: 707 val1 = d[HAL_OFFSET_DW(REO_UPDATE_RX_REO_QUEUE_STATUS_1, 708 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 709 break; 710 default: 711 qdf_nofl_err("ERROR: Unknown tlv\n"); 712 break; 713 } 714 h->tstamp = 715 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_1, TIMESTAMP, val1); 716 } 717 718 /** 719 * hal_rx_mpdu_start_mpdu_qos_control_valid_get_8074v2(): 720 * Retrieve qos control valid bit from the tlv. 721 * @buf: pointer to rx pkt TLV. 722 * 723 * Return: qos control value. 724 */ 725 static inline uint32_t 726 hal_rx_mpdu_start_mpdu_qos_control_valid_get_8074v2(uint8_t *buf) 727 { 728 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 729 struct rx_mpdu_start *mpdu_start = 730 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 731 732 return HAL_RX_MPDU_INFO_QOS_CONTROL_VALID_GET( 733 &mpdu_start->rx_mpdu_info_details); 734 } 735 736 /** 737 * hal_rx_msdu_end_sa_sw_peer_id_get_8074v2(): API to get the 738 * sa_sw_peer_id from rx_msdu_end TLV 739 * @buf: pointer to the start of RX PKT TLV headers 740 * 741 * Return: sa_sw_peer_id index 742 */ 743 static inline uint32_t 744 hal_rx_msdu_end_sa_sw_peer_id_get_8074v2(uint8_t *buf) 745 { 746 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 747 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 748 749 return HAL_RX_MSDU_END_SA_SW_PEER_ID_GET(msdu_end); 750 } 751 752 /** 753 * hal_tx_desc_set_mesh_en_8074v2 - Set mesh_enable flag in Tx descriptor 754 * @desc: Handle to Tx Descriptor 755 * @en: For raw WiFi frames, this indicates transmission to a mesh STA, 756 * enabling the interpretation of the 'Mesh Control Present' bit 757 * (bit 8) of QoS Control (otherwise this bit is ignored), 758 * For native WiFi frames, this indicates that a 'Mesh Control' field 759 * is present between the header and the LLC. 760 * 761 * Return: void 762 */ 763 static inline 764 void hal_tx_desc_set_mesh_en_8074v2(void *desc, uint8_t en) 765 { 766 HAL_SET_FLD(desc, TCL_DATA_CMD_4, MESH_ENABLE) |= 767 HAL_TX_SM(TCL_DATA_CMD_4, MESH_ENABLE, en); 768 } 769 770 static 771 void *hal_rx_msdu0_buffer_addr_lsb_8074v2(void *link_desc_va) 772 { 773 return (void *)HAL_RX_MSDU0_BUFFER_ADDR_LSB(link_desc_va); 774 } 775 776 static 777 void *hal_rx_msdu_desc_info_ptr_get_8074v2(void *msdu0) 778 { 779 return (void *)HAL_RX_MSDU_DESC_INFO_PTR_GET(msdu0); 780 } 781 782 static 783 void *hal_ent_mpdu_desc_info_8074v2(void *ent_ring_desc) 784 { 785 return (void *)HAL_ENT_MPDU_DESC_INFO(ent_ring_desc); 786 } 787 788 static 789 void *hal_dst_mpdu_desc_info_8074v2(void *dst_ring_desc) 790 { 791 return (void *)HAL_DST_MPDU_DESC_INFO(dst_ring_desc); 792 } 793 794 static 795 uint8_t hal_rx_get_fc_valid_8074v2(uint8_t *buf) 796 { 797 return HAL_RX_GET_FC_VALID(buf); 798 } 799 800 static uint8_t hal_rx_get_to_ds_flag_8074v2(uint8_t *buf) 801 { 802 return HAL_RX_GET_TO_DS_FLAG(buf); 803 } 804 805 static uint8_t hal_rx_get_mac_addr2_valid_8074v2(uint8_t *buf) 806 { 807 return HAL_RX_GET_MAC_ADDR2_VALID(buf); 808 } 809 810 static uint8_t hal_rx_get_filter_category_8074v2(uint8_t *buf) 811 { 812 return HAL_RX_GET_FILTER_CATEGORY(buf); 813 } 814 815 static uint32_t 816 hal_rx_get_ppdu_id_8074v2(uint8_t *buf) 817 { 818 struct rx_mpdu_info *rx_mpdu_info; 819 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)buf; 820 821 rx_mpdu_info = 822 &rx_desc->mpdu_start_tlv.rx_mpdu_start.rx_mpdu_info_details; 823 824 return HAL_RX_GET_PPDU_ID(rx_mpdu_info); 825 } 826 827 /** 828 * hal_reo_config_8074v2(): Set reo config parameters 829 * @soc: hal soc handle 830 * @reg_val: value to be set 831 * @reo_params: reo parameters 832 * 833 * Return: void 834 */ 835 static void 836 hal_reo_config_8074v2(struct hal_soc *soc, 837 uint32_t reg_val, 838 struct hal_reo_params *reo_params) 839 { 840 HAL_REO_R0_CONFIG(soc, reg_val, reo_params); 841 } 842 843 /** 844 * hal_rx_msdu_desc_info_get_ptr_8074v2() - Get msdu desc info ptr 845 * @msdu_details_ptr - Pointer to msdu_details_ptr 846 * 847 * Return - Pointer to rx_msdu_desc_info structure. 848 * 849 */ 850 static void *hal_rx_msdu_desc_info_get_ptr_8074v2(void *msdu_details_ptr) 851 { 852 return HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr); 853 } 854 855 /** 856 * hal_rx_link_desc_msdu0_ptr_8074v2 - Get pointer to rx_msdu details 857 * @link_desc - Pointer to link desc 858 * 859 * Return - Pointer to rx_msdu_details structure 860 * 861 */ 862 static void *hal_rx_link_desc_msdu0_ptr_8074v2(void *link_desc) 863 { 864 return HAL_RX_LINK_DESC_MSDU0_PTR(link_desc); 865 } 866 867 /** 868 * hal_rx_msdu_flow_idx_get_8074v2: API to get flow index 869 * from rx_msdu_end TLV 870 * @buf: pointer to the start of RX PKT TLV headers 871 * 872 * Return: flow index value from MSDU END TLV 873 */ 874 static inline uint32_t hal_rx_msdu_flow_idx_get_8074v2(uint8_t *buf) 875 { 876 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 877 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 878 879 return HAL_RX_MSDU_END_FLOW_IDX_GET(msdu_end); 880 } 881 882 /** 883 * hal_rx_msdu_flow_idx_invalid_8074v2: API to get flow index invalid 884 * from rx_msdu_end TLV 885 * @buf: pointer to the start of RX PKT TLV headers 886 * 887 * Return: flow index invalid value from MSDU END TLV 888 */ 889 static bool hal_rx_msdu_flow_idx_invalid_8074v2(uint8_t *buf) 890 { 891 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 892 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 893 894 return HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(msdu_end); 895 } 896 897 /** 898 * hal_rx_msdu_flow_idx_timeout_8074v2: API to get flow index timeout 899 * from rx_msdu_end TLV 900 * @buf: pointer to the start of RX PKT TLV headers 901 * 902 * Return: flow index timeout value from MSDU END TLV 903 */ 904 static bool hal_rx_msdu_flow_idx_timeout_8074v2(uint8_t *buf) 905 { 906 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 907 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 908 909 return HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(msdu_end); 910 } 911 912 /** 913 * hal_rx_msdu_fse_metadata_get_8074v2: API to get FSE metadata 914 * from rx_msdu_end TLV 915 * @buf: pointer to the start of RX PKT TLV headers 916 * 917 * Return: fse metadata value from MSDU END TLV 918 */ 919 static uint32_t hal_rx_msdu_fse_metadata_get_8074v2(uint8_t *buf) 920 { 921 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 922 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 923 924 return HAL_RX_MSDU_END_FSE_METADATA_GET(msdu_end); 925 } 926 927 /** 928 * hal_rx_msdu_cce_metadata_get_8074v2: API to get CCE metadata 929 * from rx_msdu_end TLV 930 * @buf: pointer to the start of RX PKT TLV headers 931 * 932 * Return: cce_metadata 933 */ 934 static uint16_t 935 hal_rx_msdu_cce_metadata_get_8074v2(uint8_t *buf) 936 { 937 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 938 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 939 940 return HAL_RX_MSDU_END_CCE_METADATA_GET(msdu_end); 941 } 942 943 /** 944 * hal_rx_msdu_get_flow_params_8074v2: API to get flow index, flow index invalid 945 * and flow index timeout from rx_msdu_end TLV 946 * @buf: pointer to the start of RX PKT TLV headers 947 * @flow_invalid: pointer to return value of flow_idx_valid 948 * @flow_timeout: pointer to return value of flow_idx_timeout 949 * @flow_index: pointer to return value of flow_idx 950 * 951 * Return: none 952 */ 953 static inline void 954 hal_rx_msdu_get_flow_params_8074v2(uint8_t *buf, 955 bool *flow_invalid, 956 bool *flow_timeout, 957 uint32_t *flow_index) 958 { 959 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 960 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 961 962 *flow_invalid = HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(msdu_end); 963 *flow_timeout = HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(msdu_end); 964 *flow_index = HAL_RX_MSDU_END_FLOW_IDX_GET(msdu_end); 965 } 966 967 /** 968 * hal_rx_tlv_get_tcp_chksum_8074v2() - API to get tcp checksum 969 * @buf: rx_tlv_hdr 970 * 971 * Return: tcp checksum 972 */ 973 static uint16_t 974 hal_rx_tlv_get_tcp_chksum_8074v2(uint8_t *buf) 975 { 976 return HAL_RX_TLV_GET_TCP_CHKSUM(buf); 977 } 978 979 /** 980 * hal_rx_get_rx_sequence_8074v2(): Function to retrieve rx sequence number 981 * 982 * @nbuf: Network buffer 983 * Returns: rx sequence number 984 */ 985 static 986 uint16_t hal_rx_get_rx_sequence_8074v2(uint8_t *buf) 987 { 988 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 989 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 990 991 return HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info); 992 } 993 994 /** 995 * hal_get_window_address_8074v2(): Function to get hp/tp address 996 * @hal_soc: Pointer to hal_soc 997 * @addr: address offset of register 998 * 999 * Return: modified address offset of register 1000 */ 1001 static inline qdf_iomem_t hal_get_window_address_8074v2(struct hal_soc *hal_soc, 1002 qdf_iomem_t addr) 1003 { 1004 return addr; 1005 } 1006 1007 /** 1008 * hal_rx_mpdu_start_tlv_tag_valid_8074v2 () - API to check if RX_MPDU_START 1009 * tlv tag is valid 1010 * 1011 * @rx_tlv_hdr: start address of rx_pkt_tlvs 1012 * 1013 * Return: true if RX_MPDU_START is valied, else false. 1014 */ 1015 uint8_t hal_rx_mpdu_start_tlv_tag_valid_8074v2(void *rx_tlv_hdr) 1016 { 1017 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)rx_tlv_hdr; 1018 uint32_t tlv_tag; 1019 1020 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(&rx_desc->mpdu_start_tlv); 1021 1022 return tlv_tag == WIFIRX_MPDU_START_E ? true : false; 1023 } 1024 1025 /** 1026 * hal_rx_flow_setup_fse_8074v2() - Setup a flow search entry in HW FST 1027 * @fst: Pointer to the Rx Flow Search Table 1028 * @table_offset: offset into the table where the flow is to be setup 1029 * @flow: Flow Parameters 1030 * 1031 * Return: Success/Failure 1032 */ 1033 static void * 1034 hal_rx_flow_setup_fse_8074v2(uint8_t *rx_fst, uint32_t table_offset, 1035 uint8_t *rx_flow) 1036 { 1037 struct hal_rx_fst *fst = (struct hal_rx_fst *)rx_fst; 1038 struct hal_rx_flow *flow = (struct hal_rx_flow *)rx_flow; 1039 uint8_t *fse; 1040 bool fse_valid; 1041 1042 if (table_offset >= fst->max_entries) { 1043 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR, 1044 "HAL FSE table offset %u exceeds max entries %u", 1045 table_offset, fst->max_entries); 1046 return NULL; 1047 } 1048 1049 fse = (uint8_t *)fst->base_vaddr + 1050 (table_offset * HAL_RX_FST_ENTRY_SIZE); 1051 1052 fse_valid = HAL_GET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, VALID); 1053 1054 if (fse_valid) { 1055 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_DEBUG, 1056 "HAL FSE %pK already valid", fse); 1057 return NULL; 1058 } 1059 1060 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_0, SRC_IP_127_96) = 1061 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_0, SRC_IP_127_96, 1062 qdf_htonl(flow->tuple_info.src_ip_127_96)); 1063 1064 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_1, SRC_IP_95_64) = 1065 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_1, SRC_IP_95_64, 1066 qdf_htonl(flow->tuple_info.src_ip_95_64)); 1067 1068 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_2, SRC_IP_63_32) = 1069 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_2, SRC_IP_63_32, 1070 qdf_htonl(flow->tuple_info.src_ip_63_32)); 1071 1072 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_3, SRC_IP_31_0) = 1073 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_3, SRC_IP_31_0, 1074 qdf_htonl(flow->tuple_info.src_ip_31_0)); 1075 1076 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_4, DEST_IP_127_96) = 1077 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_4, DEST_IP_127_96, 1078 qdf_htonl(flow->tuple_info.dest_ip_127_96)); 1079 1080 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_5, DEST_IP_95_64) = 1081 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_5, DEST_IP_95_64, 1082 qdf_htonl(flow->tuple_info.dest_ip_95_64)); 1083 1084 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_6, DEST_IP_63_32) = 1085 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_6, DEST_IP_63_32, 1086 qdf_htonl(flow->tuple_info.dest_ip_63_32)); 1087 1088 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_7, DEST_IP_31_0) = 1089 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_7, DEST_IP_31_0, 1090 qdf_htonl(flow->tuple_info.dest_ip_31_0)); 1091 1092 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, DEST_PORT); 1093 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, DEST_PORT) |= 1094 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_8, DEST_PORT, 1095 (flow->tuple_info.dest_port)); 1096 1097 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, SRC_PORT); 1098 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, SRC_PORT) |= 1099 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_8, SRC_PORT, 1100 (flow->tuple_info.src_port)); 1101 1102 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, L4_PROTOCOL); 1103 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, L4_PROTOCOL) |= 1104 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, L4_PROTOCOL, 1105 flow->tuple_info.l4_protocol); 1106 1107 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_HANDLER); 1108 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_HANDLER) |= 1109 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_HANDLER, 1110 flow->reo_destination_handler); 1111 1112 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, VALID); 1113 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, VALID) |= 1114 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, VALID, 1); 1115 1116 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_10, METADATA); 1117 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_10, METADATA) = 1118 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_10, METADATA, 1119 flow->fse_metadata); 1120 1121 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_11, REO_DESTINATION_INDICATION); 1122 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_11, REO_DESTINATION_INDICATION) |= 1123 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_11, 1124 REO_DESTINATION_INDICATION, 1125 flow->reo_destination_indication); 1126 1127 /* Reset all the other fields in FSE */ 1128 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, RESERVED_9); 1129 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_11, MSDU_DROP); 1130 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_11, RESERVED_11); 1131 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_11, MSDU_COUNT); 1132 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_12, MSDU_BYTE_COUNT); 1133 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_13, TIMESTAMP); 1134 1135 return fse; 1136 } 1137 1138 static 1139 void hal_compute_reo_remap_ix2_ix3_8074v2(uint32_t *ring, uint32_t num_rings, 1140 uint32_t *remap1, uint32_t *remap2) 1141 { 1142 switch (num_rings) { 1143 case 1: 1144 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 1145 HAL_REO_REMAP_IX2(ring[0], 17) | 1146 HAL_REO_REMAP_IX2(ring[0], 18) | 1147 HAL_REO_REMAP_IX2(ring[0], 19) | 1148 HAL_REO_REMAP_IX2(ring[0], 20) | 1149 HAL_REO_REMAP_IX2(ring[0], 21) | 1150 HAL_REO_REMAP_IX2(ring[0], 22) | 1151 HAL_REO_REMAP_IX2(ring[0], 23); 1152 1153 *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) | 1154 HAL_REO_REMAP_IX3(ring[0], 25) | 1155 HAL_REO_REMAP_IX3(ring[0], 26) | 1156 HAL_REO_REMAP_IX3(ring[0], 27) | 1157 HAL_REO_REMAP_IX3(ring[0], 28) | 1158 HAL_REO_REMAP_IX3(ring[0], 29) | 1159 HAL_REO_REMAP_IX3(ring[0], 30) | 1160 HAL_REO_REMAP_IX3(ring[0], 31); 1161 break; 1162 case 2: 1163 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 1164 HAL_REO_REMAP_IX2(ring[0], 17) | 1165 HAL_REO_REMAP_IX2(ring[1], 18) | 1166 HAL_REO_REMAP_IX2(ring[1], 19) | 1167 HAL_REO_REMAP_IX2(ring[0], 20) | 1168 HAL_REO_REMAP_IX2(ring[0], 21) | 1169 HAL_REO_REMAP_IX2(ring[1], 22) | 1170 HAL_REO_REMAP_IX2(ring[1], 23); 1171 1172 *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) | 1173 HAL_REO_REMAP_IX3(ring[0], 25) | 1174 HAL_REO_REMAP_IX3(ring[1], 26) | 1175 HAL_REO_REMAP_IX3(ring[1], 27) | 1176 HAL_REO_REMAP_IX3(ring[0], 28) | 1177 HAL_REO_REMAP_IX3(ring[0], 29) | 1178 HAL_REO_REMAP_IX3(ring[1], 30) | 1179 HAL_REO_REMAP_IX3(ring[1], 31); 1180 break; 1181 case 3: 1182 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 1183 HAL_REO_REMAP_IX2(ring[1], 17) | 1184 HAL_REO_REMAP_IX2(ring[2], 18) | 1185 HAL_REO_REMAP_IX2(ring[0], 19) | 1186 HAL_REO_REMAP_IX2(ring[1], 20) | 1187 HAL_REO_REMAP_IX2(ring[2], 21) | 1188 HAL_REO_REMAP_IX2(ring[0], 22) | 1189 HAL_REO_REMAP_IX2(ring[1], 23); 1190 1191 *remap2 = HAL_REO_REMAP_IX3(ring[2], 24) | 1192 HAL_REO_REMAP_IX3(ring[0], 25) | 1193 HAL_REO_REMAP_IX3(ring[1], 26) | 1194 HAL_REO_REMAP_IX3(ring[2], 27) | 1195 HAL_REO_REMAP_IX3(ring[0], 28) | 1196 HAL_REO_REMAP_IX3(ring[1], 29) | 1197 HAL_REO_REMAP_IX3(ring[2], 30) | 1198 HAL_REO_REMAP_IX3(ring[0], 31); 1199 break; 1200 case 4: 1201 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 1202 HAL_REO_REMAP_IX2(ring[1], 17) | 1203 HAL_REO_REMAP_IX2(ring[2], 18) | 1204 HAL_REO_REMAP_IX2(ring[3], 19) | 1205 HAL_REO_REMAP_IX2(ring[0], 20) | 1206 HAL_REO_REMAP_IX2(ring[1], 21) | 1207 HAL_REO_REMAP_IX2(ring[2], 22) | 1208 HAL_REO_REMAP_IX2(ring[3], 23); 1209 1210 *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) | 1211 HAL_REO_REMAP_IX3(ring[1], 25) | 1212 HAL_REO_REMAP_IX3(ring[2], 26) | 1213 HAL_REO_REMAP_IX3(ring[3], 27) | 1214 HAL_REO_REMAP_IX3(ring[0], 28) | 1215 HAL_REO_REMAP_IX3(ring[1], 29) | 1216 HAL_REO_REMAP_IX3(ring[2], 30) | 1217 HAL_REO_REMAP_IX3(ring[3], 31); 1218 break; 1219 } 1220 } 1221 1222 static void hal_hw_txrx_ops_attach_qca8074v2(struct hal_soc *hal_soc) 1223 { 1224 1225 /* init and setup */ 1226 hal_soc->ops->hal_srng_dst_hw_init = hal_srng_dst_hw_init_generic; 1227 hal_soc->ops->hal_srng_src_hw_init = hal_srng_src_hw_init_generic; 1228 hal_soc->ops->hal_get_hw_hptp = hal_get_hw_hptp_generic; 1229 hal_soc->ops->hal_reo_setup = hal_reo_setup_generic_li; 1230 hal_soc->ops->hal_get_window_address = hal_get_window_address_8074v2; 1231 1232 /* tx */ 1233 hal_soc->ops->hal_tx_desc_set_dscp_tid_table_id = 1234 hal_tx_desc_set_dscp_tid_table_id_8074v2; 1235 hal_soc->ops->hal_tx_set_dscp_tid_map = hal_tx_set_dscp_tid_map_8074v2; 1236 hal_soc->ops->hal_tx_update_dscp_tid = hal_tx_update_dscp_tid_8074v2; 1237 hal_soc->ops->hal_tx_desc_set_lmac_id = hal_tx_desc_set_lmac_id_8074v2; 1238 hal_soc->ops->hal_tx_desc_set_buf_addr = 1239 hal_tx_desc_set_buf_addr_generic_li; 1240 hal_soc->ops->hal_tx_desc_set_search_type = 1241 hal_tx_desc_set_search_type_generic_li; 1242 hal_soc->ops->hal_tx_desc_set_search_index = 1243 hal_tx_desc_set_search_index_generic_li; 1244 hal_soc->ops->hal_tx_desc_set_cache_set_num = 1245 hal_tx_desc_set_cache_set_num_generic_li; 1246 hal_soc->ops->hal_tx_comp_get_status = 1247 hal_tx_comp_get_status_generic_li; 1248 hal_soc->ops->hal_tx_comp_get_release_reason = 1249 hal_tx_comp_get_release_reason_generic_li; 1250 hal_soc->ops->hal_get_wbm_internal_error = 1251 hal_get_wbm_internal_error_generic_li; 1252 hal_soc->ops->hal_tx_desc_set_mesh_en = hal_tx_desc_set_mesh_en_8074v2; 1253 hal_soc->ops->hal_tx_init_cmd_credit_ring = 1254 hal_tx_init_cmd_credit_ring_8074v2; 1255 1256 /* rx */ 1257 hal_soc->ops->hal_rx_msdu_start_nss_get = 1258 hal_rx_msdu_start_nss_get_8074v2; 1259 hal_soc->ops->hal_rx_mon_hw_desc_get_mpdu_status = 1260 hal_rx_mon_hw_desc_get_mpdu_status_8074v2; 1261 hal_soc->ops->hal_rx_get_tlv = hal_rx_get_tlv_8074v2; 1262 hal_soc->ops->hal_rx_proc_phyrx_other_receive_info_tlv = 1263 hal_rx_proc_phyrx_other_receive_info_tlv_8074v2; 1264 hal_soc->ops->hal_rx_dump_msdu_start_tlv = 1265 hal_rx_dump_msdu_start_tlv_8074v2; 1266 hal_soc->ops->hal_rx_dump_msdu_end_tlv = hal_rx_dump_msdu_end_tlv_8074v2; 1267 hal_soc->ops->hal_get_link_desc_size = hal_get_link_desc_size_8074v2; 1268 hal_soc->ops->hal_rx_mpdu_start_tid_get = 1269 hal_rx_mpdu_start_tid_get_8074v2; 1270 hal_soc->ops->hal_rx_msdu_start_reception_type_get = 1271 hal_rx_msdu_start_reception_type_get_8074v2; 1272 hal_soc->ops->hal_rx_msdu_end_da_idx_get = 1273 hal_rx_msdu_end_da_idx_get_8074v2; 1274 hal_soc->ops->hal_rx_msdu_desc_info_get_ptr = 1275 hal_rx_msdu_desc_info_get_ptr_8074v2; 1276 hal_soc->ops->hal_rx_link_desc_msdu0_ptr = 1277 hal_rx_link_desc_msdu0_ptr_8074v2; 1278 hal_soc->ops->hal_reo_status_get_header = 1279 hal_reo_status_get_header_8074v2; 1280 hal_soc->ops->hal_rx_status_get_tlv_info = 1281 hal_rx_status_get_tlv_info_generic_li; 1282 hal_soc->ops->hal_rx_wbm_err_info_get = 1283 hal_rx_wbm_err_info_get_generic_li; 1284 hal_soc->ops->hal_rx_dump_mpdu_start_tlv = 1285 hal_rx_dump_mpdu_start_tlv_generic_li; 1286 1287 hal_soc->ops->hal_tx_set_pcp_tid_map = 1288 hal_tx_set_pcp_tid_map_generic_li; 1289 hal_soc->ops->hal_tx_update_pcp_tid_map = 1290 hal_tx_update_pcp_tid_generic_li; 1291 hal_soc->ops->hal_tx_set_tidmap_prty = 1292 hal_tx_update_tidmap_prty_generic_li; 1293 hal_soc->ops->hal_rx_get_rx_fragment_number = 1294 hal_rx_get_rx_fragment_number_8074v2; 1295 hal_soc->ops->hal_rx_msdu_end_da_is_mcbc_get = 1296 hal_rx_msdu_end_da_is_mcbc_get_8074v2; 1297 hal_soc->ops->hal_rx_msdu_end_sa_is_valid_get = 1298 hal_rx_msdu_end_sa_is_valid_get_8074v2; 1299 hal_soc->ops->hal_rx_msdu_end_sa_idx_get = 1300 hal_rx_msdu_end_sa_idx_get_8074v2; 1301 hal_soc->ops->hal_rx_desc_is_first_msdu = 1302 hal_rx_desc_is_first_msdu_8074v2; 1303 hal_soc->ops->hal_rx_msdu_end_l3_hdr_padding_get = 1304 hal_rx_msdu_end_l3_hdr_padding_get_8074v2; 1305 hal_soc->ops->hal_rx_encryption_info_valid = 1306 hal_rx_encryption_info_valid_8074v2; 1307 hal_soc->ops->hal_rx_print_pn = hal_rx_print_pn_8074v2; 1308 hal_soc->ops->hal_rx_msdu_end_first_msdu_get = 1309 hal_rx_msdu_end_first_msdu_get_8074v2; 1310 hal_soc->ops->hal_rx_msdu_end_da_is_valid_get = 1311 hal_rx_msdu_end_da_is_valid_get_8074v2; 1312 hal_soc->ops->hal_rx_msdu_end_last_msdu_get = 1313 hal_rx_msdu_end_last_msdu_get_8074v2; 1314 hal_soc->ops->hal_rx_get_mpdu_mac_ad4_valid = 1315 hal_rx_get_mpdu_mac_ad4_valid_8074v2; 1316 hal_soc->ops->hal_rx_mpdu_start_sw_peer_id_get = 1317 hal_rx_mpdu_start_sw_peer_id_get_8074v2; 1318 hal_soc->ops->hal_rx_mpdu_get_to_ds = hal_rx_mpdu_get_to_ds_8074v2; 1319 hal_soc->ops->hal_rx_mpdu_get_fr_ds = hal_rx_mpdu_get_fr_ds_8074v2; 1320 hal_soc->ops->hal_rx_get_mpdu_frame_control_valid = 1321 hal_rx_get_mpdu_frame_control_valid_8074v2; 1322 hal_soc->ops->hal_rx_mpdu_get_addr1 = hal_rx_mpdu_get_addr1_8074v2; 1323 hal_soc->ops->hal_rx_mpdu_get_addr2 = hal_rx_mpdu_get_addr2_8074v2; 1324 hal_soc->ops->hal_rx_mpdu_get_addr3 = hal_rx_mpdu_get_addr3_8074v2; 1325 hal_soc->ops->hal_rx_mpdu_get_addr4 = hal_rx_mpdu_get_addr4_8074v2; 1326 hal_soc->ops->hal_rx_get_mpdu_sequence_control_valid = 1327 hal_rx_get_mpdu_sequence_control_valid_8074v2; 1328 hal_soc->ops->hal_rx_is_unicast = hal_rx_is_unicast_8074v2; 1329 hal_soc->ops->hal_rx_tid_get = hal_rx_tid_get_8074v2; 1330 hal_soc->ops->hal_rx_hw_desc_get_ppduid_get = 1331 hal_rx_hw_desc_get_ppduid_get_8074v2; 1332 hal_soc->ops->hal_rx_mpdu_start_mpdu_qos_control_valid_get = 1333 hal_rx_mpdu_start_mpdu_qos_control_valid_get_8074v2; 1334 hal_soc->ops->hal_rx_msdu_end_sa_sw_peer_id_get = 1335 hal_rx_msdu_end_sa_sw_peer_id_get_8074v2; 1336 hal_soc->ops->hal_rx_msdu0_buffer_addr_lsb = 1337 hal_rx_msdu0_buffer_addr_lsb_8074v2; 1338 hal_soc->ops->hal_rx_msdu_desc_info_ptr_get = 1339 hal_rx_msdu_desc_info_ptr_get_8074v2; 1340 hal_soc->ops->hal_ent_mpdu_desc_info = hal_ent_mpdu_desc_info_8074v2; 1341 hal_soc->ops->hal_dst_mpdu_desc_info = hal_dst_mpdu_desc_info_8074v2; 1342 hal_soc->ops->hal_rx_get_fc_valid = hal_rx_get_fc_valid_8074v2; 1343 hal_soc->ops->hal_rx_get_to_ds_flag = hal_rx_get_to_ds_flag_8074v2; 1344 hal_soc->ops->hal_rx_get_mac_addr2_valid = 1345 hal_rx_get_mac_addr2_valid_8074v2; 1346 hal_soc->ops->hal_rx_get_filter_category = 1347 hal_rx_get_filter_category_8074v2; 1348 hal_soc->ops->hal_rx_get_ppdu_id = hal_rx_get_ppdu_id_8074v2; 1349 hal_soc->ops->hal_reo_config = hal_reo_config_8074v2; 1350 hal_soc->ops->hal_rx_msdu_flow_idx_get = hal_rx_msdu_flow_idx_get_8074v2; 1351 hal_soc->ops->hal_rx_msdu_flow_idx_invalid = 1352 hal_rx_msdu_flow_idx_invalid_8074v2; 1353 hal_soc->ops->hal_rx_msdu_flow_idx_timeout = 1354 hal_rx_msdu_flow_idx_timeout_8074v2; 1355 hal_soc->ops->hal_rx_msdu_fse_metadata_get = 1356 hal_rx_msdu_fse_metadata_get_8074v2; 1357 hal_soc->ops->hal_rx_msdu_cce_metadata_get = 1358 hal_rx_msdu_cce_metadata_get_8074v2; 1359 hal_soc->ops->hal_rx_msdu_get_flow_params = 1360 hal_rx_msdu_get_flow_params_8074v2; 1361 hal_soc->ops->hal_rx_tlv_get_tcp_chksum = 1362 hal_rx_tlv_get_tcp_chksum_8074v2; 1363 hal_soc->ops->hal_rx_get_rx_sequence = hal_rx_get_rx_sequence_8074v2; 1364 #if defined(QCA_WIFI_QCA6018) && defined(WLAN_CFR_ENABLE) && \ 1365 defined(WLAN_ENH_CFR_ENABLE) 1366 hal_soc->ops->hal_rx_get_bb_info = hal_rx_get_bb_info_8074v2; 1367 hal_soc->ops->hal_rx_get_rtt_info = hal_rx_get_rtt_info_8074v2; 1368 #endif 1369 /* rx - msdu fast path info fields */ 1370 hal_soc->ops->hal_rx_msdu_packet_metadata_get = 1371 hal_rx_msdu_packet_metadata_get_generic_li; 1372 hal_soc->ops->hal_rx_mpdu_start_tlv_tag_valid = 1373 hal_rx_mpdu_start_tlv_tag_valid_8074v2; 1374 1375 /* rx - TLV struct offsets */ 1376 hal_soc->ops->hal_rx_msdu_end_offset_get = 1377 hal_rx_msdu_end_offset_get_generic; 1378 hal_soc->ops->hal_rx_attn_offset_get = hal_rx_attn_offset_get_generic; 1379 hal_soc->ops->hal_rx_msdu_start_offset_get = 1380 hal_rx_msdu_start_offset_get_generic; 1381 hal_soc->ops->hal_rx_mpdu_start_offset_get = 1382 hal_rx_mpdu_start_offset_get_generic; 1383 hal_soc->ops->hal_rx_mpdu_end_offset_get = 1384 hal_rx_mpdu_end_offset_get_generic; 1385 #ifndef NO_RX_PKT_HDR_TLV 1386 hal_soc->ops->hal_rx_pkt_tlv_offset_get = 1387 hal_rx_pkt_tlv_offset_get_generic; 1388 #endif 1389 hal_soc->ops->hal_rx_flow_setup_fse = hal_rx_flow_setup_fse_8074v2; 1390 hal_soc->ops->hal_compute_reo_remap_ix2_ix3 = 1391 hal_compute_reo_remap_ix2_ix3_8074v2; 1392 hal_soc->ops->hal_setup_link_idle_list = 1393 hal_setup_link_idle_list_generic_li; 1394 }; 1395 1396 struct hal_hw_srng_config hw_srng_table_8074v2[] = { 1397 /* TODO: max_rings can populated by querying HW capabilities */ 1398 { /* REO_DST */ 1399 .start_ring_id = HAL_SRNG_REO2SW1, 1400 .max_rings = 4, 1401 .entry_size = sizeof(struct reo_destination_ring) >> 2, 1402 .lmac_ring = FALSE, 1403 .ring_dir = HAL_SRNG_DST_RING, 1404 .reg_start = { 1405 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR( 1406 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1407 HWIO_REO_R2_REO2SW1_RING_HP_ADDR( 1408 SEQ_WCSS_UMAC_REO_REG_OFFSET) 1409 }, 1410 .reg_size = { 1411 HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(0) - 1412 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(0), 1413 HWIO_REO_R2_REO2SW2_RING_HP_ADDR(0) - 1414 HWIO_REO_R2_REO2SW1_RING_HP_ADDR(0), 1415 }, 1416 .max_size = 1417 HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_BMSK >> 1418 HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_SHFT, 1419 }, 1420 { /* REO_EXCEPTION */ 1421 /* Designating REO2TCL ring as exception ring. This ring is 1422 * similar to other REO2SW rings though it is named as REO2TCL. 1423 * Any of theREO2SW rings can be used as exception ring. 1424 */ 1425 .start_ring_id = HAL_SRNG_REO2TCL, 1426 .max_rings = 1, 1427 .entry_size = sizeof(struct reo_destination_ring) >> 2, 1428 .lmac_ring = FALSE, 1429 .ring_dir = HAL_SRNG_DST_RING, 1430 .reg_start = { 1431 HWIO_REO_R0_REO2TCL_RING_BASE_LSB_ADDR( 1432 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1433 HWIO_REO_R2_REO2TCL_RING_HP_ADDR( 1434 SEQ_WCSS_UMAC_REO_REG_OFFSET) 1435 }, 1436 /* Single ring - provide ring size if multiple rings of this 1437 * type are supported 1438 */ 1439 .reg_size = {}, 1440 .max_size = 1441 HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_BMSK >> 1442 HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_SHFT, 1443 }, 1444 { /* REO_REINJECT */ 1445 .start_ring_id = HAL_SRNG_SW2REO, 1446 .max_rings = 1, 1447 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 1448 .lmac_ring = FALSE, 1449 .ring_dir = HAL_SRNG_SRC_RING, 1450 .reg_start = { 1451 HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR( 1452 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1453 HWIO_REO_R2_SW2REO_RING_HP_ADDR( 1454 SEQ_WCSS_UMAC_REO_REG_OFFSET) 1455 }, 1456 /* Single ring - provide ring size if multiple rings of this 1457 * type are supported 1458 */ 1459 .reg_size = {}, 1460 .max_size = HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_BMSK >> 1461 HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_SHFT, 1462 }, 1463 { /* REO_CMD */ 1464 .start_ring_id = HAL_SRNG_REO_CMD, 1465 .max_rings = 1, 1466 .entry_size = (sizeof(struct tlv_32_hdr) + 1467 sizeof(struct reo_get_queue_stats)) >> 2, 1468 .lmac_ring = FALSE, 1469 .ring_dir = HAL_SRNG_SRC_RING, 1470 .reg_start = { 1471 HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR( 1472 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1473 HWIO_REO_R2_REO_CMD_RING_HP_ADDR( 1474 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1475 }, 1476 /* Single ring - provide ring size if multiple rings of this 1477 * type are supported 1478 */ 1479 .reg_size = {}, 1480 .max_size = HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_BMSK >> 1481 HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_SHFT, 1482 }, 1483 { /* REO_STATUS */ 1484 .start_ring_id = HAL_SRNG_REO_STATUS, 1485 .max_rings = 1, 1486 .entry_size = (sizeof(struct tlv_32_hdr) + 1487 sizeof(struct reo_get_queue_stats_status)) >> 2, 1488 .lmac_ring = FALSE, 1489 .ring_dir = HAL_SRNG_DST_RING, 1490 .reg_start = { 1491 HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR( 1492 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1493 HWIO_REO_R2_REO_STATUS_RING_HP_ADDR( 1494 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1495 }, 1496 /* Single ring - provide ring size if multiple rings of this 1497 * type are supported 1498 */ 1499 .reg_size = {}, 1500 .max_size = 1501 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> 1502 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, 1503 }, 1504 { /* TCL_DATA */ 1505 .start_ring_id = HAL_SRNG_SW2TCL1, 1506 .max_rings = 3, 1507 .entry_size = (sizeof(struct tlv_32_hdr) + 1508 sizeof(struct tcl_data_cmd)) >> 2, 1509 .lmac_ring = FALSE, 1510 .ring_dir = HAL_SRNG_SRC_RING, 1511 .reg_start = { 1512 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR( 1513 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1514 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR( 1515 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1516 }, 1517 .reg_size = { 1518 HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(0) - 1519 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(0), 1520 HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(0) - 1521 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(0), 1522 }, 1523 .max_size = 1524 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK >> 1525 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT, 1526 }, 1527 { /* TCL_CMD */ 1528 /* qca8074v2 and qcn9000 uses this ring for data commands */ 1529 .start_ring_id = HAL_SRNG_SW2TCL_CMD, 1530 .max_rings = 1, 1531 .entry_size = (sizeof(struct tlv_32_hdr) + 1532 sizeof(struct tcl_data_cmd)) >> 2, 1533 .lmac_ring = FALSE, 1534 .ring_dir = HAL_SRNG_SRC_RING, 1535 .reg_start = { 1536 HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_ADDR( 1537 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1538 HWIO_TCL_R2_SW2TCL_CMD_RING_HP_ADDR( 1539 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1540 }, 1541 /* Single ring - provide ring size if multiple rings of this 1542 * type are supported 1543 */ 1544 .reg_size = {}, 1545 .max_size = 1546 HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RING_SIZE_BMSK >> 1547 HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RING_SIZE_SHFT, 1548 }, 1549 { /* TCL_STATUS */ 1550 .start_ring_id = HAL_SRNG_TCL_STATUS, 1551 .max_rings = 1, 1552 .entry_size = (sizeof(struct tlv_32_hdr) + 1553 sizeof(struct tcl_status_ring)) >> 2, 1554 .lmac_ring = FALSE, 1555 .ring_dir = HAL_SRNG_DST_RING, 1556 .reg_start = { 1557 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR( 1558 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1559 HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR( 1560 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1561 }, 1562 /* Single ring - provide ring size if multiple rings of this 1563 * type are supported 1564 */ 1565 .reg_size = {}, 1566 .max_size = 1567 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_BMSK >> 1568 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_SHFT, 1569 }, 1570 { /* CE_SRC */ 1571 .start_ring_id = HAL_SRNG_CE_0_SRC, 1572 .max_rings = 12, 1573 .entry_size = sizeof(struct ce_src_desc) >> 2, 1574 .lmac_ring = FALSE, 1575 .ring_dir = HAL_SRNG_SRC_RING, 1576 .reg_start = { 1577 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR( 1578 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET), 1579 HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR( 1580 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET), 1581 }, 1582 .reg_size = { 1583 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET - 1584 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET, 1585 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET - 1586 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET, 1587 }, 1588 .max_size = 1589 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >> 1590 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT, 1591 }, 1592 { /* CE_DST */ 1593 .start_ring_id = HAL_SRNG_CE_0_DST, 1594 .max_rings = 12, 1595 .entry_size = 8 >> 2, 1596 /*TODO: entry_size above should actually be 1597 * sizeof(struct ce_dst_desc) >> 2, but couldn't find definition 1598 * of struct ce_dst_desc in HW header files 1599 */ 1600 .lmac_ring = FALSE, 1601 .ring_dir = HAL_SRNG_SRC_RING, 1602 .reg_start = { 1603 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR( 1604 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 1605 HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR( 1606 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 1607 }, 1608 .reg_size = { 1609 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 1610 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 1611 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 1612 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 1613 }, 1614 .max_size = 1615 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >> 1616 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT, 1617 }, 1618 { /* CE_DST_STATUS */ 1619 .start_ring_id = HAL_SRNG_CE_0_DST_STATUS, 1620 .max_rings = 12, 1621 .entry_size = sizeof(struct ce_stat_desc) >> 2, 1622 .lmac_ring = FALSE, 1623 .ring_dir = HAL_SRNG_DST_RING, 1624 .reg_start = { 1625 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR( 1626 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 1627 HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR( 1628 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 1629 }, 1630 /* TODO: check destination status ring registers */ 1631 .reg_size = { 1632 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 1633 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 1634 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 1635 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 1636 }, 1637 .max_size = 1638 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> 1639 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, 1640 }, 1641 { /* WBM_IDLE_LINK */ 1642 .start_ring_id = HAL_SRNG_WBM_IDLE_LINK, 1643 .max_rings = 1, 1644 .entry_size = sizeof(struct wbm_link_descriptor_ring) >> 2, 1645 .lmac_ring = FALSE, 1646 .ring_dir = HAL_SRNG_SRC_RING, 1647 .reg_start = { 1648 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1649 HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1650 }, 1651 /* Single ring - provide ring size if multiple rings of this 1652 * type are supported 1653 */ 1654 .reg_size = {}, 1655 .max_size = 1656 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_BMSK >> 1657 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_SHFT, 1658 }, 1659 { /* SW2WBM_RELEASE */ 1660 .start_ring_id = HAL_SRNG_WBM_SW_RELEASE, 1661 .max_rings = 1, 1662 .entry_size = sizeof(struct wbm_release_ring) >> 2, 1663 .lmac_ring = FALSE, 1664 .ring_dir = HAL_SRNG_SRC_RING, 1665 .reg_start = { 1666 HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1667 HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1668 }, 1669 /* Single ring - provide ring size if multiple rings of this 1670 * type are supported 1671 */ 1672 .reg_size = {}, 1673 .max_size = 1674 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> 1675 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, 1676 }, 1677 { /* WBM2SW_RELEASE */ 1678 .start_ring_id = HAL_SRNG_WBM2SW0_RELEASE, 1679 .max_rings = 4, 1680 .entry_size = sizeof(struct wbm_release_ring) >> 2, 1681 .lmac_ring = FALSE, 1682 .ring_dir = HAL_SRNG_DST_RING, 1683 .reg_start = { 1684 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1685 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1686 }, 1687 .reg_size = { 1688 HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) - 1689 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1690 HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) - 1691 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1692 }, 1693 .max_size = 1694 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> 1695 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, 1696 }, 1697 { /* RXDMA_BUF */ 1698 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA0_BUF0, 1699 #ifdef IPA_OFFLOAD 1700 .max_rings = 3, 1701 #else 1702 .max_rings = 2, 1703 #endif 1704 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 1705 .lmac_ring = TRUE, 1706 .ring_dir = HAL_SRNG_SRC_RING, 1707 /* reg_start is not set because LMAC rings are not accessed 1708 * from host 1709 */ 1710 .reg_start = {}, 1711 .reg_size = {}, 1712 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1713 }, 1714 { /* RXDMA_DST */ 1715 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW0, 1716 .max_rings = 1, 1717 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 1718 .lmac_ring = TRUE, 1719 .ring_dir = HAL_SRNG_DST_RING, 1720 /* reg_start is not set because LMAC rings are not accessed 1721 * from host 1722 */ 1723 .reg_start = {}, 1724 .reg_size = {}, 1725 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1726 }, 1727 { /* RXDMA_MONITOR_BUF */ 1728 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA2_BUF, 1729 .max_rings = 1, 1730 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 1731 .lmac_ring = TRUE, 1732 .ring_dir = HAL_SRNG_SRC_RING, 1733 /* reg_start is not set because LMAC rings are not accessed 1734 * from host 1735 */ 1736 .reg_start = {}, 1737 .reg_size = {}, 1738 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1739 }, 1740 { /* RXDMA_MONITOR_STATUS */ 1741 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_STATBUF, 1742 .max_rings = 1, 1743 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 1744 .lmac_ring = TRUE, 1745 .ring_dir = HAL_SRNG_SRC_RING, 1746 /* reg_start is not set because LMAC rings are not accessed 1747 * from host 1748 */ 1749 .reg_start = {}, 1750 .reg_size = {}, 1751 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1752 }, 1753 { /* RXDMA_MONITOR_DST */ 1754 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW1, 1755 .max_rings = 1, 1756 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 1757 .lmac_ring = TRUE, 1758 .ring_dir = HAL_SRNG_DST_RING, 1759 /* reg_start is not set because LMAC rings are not accessed 1760 * from host 1761 */ 1762 .reg_start = {}, 1763 .reg_size = {}, 1764 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1765 }, 1766 { /* RXDMA_MONITOR_DESC */ 1767 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_DESC, 1768 .max_rings = 1, 1769 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 1770 .lmac_ring = TRUE, 1771 .ring_dir = HAL_SRNG_SRC_RING, 1772 /* reg_start is not set because LMAC rings are not accessed 1773 * from host 1774 */ 1775 .reg_start = {}, 1776 .reg_size = {}, 1777 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1778 }, 1779 { /* DIR_BUF_RX_DMA_SRC */ 1780 .start_ring_id = HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING, 1781 /* one ring for spectral and one ring for cfr */ 1782 .max_rings = 2, 1783 .entry_size = 2, 1784 .lmac_ring = TRUE, 1785 .ring_dir = HAL_SRNG_SRC_RING, 1786 /* reg_start is not set because LMAC rings are not accessed 1787 * from host 1788 */ 1789 .reg_start = {}, 1790 .reg_size = {}, 1791 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1792 }, 1793 #ifdef WLAN_FEATURE_CIF_CFR 1794 { /* WIFI_POS_SRC */ 1795 .start_ring_id = HAL_SRNG_WIFI_POS_SRC_DMA_RING, 1796 .max_rings = 1, 1797 .entry_size = sizeof(wmi_oem_dma_buf_release_entry) >> 2, 1798 .lmac_ring = TRUE, 1799 .ring_dir = HAL_SRNG_SRC_RING, 1800 /* reg_start is not set because LMAC rings are not accessed 1801 * from host 1802 */ 1803 .reg_start = {}, 1804 .reg_size = {}, 1805 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1806 }, 1807 #endif 1808 { /* REO2PPE */ 0}, 1809 { /* PPE2TCL */ 0}, 1810 { /* PPE_RELEASE */ 0}, 1811 { /* TX_MONITOR_BUF */ 0}, 1812 { /* TX_MONITOR_DST */ 0}, 1813 { /* SW2RXDMA_NEW */ 0}, 1814 }; 1815 1816 1817 /** 1818 * hal_qca8074v2_attach() - Attach 8074v2 target specific hal_soc ops, 1819 * offset and srng table 1820 */ 1821 void hal_qca8074v2_attach(struct hal_soc *hal_soc) 1822 { 1823 hal_soc->hw_srng_table = hw_srng_table_8074v2; 1824 hal_srng_hw_reg_offset_init_generic(hal_soc); 1825 hal_hw_txrx_default_ops_attach_li(hal_soc); 1826 hal_hw_txrx_ops_attach_qca8074v2(hal_soc); 1827 } 1828