1 /* 2 * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved. 3 * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 #include "hal_li_hw_headers.h" 20 #include "hal_internal.h" 21 #include "hal_api.h" 22 #include "target_type.h" 23 #include "wcss_version.h" 24 #include "qdf_module.h" 25 #include "hal_flow.h" 26 #include "rx_flow_search_entry.h" 27 #include "hal_rx_flow_info.h" 28 29 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_OFFSET \ 30 RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_OFFSET 31 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_MASK \ 32 RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_MASK 33 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_LSB \ 34 RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_LSB 35 #define UNIFIED_RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_OFFSET \ 36 RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_OFFSET 37 #define UNIFIED_RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_MASK \ 38 RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_MASK 39 #define UNIFIED_RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_LSB \ 40 RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_LSB 41 #define UNIFIED_PHYRX_HT_SIG_0_HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS_OFFSET \ 42 PHYRX_HT_SIG_0_PHYRX_HT_SIG_INFO_DETAILS_MCS_OFFSET 43 #define UNIFIED_PHYRX_L_SIG_B_0_L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS_OFFSET \ 44 PHYRX_L_SIG_B_0_PHYRX_L_SIG_B_INFO_DETAILS_RATE_OFFSET 45 #define UNIFIED_PHYRX_L_SIG_A_0_L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS_OFFSET \ 46 PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_RATE_OFFSET 47 #define UNIFIED_PHYRX_VHT_SIG_A_0_VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS_OFFSET \ 48 PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_OFFSET 49 #define UNIFIED_PHYRX_HE_SIG_A_SU_0_HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS_OFFSET \ 50 PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_OFFSET 51 #define UNIFIED_PHYRX_HE_SIG_A_MU_DL_0_HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_OFFSET \ 52 PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_OFFSET 53 #define UNIFIED_PHYRX_HE_SIG_B1_MU_0_HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_OFFSET \ 54 PHYRX_HE_SIG_B1_MU_0_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_OFFSET 55 #define UNIFIED_PHYRX_HE_SIG_B2_MU_0_HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_OFFSET \ 56 PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_OFFSET 57 #define UNIFIED_PHYRX_HE_SIG_B2_OFDMA_0_HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_OFFSET \ 58 PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_OFFSET 59 #define UNIFIED_PHYRX_RSSI_LEGACY_3_RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS_OFFSET \ 60 PHYRX_RSSI_LEGACY_3_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 61 #define UNIFIED_PHYRX_RSSI_LEGACY_19_RECEIVE_RSSI_INFO_PREAMBLE_RSSI_INFO_DETAILS_OFFSET \ 62 PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 63 #define UNIFIED_RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET \ 64 RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 65 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 66 RX_MSDU_LINK_8_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 67 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ 68 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 69 #define UNIFIED_RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 70 RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 71 #define UNIFIED_REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 72 REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 73 #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER \ 74 STATUS_HEADER_REO_STATUS_NUMBER 75 #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC \ 76 STATUS_HEADER_TIMESTAMP 77 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ 78 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 79 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 80 RX_MSDU_LINK_8_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 81 #define UNIFIED_TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 82 TCL_DATA_CMD_0_BUF_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 83 #define UNIFIED_TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 84 TCL_DATA_CMD_1_BUF_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 85 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET \ 86 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET 87 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB \ 88 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB 89 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK \ 90 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK 91 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB \ 92 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB 93 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK \ 94 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK 95 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB \ 96 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB 97 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK \ 98 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK 99 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB \ 100 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB 101 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK \ 102 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK 103 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB \ 104 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB 105 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK \ 106 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK 107 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_MASK \ 108 WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MASK 109 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_OFFSET \ 110 WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_OFFSET 111 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_LSB \ 112 WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_LSB 113 114 #include "hal_8074v2_tx.h" 115 #include "hal_8074v2_rx.h" 116 #include <hal_generic_api.h> 117 #include "hal_li_rx.h" 118 #include "hal_li_api.h" 119 #include "hal_li_generic_api.h" 120 121 /** 122 * hal_rx_get_rx_fragment_number_8074v2(): Function to retrieve 123 * rx fragment number 124 * 125 * @nbuf: Network buffer 126 * Returns: rx fragment number 127 */ 128 static 129 uint8_t hal_rx_get_rx_fragment_number_8074v2(uint8_t *buf) 130 { 131 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 132 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 133 134 /* Return first 4 bits as fragment number */ 135 return HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info) & 136 DOT11_SEQ_FRAG_MASK; 137 } 138 139 /** 140 * hal_rx_msdu_end_da_is_mcbc_get_8074v2: API to check if pkt is MCBC 141 * from rx_msdu_end TLV 142 * 143 * @ buf: pointer to the start of RX PKT TLV headers 144 * Return: da_is_mcbc 145 */ 146 static uint8_t 147 hal_rx_msdu_end_da_is_mcbc_get_8074v2(uint8_t *buf) 148 { 149 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 150 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 151 152 return HAL_RX_MSDU_END_DA_IS_MCBC_GET(msdu_end); 153 } 154 155 /** 156 * hal_rx_msdu_end_sa_is_valid_get_8074v2(): API to get_8074v2 the 157 * sa_is_valid bit from rx_msdu_end TLV 158 * 159 * @ buf: pointer to the start of RX PKT TLV headers 160 * Return: sa_is_valid bit 161 */ 162 static uint8_t 163 hal_rx_msdu_end_sa_is_valid_get_8074v2(uint8_t *buf) 164 { 165 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 166 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 167 uint8_t sa_is_valid; 168 169 sa_is_valid = HAL_RX_MSDU_END_SA_IS_VALID_GET(msdu_end); 170 171 return sa_is_valid; 172 } 173 174 /** 175 * hal_rx_msdu_end_sa_idx_get_8074v2(): API to get_8074v2 the 176 * sa_idx from rx_msdu_end TLV 177 * 178 * @ buf: pointer to the start of RX PKT TLV headers 179 * Return: sa_idx (SA AST index) 180 */ 181 static uint16_t hal_rx_msdu_end_sa_idx_get_8074v2(uint8_t *buf) 182 { 183 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 184 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 185 uint16_t sa_idx; 186 187 sa_idx = HAL_RX_MSDU_END_SA_IDX_GET(msdu_end); 188 189 return sa_idx; 190 } 191 192 /** 193 * hal_rx_desc_is_first_msdu_8074v2() - Check if first msdu 194 * 195 * @hal_soc_hdl: hal_soc handle 196 * @hw_desc_addr: hardware descriptor address 197 * 198 * Return: 0 - success/ non-zero failure 199 */ 200 static uint32_t hal_rx_desc_is_first_msdu_8074v2(void *hw_desc_addr) 201 { 202 struct rx_pkt_tlvs *rx_tlvs = (struct rx_pkt_tlvs *)hw_desc_addr; 203 struct rx_msdu_end *msdu_end = &rx_tlvs->msdu_end_tlv.rx_msdu_end; 204 205 return HAL_RX_GET(msdu_end, RX_MSDU_END_5, FIRST_MSDU); 206 } 207 208 /** 209 * hal_rx_msdu_end_l3_hdr_padding_get_8074v2(): API to get_8074v2 the 210 * l3_header padding from rx_msdu_end TLV 211 * 212 * @ buf: pointer to the start of RX PKT TLV headers 213 * Return: number of l3 header padding bytes 214 */ 215 static uint32_t hal_rx_msdu_end_l3_hdr_padding_get_8074v2(uint8_t *buf) 216 { 217 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 218 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 219 uint32_t l3_header_padding; 220 221 l3_header_padding = HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(msdu_end); 222 223 return l3_header_padding; 224 } 225 226 /* 227 * @ hal_rx_encryption_info_valid_8074v2: Returns encryption type. 228 * 229 * @ buf: rx_tlv_hdr of the received packet 230 * @ Return: encryption type 231 */ 232 static uint32_t hal_rx_encryption_info_valid_8074v2(uint8_t *buf) 233 { 234 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 235 struct rx_mpdu_start *mpdu_start = 236 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 237 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 238 uint32_t encryption_info = HAL_RX_MPDU_ENCRYPTION_INFO_VALID(mpdu_info); 239 240 return encryption_info; 241 } 242 243 /* 244 * @ hal_rx_print_pn_8074v2: Prints the PN of rx packet. 245 * 246 * @ buf: rx_tlv_hdr of the received packet 247 * @ Return: void 248 */ 249 static void hal_rx_print_pn_8074v2(uint8_t *buf) 250 { 251 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 252 struct rx_mpdu_start *mpdu_start = 253 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 254 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 255 256 uint32_t pn_31_0 = HAL_RX_MPDU_PN_31_0_GET(mpdu_info); 257 uint32_t pn_63_32 = HAL_RX_MPDU_PN_63_32_GET(mpdu_info); 258 uint32_t pn_95_64 = HAL_RX_MPDU_PN_95_64_GET(mpdu_info); 259 uint32_t pn_127_96 = HAL_RX_MPDU_PN_127_96_GET(mpdu_info); 260 261 hal_debug("PN number pn_127_96 0x%x pn_95_64 0x%x pn_63_32 0x%x pn_31_0 0x%x ", 262 pn_127_96, pn_95_64, pn_63_32, pn_31_0); 263 } 264 265 /** 266 * hal_rx_msdu_end_first_msdu_get_8074v2: API to get first msdu status 267 * from rx_msdu_end TLV 268 * 269 * @ buf: pointer to the start of RX PKT TLV headers 270 * Return: first_msdu 271 */ 272 static uint8_t hal_rx_msdu_end_first_msdu_get_8074v2(uint8_t *buf) 273 { 274 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 275 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 276 uint8_t first_msdu; 277 278 first_msdu = HAL_RX_MSDU_END_FIRST_MSDU_GET(msdu_end); 279 280 return first_msdu; 281 } 282 283 /** 284 * hal_rx_msdu_end_da_is_valid_get_8074v2: API to check if da is valid 285 * from rx_msdu_end TLV 286 * 287 * @ buf: pointer to the start of RX PKT TLV headers 288 * Return: da_is_valid 289 */ 290 static uint8_t hal_rx_msdu_end_da_is_valid_get_8074v2(uint8_t *buf) 291 { 292 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 293 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 294 uint8_t da_is_valid; 295 296 da_is_valid = HAL_RX_MSDU_END_DA_IS_VALID_GET(msdu_end); 297 298 return da_is_valid; 299 } 300 301 /** 302 * hal_rx_msdu_end_last_msdu_get_8074v2: API to get last msdu status 303 * from rx_msdu_end TLV 304 * 305 * @ buf: pointer to the start of RX PKT TLV headers 306 * Return: last_msdu 307 */ 308 static uint8_t hal_rx_msdu_end_last_msdu_get_8074v2(uint8_t *buf) 309 { 310 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 311 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 312 uint8_t last_msdu; 313 314 last_msdu = HAL_RX_MSDU_END_LAST_MSDU_GET(msdu_end); 315 316 return last_msdu; 317 } 318 319 /* 320 * hal_rx_get_mpdu_mac_ad4_valid_8074v2(): Retrieves if mpdu 4th addr is valid 321 * 322 * @nbuf: Network buffer 323 * Returns: value of mpdu 4th address valid field 324 */ 325 static bool hal_rx_get_mpdu_mac_ad4_valid_8074v2(uint8_t *buf) 326 { 327 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 328 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 329 bool ad4_valid = 0; 330 331 ad4_valid = HAL_RX_MPDU_GET_MAC_AD4_VALID(rx_mpdu_info); 332 333 return ad4_valid; 334 } 335 336 /** 337 * hal_rx_mpdu_start_sw_peer_id_get_8074v2: Retrieve sw peer_id 338 * @buf: network buffer 339 * 340 * Return: sw peer_id 341 */ 342 static uint32_t hal_rx_mpdu_start_sw_peer_id_get_8074v2(uint8_t *buf) 343 { 344 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 345 struct rx_mpdu_start *mpdu_start = 346 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 347 348 return HAL_RX_MPDU_INFO_SW_PEER_ID_GET( 349 &mpdu_start->rx_mpdu_info_details); 350 } 351 352 /* 353 * hal_rx_mpdu_get_to_ds_8074v2(): API to get the tods info 354 * from rx_mpdu_start 355 * 356 * @buf: pointer to the start of RX PKT TLV header 357 * Return: uint32_t(to_ds) 358 */ 359 static uint32_t hal_rx_mpdu_get_to_ds_8074v2(uint8_t *buf) 360 { 361 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 362 struct rx_mpdu_start *mpdu_start = 363 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 364 365 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 366 367 return HAL_RX_MPDU_GET_TODS(mpdu_info); 368 } 369 370 /* 371 * hal_rx_mpdu_get_fr_ds_8074v2(): API to get the from ds info 372 * from rx_mpdu_start 373 * 374 * @buf: pointer to the start of RX PKT TLV header 375 * Return: uint32_t(fr_ds) 376 */ 377 static uint32_t hal_rx_mpdu_get_fr_ds_8074v2(uint8_t *buf) 378 { 379 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 380 struct rx_mpdu_start *mpdu_start = 381 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 382 383 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 384 385 return HAL_RX_MPDU_GET_FROMDS(mpdu_info); 386 } 387 388 /* 389 * hal_rx_get_mpdu_frame_control_valid_8074v2(): Retrieves mpdu 390 * frame control valid 391 * 392 * @nbuf: Network buffer 393 * Returns: value of frame control valid field 394 */ 395 static uint8_t hal_rx_get_mpdu_frame_control_valid_8074v2(uint8_t *buf) 396 { 397 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 398 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 399 400 return HAL_RX_MPDU_GET_FRAME_CONTROL_VALID(rx_mpdu_info); 401 } 402 403 /* 404 * hal_rx_mpdu_get_addr1_8074v2(): API to check get address1 of the mpdu 405 * 406 * @buf: pointer to the start of RX PKT TLV headera 407 * @mac_addr: pointer to mac address 408 * Return: success/failure 409 */ 410 static QDF_STATUS hal_rx_mpdu_get_addr1_8074v2(uint8_t *buf, uint8_t *mac_addr) 411 { 412 struct __attribute__((__packed__)) hal_addr1 { 413 uint32_t ad1_31_0; 414 uint16_t ad1_47_32; 415 }; 416 417 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 418 struct rx_mpdu_start *mpdu_start = 419 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 420 421 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 422 struct hal_addr1 *addr = (struct hal_addr1 *)mac_addr; 423 uint32_t mac_addr_ad1_valid; 424 425 mac_addr_ad1_valid = HAL_RX_MPDU_MAC_ADDR_AD1_VALID_GET(mpdu_info); 426 427 if (mac_addr_ad1_valid) { 428 addr->ad1_31_0 = HAL_RX_MPDU_AD1_31_0_GET(mpdu_info); 429 addr->ad1_47_32 = HAL_RX_MPDU_AD1_47_32_GET(mpdu_info); 430 return QDF_STATUS_SUCCESS; 431 } 432 433 return QDF_STATUS_E_FAILURE; 434 } 435 436 /* 437 * hal_rx_mpdu_get_addr2_8074v2(): API to check get address2 of the mpdu 438 * in the packet 439 * 440 * @buf: pointer to the start of RX PKT TLV header 441 * @mac_addr: pointer to mac address 442 * Return: success/failure 443 */ 444 static QDF_STATUS hal_rx_mpdu_get_addr2_8074v2(uint8_t *buf, uint8_t *mac_addr) 445 { 446 struct __attribute__((__packed__)) hal_addr2 { 447 uint16_t ad2_15_0; 448 uint32_t ad2_47_16; 449 }; 450 451 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 452 struct rx_mpdu_start *mpdu_start = 453 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 454 455 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 456 struct hal_addr2 *addr = (struct hal_addr2 *)mac_addr; 457 uint32_t mac_addr_ad2_valid; 458 459 mac_addr_ad2_valid = HAL_RX_MPDU_MAC_ADDR_AD2_VALID_GET(mpdu_info); 460 461 if (mac_addr_ad2_valid) { 462 addr->ad2_15_0 = HAL_RX_MPDU_AD2_15_0_GET(mpdu_info); 463 addr->ad2_47_16 = HAL_RX_MPDU_AD2_47_16_GET(mpdu_info); 464 return QDF_STATUS_SUCCESS; 465 } 466 467 return QDF_STATUS_E_FAILURE; 468 } 469 470 /* 471 * hal_rx_mpdu_get_addr3_8074v2(): API to get address3 of the mpdu 472 * in the packet 473 * 474 * @buf: pointer to the start of RX PKT TLV header 475 * @mac_addr: pointer to mac address 476 * Return: success/failure 477 */ 478 static QDF_STATUS hal_rx_mpdu_get_addr3_8074v2(uint8_t *buf, uint8_t *mac_addr) 479 { 480 struct __attribute__((__packed__)) hal_addr3 { 481 uint32_t ad3_31_0; 482 uint16_t ad3_47_32; 483 }; 484 485 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 486 struct rx_mpdu_start *mpdu_start = 487 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 488 489 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 490 struct hal_addr3 *addr = (struct hal_addr3 *)mac_addr; 491 uint32_t mac_addr_ad3_valid; 492 493 mac_addr_ad3_valid = HAL_RX_MPDU_MAC_ADDR_AD3_VALID_GET(mpdu_info); 494 495 if (mac_addr_ad3_valid) { 496 addr->ad3_31_0 = HAL_RX_MPDU_AD3_31_0_GET(mpdu_info); 497 addr->ad3_47_32 = HAL_RX_MPDU_AD3_47_32_GET(mpdu_info); 498 return QDF_STATUS_SUCCESS; 499 } 500 501 return QDF_STATUS_E_FAILURE; 502 } 503 504 /* 505 * hal_rx_mpdu_get_addr4_8074v2(): API to get address4 of the mpdu 506 * in the packet 507 * 508 * @buf: pointer to the start of RX PKT TLV header 509 * @mac_addr: pointer to mac address 510 * Return: success/failure 511 */ 512 static QDF_STATUS hal_rx_mpdu_get_addr4_8074v2(uint8_t *buf, uint8_t *mac_addr) 513 { 514 struct __attribute__((__packed__)) hal_addr4 { 515 uint32_t ad4_31_0; 516 uint16_t ad4_47_32; 517 }; 518 519 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 520 struct rx_mpdu_start *mpdu_start = 521 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 522 523 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 524 struct hal_addr4 *addr = (struct hal_addr4 *)mac_addr; 525 uint32_t mac_addr_ad4_valid; 526 527 mac_addr_ad4_valid = HAL_RX_MPDU_MAC_ADDR_AD4_VALID_GET(mpdu_info); 528 529 if (mac_addr_ad4_valid) { 530 addr->ad4_31_0 = HAL_RX_MPDU_AD4_31_0_GET(mpdu_info); 531 addr->ad4_47_32 = HAL_RX_MPDU_AD4_47_32_GET(mpdu_info); 532 return QDF_STATUS_SUCCESS; 533 } 534 535 return QDF_STATUS_E_FAILURE; 536 } 537 538 /* 539 * hal_rx_get_mpdu_sequence_control_valid_8074v2(): Get mpdu 540 * sequence control valid 541 * 542 * @nbuf: Network buffer 543 * Returns: value of sequence control valid field 544 */ 545 static uint8_t hal_rx_get_mpdu_sequence_control_valid_8074v2(uint8_t *buf) 546 { 547 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 548 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 549 550 return HAL_RX_MPDU_GET_SEQUENCE_CONTROL_VALID(rx_mpdu_info); 551 } 552 553 /** 554 * hal_rx_is_unicast_8074v2: check packet is unicast frame or not. 555 * 556 * @ buf: pointer to rx pkt TLV. 557 * 558 * Return: true on unicast. 559 */ 560 static bool hal_rx_is_unicast_8074v2(uint8_t *buf) 561 { 562 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 563 struct rx_mpdu_start *mpdu_start = 564 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 565 uint32_t grp_id; 566 uint8_t *rx_mpdu_info = (uint8_t *)&mpdu_start->rx_mpdu_info_details; 567 568 grp_id = (_HAL_MS((*_OFFSET_TO_WORD_PTR((rx_mpdu_info), 569 RX_MPDU_INFO_0_SW_FRAME_GROUP_ID_OFFSET)), 570 RX_MPDU_INFO_0_SW_FRAME_GROUP_ID_MASK, 571 RX_MPDU_INFO_0_SW_FRAME_GROUP_ID_LSB)); 572 573 return (HAL_MPDU_SW_FRAME_GROUP_UNICAST_DATA == grp_id) ? true : false; 574 } 575 576 /** 577 * hal_rx_tid_get_8074v2: get tid based on qos control valid. 578 * @hal_soc_hdl: hal soc handle 579 * @buf: pointer to rx pkt TLV. 580 * 581 * Return: tid 582 */ 583 static uint32_t hal_rx_tid_get_8074v2(hal_soc_handle_t hal_soc_hdl, 584 uint8_t *buf) 585 { 586 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 587 struct rx_mpdu_start *mpdu_start = 588 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 589 uint8_t *rx_mpdu_info = (uint8_t *)&mpdu_start->rx_mpdu_info_details; 590 uint8_t qos_control_valid = 591 (_HAL_MS((*_OFFSET_TO_WORD_PTR((rx_mpdu_info), 592 RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_OFFSET)), 593 RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_MASK, 594 RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_LSB)); 595 596 if (qos_control_valid) 597 return hal_rx_mpdu_start_tid_get_8074v2(buf); 598 599 return HAL_RX_NON_QOS_TID; 600 } 601 602 /** 603 * hal_rx_hw_desc_get_ppduid_get_8074v2(): retrieve ppdu id 604 * @rx_tlv_hdr: packtet rx tlv header 605 * @rxdma_dst_ring_desc: rxdma HW descriptor 606 * 607 * Return: ppdu id 608 */ 609 static uint32_t hal_rx_hw_desc_get_ppduid_get_8074v2(void *rx_tlv_hdr, 610 void *rxdma_dst_ring_desc) 611 { 612 struct rx_mpdu_info *rx_mpdu_info; 613 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)rx_tlv_hdr; 614 615 rx_mpdu_info = 616 &rx_desc->mpdu_start_tlv.rx_mpdu_start.rx_mpdu_info_details; 617 618 return HAL_RX_GET(rx_mpdu_info, RX_MPDU_INFO_0, PHY_PPDU_ID); 619 } 620 621 /** 622 * hal_reo_status_get_header_8074v2 - Process reo desc info 623 * @ring_desc: REO status ring descriptor 624 * @b - tlv type info 625 * @h1 - Pointer to hal_reo_status_header where info to be stored 626 * 627 * Return - none. 628 * 629 */ 630 static void hal_reo_status_get_header_8074v2(hal_ring_desc_t ring_desc, int b, 631 void *h1) 632 { 633 uint32_t *d = (uint32_t *)ring_desc; 634 uint32_t val1 = 0; 635 struct hal_reo_status_header *h = 636 (struct hal_reo_status_header *)h1; 637 638 /* Offsets of descriptor fields defined in HW headers start 639 * from the field after TLV header 640 */ 641 d += HAL_GET_NUM_DWORDS(sizeof(struct tlv_32_hdr)); 642 643 switch (b) { 644 case HAL_REO_QUEUE_STATS_STATUS_TLV: 645 val1 = d[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_0, 646 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 647 break; 648 case HAL_REO_FLUSH_QUEUE_STATUS_TLV: 649 val1 = d[HAL_OFFSET_DW(REO_FLUSH_QUEUE_STATUS_0, 650 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 651 break; 652 case HAL_REO_FLUSH_CACHE_STATUS_TLV: 653 val1 = d[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_0, 654 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 655 break; 656 case HAL_REO_UNBLK_CACHE_STATUS_TLV: 657 val1 = d[HAL_OFFSET_DW(REO_UNBLOCK_CACHE_STATUS_0, 658 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 659 break; 660 case HAL_REO_TIMOUT_LIST_STATUS_TLV: 661 val1 = d[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_0, 662 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 663 break; 664 case HAL_REO_DESC_THRES_STATUS_TLV: 665 val1 = 666 d[HAL_OFFSET_DW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0, 667 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 668 break; 669 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: 670 val1 = d[HAL_OFFSET_DW(REO_UPDATE_RX_REO_QUEUE_STATUS_0, 671 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 672 break; 673 default: 674 qdf_nofl_err("ERROR: Unknown tlv\n"); 675 break; 676 } 677 h->cmd_num = 678 HAL_GET_FIELD( 679 UNIFORM_REO_STATUS_HEADER_0, REO_STATUS_NUMBER, 680 val1); 681 h->exec_time = 682 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_0, 683 CMD_EXECUTION_TIME, val1); 684 h->status = 685 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_0, 686 REO_CMD_EXECUTION_STATUS, val1); 687 switch (b) { 688 case HAL_REO_QUEUE_STATS_STATUS_TLV: 689 val1 = d[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_1, 690 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 691 break; 692 case HAL_REO_FLUSH_QUEUE_STATUS_TLV: 693 val1 = d[HAL_OFFSET_DW(REO_FLUSH_QUEUE_STATUS_1, 694 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 695 break; 696 case HAL_REO_FLUSH_CACHE_STATUS_TLV: 697 val1 = d[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_1, 698 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 699 break; 700 case HAL_REO_UNBLK_CACHE_STATUS_TLV: 701 val1 = d[HAL_OFFSET_DW(REO_UNBLOCK_CACHE_STATUS_1, 702 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 703 break; 704 case HAL_REO_TIMOUT_LIST_STATUS_TLV: 705 val1 = d[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_1, 706 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 707 break; 708 case HAL_REO_DESC_THRES_STATUS_TLV: 709 val1 = 710 d[HAL_OFFSET_DW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_1, 711 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 712 break; 713 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: 714 val1 = d[HAL_OFFSET_DW(REO_UPDATE_RX_REO_QUEUE_STATUS_1, 715 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 716 break; 717 default: 718 qdf_nofl_err("ERROR: Unknown tlv\n"); 719 break; 720 } 721 h->tstamp = 722 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_1, TIMESTAMP, val1); 723 } 724 725 /** 726 * hal_rx_mpdu_start_mpdu_qos_control_valid_get_8074v2(): 727 * Retrieve qos control valid bit from the tlv. 728 * @buf: pointer to rx pkt TLV. 729 * 730 * Return: qos control value. 731 */ 732 static inline uint32_t 733 hal_rx_mpdu_start_mpdu_qos_control_valid_get_8074v2(uint8_t *buf) 734 { 735 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 736 struct rx_mpdu_start *mpdu_start = 737 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 738 739 return HAL_RX_MPDU_INFO_QOS_CONTROL_VALID_GET( 740 &mpdu_start->rx_mpdu_info_details); 741 } 742 743 /** 744 * hal_rx_msdu_end_sa_sw_peer_id_get_8074v2(): API to get the 745 * sa_sw_peer_id from rx_msdu_end TLV 746 * @buf: pointer to the start of RX PKT TLV headers 747 * 748 * Return: sa_sw_peer_id index 749 */ 750 static inline uint32_t 751 hal_rx_msdu_end_sa_sw_peer_id_get_8074v2(uint8_t *buf) 752 { 753 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 754 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 755 756 return HAL_RX_MSDU_END_SA_SW_PEER_ID_GET(msdu_end); 757 } 758 759 /** 760 * hal_tx_desc_set_mesh_en_8074v2 - Set mesh_enable flag in Tx descriptor 761 * @desc: Handle to Tx Descriptor 762 * @en: For raw WiFi frames, this indicates transmission to a mesh STA, 763 * enabling the interpretation of the 'Mesh Control Present' bit 764 * (bit 8) of QoS Control (otherwise this bit is ignored), 765 * For native WiFi frames, this indicates that a 'Mesh Control' field 766 * is present between the header and the LLC. 767 * 768 * Return: void 769 */ 770 static inline 771 void hal_tx_desc_set_mesh_en_8074v2(void *desc, uint8_t en) 772 { 773 HAL_SET_FLD(desc, TCL_DATA_CMD_4, MESH_ENABLE) |= 774 HAL_TX_SM(TCL_DATA_CMD_4, MESH_ENABLE, en); 775 } 776 777 static 778 void *hal_rx_msdu0_buffer_addr_lsb_8074v2(void *link_desc_va) 779 { 780 return (void *)HAL_RX_MSDU0_BUFFER_ADDR_LSB(link_desc_va); 781 } 782 783 static 784 void *hal_rx_msdu_desc_info_ptr_get_8074v2(void *msdu0) 785 { 786 return (void *)HAL_RX_MSDU_DESC_INFO_PTR_GET(msdu0); 787 } 788 789 static 790 void *hal_ent_mpdu_desc_info_8074v2(void *ent_ring_desc) 791 { 792 return (void *)HAL_ENT_MPDU_DESC_INFO(ent_ring_desc); 793 } 794 795 static 796 void *hal_dst_mpdu_desc_info_8074v2(void *dst_ring_desc) 797 { 798 return (void *)HAL_DST_MPDU_DESC_INFO(dst_ring_desc); 799 } 800 801 static 802 uint8_t hal_rx_get_fc_valid_8074v2(uint8_t *buf) 803 { 804 return HAL_RX_GET_FC_VALID(buf); 805 } 806 807 static uint8_t hal_rx_get_to_ds_flag_8074v2(uint8_t *buf) 808 { 809 return HAL_RX_GET_TO_DS_FLAG(buf); 810 } 811 812 static uint8_t hal_rx_get_mac_addr2_valid_8074v2(uint8_t *buf) 813 { 814 return HAL_RX_GET_MAC_ADDR2_VALID(buf); 815 } 816 817 static uint8_t hal_rx_get_filter_category_8074v2(uint8_t *buf) 818 { 819 return HAL_RX_GET_FILTER_CATEGORY(buf); 820 } 821 822 static uint32_t 823 hal_rx_get_ppdu_id_8074v2(uint8_t *buf) 824 { 825 struct rx_mpdu_info *rx_mpdu_info; 826 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)buf; 827 828 rx_mpdu_info = 829 &rx_desc->mpdu_start_tlv.rx_mpdu_start.rx_mpdu_info_details; 830 831 return HAL_RX_GET_PPDU_ID(rx_mpdu_info); 832 } 833 834 /** 835 * hal_reo_config_8074v2(): Set reo config parameters 836 * @soc: hal soc handle 837 * @reg_val: value to be set 838 * @reo_params: reo parameters 839 * 840 * Return: void 841 */ 842 static void 843 hal_reo_config_8074v2(struct hal_soc *soc, 844 uint32_t reg_val, 845 struct hal_reo_params *reo_params) 846 { 847 HAL_REO_R0_CONFIG(soc, reg_val, reo_params); 848 } 849 850 /** 851 * hal_rx_msdu_desc_info_get_ptr_8074v2() - Get msdu desc info ptr 852 * @msdu_details_ptr - Pointer to msdu_details_ptr 853 * 854 * Return - Pointer to rx_msdu_desc_info structure. 855 * 856 */ 857 static void *hal_rx_msdu_desc_info_get_ptr_8074v2(void *msdu_details_ptr) 858 { 859 return HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr); 860 } 861 862 /** 863 * hal_rx_link_desc_msdu0_ptr_8074v2 - Get pointer to rx_msdu details 864 * @link_desc - Pointer to link desc 865 * 866 * Return - Pointer to rx_msdu_details structure 867 * 868 */ 869 static void *hal_rx_link_desc_msdu0_ptr_8074v2(void *link_desc) 870 { 871 return HAL_RX_LINK_DESC_MSDU0_PTR(link_desc); 872 } 873 874 /** 875 * hal_rx_msdu_flow_idx_get_8074v2: API to get flow index 876 * from rx_msdu_end TLV 877 * @buf: pointer to the start of RX PKT TLV headers 878 * 879 * Return: flow index value from MSDU END TLV 880 */ 881 static inline uint32_t hal_rx_msdu_flow_idx_get_8074v2(uint8_t *buf) 882 { 883 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 884 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 885 886 return HAL_RX_MSDU_END_FLOW_IDX_GET(msdu_end); 887 } 888 889 /** 890 * hal_rx_msdu_flow_idx_invalid_8074v2: API to get flow index invalid 891 * from rx_msdu_end TLV 892 * @buf: pointer to the start of RX PKT TLV headers 893 * 894 * Return: flow index invalid value from MSDU END TLV 895 */ 896 static bool hal_rx_msdu_flow_idx_invalid_8074v2(uint8_t *buf) 897 { 898 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 899 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 900 901 return HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(msdu_end); 902 } 903 904 /** 905 * hal_rx_msdu_flow_idx_timeout_8074v2: API to get flow index timeout 906 * from rx_msdu_end TLV 907 * @buf: pointer to the start of RX PKT TLV headers 908 * 909 * Return: flow index timeout value from MSDU END TLV 910 */ 911 static bool hal_rx_msdu_flow_idx_timeout_8074v2(uint8_t *buf) 912 { 913 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 914 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 915 916 return HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(msdu_end); 917 } 918 919 /** 920 * hal_rx_msdu_fse_metadata_get_8074v2: API to get FSE metadata 921 * from rx_msdu_end TLV 922 * @buf: pointer to the start of RX PKT TLV headers 923 * 924 * Return: fse metadata value from MSDU END TLV 925 */ 926 static uint32_t hal_rx_msdu_fse_metadata_get_8074v2(uint8_t *buf) 927 { 928 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 929 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 930 931 return HAL_RX_MSDU_END_FSE_METADATA_GET(msdu_end); 932 } 933 934 /** 935 * hal_rx_msdu_cce_metadata_get_8074v2: API to get CCE metadata 936 * from rx_msdu_end TLV 937 * @buf: pointer to the start of RX PKT TLV headers 938 * 939 * Return: cce_metadata 940 */ 941 static uint16_t 942 hal_rx_msdu_cce_metadata_get_8074v2(uint8_t *buf) 943 { 944 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 945 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 946 947 return HAL_RX_MSDU_END_CCE_METADATA_GET(msdu_end); 948 } 949 950 /** 951 * hal_rx_msdu_get_flow_params_8074v2: API to get flow index, flow index invalid 952 * and flow index timeout from rx_msdu_end TLV 953 * @buf: pointer to the start of RX PKT TLV headers 954 * @flow_invalid: pointer to return value of flow_idx_valid 955 * @flow_timeout: pointer to return value of flow_idx_timeout 956 * @flow_index: pointer to return value of flow_idx 957 * 958 * Return: none 959 */ 960 static inline void 961 hal_rx_msdu_get_flow_params_8074v2(uint8_t *buf, 962 bool *flow_invalid, 963 bool *flow_timeout, 964 uint32_t *flow_index) 965 { 966 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 967 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 968 969 *flow_invalid = HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(msdu_end); 970 *flow_timeout = HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(msdu_end); 971 *flow_index = HAL_RX_MSDU_END_FLOW_IDX_GET(msdu_end); 972 } 973 974 /** 975 * hal_rx_tlv_get_tcp_chksum_8074v2() - API to get tcp checksum 976 * @buf: rx_tlv_hdr 977 * 978 * Return: tcp checksum 979 */ 980 static uint16_t 981 hal_rx_tlv_get_tcp_chksum_8074v2(uint8_t *buf) 982 { 983 return HAL_RX_TLV_GET_TCP_CHKSUM(buf); 984 } 985 986 /** 987 * hal_rx_get_rx_sequence_8074v2(): Function to retrieve rx sequence number 988 * 989 * @nbuf: Network buffer 990 * Returns: rx sequence number 991 */ 992 static 993 uint16_t hal_rx_get_rx_sequence_8074v2(uint8_t *buf) 994 { 995 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 996 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 997 998 return HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info); 999 } 1000 1001 /** 1002 * hal_get_window_address_8074v2(): Function to get hp/tp address 1003 * @hal_soc: Pointer to hal_soc 1004 * @addr: address offset of register 1005 * 1006 * Return: modified address offset of register 1007 */ 1008 static inline qdf_iomem_t hal_get_window_address_8074v2(struct hal_soc *hal_soc, 1009 qdf_iomem_t addr) 1010 { 1011 return addr; 1012 } 1013 1014 /** 1015 * hal_rx_mpdu_start_tlv_tag_valid_8074v2 () - API to check if RX_MPDU_START 1016 * tlv tag is valid 1017 * 1018 * @rx_tlv_hdr: start address of rx_pkt_tlvs 1019 * 1020 * Return: true if RX_MPDU_START is valied, else false. 1021 */ 1022 uint8_t hal_rx_mpdu_start_tlv_tag_valid_8074v2(void *rx_tlv_hdr) 1023 { 1024 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)rx_tlv_hdr; 1025 uint32_t tlv_tag; 1026 1027 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(&rx_desc->mpdu_start_tlv); 1028 1029 return tlv_tag == WIFIRX_MPDU_START_E ? true : false; 1030 } 1031 1032 /** 1033 * hal_rx_flow_setup_fse_8074v2() - Setup a flow search entry in HW FST 1034 * @fst: Pointer to the Rx Flow Search Table 1035 * @table_offset: offset into the table where the flow is to be setup 1036 * @flow: Flow Parameters 1037 * 1038 * Return: Success/Failure 1039 */ 1040 static void * 1041 hal_rx_flow_setup_fse_8074v2(uint8_t *rx_fst, uint32_t table_offset, 1042 uint8_t *rx_flow) 1043 { 1044 struct hal_rx_fst *fst = (struct hal_rx_fst *)rx_fst; 1045 struct hal_rx_flow *flow = (struct hal_rx_flow *)rx_flow; 1046 uint8_t *fse; 1047 bool fse_valid; 1048 1049 if (table_offset >= fst->max_entries) { 1050 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR, 1051 "HAL FSE table offset %u exceeds max entries %u", 1052 table_offset, fst->max_entries); 1053 return NULL; 1054 } 1055 1056 fse = (uint8_t *)fst->base_vaddr + 1057 (table_offset * HAL_RX_FST_ENTRY_SIZE); 1058 1059 fse_valid = HAL_GET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, VALID); 1060 1061 if (fse_valid) { 1062 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_DEBUG, 1063 "HAL FSE %pK already valid", fse); 1064 return NULL; 1065 } 1066 1067 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_0, SRC_IP_127_96) = 1068 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_0, SRC_IP_127_96, 1069 qdf_htonl(flow->tuple_info.src_ip_127_96)); 1070 1071 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_1, SRC_IP_95_64) = 1072 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_1, SRC_IP_95_64, 1073 qdf_htonl(flow->tuple_info.src_ip_95_64)); 1074 1075 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_2, SRC_IP_63_32) = 1076 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_2, SRC_IP_63_32, 1077 qdf_htonl(flow->tuple_info.src_ip_63_32)); 1078 1079 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_3, SRC_IP_31_0) = 1080 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_3, SRC_IP_31_0, 1081 qdf_htonl(flow->tuple_info.src_ip_31_0)); 1082 1083 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_4, DEST_IP_127_96) = 1084 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_4, DEST_IP_127_96, 1085 qdf_htonl(flow->tuple_info.dest_ip_127_96)); 1086 1087 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_5, DEST_IP_95_64) = 1088 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_5, DEST_IP_95_64, 1089 qdf_htonl(flow->tuple_info.dest_ip_95_64)); 1090 1091 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_6, DEST_IP_63_32) = 1092 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_6, DEST_IP_63_32, 1093 qdf_htonl(flow->tuple_info.dest_ip_63_32)); 1094 1095 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_7, DEST_IP_31_0) = 1096 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_7, DEST_IP_31_0, 1097 qdf_htonl(flow->tuple_info.dest_ip_31_0)); 1098 1099 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, DEST_PORT); 1100 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, DEST_PORT) |= 1101 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_8, DEST_PORT, 1102 (flow->tuple_info.dest_port)); 1103 1104 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, SRC_PORT); 1105 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, SRC_PORT) |= 1106 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_8, SRC_PORT, 1107 (flow->tuple_info.src_port)); 1108 1109 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, L4_PROTOCOL); 1110 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, L4_PROTOCOL) |= 1111 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, L4_PROTOCOL, 1112 flow->tuple_info.l4_protocol); 1113 1114 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_HANDLER); 1115 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_HANDLER) |= 1116 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_HANDLER, 1117 flow->reo_destination_handler); 1118 1119 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, VALID); 1120 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, VALID) |= 1121 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, VALID, 1); 1122 1123 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_10, METADATA); 1124 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_10, METADATA) = 1125 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_10, METADATA, 1126 flow->fse_metadata); 1127 1128 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_11, REO_DESTINATION_INDICATION); 1129 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_11, REO_DESTINATION_INDICATION) |= 1130 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_11, 1131 REO_DESTINATION_INDICATION, 1132 flow->reo_destination_indication); 1133 1134 /* Reset all the other fields in FSE */ 1135 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, RESERVED_9); 1136 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_11, MSDU_DROP); 1137 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_11, RESERVED_11); 1138 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_11, MSDU_COUNT); 1139 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_12, MSDU_BYTE_COUNT); 1140 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_13, TIMESTAMP); 1141 1142 return fse; 1143 } 1144 1145 static 1146 void hal_compute_reo_remap_ix2_ix3_8074v2(uint32_t *ring, uint32_t num_rings, 1147 uint32_t *remap1, uint32_t *remap2) 1148 { 1149 switch (num_rings) { 1150 case 1: 1151 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 1152 HAL_REO_REMAP_IX2(ring[0], 17) | 1153 HAL_REO_REMAP_IX2(ring[0], 18) | 1154 HAL_REO_REMAP_IX2(ring[0], 19) | 1155 HAL_REO_REMAP_IX2(ring[0], 20) | 1156 HAL_REO_REMAP_IX2(ring[0], 21) | 1157 HAL_REO_REMAP_IX2(ring[0], 22) | 1158 HAL_REO_REMAP_IX2(ring[0], 23); 1159 1160 *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) | 1161 HAL_REO_REMAP_IX3(ring[0], 25) | 1162 HAL_REO_REMAP_IX3(ring[0], 26) | 1163 HAL_REO_REMAP_IX3(ring[0], 27) | 1164 HAL_REO_REMAP_IX3(ring[0], 28) | 1165 HAL_REO_REMAP_IX3(ring[0], 29) | 1166 HAL_REO_REMAP_IX3(ring[0], 30) | 1167 HAL_REO_REMAP_IX3(ring[0], 31); 1168 break; 1169 case 2: 1170 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 1171 HAL_REO_REMAP_IX2(ring[0], 17) | 1172 HAL_REO_REMAP_IX2(ring[1], 18) | 1173 HAL_REO_REMAP_IX2(ring[1], 19) | 1174 HAL_REO_REMAP_IX2(ring[0], 20) | 1175 HAL_REO_REMAP_IX2(ring[0], 21) | 1176 HAL_REO_REMAP_IX2(ring[1], 22) | 1177 HAL_REO_REMAP_IX2(ring[1], 23); 1178 1179 *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) | 1180 HAL_REO_REMAP_IX3(ring[0], 25) | 1181 HAL_REO_REMAP_IX3(ring[1], 26) | 1182 HAL_REO_REMAP_IX3(ring[1], 27) | 1183 HAL_REO_REMAP_IX3(ring[0], 28) | 1184 HAL_REO_REMAP_IX3(ring[0], 29) | 1185 HAL_REO_REMAP_IX3(ring[1], 30) | 1186 HAL_REO_REMAP_IX3(ring[1], 31); 1187 break; 1188 case 3: 1189 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 1190 HAL_REO_REMAP_IX2(ring[1], 17) | 1191 HAL_REO_REMAP_IX2(ring[2], 18) | 1192 HAL_REO_REMAP_IX2(ring[0], 19) | 1193 HAL_REO_REMAP_IX2(ring[1], 20) | 1194 HAL_REO_REMAP_IX2(ring[2], 21) | 1195 HAL_REO_REMAP_IX2(ring[0], 22) | 1196 HAL_REO_REMAP_IX2(ring[1], 23); 1197 1198 *remap2 = HAL_REO_REMAP_IX3(ring[2], 24) | 1199 HAL_REO_REMAP_IX3(ring[0], 25) | 1200 HAL_REO_REMAP_IX3(ring[1], 26) | 1201 HAL_REO_REMAP_IX3(ring[2], 27) | 1202 HAL_REO_REMAP_IX3(ring[0], 28) | 1203 HAL_REO_REMAP_IX3(ring[1], 29) | 1204 HAL_REO_REMAP_IX3(ring[2], 30) | 1205 HAL_REO_REMAP_IX3(ring[0], 31); 1206 break; 1207 case 4: 1208 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 1209 HAL_REO_REMAP_IX2(ring[1], 17) | 1210 HAL_REO_REMAP_IX2(ring[2], 18) | 1211 HAL_REO_REMAP_IX2(ring[3], 19) | 1212 HAL_REO_REMAP_IX2(ring[0], 20) | 1213 HAL_REO_REMAP_IX2(ring[1], 21) | 1214 HAL_REO_REMAP_IX2(ring[2], 22) | 1215 HAL_REO_REMAP_IX2(ring[3], 23); 1216 1217 *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) | 1218 HAL_REO_REMAP_IX3(ring[1], 25) | 1219 HAL_REO_REMAP_IX3(ring[2], 26) | 1220 HAL_REO_REMAP_IX3(ring[3], 27) | 1221 HAL_REO_REMAP_IX3(ring[0], 28) | 1222 HAL_REO_REMAP_IX3(ring[1], 29) | 1223 HAL_REO_REMAP_IX3(ring[2], 30) | 1224 HAL_REO_REMAP_IX3(ring[3], 31); 1225 break; 1226 } 1227 } 1228 1229 static void hal_hw_txrx_ops_attach_qca8074v2(struct hal_soc *hal_soc) 1230 { 1231 1232 /* init and setup */ 1233 hal_soc->ops->hal_srng_dst_hw_init = hal_srng_dst_hw_init_generic; 1234 hal_soc->ops->hal_srng_src_hw_init = hal_srng_src_hw_init_generic; 1235 hal_soc->ops->hal_get_hw_hptp = hal_get_hw_hptp_generic; 1236 hal_soc->ops->hal_reo_setup = hal_reo_setup_generic_li; 1237 hal_soc->ops->hal_get_window_address = hal_get_window_address_8074v2; 1238 1239 /* tx */ 1240 hal_soc->ops->hal_tx_desc_set_dscp_tid_table_id = 1241 hal_tx_desc_set_dscp_tid_table_id_8074v2; 1242 hal_soc->ops->hal_tx_set_dscp_tid_map = hal_tx_set_dscp_tid_map_8074v2; 1243 hal_soc->ops->hal_tx_update_dscp_tid = hal_tx_update_dscp_tid_8074v2; 1244 hal_soc->ops->hal_tx_desc_set_lmac_id = hal_tx_desc_set_lmac_id_8074v2; 1245 hal_soc->ops->hal_tx_desc_set_buf_addr = 1246 hal_tx_desc_set_buf_addr_generic_li; 1247 hal_soc->ops->hal_tx_desc_set_search_type = 1248 hal_tx_desc_set_search_type_generic_li; 1249 hal_soc->ops->hal_tx_desc_set_search_index = 1250 hal_tx_desc_set_search_index_generic_li; 1251 hal_soc->ops->hal_tx_desc_set_cache_set_num = 1252 hal_tx_desc_set_cache_set_num_generic_li; 1253 hal_soc->ops->hal_tx_comp_get_status = 1254 hal_tx_comp_get_status_generic_li; 1255 hal_soc->ops->hal_tx_comp_get_release_reason = 1256 hal_tx_comp_get_release_reason_generic_li; 1257 hal_soc->ops->hal_get_wbm_internal_error = 1258 hal_get_wbm_internal_error_generic_li; 1259 hal_soc->ops->hal_tx_desc_set_mesh_en = hal_tx_desc_set_mesh_en_8074v2; 1260 hal_soc->ops->hal_tx_init_cmd_credit_ring = 1261 hal_tx_init_cmd_credit_ring_8074v2; 1262 1263 /* rx */ 1264 hal_soc->ops->hal_rx_msdu_start_nss_get = 1265 hal_rx_msdu_start_nss_get_8074v2; 1266 hal_soc->ops->hal_rx_mon_hw_desc_get_mpdu_status = 1267 hal_rx_mon_hw_desc_get_mpdu_status_8074v2; 1268 hal_soc->ops->hal_rx_get_tlv = hal_rx_get_tlv_8074v2; 1269 hal_soc->ops->hal_rx_proc_phyrx_other_receive_info_tlv = 1270 hal_rx_proc_phyrx_other_receive_info_tlv_8074v2; 1271 hal_soc->ops->hal_rx_dump_msdu_start_tlv = 1272 hal_rx_dump_msdu_start_tlv_8074v2; 1273 hal_soc->ops->hal_rx_dump_msdu_end_tlv = hal_rx_dump_msdu_end_tlv_8074v2; 1274 hal_soc->ops->hal_get_link_desc_size = hal_get_link_desc_size_8074v2; 1275 hal_soc->ops->hal_rx_mpdu_start_tid_get = 1276 hal_rx_mpdu_start_tid_get_8074v2; 1277 hal_soc->ops->hal_rx_msdu_start_reception_type_get = 1278 hal_rx_msdu_start_reception_type_get_8074v2; 1279 hal_soc->ops->hal_rx_msdu_end_da_idx_get = 1280 hal_rx_msdu_end_da_idx_get_8074v2; 1281 hal_soc->ops->hal_rx_msdu_desc_info_get_ptr = 1282 hal_rx_msdu_desc_info_get_ptr_8074v2; 1283 hal_soc->ops->hal_rx_link_desc_msdu0_ptr = 1284 hal_rx_link_desc_msdu0_ptr_8074v2; 1285 hal_soc->ops->hal_reo_status_get_header = 1286 hal_reo_status_get_header_8074v2; 1287 hal_soc->ops->hal_rx_status_get_tlv_info = 1288 hal_rx_status_get_tlv_info_generic_li; 1289 hal_soc->ops->hal_rx_wbm_err_info_get = 1290 hal_rx_wbm_err_info_get_generic_li; 1291 hal_soc->ops->hal_rx_dump_mpdu_start_tlv = 1292 hal_rx_dump_mpdu_start_tlv_generic_li; 1293 1294 hal_soc->ops->hal_tx_set_pcp_tid_map = 1295 hal_tx_set_pcp_tid_map_generic_li; 1296 hal_soc->ops->hal_tx_update_pcp_tid_map = 1297 hal_tx_update_pcp_tid_generic_li; 1298 hal_soc->ops->hal_tx_set_tidmap_prty = 1299 hal_tx_update_tidmap_prty_generic_li; 1300 hal_soc->ops->hal_rx_get_rx_fragment_number = 1301 hal_rx_get_rx_fragment_number_8074v2; 1302 hal_soc->ops->hal_rx_msdu_end_da_is_mcbc_get = 1303 hal_rx_msdu_end_da_is_mcbc_get_8074v2; 1304 hal_soc->ops->hal_rx_msdu_end_sa_is_valid_get = 1305 hal_rx_msdu_end_sa_is_valid_get_8074v2; 1306 hal_soc->ops->hal_rx_msdu_end_sa_idx_get = 1307 hal_rx_msdu_end_sa_idx_get_8074v2; 1308 hal_soc->ops->hal_rx_desc_is_first_msdu = 1309 hal_rx_desc_is_first_msdu_8074v2; 1310 hal_soc->ops->hal_rx_msdu_end_l3_hdr_padding_get = 1311 hal_rx_msdu_end_l3_hdr_padding_get_8074v2; 1312 hal_soc->ops->hal_rx_encryption_info_valid = 1313 hal_rx_encryption_info_valid_8074v2; 1314 hal_soc->ops->hal_rx_print_pn = hal_rx_print_pn_8074v2; 1315 hal_soc->ops->hal_rx_msdu_end_first_msdu_get = 1316 hal_rx_msdu_end_first_msdu_get_8074v2; 1317 hal_soc->ops->hal_rx_msdu_end_da_is_valid_get = 1318 hal_rx_msdu_end_da_is_valid_get_8074v2; 1319 hal_soc->ops->hal_rx_msdu_end_last_msdu_get = 1320 hal_rx_msdu_end_last_msdu_get_8074v2; 1321 hal_soc->ops->hal_rx_get_mpdu_mac_ad4_valid = 1322 hal_rx_get_mpdu_mac_ad4_valid_8074v2; 1323 hal_soc->ops->hal_rx_mpdu_start_sw_peer_id_get = 1324 hal_rx_mpdu_start_sw_peer_id_get_8074v2; 1325 hal_soc->ops->hal_rx_tlv_peer_meta_data_get = 1326 hal_rx_mpdu_peer_meta_data_get_li; 1327 hal_soc->ops->hal_rx_mpdu_get_to_ds = hal_rx_mpdu_get_to_ds_8074v2; 1328 hal_soc->ops->hal_rx_mpdu_get_fr_ds = hal_rx_mpdu_get_fr_ds_8074v2; 1329 hal_soc->ops->hal_rx_get_mpdu_frame_control_valid = 1330 hal_rx_get_mpdu_frame_control_valid_8074v2; 1331 hal_soc->ops->hal_rx_mpdu_get_addr1 = hal_rx_mpdu_get_addr1_8074v2; 1332 hal_soc->ops->hal_rx_mpdu_get_addr2 = hal_rx_mpdu_get_addr2_8074v2; 1333 hal_soc->ops->hal_rx_mpdu_get_addr3 = hal_rx_mpdu_get_addr3_8074v2; 1334 hal_soc->ops->hal_rx_mpdu_get_addr4 = hal_rx_mpdu_get_addr4_8074v2; 1335 hal_soc->ops->hal_rx_get_mpdu_sequence_control_valid = 1336 hal_rx_get_mpdu_sequence_control_valid_8074v2; 1337 hal_soc->ops->hal_rx_is_unicast = hal_rx_is_unicast_8074v2; 1338 hal_soc->ops->hal_rx_tid_get = hal_rx_tid_get_8074v2; 1339 hal_soc->ops->hal_rx_hw_desc_get_ppduid_get = 1340 hal_rx_hw_desc_get_ppduid_get_8074v2; 1341 hal_soc->ops->hal_rx_mpdu_start_mpdu_qos_control_valid_get = 1342 hal_rx_mpdu_start_mpdu_qos_control_valid_get_8074v2; 1343 hal_soc->ops->hal_rx_msdu_end_sa_sw_peer_id_get = 1344 hal_rx_msdu_end_sa_sw_peer_id_get_8074v2; 1345 hal_soc->ops->hal_rx_msdu0_buffer_addr_lsb = 1346 hal_rx_msdu0_buffer_addr_lsb_8074v2; 1347 hal_soc->ops->hal_rx_msdu_desc_info_ptr_get = 1348 hal_rx_msdu_desc_info_ptr_get_8074v2; 1349 hal_soc->ops->hal_ent_mpdu_desc_info = hal_ent_mpdu_desc_info_8074v2; 1350 hal_soc->ops->hal_dst_mpdu_desc_info = hal_dst_mpdu_desc_info_8074v2; 1351 hal_soc->ops->hal_rx_get_fc_valid = hal_rx_get_fc_valid_8074v2; 1352 hal_soc->ops->hal_rx_get_to_ds_flag = hal_rx_get_to_ds_flag_8074v2; 1353 hal_soc->ops->hal_rx_get_mac_addr2_valid = 1354 hal_rx_get_mac_addr2_valid_8074v2; 1355 hal_soc->ops->hal_rx_get_filter_category = 1356 hal_rx_get_filter_category_8074v2; 1357 hal_soc->ops->hal_rx_get_ppdu_id = hal_rx_get_ppdu_id_8074v2; 1358 hal_soc->ops->hal_reo_config = hal_reo_config_8074v2; 1359 hal_soc->ops->hal_rx_msdu_flow_idx_get = hal_rx_msdu_flow_idx_get_8074v2; 1360 hal_soc->ops->hal_rx_msdu_flow_idx_invalid = 1361 hal_rx_msdu_flow_idx_invalid_8074v2; 1362 hal_soc->ops->hal_rx_msdu_flow_idx_timeout = 1363 hal_rx_msdu_flow_idx_timeout_8074v2; 1364 hal_soc->ops->hal_rx_msdu_fse_metadata_get = 1365 hal_rx_msdu_fse_metadata_get_8074v2; 1366 hal_soc->ops->hal_rx_msdu_cce_match_get = 1367 hal_rx_msdu_cce_match_get_li; 1368 hal_soc->ops->hal_rx_msdu_cce_metadata_get = 1369 hal_rx_msdu_cce_metadata_get_8074v2; 1370 hal_soc->ops->hal_rx_msdu_get_flow_params = 1371 hal_rx_msdu_get_flow_params_8074v2; 1372 hal_soc->ops->hal_rx_tlv_get_tcp_chksum = 1373 hal_rx_tlv_get_tcp_chksum_8074v2; 1374 hal_soc->ops->hal_rx_get_rx_sequence = hal_rx_get_rx_sequence_8074v2; 1375 #if defined(QCA_WIFI_QCA6018) && defined(WLAN_CFR_ENABLE) && \ 1376 defined(WLAN_ENH_CFR_ENABLE) 1377 hal_soc->ops->hal_rx_get_bb_info = hal_rx_get_bb_info_8074v2; 1378 hal_soc->ops->hal_rx_get_rtt_info = hal_rx_get_rtt_info_8074v2; 1379 #endif 1380 /* rx - msdu fast path info fields */ 1381 hal_soc->ops->hal_rx_msdu_packet_metadata_get = 1382 hal_rx_msdu_packet_metadata_get_generic_li; 1383 hal_soc->ops->hal_rx_mpdu_start_tlv_tag_valid = 1384 hal_rx_mpdu_start_tlv_tag_valid_8074v2; 1385 1386 /* rx - TLV struct offsets */ 1387 hal_soc->ops->hal_rx_msdu_end_offset_get = 1388 hal_rx_msdu_end_offset_get_generic; 1389 hal_soc->ops->hal_rx_attn_offset_get = hal_rx_attn_offset_get_generic; 1390 hal_soc->ops->hal_rx_msdu_start_offset_get = 1391 hal_rx_msdu_start_offset_get_generic; 1392 hal_soc->ops->hal_rx_mpdu_start_offset_get = 1393 hal_rx_mpdu_start_offset_get_generic; 1394 hal_soc->ops->hal_rx_mpdu_end_offset_get = 1395 hal_rx_mpdu_end_offset_get_generic; 1396 #ifndef NO_RX_PKT_HDR_TLV 1397 hal_soc->ops->hal_rx_pkt_tlv_offset_get = 1398 hal_rx_pkt_tlv_offset_get_generic; 1399 #endif 1400 hal_soc->ops->hal_rx_flow_setup_fse = hal_rx_flow_setup_fse_8074v2; 1401 hal_soc->ops->hal_rx_flow_get_tuple_info = 1402 hal_rx_flow_get_tuple_info_li; 1403 hal_soc->ops->hal_rx_flow_delete_entry = 1404 hal_rx_flow_delete_entry_li; 1405 hal_soc->ops->hal_rx_fst_get_fse_size = hal_rx_fst_get_fse_size_li; 1406 hal_soc->ops->hal_compute_reo_remap_ix2_ix3 = 1407 hal_compute_reo_remap_ix2_ix3_8074v2; 1408 hal_soc->ops->hal_setup_link_idle_list = 1409 hal_setup_link_idle_list_generic_li; 1410 hal_soc->ops->hal_compute_reo_remap_ix0 = NULL; 1411 }; 1412 1413 struct hal_hw_srng_config hw_srng_table_8074v2[] = { 1414 /* TODO: max_rings can populated by querying HW capabilities */ 1415 { /* REO_DST */ 1416 .start_ring_id = HAL_SRNG_REO2SW1, 1417 .max_rings = 4, 1418 .entry_size = sizeof(struct reo_destination_ring) >> 2, 1419 .lmac_ring = FALSE, 1420 .ring_dir = HAL_SRNG_DST_RING, 1421 .reg_start = { 1422 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR( 1423 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1424 HWIO_REO_R2_REO2SW1_RING_HP_ADDR( 1425 SEQ_WCSS_UMAC_REO_REG_OFFSET) 1426 }, 1427 .reg_size = { 1428 HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(0) - 1429 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(0), 1430 HWIO_REO_R2_REO2SW2_RING_HP_ADDR(0) - 1431 HWIO_REO_R2_REO2SW1_RING_HP_ADDR(0), 1432 }, 1433 .max_size = 1434 HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_BMSK >> 1435 HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_SHFT, 1436 }, 1437 { /* REO_EXCEPTION */ 1438 /* Designating REO2TCL ring as exception ring. This ring is 1439 * similar to other REO2SW rings though it is named as REO2TCL. 1440 * Any of theREO2SW rings can be used as exception ring. 1441 */ 1442 .start_ring_id = HAL_SRNG_REO2TCL, 1443 .max_rings = 1, 1444 .entry_size = sizeof(struct reo_destination_ring) >> 2, 1445 .lmac_ring = FALSE, 1446 .ring_dir = HAL_SRNG_DST_RING, 1447 .reg_start = { 1448 HWIO_REO_R0_REO2TCL_RING_BASE_LSB_ADDR( 1449 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1450 HWIO_REO_R2_REO2TCL_RING_HP_ADDR( 1451 SEQ_WCSS_UMAC_REO_REG_OFFSET) 1452 }, 1453 /* Single ring - provide ring size if multiple rings of this 1454 * type are supported 1455 */ 1456 .reg_size = {}, 1457 .max_size = 1458 HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_BMSK >> 1459 HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_SHFT, 1460 }, 1461 { /* REO_REINJECT */ 1462 .start_ring_id = HAL_SRNG_SW2REO, 1463 .max_rings = 1, 1464 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 1465 .lmac_ring = FALSE, 1466 .ring_dir = HAL_SRNG_SRC_RING, 1467 .reg_start = { 1468 HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR( 1469 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1470 HWIO_REO_R2_SW2REO_RING_HP_ADDR( 1471 SEQ_WCSS_UMAC_REO_REG_OFFSET) 1472 }, 1473 /* Single ring - provide ring size if multiple rings of this 1474 * type are supported 1475 */ 1476 .reg_size = {}, 1477 .max_size = HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_BMSK >> 1478 HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_SHFT, 1479 }, 1480 { /* REO_CMD */ 1481 .start_ring_id = HAL_SRNG_REO_CMD, 1482 .max_rings = 1, 1483 .entry_size = (sizeof(struct tlv_32_hdr) + 1484 sizeof(struct reo_get_queue_stats)) >> 2, 1485 .lmac_ring = FALSE, 1486 .ring_dir = HAL_SRNG_SRC_RING, 1487 .reg_start = { 1488 HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR( 1489 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1490 HWIO_REO_R2_REO_CMD_RING_HP_ADDR( 1491 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1492 }, 1493 /* Single ring - provide ring size if multiple rings of this 1494 * type are supported 1495 */ 1496 .reg_size = {}, 1497 .max_size = HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_BMSK >> 1498 HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_SHFT, 1499 }, 1500 { /* REO_STATUS */ 1501 .start_ring_id = HAL_SRNG_REO_STATUS, 1502 .max_rings = 1, 1503 .entry_size = (sizeof(struct tlv_32_hdr) + 1504 sizeof(struct reo_get_queue_stats_status)) >> 2, 1505 .lmac_ring = FALSE, 1506 .ring_dir = HAL_SRNG_DST_RING, 1507 .reg_start = { 1508 HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR( 1509 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1510 HWIO_REO_R2_REO_STATUS_RING_HP_ADDR( 1511 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1512 }, 1513 /* Single ring - provide ring size if multiple rings of this 1514 * type are supported 1515 */ 1516 .reg_size = {}, 1517 .max_size = 1518 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> 1519 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, 1520 }, 1521 { /* TCL_DATA */ 1522 .start_ring_id = HAL_SRNG_SW2TCL1, 1523 .max_rings = 3, 1524 .entry_size = (sizeof(struct tlv_32_hdr) + 1525 sizeof(struct tcl_data_cmd)) >> 2, 1526 .lmac_ring = FALSE, 1527 .ring_dir = HAL_SRNG_SRC_RING, 1528 .reg_start = { 1529 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR( 1530 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1531 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR( 1532 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1533 }, 1534 .reg_size = { 1535 HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(0) - 1536 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(0), 1537 HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(0) - 1538 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(0), 1539 }, 1540 .max_size = 1541 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK >> 1542 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT, 1543 }, 1544 { /* TCL_CMD */ 1545 /* qca8074v2 and qcn9000 uses this ring for data commands */ 1546 .start_ring_id = HAL_SRNG_SW2TCL_CMD, 1547 .max_rings = 1, 1548 .entry_size = (sizeof(struct tlv_32_hdr) + 1549 sizeof(struct tcl_data_cmd)) >> 2, 1550 .lmac_ring = FALSE, 1551 .ring_dir = HAL_SRNG_SRC_RING, 1552 .reg_start = { 1553 HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_ADDR( 1554 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1555 HWIO_TCL_R2_SW2TCL_CMD_RING_HP_ADDR( 1556 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1557 }, 1558 /* Single ring - provide ring size if multiple rings of this 1559 * type are supported 1560 */ 1561 .reg_size = {}, 1562 .max_size = 1563 HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RING_SIZE_BMSK >> 1564 HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RING_SIZE_SHFT, 1565 }, 1566 { /* TCL_STATUS */ 1567 .start_ring_id = HAL_SRNG_TCL_STATUS, 1568 .max_rings = 1, 1569 .entry_size = (sizeof(struct tlv_32_hdr) + 1570 sizeof(struct tcl_status_ring)) >> 2, 1571 .lmac_ring = FALSE, 1572 .ring_dir = HAL_SRNG_DST_RING, 1573 .reg_start = { 1574 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR( 1575 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1576 HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR( 1577 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1578 }, 1579 /* Single ring - provide ring size if multiple rings of this 1580 * type are supported 1581 */ 1582 .reg_size = {}, 1583 .max_size = 1584 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_BMSK >> 1585 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_SHFT, 1586 }, 1587 { /* CE_SRC */ 1588 .start_ring_id = HAL_SRNG_CE_0_SRC, 1589 .max_rings = 12, 1590 .entry_size = sizeof(struct ce_src_desc) >> 2, 1591 .lmac_ring = FALSE, 1592 .ring_dir = HAL_SRNG_SRC_RING, 1593 .reg_start = { 1594 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR( 1595 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET), 1596 HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR( 1597 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET), 1598 }, 1599 .reg_size = { 1600 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET - 1601 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET, 1602 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET - 1603 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET, 1604 }, 1605 .max_size = 1606 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >> 1607 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT, 1608 }, 1609 { /* CE_DST */ 1610 .start_ring_id = HAL_SRNG_CE_0_DST, 1611 .max_rings = 12, 1612 .entry_size = 8 >> 2, 1613 /*TODO: entry_size above should actually be 1614 * sizeof(struct ce_dst_desc) >> 2, but couldn't find definition 1615 * of struct ce_dst_desc in HW header files 1616 */ 1617 .lmac_ring = FALSE, 1618 .ring_dir = HAL_SRNG_SRC_RING, 1619 .reg_start = { 1620 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR( 1621 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 1622 HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR( 1623 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 1624 }, 1625 .reg_size = { 1626 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 1627 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 1628 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 1629 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 1630 }, 1631 .max_size = 1632 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >> 1633 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT, 1634 }, 1635 { /* CE_DST_STATUS */ 1636 .start_ring_id = HAL_SRNG_CE_0_DST_STATUS, 1637 .max_rings = 12, 1638 .entry_size = sizeof(struct ce_stat_desc) >> 2, 1639 .lmac_ring = FALSE, 1640 .ring_dir = HAL_SRNG_DST_RING, 1641 .reg_start = { 1642 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR( 1643 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 1644 HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR( 1645 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 1646 }, 1647 /* TODO: check destination status ring registers */ 1648 .reg_size = { 1649 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 1650 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 1651 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 1652 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 1653 }, 1654 .max_size = 1655 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> 1656 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, 1657 }, 1658 { /* WBM_IDLE_LINK */ 1659 .start_ring_id = HAL_SRNG_WBM_IDLE_LINK, 1660 .max_rings = 1, 1661 .entry_size = sizeof(struct wbm_link_descriptor_ring) >> 2, 1662 .lmac_ring = FALSE, 1663 .ring_dir = HAL_SRNG_SRC_RING, 1664 .reg_start = { 1665 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1666 HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1667 }, 1668 /* Single ring - provide ring size if multiple rings of this 1669 * type are supported 1670 */ 1671 .reg_size = {}, 1672 .max_size = 1673 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_BMSK >> 1674 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_SHFT, 1675 }, 1676 { /* SW2WBM_RELEASE */ 1677 .start_ring_id = HAL_SRNG_WBM_SW_RELEASE, 1678 .max_rings = 1, 1679 .entry_size = sizeof(struct wbm_release_ring) >> 2, 1680 .lmac_ring = FALSE, 1681 .ring_dir = HAL_SRNG_SRC_RING, 1682 .reg_start = { 1683 HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1684 HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1685 }, 1686 /* Single ring - provide ring size if multiple rings of this 1687 * type are supported 1688 */ 1689 .reg_size = {}, 1690 .max_size = 1691 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> 1692 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, 1693 }, 1694 { /* WBM2SW_RELEASE */ 1695 .start_ring_id = HAL_SRNG_WBM2SW0_RELEASE, 1696 .max_rings = 5, 1697 .entry_size = sizeof(struct wbm_release_ring) >> 2, 1698 .lmac_ring = FALSE, 1699 .ring_dir = HAL_SRNG_DST_RING, 1700 .reg_start = { 1701 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1702 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1703 }, 1704 .reg_size = { 1705 HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) - 1706 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1707 HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) - 1708 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1709 }, 1710 .max_size = 1711 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> 1712 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, 1713 }, 1714 { /* RXDMA_BUF */ 1715 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA0_BUF0, 1716 #ifdef IPA_OFFLOAD 1717 .max_rings = 3, 1718 #else 1719 .max_rings = 2, 1720 #endif 1721 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 1722 .lmac_ring = TRUE, 1723 .ring_dir = HAL_SRNG_SRC_RING, 1724 /* reg_start is not set because LMAC rings are not accessed 1725 * from host 1726 */ 1727 .reg_start = {}, 1728 .reg_size = {}, 1729 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1730 }, 1731 { /* RXDMA_DST */ 1732 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW0, 1733 .max_rings = 1, 1734 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 1735 .lmac_ring = TRUE, 1736 .ring_dir = HAL_SRNG_DST_RING, 1737 /* reg_start is not set because LMAC rings are not accessed 1738 * from host 1739 */ 1740 .reg_start = {}, 1741 .reg_size = {}, 1742 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1743 }, 1744 { /* RXDMA_MONITOR_BUF */ 1745 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA2_BUF, 1746 .max_rings = 1, 1747 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 1748 .lmac_ring = TRUE, 1749 .ring_dir = HAL_SRNG_SRC_RING, 1750 /* reg_start is not set because LMAC rings are not accessed 1751 * from host 1752 */ 1753 .reg_start = {}, 1754 .reg_size = {}, 1755 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1756 }, 1757 { /* RXDMA_MONITOR_STATUS */ 1758 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_STATBUF, 1759 .max_rings = 1, 1760 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 1761 .lmac_ring = TRUE, 1762 .ring_dir = HAL_SRNG_SRC_RING, 1763 /* reg_start is not set because LMAC rings are not accessed 1764 * from host 1765 */ 1766 .reg_start = {}, 1767 .reg_size = {}, 1768 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1769 }, 1770 { /* RXDMA_MONITOR_DST */ 1771 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW1, 1772 .max_rings = 1, 1773 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 1774 .lmac_ring = TRUE, 1775 .ring_dir = HAL_SRNG_DST_RING, 1776 /* reg_start is not set because LMAC rings are not accessed 1777 * from host 1778 */ 1779 .reg_start = {}, 1780 .reg_size = {}, 1781 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1782 }, 1783 { /* RXDMA_MONITOR_DESC */ 1784 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_DESC, 1785 .max_rings = 1, 1786 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 1787 .lmac_ring = TRUE, 1788 .ring_dir = HAL_SRNG_SRC_RING, 1789 /* reg_start is not set because LMAC rings are not accessed 1790 * from host 1791 */ 1792 .reg_start = {}, 1793 .reg_size = {}, 1794 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1795 }, 1796 { /* DIR_BUF_RX_DMA_SRC */ 1797 .start_ring_id = HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING, 1798 /* one ring for spectral and one ring for cfr */ 1799 .max_rings = 2, 1800 .entry_size = 2, 1801 .lmac_ring = TRUE, 1802 .ring_dir = HAL_SRNG_SRC_RING, 1803 /* reg_start is not set because LMAC rings are not accessed 1804 * from host 1805 */ 1806 .reg_start = {}, 1807 .reg_size = {}, 1808 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1809 }, 1810 #ifdef WLAN_FEATURE_CIF_CFR 1811 { /* WIFI_POS_SRC */ 1812 .start_ring_id = HAL_SRNG_WIFI_POS_SRC_DMA_RING, 1813 .max_rings = 1, 1814 .entry_size = sizeof(wmi_oem_dma_buf_release_entry) >> 2, 1815 .lmac_ring = TRUE, 1816 .ring_dir = HAL_SRNG_SRC_RING, 1817 /* reg_start is not set because LMAC rings are not accessed 1818 * from host 1819 */ 1820 .reg_start = {}, 1821 .reg_size = {}, 1822 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1823 }, 1824 #endif 1825 { /* REO2PPE */ 0}, 1826 { /* PPE2TCL */ 0}, 1827 { /* PPE_RELEASE */ 0}, 1828 { /* TX_MONITOR_BUF */ 0}, 1829 { /* TX_MONITOR_DST */ 0}, 1830 { /* SW2RXDMA_NEW */ 0}, 1831 }; 1832 1833 1834 /** 1835 * hal_qca8074v2_attach() - Attach 8074v2 target specific hal_soc ops, 1836 * offset and srng table 1837 */ 1838 void hal_qca8074v2_attach(struct hal_soc *hal_soc) 1839 { 1840 hal_soc->hw_srng_table = hw_srng_table_8074v2; 1841 hal_srng_hw_reg_offset_init_generic(hal_soc); 1842 hal_hw_txrx_default_ops_attach_li(hal_soc); 1843 hal_hw_txrx_ops_attach_qca8074v2(hal_soc); 1844 } 1845