1 /* 2 * Copyright (c) 2016-2018 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 #include "hal_hw_headers.h" 19 #include "hal_internal.h" 20 #include "hal_api.h" 21 #include "target_type.h" 22 #include "wcss_version.h" 23 #include "qdf_module.h" 24 25 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_OFFSET \ 26 RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_OFFSET 27 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_MASK \ 28 RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_MASK 29 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_LSB \ 30 RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_LSB 31 #define UNIFIED_PHYRX_HT_SIG_0_HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS_OFFSET \ 32 PHYRX_HT_SIG_0_PHYRX_HT_SIG_INFO_DETAILS_MCS_OFFSET 33 #define UNIFIED_PHYRX_L_SIG_B_0_L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS_OFFSET \ 34 PHYRX_L_SIG_B_0_PHYRX_L_SIG_B_INFO_DETAILS_RATE_OFFSET 35 #define UNIFIED_PHYRX_L_SIG_A_0_L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS_OFFSET \ 36 PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_RATE_OFFSET 37 #define UNIFIED_PHYRX_VHT_SIG_A_0_VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS_OFFSET \ 38 PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_OFFSET 39 #define UNIFIED_PHYRX_HE_SIG_A_SU_0_HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS_OFFSET \ 40 PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_OFFSET 41 #define UNIFIED_PHYRX_HE_SIG_A_MU_DL_0_HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_OFFSET \ 42 PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_OFFSET 43 #define UNIFIED_PHYRX_HE_SIG_B1_MU_0_HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_OFFSET \ 44 PHYRX_HE_SIG_B1_MU_0_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_OFFSET 45 #define UNIFIED_PHYRX_HE_SIG_B2_MU_0_HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_OFFSET \ 46 PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_OFFSET 47 #define UNIFIED_PHYRX_HE_SIG_B2_OFDMA_0_HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_OFFSET \ 48 PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_OFFSET 49 #define UNIFIED_PHYRX_RSSI_LEGACY_3_RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS_OFFSET \ 50 PHYRX_RSSI_LEGACY_3_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 51 #define UNIFIED_RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET \ 52 RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 53 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 54 RX_MSDU_LINK_8_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 55 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ 56 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 57 #define UNIFIED_RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 58 RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 59 #define UNIFIED_REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 60 REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 61 #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER \ 62 STATUS_HEADER_REO_STATUS_NUMBER 63 #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC \ 64 STATUS_HEADER_TIMESTAMP 65 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ 66 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 67 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 68 RX_MSDU_LINK_8_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 69 #define UNIFIED_TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 70 TCL_DATA_CMD_0_BUF_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 71 #define UNIFIED_TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 72 TCL_DATA_CMD_1_BUF_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 73 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET \ 74 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET 75 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB \ 76 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB 77 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK \ 78 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK 79 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB \ 80 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB 81 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK \ 82 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK 83 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB \ 84 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB 85 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK \ 86 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK 87 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB \ 88 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB 89 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK \ 90 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK 91 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB \ 92 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB 93 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK \ 94 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK 95 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_MASK \ 96 WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MASK 97 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_OFFSET \ 98 WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_OFFSET 99 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_LSB \ 100 WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_LSB 101 #include "hal_8074v2_tx.h" 102 #include "hal_8074v2_rx.h" 103 #include <hal_generic_api.h> 104 #include <hal_wbm.h> 105 106 struct hal_hw_txrx_ops qca8074v2_hal_hw_txrx_ops = { 107 108 /* init and setup */ 109 hal_srng_dst_hw_init_generic, 110 hal_srng_src_hw_init_generic, 111 hal_reo_setup_generic, 112 hal_setup_link_idle_list_generic, 113 114 /* tx */ 115 hal_tx_desc_set_dscp_tid_table_id_8074v2, 116 hal_tx_set_dscp_tid_map_8074v2, 117 hal_tx_update_dscp_tid_8074v2, 118 hal_tx_desc_set_lmac_id_8074v2, 119 hal_tx_desc_set_buf_addr_generic, 120 hal_tx_comp_get_status_generic, 121 122 /* rx */ 123 hal_rx_msdu_start_nss_get_8074v2, 124 hal_rx_mon_hw_desc_get_mpdu_status_8074v2, 125 hal_rx_get_tlv_8074v2, 126 hal_rx_proc_phyrx_other_receive_info_tlv_8074v2, 127 hal_rx_dump_msdu_start_tlv_8074v2, 128 hal_rx_dump_msdu_end_tlv_8074v2, 129 hal_get_link_desc_size_8074v2, 130 hal_rx_mpdu_start_tid_get_8074v2, 131 hal_rx_msdu_start_reception_type_get_8074v2, 132 hal_rx_msdu_end_da_idx_get_8074v2, 133 hal_rx_msdu_desc_info_get_ptr_generic, 134 hal_rx_link_desc_msdu0_ptr_generic, 135 hal_reo_status_get_header_generic, 136 hal_rx_status_get_tlv_info_generic, 137 hal_tx_desc_set_search_type_generic, 138 hal_tx_desc_set_search_index_generic, 139 }; 140 141 struct hal_hw_srng_config hw_srng_table_8074v2[] = { 142 /* TODO: max_rings can populated by querying HW capabilities */ 143 { /* REO_DST */ 144 .start_ring_id = HAL_SRNG_REO2SW1, 145 .max_rings = 4, 146 .entry_size = sizeof(struct reo_destination_ring) >> 2, 147 .lmac_ring = FALSE, 148 .ring_dir = HAL_SRNG_DST_RING, 149 .reg_start = { 150 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR( 151 SEQ_WCSS_UMAC_REO_REG_OFFSET), 152 HWIO_REO_R2_REO2SW1_RING_HP_ADDR( 153 SEQ_WCSS_UMAC_REO_REG_OFFSET) 154 }, 155 .reg_size = { 156 HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(0) - 157 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(0), 158 HWIO_REO_R2_REO2SW2_RING_HP_ADDR(0) - 159 HWIO_REO_R2_REO2SW1_RING_HP_ADDR(0), 160 }, 161 .max_size = 162 HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_BMSK >> 163 HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_SHFT, 164 }, 165 { /* REO_EXCEPTION */ 166 /* Designating REO2TCL ring as exception ring. This ring is 167 * similar to other REO2SW rings though it is named as REO2TCL. 168 * Any of theREO2SW rings can be used as exception ring. 169 */ 170 .start_ring_id = HAL_SRNG_REO2TCL, 171 .max_rings = 1, 172 .entry_size = sizeof(struct reo_destination_ring) >> 2, 173 .lmac_ring = FALSE, 174 .ring_dir = HAL_SRNG_DST_RING, 175 .reg_start = { 176 HWIO_REO_R0_REO2TCL_RING_BASE_LSB_ADDR( 177 SEQ_WCSS_UMAC_REO_REG_OFFSET), 178 HWIO_REO_R2_REO2TCL_RING_HP_ADDR( 179 SEQ_WCSS_UMAC_REO_REG_OFFSET) 180 }, 181 /* Single ring - provide ring size if multiple rings of this 182 * type are supported 183 */ 184 .reg_size = {}, 185 .max_size = 186 HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_BMSK >> 187 HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_SHFT, 188 }, 189 { /* REO_REINJECT */ 190 .start_ring_id = HAL_SRNG_SW2REO, 191 .max_rings = 1, 192 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 193 .lmac_ring = FALSE, 194 .ring_dir = HAL_SRNG_SRC_RING, 195 .reg_start = { 196 HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR( 197 SEQ_WCSS_UMAC_REO_REG_OFFSET), 198 HWIO_REO_R2_SW2REO_RING_HP_ADDR( 199 SEQ_WCSS_UMAC_REO_REG_OFFSET) 200 }, 201 /* Single ring - provide ring size if multiple rings of this 202 * type are supported 203 */ 204 .reg_size = {}, 205 .max_size = HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_BMSK >> 206 HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_SHFT, 207 }, 208 { /* REO_CMD */ 209 .start_ring_id = HAL_SRNG_REO_CMD, 210 .max_rings = 1, 211 .entry_size = (sizeof(struct tlv_32_hdr) + 212 sizeof(struct reo_get_queue_stats)) >> 2, 213 .lmac_ring = FALSE, 214 .ring_dir = HAL_SRNG_SRC_RING, 215 .reg_start = { 216 HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR( 217 SEQ_WCSS_UMAC_REO_REG_OFFSET), 218 HWIO_REO_R2_REO_CMD_RING_HP_ADDR( 219 SEQ_WCSS_UMAC_REO_REG_OFFSET), 220 }, 221 /* Single ring - provide ring size if multiple rings of this 222 * type are supported 223 */ 224 .reg_size = {}, 225 .max_size = HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_BMSK >> 226 HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_SHFT, 227 }, 228 { /* REO_STATUS */ 229 .start_ring_id = HAL_SRNG_REO_STATUS, 230 .max_rings = 1, 231 .entry_size = (sizeof(struct tlv_32_hdr) + 232 sizeof(struct reo_get_queue_stats_status)) >> 2, 233 .lmac_ring = FALSE, 234 .ring_dir = HAL_SRNG_DST_RING, 235 .reg_start = { 236 HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR( 237 SEQ_WCSS_UMAC_REO_REG_OFFSET), 238 HWIO_REO_R2_REO_STATUS_RING_HP_ADDR( 239 SEQ_WCSS_UMAC_REO_REG_OFFSET), 240 }, 241 /* Single ring - provide ring size if multiple rings of this 242 * type are supported 243 */ 244 .reg_size = {}, 245 .max_size = 246 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> 247 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, 248 }, 249 { /* TCL_DATA */ 250 .start_ring_id = HAL_SRNG_SW2TCL1, 251 .max_rings = 3, 252 .entry_size = (sizeof(struct tlv_32_hdr) + 253 sizeof(struct tcl_data_cmd)) >> 2, 254 .lmac_ring = FALSE, 255 .ring_dir = HAL_SRNG_SRC_RING, 256 .reg_start = { 257 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR( 258 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 259 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR( 260 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 261 }, 262 .reg_size = { 263 HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(0) - 264 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(0), 265 HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(0) - 266 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(0), 267 }, 268 .max_size = 269 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK >> 270 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT, 271 }, 272 { /* TCL_CMD */ 273 .start_ring_id = HAL_SRNG_SW2TCL_CMD, 274 .max_rings = 1, 275 .entry_size = (sizeof(struct tlv_32_hdr) + 276 sizeof(struct tcl_gse_cmd)) >> 2, 277 .lmac_ring = FALSE, 278 .ring_dir = HAL_SRNG_SRC_RING, 279 .reg_start = { 280 HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_ADDR( 281 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 282 HWIO_TCL_R2_SW2TCL_CMD_RING_HP_ADDR( 283 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 284 }, 285 /* Single ring - provide ring size if multiple rings of this 286 * type are supported 287 */ 288 .reg_size = {}, 289 .max_size = 290 HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RING_SIZE_BMSK >> 291 HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RING_SIZE_SHFT, 292 }, 293 { /* TCL_STATUS */ 294 .start_ring_id = HAL_SRNG_TCL_STATUS, 295 .max_rings = 1, 296 .entry_size = (sizeof(struct tlv_32_hdr) + 297 sizeof(struct tcl_status_ring)) >> 2, 298 .lmac_ring = FALSE, 299 .ring_dir = HAL_SRNG_DST_RING, 300 .reg_start = { 301 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR( 302 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 303 HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR( 304 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 305 }, 306 /* Single ring - provide ring size if multiple rings of this 307 * type are supported 308 */ 309 .reg_size = {}, 310 .max_size = 311 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_BMSK >> 312 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_SHFT, 313 }, 314 { /* CE_SRC */ 315 .start_ring_id = HAL_SRNG_CE_0_SRC, 316 .max_rings = 12, 317 .entry_size = sizeof(struct ce_src_desc) >> 2, 318 .lmac_ring = FALSE, 319 .ring_dir = HAL_SRNG_SRC_RING, 320 .reg_start = { 321 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR( 322 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET), 323 HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR( 324 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET), 325 }, 326 .reg_size = { 327 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET - 328 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET, 329 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET - 330 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET, 331 }, 332 .max_size = 333 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >> 334 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT, 335 }, 336 { /* CE_DST */ 337 .start_ring_id = HAL_SRNG_CE_0_DST, 338 .max_rings = 12, 339 .entry_size = 8 >> 2, 340 /*TODO: entry_size above should actually be 341 * sizeof(struct ce_dst_desc) >> 2, but couldn't find definition 342 * of struct ce_dst_desc in HW header files 343 */ 344 .lmac_ring = FALSE, 345 .ring_dir = HAL_SRNG_SRC_RING, 346 .reg_start = { 347 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR( 348 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 349 HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR( 350 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 351 }, 352 .reg_size = { 353 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 354 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 355 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 356 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 357 }, 358 .max_size = 359 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >> 360 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT, 361 }, 362 { /* CE_DST_STATUS */ 363 .start_ring_id = HAL_SRNG_CE_0_DST_STATUS, 364 .max_rings = 12, 365 .entry_size = sizeof(struct ce_stat_desc) >> 2, 366 .lmac_ring = FALSE, 367 .ring_dir = HAL_SRNG_DST_RING, 368 .reg_start = { 369 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR( 370 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 371 HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR( 372 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 373 }, 374 /* TODO: check destination status ring registers */ 375 .reg_size = { 376 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 377 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 378 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 379 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 380 }, 381 .max_size = 382 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> 383 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, 384 }, 385 { /* WBM_IDLE_LINK */ 386 .start_ring_id = HAL_SRNG_WBM_IDLE_LINK, 387 .max_rings = 1, 388 .entry_size = sizeof(struct wbm_link_descriptor_ring) >> 2, 389 .lmac_ring = FALSE, 390 .ring_dir = HAL_SRNG_SRC_RING, 391 .reg_start = { 392 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 393 HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 394 }, 395 /* Single ring - provide ring size if multiple rings of this 396 * type are supported 397 */ 398 .reg_size = {}, 399 .max_size = 400 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_BMSK >> 401 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_SHFT, 402 }, 403 { /* SW2WBM_RELEASE */ 404 .start_ring_id = HAL_SRNG_WBM_SW_RELEASE, 405 .max_rings = 1, 406 .entry_size = sizeof(struct wbm_release_ring) >> 2, 407 .lmac_ring = FALSE, 408 .ring_dir = HAL_SRNG_SRC_RING, 409 .reg_start = { 410 HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 411 HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 412 }, 413 /* Single ring - provide ring size if multiple rings of this 414 * type are supported 415 */ 416 .reg_size = {}, 417 .max_size = 418 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> 419 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, 420 }, 421 { /* WBM2SW_RELEASE */ 422 .start_ring_id = HAL_SRNG_WBM2SW0_RELEASE, 423 .max_rings = 4, 424 .entry_size = sizeof(struct wbm_release_ring) >> 2, 425 .lmac_ring = FALSE, 426 .ring_dir = HAL_SRNG_DST_RING, 427 .reg_start = { 428 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 429 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 430 }, 431 .reg_size = { 432 HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) - 433 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 434 HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) - 435 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 436 }, 437 .max_size = 438 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> 439 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, 440 }, 441 { /* RXDMA_BUF */ 442 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA0_BUF0, 443 #ifdef IPA_OFFLOAD 444 .max_rings = 3, 445 #else 446 .max_rings = 2, 447 #endif 448 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 449 .lmac_ring = TRUE, 450 .ring_dir = HAL_SRNG_SRC_RING, 451 /* reg_start is not set because LMAC rings are not accessed 452 * from host 453 */ 454 .reg_start = {}, 455 .reg_size = {}, 456 .max_size = HAL_RXDMA_MAX_RING_SIZE, 457 }, 458 { /* RXDMA_DST */ 459 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW0, 460 .max_rings = 1, 461 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 462 .lmac_ring = TRUE, 463 .ring_dir = HAL_SRNG_DST_RING, 464 /* reg_start is not set because LMAC rings are not accessed 465 * from host 466 */ 467 .reg_start = {}, 468 .reg_size = {}, 469 .max_size = HAL_RXDMA_MAX_RING_SIZE, 470 }, 471 { /* RXDMA_MONITOR_BUF */ 472 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA2_BUF, 473 .max_rings = 1, 474 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 475 .lmac_ring = TRUE, 476 .ring_dir = HAL_SRNG_SRC_RING, 477 /* reg_start is not set because LMAC rings are not accessed 478 * from host 479 */ 480 .reg_start = {}, 481 .reg_size = {}, 482 .max_size = HAL_RXDMA_MAX_RING_SIZE, 483 }, 484 { /* RXDMA_MONITOR_STATUS */ 485 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_STATBUF, 486 .max_rings = 1, 487 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 488 .lmac_ring = TRUE, 489 .ring_dir = HAL_SRNG_SRC_RING, 490 /* reg_start is not set because LMAC rings are not accessed 491 * from host 492 */ 493 .reg_start = {}, 494 .reg_size = {}, 495 .max_size = HAL_RXDMA_MAX_RING_SIZE, 496 }, 497 { /* RXDMA_MONITOR_DST */ 498 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW1, 499 .max_rings = 1, 500 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 501 .lmac_ring = TRUE, 502 .ring_dir = HAL_SRNG_DST_RING, 503 /* reg_start is not set because LMAC rings are not accessed 504 * from host 505 */ 506 .reg_start = {}, 507 .reg_size = {}, 508 .max_size = HAL_RXDMA_MAX_RING_SIZE, 509 }, 510 { /* RXDMA_MONITOR_DESC */ 511 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_DESC, 512 .max_rings = 1, 513 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 514 .lmac_ring = TRUE, 515 .ring_dir = HAL_SRNG_SRC_RING, 516 /* reg_start is not set because LMAC rings are not accessed 517 * from host 518 */ 519 .reg_start = {}, 520 .reg_size = {}, 521 .max_size = HAL_RXDMA_MAX_RING_SIZE, 522 }, 523 { /* DIR_BUF_RX_DMA_SRC */ 524 .start_ring_id = HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING, 525 .max_rings = 1, 526 .entry_size = 2, 527 .lmac_ring = TRUE, 528 .ring_dir = HAL_SRNG_SRC_RING, 529 /* reg_start is not set because LMAC rings are not accessed 530 * from host 531 */ 532 .reg_start = {}, 533 .reg_size = {}, 534 .max_size = HAL_RXDMA_MAX_RING_SIZE, 535 }, 536 #ifdef WLAN_FEATURE_CIF_CFR 537 { /* WIFI_POS_SRC */ 538 .start_ring_id = HAL_SRNG_WIFI_POS_SRC_DMA_RING, 539 .max_rings = 1, 540 .entry_size = sizeof(wmi_oem_dma_buf_release_entry) >> 2, 541 .lmac_ring = TRUE, 542 .ring_dir = HAL_SRNG_SRC_RING, 543 /* reg_start is not set because LMAC rings are not accessed 544 * from host 545 */ 546 .reg_start = {}, 547 .reg_size = {}, 548 .max_size = HAL_RXDMA_MAX_RING_SIZE, 549 }, 550 #endif 551 }; 552 553 int32_t hal_hw_reg_offset_qca8074v2[] = { 554 /* dst */ 555 REG_OFFSET(DST, HP), 556 REG_OFFSET(DST, TP), 557 REG_OFFSET(DST, ID), 558 REG_OFFSET(DST, MISC), 559 REG_OFFSET(DST, HP_ADDR_LSB), 560 REG_OFFSET(DST, HP_ADDR_MSB), 561 REG_OFFSET(DST, MSI1_BASE_LSB), 562 REG_OFFSET(DST, MSI1_BASE_MSB), 563 REG_OFFSET(DST, MSI1_DATA), 564 REG_OFFSET(DST, BASE_LSB), 565 REG_OFFSET(DST, BASE_MSB), 566 REG_OFFSET(DST, PRODUCER_INT_SETUP), 567 /* src */ 568 REG_OFFSET(SRC, HP), 569 REG_OFFSET(SRC, TP), 570 REG_OFFSET(SRC, ID), 571 REG_OFFSET(SRC, MISC), 572 REG_OFFSET(SRC, TP_ADDR_LSB), 573 REG_OFFSET(SRC, TP_ADDR_MSB), 574 REG_OFFSET(SRC, MSI1_BASE_LSB), 575 REG_OFFSET(SRC, MSI1_BASE_MSB), 576 REG_OFFSET(SRC, MSI1_DATA), 577 REG_OFFSET(SRC, BASE_LSB), 578 REG_OFFSET(SRC, BASE_MSB), 579 REG_OFFSET(SRC, CONSUMER_INT_SETUP_IX0), 580 REG_OFFSET(SRC, CONSUMER_INT_SETUP_IX1), 581 }; 582 583 584 /** 585 * hal_qca8074v2_attach() - Attach 8074v2 target specific hal_soc ops, 586 * offset and srng table 587 */ 588 void hal_qca8074v2_attach(struct hal_soc *hal_soc) 589 { 590 hal_soc->hw_srng_table = hw_srng_table_8074v2; 591 hal_soc->hal_hw_reg_offset = hal_hw_reg_offset_qca8074v2; 592 hal_soc->ops = &qca8074v2_hal_hw_txrx_ops; 593 } 594 595 596 597