1 /* 2 * Copyright (c) 2016-2020 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 #include "hal_hw_headers.h" 19 #include "hal_internal.h" 20 #include "cdp_txrx_mon_struct.h" 21 #include "qdf_trace.h" 22 #include "hal_rx.h" 23 #include "hal_tx.h" 24 #include "dp_types.h" 25 #include "hal_api_mon.h" 26 27 #define HAL_RX_MPDU_GET_SEQUENCE_NUMBER(_rx_mpdu_info) \ 28 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 29 RX_MPDU_INFO_2_MPDU_SEQUENCE_NUMBER_OFFSET)), \ 30 RX_MPDU_INFO_2_MPDU_SEQUENCE_NUMBER_MASK, \ 31 RX_MPDU_INFO_2_MPDU_SEQUENCE_NUMBER_LSB)) 32 33 #define HAL_RX_MSDU_END_DA_IS_MCBC_GET(_rx_msdu_end) \ 34 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 35 RX_MSDU_END_5_DA_IS_MCBC_OFFSET)), \ 36 RX_MSDU_END_5_DA_IS_MCBC_MASK, \ 37 RX_MSDU_END_5_DA_IS_MCBC_LSB)) 38 39 #define HAL_RX_MSDU_END_SA_IS_VALID_GET(_rx_msdu_end) \ 40 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 41 RX_MSDU_END_5_SA_IS_VALID_OFFSET)), \ 42 RX_MSDU_END_5_SA_IS_VALID_MASK, \ 43 RX_MSDU_END_5_SA_IS_VALID_LSB)) 44 45 #define HAL_RX_MSDU_END_SA_IDX_GET(_rx_msdu_end) \ 46 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 47 RX_MSDU_END_13_SA_IDX_OFFSET)), \ 48 RX_MSDU_END_13_SA_IDX_MASK, \ 49 RX_MSDU_END_13_SA_IDX_LSB)) 50 51 #define HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(_rx_msdu_end) \ 52 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 53 RX_MSDU_END_5_L3_HEADER_PADDING_OFFSET)), \ 54 RX_MSDU_END_5_L3_HEADER_PADDING_MASK, \ 55 RX_MSDU_END_5_L3_HEADER_PADDING_LSB)) 56 57 #define HAL_RX_MPDU_ENCRYPTION_INFO_VALID(_rx_mpdu_info) \ 58 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 59 RX_MPDU_INFO_2_FRAME_ENCRYPTION_INFO_VALID_OFFSET)), \ 60 RX_MPDU_INFO_2_FRAME_ENCRYPTION_INFO_VALID_MASK, \ 61 RX_MPDU_INFO_2_FRAME_ENCRYPTION_INFO_VALID_LSB)) 62 63 #define HAL_RX_MPDU_PN_31_0_GET(_rx_mpdu_info) \ 64 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 65 RX_MPDU_INFO_4_PN_31_0_OFFSET)), \ 66 RX_MPDU_INFO_4_PN_31_0_MASK, \ 67 RX_MPDU_INFO_4_PN_31_0_LSB)) 68 69 #define HAL_RX_MPDU_PN_63_32_GET(_rx_mpdu_info) \ 70 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 71 RX_MPDU_INFO_5_PN_63_32_OFFSET)), \ 72 RX_MPDU_INFO_5_PN_63_32_MASK, \ 73 RX_MPDU_INFO_5_PN_63_32_LSB)) 74 75 #define HAL_RX_MPDU_PN_95_64_GET(_rx_mpdu_info) \ 76 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 77 RX_MPDU_INFO_6_PN_95_64_OFFSET)), \ 78 RX_MPDU_INFO_6_PN_95_64_MASK, \ 79 RX_MPDU_INFO_6_PN_95_64_LSB)) 80 81 #define HAL_RX_MPDU_PN_127_96_GET(_rx_mpdu_info) \ 82 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 83 RX_MPDU_INFO_7_PN_127_96_OFFSET)), \ 84 RX_MPDU_INFO_7_PN_127_96_MASK, \ 85 RX_MPDU_INFO_7_PN_127_96_LSB)) 86 87 #define HAL_RX_MSDU_END_FIRST_MSDU_GET(_rx_msdu_end) \ 88 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 89 RX_MSDU_END_5_FIRST_MSDU_OFFSET)), \ 90 RX_MSDU_END_5_FIRST_MSDU_MASK, \ 91 RX_MSDU_END_5_FIRST_MSDU_LSB)) 92 93 #define HAL_RX_MSDU_END_DA_IS_VALID_GET(_rx_msdu_end) \ 94 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 95 RX_MSDU_END_5_DA_IS_VALID_OFFSET)), \ 96 RX_MSDU_END_5_DA_IS_VALID_MASK, \ 97 RX_MSDU_END_5_DA_IS_VALID_LSB)) 98 99 #define HAL_RX_MSDU_END_LAST_MSDU_GET(_rx_msdu_end) \ 100 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 101 RX_MSDU_END_5_LAST_MSDU_OFFSET)), \ 102 RX_MSDU_END_5_LAST_MSDU_MASK, \ 103 RX_MSDU_END_5_LAST_MSDU_LSB)) 104 105 #define HAL_RX_MPDU_GET_MAC_AD4_VALID(_rx_mpdu_info) \ 106 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 107 RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_OFFSET)), \ 108 RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_MASK, \ 109 RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_LSB)) 110 111 #define HAL_RX_MPDU_INFO_SW_PEER_ID_GET(_rx_mpdu_info) \ 112 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_info), \ 113 RX_MPDU_INFO_1_SW_PEER_ID_OFFSET)), \ 114 RX_MPDU_INFO_1_SW_PEER_ID_MASK, \ 115 RX_MPDU_INFO_1_SW_PEER_ID_LSB)) 116 117 #define HAL_RX_MPDU_GET_TODS(_rx_mpdu_info) \ 118 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 119 RX_MPDU_INFO_2_TO_DS_OFFSET)), \ 120 RX_MPDU_INFO_2_TO_DS_MASK, \ 121 RX_MPDU_INFO_2_TO_DS_LSB)) 122 123 #define HAL_RX_MPDU_GET_FROMDS(_rx_mpdu_info) \ 124 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 125 RX_MPDU_INFO_2_FR_DS_OFFSET)), \ 126 RX_MPDU_INFO_2_FR_DS_MASK, \ 127 RX_MPDU_INFO_2_FR_DS_LSB)) 128 129 #define HAL_RX_MPDU_GET_FRAME_CONTROL_VALID(_rx_mpdu_info) \ 130 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 131 RX_MPDU_INFO_2_MPDU_FRAME_CONTROL_VALID_OFFSET)), \ 132 RX_MPDU_INFO_2_MPDU_FRAME_CONTROL_VALID_MASK, \ 133 RX_MPDU_INFO_2_MPDU_FRAME_CONTROL_VALID_LSB)) 134 135 #define HAL_RX_MPDU_MAC_ADDR_AD1_VALID_GET(_rx_mpdu_info) \ 136 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 137 RX_MPDU_INFO_2_MAC_ADDR_AD1_VALID_OFFSET)), \ 138 RX_MPDU_INFO_2_MAC_ADDR_AD1_VALID_MASK, \ 139 RX_MPDU_INFO_2_MAC_ADDR_AD1_VALID_LSB)) 140 141 #define HAL_RX_MPDU_AD1_31_0_GET(_rx_mpdu_info) \ 142 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 143 RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_OFFSET)), \ 144 RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_MASK, \ 145 RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_LSB)) 146 147 #define HAL_RX_MPDU_AD1_47_32_GET(_rx_mpdu_info) \ 148 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 149 RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_OFFSET)), \ 150 RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_MASK, \ 151 RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_LSB)) 152 153 #define HAL_RX_MPDU_MAC_ADDR_AD2_VALID_GET(_rx_mpdu_info) \ 154 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 155 RX_MPDU_INFO_2_MAC_ADDR_AD2_VALID_OFFSET)), \ 156 RX_MPDU_INFO_2_MAC_ADDR_AD2_VALID_MASK, \ 157 RX_MPDU_INFO_2_MAC_ADDR_AD2_VALID_LSB)) 158 159 #define HAL_RX_MPDU_AD2_15_0_GET(_rx_mpdu_info) \ 160 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 161 RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_OFFSET)), \ 162 RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_MASK, \ 163 RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_LSB)) 164 165 #define HAL_RX_MPDU_AD2_47_16_GET(_rx_mpdu_info) \ 166 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 167 RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_OFFSET)), \ 168 RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_MASK, \ 169 RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_LSB)) 170 171 #define HAL_RX_MPDU_MAC_ADDR_AD3_VALID_GET(_rx_mpdu_info) \ 172 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 173 RX_MPDU_INFO_2_MAC_ADDR_AD3_VALID_OFFSET)), \ 174 RX_MPDU_INFO_2_MAC_ADDR_AD3_VALID_MASK, \ 175 RX_MPDU_INFO_2_MAC_ADDR_AD3_VALID_LSB)) 176 177 #define HAL_RX_MPDU_AD3_31_0_GET(_rx_mpdu_info) \ 178 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 179 RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_OFFSET)), \ 180 RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_MASK, \ 181 RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_LSB)) 182 183 #define HAL_RX_MPDU_AD3_47_32_GET(_rx_mpdu_info) \ 184 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 185 RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_OFFSET)), \ 186 RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_MASK, \ 187 RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_LSB)) 188 189 #define HAL_RX_MPDU_MAC_ADDR_AD4_VALID_GET(_rx_mpdu_info) \ 190 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 191 RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_OFFSET)), \ 192 RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_MASK, \ 193 RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_LSB)) 194 195 #define HAL_RX_MPDU_AD4_31_0_GET(_rx_mpdu_info) \ 196 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 197 RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_OFFSET)), \ 198 RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_MASK, \ 199 RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_LSB)) 200 201 #define HAL_RX_MPDU_AD4_47_32_GET(_rx_mpdu_info) \ 202 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 203 RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_OFFSET)), \ 204 RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_MASK, \ 205 RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_LSB)) 206 207 #define HAL_RX_MPDU_GET_SEQUENCE_CONTROL_VALID(_rx_mpdu_info) \ 208 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 209 RX_MPDU_INFO_2_MPDU_SEQUENCE_CONTROL_VALID_OFFSET)), \ 210 RX_MPDU_INFO_2_MPDU_SEQUENCE_CONTROL_VALID_MASK, \ 211 RX_MPDU_INFO_2_MPDU_SEQUENCE_CONTROL_VALID_LSB)) 212 213 #define HAL_RX_MPDU_INFO_QOS_CONTROL_VALID_GET(_rx_mpdu_info) \ 214 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_info), \ 215 RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_OFFSET)), \ 216 RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_MASK, \ 217 RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_LSB)) 218 219 #define HAL_RX_MSDU_END_SA_SW_PEER_ID_GET(_rx_msdu_end) \ 220 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 221 RX_MSDU_END_16_SA_SW_PEER_ID_OFFSET)), \ 222 RX_MSDU_END_16_SA_SW_PEER_ID_MASK, \ 223 RX_MSDU_END_16_SA_SW_PEER_ID_LSB)) 224 225 #define HAL_RX_MSDU0_BUFFER_ADDR_LSB(link_desc_va) \ 226 (uint8_t *)(link_desc_va) + \ 227 RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET 228 229 #define HAL_RX_MSDU_DESC_INFO_PTR_GET(msdu0) \ 230 (uint8_t *)(msdu0) + \ 231 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET 232 233 #define HAL_ENT_MPDU_DESC_INFO(ent_ring_desc) \ 234 (uint8_t *)(ent_ring_desc) + \ 235 RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET 236 237 #define HAL_DST_MPDU_DESC_INFO(dst_ring_desc) \ 238 (uint8_t *)(dst_ring_desc) + \ 239 REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET 240 241 #define HAL_RX_GET_FC_VALID(rx_mpdu_start) \ 242 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_2, MPDU_FRAME_CONTROL_VALID) 243 244 #define HAL_RX_GET_TO_DS_FLAG(rx_mpdu_start) \ 245 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_2, TO_DS) 246 247 #define HAL_RX_GET_MAC_ADDR1_VALID(rx_mpdu_start) \ 248 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_2, MAC_ADDR_AD1_VALID) 249 250 #define HAL_RX_GET_MAC_ADDR2_VALID(rx_mpdu_start) \ 251 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_2, MAC_ADDR_AD2_VALID) 252 253 #define HAL_RX_GET_FILTER_CATEGORY(rx_mpdu_start) \ 254 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_0, RXPCU_MPDU_FILTER_IN_CATEGORY) 255 256 #define HAL_RX_GET_PPDU_ID(rx_mpdu_start) \ 257 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_0, PHY_PPDU_ID) 258 259 #define HAL_RX_GET_SW_FRAME_GROUP_ID(rx_mpdu_start) \ 260 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_0, SW_FRAME_GROUP_ID) 261 262 #define HAL_REO_R0_CONFIG(soc, reg_val, reo_params) \ 263 do { \ 264 reg_val &= \ 265 ~(HWIO_REO_R0_GENERAL_ENABLE_FRAGMENT_DEST_RING_BMSK |\ 266 HWIO_REO_R0_GENERAL_ENABLE_AGING_LIST_ENABLE_BMSK | \ 267 HWIO_REO_R0_GENERAL_ENABLE_AGING_FLUSH_ENABLE_BMSK); \ 268 reg_val |= \ 269 HAL_SM(HWIO_REO_R0_GENERAL_ENABLE, \ 270 FRAGMENT_DEST_RING, \ 271 (reo_params)->frag_dst_ring) | \ 272 HAL_SM(HWIO_REO_R0_GENERAL_ENABLE, \ 273 AGING_LIST_ENABLE, 1) |\ 274 HAL_SM(HWIO_REO_R0_GENERAL_ENABLE, \ 275 AGING_FLUSH_ENABLE, 1);\ 276 HAL_REG_WRITE((soc), \ 277 HWIO_REO_R0_GENERAL_ENABLE_ADDR( \ 278 SEQ_WCSS_UMAC_REO_REG_OFFSET),\ 279 (reg_val)); \ 280 } while (0) 281 282 #define HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr) \ 283 ((struct rx_msdu_desc_info *) \ 284 _OFFSET_TO_BYTE_PTR((msdu_details_ptr), \ 285 UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET)) 286 287 #define HAL_RX_LINK_DESC_MSDU0_PTR(link_desc) \ 288 ((struct rx_msdu_details *) \ 289 _OFFSET_TO_BYTE_PTR((link_desc),\ 290 UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET)) 291 292 #define HAL_RX_MSDU_END_FLOW_IDX_GET(_rx_msdu_end) \ 293 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 294 RX_MSDU_END_14_FLOW_IDX_OFFSET)), \ 295 RX_MSDU_END_14_FLOW_IDX_MASK, \ 296 RX_MSDU_END_14_FLOW_IDX_LSB)) 297 298 #define HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(_rx_msdu_end) \ 299 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 300 RX_MSDU_END_5_FLOW_IDX_INVALID_OFFSET)), \ 301 RX_MSDU_END_5_FLOW_IDX_INVALID_MASK, \ 302 RX_MSDU_END_5_FLOW_IDX_INVALID_LSB)) 303 304 #define HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(_rx_msdu_end) \ 305 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 306 RX_MSDU_END_5_FLOW_IDX_TIMEOUT_OFFSET)), \ 307 RX_MSDU_END_5_FLOW_IDX_TIMEOUT_MASK, \ 308 RX_MSDU_END_5_FLOW_IDX_TIMEOUT_LSB)) 309 310 #define HAL_RX_MSDU_END_FSE_METADATA_GET(_rx_msdu_end) \ 311 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 312 RX_MSDU_END_15_FSE_METADATA_OFFSET)), \ 313 RX_MSDU_END_15_FSE_METADATA_MASK, \ 314 RX_MSDU_END_15_FSE_METADATA_LSB)) 315 316 #define HAL_RX_MSDU_END_CCE_METADATA_GET(_rx_msdu_end) \ 317 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 318 RX_MSDU_END_16_CCE_METADATA_OFFSET)), \ 319 RX_MSDU_END_16_CCE_METADATA_MASK, \ 320 RX_MSDU_END_16_CCE_METADATA_LSB)) 321 322 #define HAL_RX_TLV_GET_TCP_CHKSUM(buf) \ 323 (_HAL_MS( \ 324 (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ 325 msdu_end_tlv.rx_msdu_end), \ 326 RX_MSDU_END_1_TCP_UDP_CHKSUM_OFFSET)), \ 327 RX_MSDU_END_1_TCP_UDP_CHKSUM_MASK, \ 328 RX_MSDU_END_1_TCP_UDP_CHKSUM_LSB)) 329 330 /* 331 * hal_rx_msdu_start_nss_get_8074(): API to get the NSS 332 * Interval from rx_msdu_start 333 * 334 * @buf: pointer to the start of RX PKT TLV header 335 * Return: uint32_t(nss) 336 */ 337 static uint32_t 338 hal_rx_msdu_start_nss_get_8074(uint8_t *buf) 339 { 340 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 341 struct rx_msdu_start *msdu_start = 342 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 343 uint32_t nss; 344 345 nss = HAL_RX_MSDU_START_NSS_GET(msdu_start); 346 return nss; 347 } 348 349 /** 350 * hal_rx_mon_hw_desc_get_mpdu_status_8074(): Retrieve MPDU status 351 * 352 * @ hw_desc_addr: Start address of Rx HW TLVs 353 * @ rs: Status for monitor mode 354 * 355 * Return: void 356 */ 357 static void hal_rx_mon_hw_desc_get_mpdu_status_8074(void *hw_desc_addr, 358 struct mon_rx_status *rs) 359 { 360 struct rx_msdu_start *rx_msdu_start; 361 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr; 362 uint32_t reg_value; 363 const uint32_t sgi_hw_to_cdp[] = { 364 CDP_SGI_0_8_US, 365 CDP_SGI_0_4_US, 366 CDP_SGI_1_6_US, 367 CDP_SGI_3_2_US, 368 }; 369 370 rx_msdu_start = &rx_desc->msdu_start_tlv.rx_msdu_start; 371 372 HAL_RX_GET_MSDU_AGGREGATION(rx_desc, rs); 373 374 rs->ant_signal_db = HAL_RX_GET(rx_msdu_start, 375 RX_MSDU_START_5, USER_RSSI); 376 rs->is_stbc = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, STBC); 377 378 reg_value = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, SGI); 379 rs->sgi = sgi_hw_to_cdp[reg_value]; 380 rs->nr_ant = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, NSS); 381 reg_value = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, RECEPTION_TYPE); 382 rs->beamformed = (reg_value == HAL_RX_RECEPTION_TYPE_MU_MIMO) ? 1 : 0; 383 /* TODO: rs->beamformed should be set for SU beamforming also */ 384 } 385 386 #define LINK_DESC_SIZE (NUM_OF_DWORDS_RX_MSDU_LINK << 2) 387 static uint32_t hal_get_link_desc_size_8074(void) 388 { 389 return LINK_DESC_SIZE; 390 } 391 392 /* 393 * hal_rx_get_tlv_8074(): API to get the tlv 394 * 395 * @rx_tlv: TLV data extracted from the rx packet 396 * Return: uint8_t 397 */ 398 static uint8_t hal_rx_get_tlv_8074(void *rx_tlv) 399 { 400 return HAL_RX_GET(rx_tlv, PHYRX_RSSI_LEGACY_35, RECEIVE_BANDWIDTH); 401 } 402 403 /** 404 * hal_rx_proc_phyrx_other_receive_info_tlv_8074() 405 * -process other receive info TLV 406 * @rx_tlv_hdr: pointer to TLV header 407 * @ppdu_info: pointer to ppdu_info 408 * 409 * Return: None 410 */ 411 static 412 void hal_rx_proc_phyrx_other_receive_info_tlv_8074(void *rx_tlv_hdr, 413 void *ppdu_info) 414 { 415 } 416 417 418 /** 419 * hal_rx_dump_msdu_start_tlv_8074() : dump RX msdu_start TLV in structured 420 * human readable format. 421 * @ msdu_start: pointer the msdu_start TLV in pkt. 422 * @ dbg_level: log level. 423 * 424 * Return: void 425 */ 426 static void hal_rx_dump_msdu_start_tlv_8074(void *msdustart, 427 uint8_t dbg_level) 428 { 429 struct rx_msdu_start *msdu_start = (struct rx_msdu_start *)msdustart; 430 431 QDF_TRACE(QDF_MODULE_ID_DP, dbg_level, 432 "rx_msdu_start tlv - " 433 "rxpcu_mpdu_filter_in_category: %d " 434 "sw_frame_group_id: %d " 435 "phy_ppdu_id: %d " 436 "msdu_length: %d " 437 "ipsec_esp: %d " 438 "l3_offset: %d " 439 "ipsec_ah: %d " 440 "l4_offset: %d " 441 "msdu_number: %d " 442 "decap_format: %d " 443 "ipv4_proto: %d " 444 "ipv6_proto: %d " 445 "tcp_proto: %d " 446 "udp_proto: %d " 447 "ip_frag: %d " 448 "tcp_only_ack: %d " 449 "da_is_bcast_mcast: %d " 450 "ip4_protocol_ip6_next_header: %d " 451 "toeplitz_hash_2_or_4: %d " 452 "flow_id_toeplitz: %d " 453 "user_rssi: %d " 454 "pkt_type: %d " 455 "stbc: %d " 456 "sgi: %d " 457 "rate_mcs: %d " 458 "receive_bandwidth: %d " 459 "reception_type: %d " 460 "toeplitz_hash: %d " 461 "nss: %d " 462 "ppdu_start_timestamp: %d " 463 "sw_phy_meta_data: %d ", 464 msdu_start->rxpcu_mpdu_filter_in_category, 465 msdu_start->sw_frame_group_id, 466 msdu_start->phy_ppdu_id, 467 msdu_start->msdu_length, 468 msdu_start->ipsec_esp, 469 msdu_start->l3_offset, 470 msdu_start->ipsec_ah, 471 msdu_start->l4_offset, 472 msdu_start->msdu_number, 473 msdu_start->decap_format, 474 msdu_start->ipv4_proto, 475 msdu_start->ipv6_proto, 476 msdu_start->tcp_proto, 477 msdu_start->udp_proto, 478 msdu_start->ip_frag, 479 msdu_start->tcp_only_ack, 480 msdu_start->da_is_bcast_mcast, 481 msdu_start->ip4_protocol_ip6_next_header, 482 msdu_start->toeplitz_hash_2_or_4, 483 msdu_start->flow_id_toeplitz, 484 msdu_start->user_rssi, 485 msdu_start->pkt_type, 486 msdu_start->stbc, 487 msdu_start->sgi, 488 msdu_start->rate_mcs, 489 msdu_start->receive_bandwidth, 490 msdu_start->reception_type, 491 msdu_start->toeplitz_hash, 492 msdu_start->nss, 493 msdu_start->ppdu_start_timestamp, 494 msdu_start->sw_phy_meta_data); 495 } 496 497 /** 498 * hal_rx_dump_msdu_end_tlv_8074: dump RX msdu_end TLV in structured 499 * human readable format. 500 * @ msdu_end: pointer the msdu_end TLV in pkt. 501 * @ dbg_level: log level. 502 * 503 * Return: void 504 */ 505 static void hal_rx_dump_msdu_end_tlv_8074(void *msduend, 506 uint8_t dbg_level) 507 { 508 struct rx_msdu_end *msdu_end = (struct rx_msdu_end *)msduend; 509 510 QDF_TRACE(QDF_MODULE_ID_DP, dbg_level, 511 "rx_msdu_end tlv - " 512 "rxpcu_mpdu_filter_in_category: %d " 513 "sw_frame_group_id: %d " 514 "phy_ppdu_id: %d " 515 "ip_hdr_chksum: %d " 516 "tcp_udp_chksum: %d " 517 "key_id_octet: %d " 518 "cce_super_rule: %d " 519 "cce_classify_not_done_truncat: %d " 520 "cce_classify_not_done_cce_dis: %d " 521 "ext_wapi_pn_63_48: %d " 522 "ext_wapi_pn_95_64: %d " 523 "ext_wapi_pn_127_96: %d " 524 "reported_mpdu_length: %d " 525 "first_msdu: %d " 526 "last_msdu: %d " 527 "sa_idx_timeout: %d " 528 "da_idx_timeout: %d " 529 "msdu_limit_error: %d " 530 "flow_idx_timeout: %d " 531 "flow_idx_invalid: %d " 532 "wifi_parser_error: %d " 533 "amsdu_parser_error: %d " 534 "sa_is_valid: %d " 535 "da_is_valid: %d " 536 "da_is_mcbc: %d " 537 "l3_header_padding: %d " 538 "ipv6_options_crc: %d " 539 "tcp_seq_number: %d " 540 "tcp_ack_number: %d " 541 "tcp_flag: %d " 542 "lro_eligible: %d " 543 "window_size: %d " 544 "da_offset: %d " 545 "sa_offset: %d " 546 "da_offset_valid: %d " 547 "sa_offset_valid: %d " 548 "rule_indication_31_0: %d " 549 "rule_indication_63_32: %d " 550 "sa_idx: %d " 551 "da_idx: %d " 552 "msdu_drop: %d " 553 "reo_destination_indication: %d " 554 "flow_idx: %d " 555 "fse_metadata: %d " 556 "cce_metadata: %d " 557 "sa_sw_peer_id: %d ", 558 msdu_end->rxpcu_mpdu_filter_in_category, 559 msdu_end->sw_frame_group_id, 560 msdu_end->phy_ppdu_id, 561 msdu_end->ip_hdr_chksum, 562 msdu_end->tcp_udp_chksum, 563 msdu_end->key_id_octet, 564 msdu_end->cce_super_rule, 565 msdu_end->cce_classify_not_done_truncate, 566 msdu_end->cce_classify_not_done_cce_dis, 567 msdu_end->ext_wapi_pn_63_48, 568 msdu_end->ext_wapi_pn_95_64, 569 msdu_end->ext_wapi_pn_127_96, 570 msdu_end->reported_mpdu_length, 571 msdu_end->first_msdu, 572 msdu_end->last_msdu, 573 msdu_end->sa_idx_timeout, 574 msdu_end->da_idx_timeout, 575 msdu_end->msdu_limit_error, 576 msdu_end->flow_idx_timeout, 577 msdu_end->flow_idx_invalid, 578 msdu_end->wifi_parser_error, 579 msdu_end->amsdu_parser_error, 580 msdu_end->sa_is_valid, 581 msdu_end->da_is_valid, 582 msdu_end->da_is_mcbc, 583 msdu_end->l3_header_padding, 584 msdu_end->ipv6_options_crc, 585 msdu_end->tcp_seq_number, 586 msdu_end->tcp_ack_number, 587 msdu_end->tcp_flag, 588 msdu_end->lro_eligible, 589 msdu_end->window_size, 590 msdu_end->da_offset, 591 msdu_end->sa_offset, 592 msdu_end->da_offset_valid, 593 msdu_end->sa_offset_valid, 594 msdu_end->rule_indication_31_0, 595 msdu_end->rule_indication_63_32, 596 msdu_end->sa_idx, 597 msdu_end->da_idx, 598 msdu_end->msdu_drop, 599 msdu_end->reo_destination_indication, 600 msdu_end->flow_idx, 601 msdu_end->fse_metadata, 602 msdu_end->cce_metadata, 603 msdu_end->sa_sw_peer_id); 604 } 605 606 607 /* 608 * Get tid from RX_MPDU_START 609 */ 610 #define HAL_RX_MPDU_INFO_TID_GET(_rx_mpdu_info) \ 611 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_info), \ 612 RX_MPDU_INFO_3_TID_OFFSET)), \ 613 RX_MPDU_INFO_3_TID_MASK, \ 614 RX_MPDU_INFO_3_TID_LSB)) 615 616 static uint32_t hal_rx_mpdu_start_tid_get_8074(uint8_t *buf) 617 { 618 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 619 struct rx_mpdu_start *mpdu_start = 620 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 621 uint32_t tid; 622 623 tid = HAL_RX_MPDU_INFO_TID_GET(&mpdu_start->rx_mpdu_info_details); 624 625 return tid; 626 } 627 628 #define HAL_RX_MSDU_START_RECEPTION_TYPE_GET(_rx_msdu_start) \ 629 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start), \ 630 RX_MSDU_START_5_RECEPTION_TYPE_OFFSET)), \ 631 RX_MSDU_START_5_RECEPTION_TYPE_MASK, \ 632 RX_MSDU_START_5_RECEPTION_TYPE_LSB)) 633 634 /* 635 * hal_rx_msdu_start_reception_type_get(): API to get the reception type 636 * Interval from rx_msdu_start 637 * 638 * @buf: pointer to the start of RX PKT TLV header 639 * Return: uint32_t(reception_type) 640 */ 641 static uint32_t hal_rx_msdu_start_reception_type_get_8074(uint8_t *buf) 642 { 643 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 644 struct rx_msdu_start *msdu_start = 645 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 646 uint32_t reception_type; 647 648 reception_type = HAL_RX_MSDU_START_RECEPTION_TYPE_GET(msdu_start); 649 650 return reception_type; 651 } 652 653 #define HAL_RX_MSDU_END_DA_IDX_GET(_rx_msdu_end) \ 654 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 655 RX_MSDU_END_13_DA_IDX_OFFSET)), \ 656 RX_MSDU_END_13_DA_IDX_MASK, \ 657 RX_MSDU_END_13_DA_IDX_LSB)) 658 659 /** 660 * hal_rx_msdu_end_da_idx_get_8074: API to get da_idx 661 * from rx_msdu_end TLV 662 * 663 * @ buf: pointer to the start of RX PKT TLV headers 664 * Return: da index 665 */ 666 static uint16_t hal_rx_msdu_end_da_idx_get_8074(uint8_t *buf) 667 { 668 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 669 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 670 uint16_t da_idx; 671 672 da_idx = HAL_RX_MSDU_END_DA_IDX_GET(msdu_end); 673 674 return da_idx; 675 } 676