1 /* 2 * Copyright (c) 2016-2020 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 #include "hal_hw_headers.h" 19 #include "hal_internal.h" 20 #include "cdp_txrx_mon_struct.h" 21 #include "qdf_trace.h" 22 #include "hal_rx.h" 23 #include "hal_tx.h" 24 #include "dp_types.h" 25 #include "hal_api_mon.h" 26 27 #define HAL_RX_MPDU_GET_SEQUENCE_NUMBER(_rx_mpdu_info) \ 28 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 29 RX_MPDU_INFO_2_MPDU_SEQUENCE_NUMBER_OFFSET)), \ 30 RX_MPDU_INFO_2_MPDU_SEQUENCE_NUMBER_MASK, \ 31 RX_MPDU_INFO_2_MPDU_SEQUENCE_NUMBER_LSB)) 32 33 #define HAL_RX_MSDU_END_DA_IS_MCBC_GET(_rx_msdu_end) \ 34 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 35 RX_MSDU_END_5_DA_IS_MCBC_OFFSET)), \ 36 RX_MSDU_END_5_DA_IS_MCBC_MASK, \ 37 RX_MSDU_END_5_DA_IS_MCBC_LSB)) 38 39 #define HAL_RX_MSDU_END_SA_IS_VALID_GET(_rx_msdu_end) \ 40 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 41 RX_MSDU_END_5_SA_IS_VALID_OFFSET)), \ 42 RX_MSDU_END_5_SA_IS_VALID_MASK, \ 43 RX_MSDU_END_5_SA_IS_VALID_LSB)) 44 45 #define HAL_RX_MSDU_END_SA_IDX_GET(_rx_msdu_end) \ 46 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 47 RX_MSDU_END_13_SA_IDX_OFFSET)), \ 48 RX_MSDU_END_13_SA_IDX_MASK, \ 49 RX_MSDU_END_13_SA_IDX_LSB)) 50 51 #define HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(_rx_msdu_end) \ 52 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 53 RX_MSDU_END_5_L3_HEADER_PADDING_OFFSET)), \ 54 RX_MSDU_END_5_L3_HEADER_PADDING_MASK, \ 55 RX_MSDU_END_5_L3_HEADER_PADDING_LSB)) 56 57 #define HAL_RX_MPDU_ENCRYPTION_INFO_VALID(_rx_mpdu_info) \ 58 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 59 RX_MPDU_INFO_2_FRAME_ENCRYPTION_INFO_VALID_OFFSET)), \ 60 RX_MPDU_INFO_2_FRAME_ENCRYPTION_INFO_VALID_MASK, \ 61 RX_MPDU_INFO_2_FRAME_ENCRYPTION_INFO_VALID_LSB)) 62 63 #define HAL_RX_MPDU_PN_31_0_GET(_rx_mpdu_info) \ 64 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 65 RX_MPDU_INFO_4_PN_31_0_OFFSET)), \ 66 RX_MPDU_INFO_4_PN_31_0_MASK, \ 67 RX_MPDU_INFO_4_PN_31_0_LSB)) 68 69 #define HAL_RX_MPDU_PN_63_32_GET(_rx_mpdu_info) \ 70 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 71 RX_MPDU_INFO_5_PN_63_32_OFFSET)), \ 72 RX_MPDU_INFO_5_PN_63_32_MASK, \ 73 RX_MPDU_INFO_5_PN_63_32_LSB)) 74 75 #define HAL_RX_MPDU_PN_95_64_GET(_rx_mpdu_info) \ 76 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 77 RX_MPDU_INFO_6_PN_95_64_OFFSET)), \ 78 RX_MPDU_INFO_6_PN_95_64_MASK, \ 79 RX_MPDU_INFO_6_PN_95_64_LSB)) 80 81 #define HAL_RX_MPDU_PN_127_96_GET(_rx_mpdu_info) \ 82 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 83 RX_MPDU_INFO_7_PN_127_96_OFFSET)), \ 84 RX_MPDU_INFO_7_PN_127_96_MASK, \ 85 RX_MPDU_INFO_7_PN_127_96_LSB)) 86 87 #define HAL_RX_MSDU_END_FIRST_MSDU_GET(_rx_msdu_end) \ 88 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 89 RX_MSDU_END_5_FIRST_MSDU_OFFSET)), \ 90 RX_MSDU_END_5_FIRST_MSDU_MASK, \ 91 RX_MSDU_END_5_FIRST_MSDU_LSB)) 92 93 #define HAL_RX_MSDU_END_DA_IS_VALID_GET(_rx_msdu_end) \ 94 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 95 RX_MSDU_END_5_DA_IS_VALID_OFFSET)), \ 96 RX_MSDU_END_5_DA_IS_VALID_MASK, \ 97 RX_MSDU_END_5_DA_IS_VALID_LSB)) 98 99 #define HAL_RX_MSDU_END_LAST_MSDU_GET(_rx_msdu_end) \ 100 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 101 RX_MSDU_END_5_LAST_MSDU_OFFSET)), \ 102 RX_MSDU_END_5_LAST_MSDU_MASK, \ 103 RX_MSDU_END_5_LAST_MSDU_LSB)) 104 105 #define HAL_RX_MPDU_GET_MAC_AD4_VALID(_rx_mpdu_info) \ 106 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 107 RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_OFFSET)), \ 108 RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_MASK, \ 109 RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_LSB)) 110 111 #define HAL_RX_MPDU_INFO_SW_PEER_ID_GET(_rx_mpdu_info) \ 112 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_info), \ 113 RX_MPDU_INFO_1_SW_PEER_ID_OFFSET)), \ 114 RX_MPDU_INFO_1_SW_PEER_ID_MASK, \ 115 RX_MPDU_INFO_1_SW_PEER_ID_LSB)) 116 117 #define HAL_RX_MPDU_GET_TODS(_rx_mpdu_info) \ 118 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 119 RX_MPDU_INFO_2_TO_DS_OFFSET)), \ 120 RX_MPDU_INFO_2_TO_DS_MASK, \ 121 RX_MPDU_INFO_2_TO_DS_LSB)) 122 123 #define HAL_RX_MPDU_GET_FROMDS(_rx_mpdu_info) \ 124 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 125 RX_MPDU_INFO_2_FR_DS_OFFSET)), \ 126 RX_MPDU_INFO_2_FR_DS_MASK, \ 127 RX_MPDU_INFO_2_FR_DS_LSB)) 128 129 #define HAL_RX_MPDU_GET_FRAME_CONTROL_VALID(_rx_mpdu_info) \ 130 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 131 RX_MPDU_INFO_2_MPDU_FRAME_CONTROL_VALID_OFFSET)), \ 132 RX_MPDU_INFO_2_MPDU_FRAME_CONTROL_VALID_MASK, \ 133 RX_MPDU_INFO_2_MPDU_FRAME_CONTROL_VALID_LSB)) 134 135 #define HAL_RX_MPDU_MAC_ADDR_AD1_VALID_GET(_rx_mpdu_info) \ 136 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 137 RX_MPDU_INFO_2_MAC_ADDR_AD1_VALID_OFFSET)), \ 138 RX_MPDU_INFO_2_MAC_ADDR_AD1_VALID_MASK, \ 139 RX_MPDU_INFO_2_MAC_ADDR_AD1_VALID_LSB)) 140 141 #define HAL_RX_MPDU_AD1_31_0_GET(_rx_mpdu_info) \ 142 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 143 RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_OFFSET)), \ 144 RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_MASK, \ 145 RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_LSB)) 146 147 #define HAL_RX_MPDU_AD1_47_32_GET(_rx_mpdu_info) \ 148 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 149 RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_OFFSET)), \ 150 RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_MASK, \ 151 RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_LSB)) 152 153 #define HAL_RX_MPDU_MAC_ADDR_AD2_VALID_GET(_rx_mpdu_info) \ 154 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 155 RX_MPDU_INFO_2_MAC_ADDR_AD2_VALID_OFFSET)), \ 156 RX_MPDU_INFO_2_MAC_ADDR_AD2_VALID_MASK, \ 157 RX_MPDU_INFO_2_MAC_ADDR_AD2_VALID_LSB)) 158 159 #define HAL_RX_MPDU_AD2_15_0_GET(_rx_mpdu_info) \ 160 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 161 RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_OFFSET)), \ 162 RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_MASK, \ 163 RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_LSB)) 164 165 #define HAL_RX_MPDU_AD2_47_16_GET(_rx_mpdu_info) \ 166 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 167 RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_OFFSET)), \ 168 RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_MASK, \ 169 RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_LSB)) 170 171 #define HAL_RX_MPDU_MAC_ADDR_AD3_VALID_GET(_rx_mpdu_info) \ 172 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 173 RX_MPDU_INFO_2_MAC_ADDR_AD3_VALID_OFFSET)), \ 174 RX_MPDU_INFO_2_MAC_ADDR_AD3_VALID_MASK, \ 175 RX_MPDU_INFO_2_MAC_ADDR_AD3_VALID_LSB)) 176 177 #define HAL_RX_MPDU_AD3_31_0_GET(_rx_mpdu_info) \ 178 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 179 RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_OFFSET)), \ 180 RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_MASK, \ 181 RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_LSB)) 182 183 #define HAL_RX_MPDU_AD3_47_32_GET(_rx_mpdu_info) \ 184 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 185 RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_OFFSET)), \ 186 RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_MASK, \ 187 RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_LSB)) 188 189 #define HAL_RX_MPDU_MAC_ADDR_AD4_VALID_GET(_rx_mpdu_info) \ 190 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 191 RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_OFFSET)), \ 192 RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_MASK, \ 193 RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_LSB)) 194 195 #define HAL_RX_MPDU_AD4_31_0_GET(_rx_mpdu_info) \ 196 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 197 RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_OFFSET)), \ 198 RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_MASK, \ 199 RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_LSB)) 200 201 #define HAL_RX_MPDU_AD4_47_32_GET(_rx_mpdu_info) \ 202 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 203 RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_OFFSET)), \ 204 RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_MASK, \ 205 RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_LSB)) 206 207 #define HAL_RX_MPDU_GET_SEQUENCE_CONTROL_VALID(_rx_mpdu_info) \ 208 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 209 RX_MPDU_INFO_2_MPDU_SEQUENCE_CONTROL_VALID_OFFSET)), \ 210 RX_MPDU_INFO_2_MPDU_SEQUENCE_CONTROL_VALID_MASK, \ 211 RX_MPDU_INFO_2_MPDU_SEQUENCE_CONTROL_VALID_LSB)) 212 213 #define HAL_RX_MPDU_INFO_QOS_CONTROL_VALID_GET(_rx_mpdu_info) \ 214 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_info), \ 215 RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_OFFSET)), \ 216 RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_MASK, \ 217 RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_LSB)) 218 219 #define HAL_RX_MSDU_END_SA_SW_PEER_ID_GET(_rx_msdu_end) \ 220 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 221 RX_MSDU_END_16_SA_SW_PEER_ID_OFFSET)), \ 222 RX_MSDU_END_16_SA_SW_PEER_ID_MASK, \ 223 RX_MSDU_END_16_SA_SW_PEER_ID_LSB)) 224 225 #define HAL_RX_MSDU0_BUFFER_ADDR_LSB(link_desc_va) \ 226 (uint8_t *)(link_desc_va) + \ 227 RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET 228 229 #define HAL_RX_MSDU_DESC_INFO_PTR_GET(msdu0) \ 230 (uint8_t *)(msdu0) + \ 231 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET 232 233 #define HAL_ENT_MPDU_DESC_INFO(ent_ring_desc) \ 234 (uint8_t *)(ent_ring_desc) + \ 235 RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET 236 237 #define HAL_DST_MPDU_DESC_INFO(dst_ring_desc) \ 238 (uint8_t *)(dst_ring_desc) + \ 239 REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET 240 241 #define HAL_RX_GET_FC_VALID(rx_mpdu_start) \ 242 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_2, MPDU_FRAME_CONTROL_VALID) 243 244 #define HAL_RX_GET_TO_DS_FLAG(rx_mpdu_start) \ 245 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_2, TO_DS) 246 247 #define HAL_RX_GET_MAC_ADDR1_VALID(rx_mpdu_start) \ 248 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_2, MAC_ADDR_AD1_VALID) 249 250 #define HAL_RX_GET_MAC_ADDR2_VALID(rx_mpdu_start) \ 251 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_2, MAC_ADDR_AD2_VALID) 252 253 #define HAL_RX_GET_FILTER_CATEGORY(rx_mpdu_start) \ 254 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_0, RXPCU_MPDU_FILTER_IN_CATEGORY) 255 256 #define HAL_RX_GET_PPDU_ID(rx_mpdu_start) \ 257 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_0, PHY_PPDU_ID) 258 259 #define HAL_RX_GET_SW_FRAME_GROUP_ID(rx_mpdu_start) \ 260 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_0, SW_FRAME_GROUP_ID) 261 262 #define HAL_REO_R0_CONFIG(soc, reg_val, reo_params) \ 263 do { \ 264 reg_val &= \ 265 ~(HWIO_REO_R0_GENERAL_ENABLE_FRAGMENT_DEST_RING_BMSK |\ 266 HWIO_REO_R0_GENERAL_ENABLE_AGING_LIST_ENABLE_BMSK | \ 267 HWIO_REO_R0_GENERAL_ENABLE_AGING_FLUSH_ENABLE_BMSK); \ 268 reg_val |= \ 269 HAL_SM(HWIO_REO_R0_GENERAL_ENABLE, \ 270 FRAGMENT_DEST_RING, \ 271 (reo_params)->frag_dst_ring) | \ 272 HAL_SM(HWIO_REO_R0_GENERAL_ENABLE, \ 273 AGING_LIST_ENABLE, 1) |\ 274 HAL_SM(HWIO_REO_R0_GENERAL_ENABLE, \ 275 AGING_FLUSH_ENABLE, 1);\ 276 HAL_REG_WRITE((soc), \ 277 HWIO_REO_R0_GENERAL_ENABLE_ADDR( \ 278 SEQ_WCSS_UMAC_REO_REG_OFFSET),\ 279 (reg_val)); \ 280 (reg_val) = \ 281 HAL_REG_READ((soc), \ 282 HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_ADDR( \ 283 SEQ_WCSS_UMAC_REO_REG_OFFSET)); \ 284 (reg_val) &= \ 285 ~(HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_0_BMSK); \ 286 (reg_val) |= \ 287 HAL_SM(HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0, \ 288 DEST_RING_ALT_MAPPING_0, \ 289 (reo_params)->alt_dst_ind_0); \ 290 HAL_REG_WRITE((soc), \ 291 HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_ADDR( \ 292 SEQ_WCSS_UMAC_REO_REG_OFFSET), \ 293 (reg_val)); \ 294 } while (0) 295 296 #define HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr) \ 297 ((struct rx_msdu_desc_info *) \ 298 _OFFSET_TO_BYTE_PTR((msdu_details_ptr), \ 299 UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET)) 300 301 #define HAL_RX_LINK_DESC_MSDU0_PTR(link_desc) \ 302 ((struct rx_msdu_details *) \ 303 _OFFSET_TO_BYTE_PTR((link_desc),\ 304 UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET)) 305 306 #define HAL_RX_MSDU_END_FLOW_IDX_GET(_rx_msdu_end) \ 307 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 308 RX_MSDU_END_14_FLOW_IDX_OFFSET)), \ 309 RX_MSDU_END_14_FLOW_IDX_MASK, \ 310 RX_MSDU_END_14_FLOW_IDX_LSB)) 311 312 #define HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(_rx_msdu_end) \ 313 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 314 RX_MSDU_END_5_FLOW_IDX_INVALID_OFFSET)), \ 315 RX_MSDU_END_5_FLOW_IDX_INVALID_MASK, \ 316 RX_MSDU_END_5_FLOW_IDX_INVALID_LSB)) 317 318 #define HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(_rx_msdu_end) \ 319 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 320 RX_MSDU_END_5_FLOW_IDX_TIMEOUT_OFFSET)), \ 321 RX_MSDU_END_5_FLOW_IDX_TIMEOUT_MASK, \ 322 RX_MSDU_END_5_FLOW_IDX_TIMEOUT_LSB)) 323 324 #define HAL_RX_MSDU_END_FSE_METADATA_GET(_rx_msdu_end) \ 325 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 326 RX_MSDU_END_15_FSE_METADATA_OFFSET)), \ 327 RX_MSDU_END_15_FSE_METADATA_MASK, \ 328 RX_MSDU_END_15_FSE_METADATA_LSB)) 329 330 #define HAL_RX_MSDU_END_CCE_METADATA_GET(_rx_msdu_end) \ 331 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 332 RX_MSDU_END_16_CCE_METADATA_OFFSET)), \ 333 RX_MSDU_END_16_CCE_METADATA_MASK, \ 334 RX_MSDU_END_16_CCE_METADATA_LSB)) 335 336 #define HAL_RX_TLV_GET_TCP_CHKSUM(buf) \ 337 (_HAL_MS( \ 338 (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ 339 msdu_end_tlv.rx_msdu_end), \ 340 RX_MSDU_END_1_TCP_UDP_CHKSUM_OFFSET)), \ 341 RX_MSDU_END_1_TCP_UDP_CHKSUM_MASK, \ 342 RX_MSDU_END_1_TCP_UDP_CHKSUM_LSB)) 343 344 /* 345 * hal_rx_msdu_start_nss_get_8074(): API to get the NSS 346 * Interval from rx_msdu_start 347 * 348 * @buf: pointer to the start of RX PKT TLV header 349 * Return: uint32_t(nss) 350 */ 351 static uint32_t 352 hal_rx_msdu_start_nss_get_8074(uint8_t *buf) 353 { 354 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 355 struct rx_msdu_start *msdu_start = 356 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 357 uint32_t nss; 358 359 nss = HAL_RX_MSDU_START_NSS_GET(msdu_start); 360 return nss; 361 } 362 363 /** 364 * hal_rx_mon_hw_desc_get_mpdu_status_8074(): Retrieve MPDU status 365 * 366 * @ hw_desc_addr: Start address of Rx HW TLVs 367 * @ rs: Status for monitor mode 368 * 369 * Return: void 370 */ 371 static void hal_rx_mon_hw_desc_get_mpdu_status_8074(void *hw_desc_addr, 372 struct mon_rx_status *rs) 373 { 374 struct rx_msdu_start *rx_msdu_start; 375 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr; 376 uint32_t reg_value; 377 const uint32_t sgi_hw_to_cdp[] = { 378 CDP_SGI_0_8_US, 379 CDP_SGI_0_4_US, 380 CDP_SGI_1_6_US, 381 CDP_SGI_3_2_US, 382 }; 383 384 rx_msdu_start = &rx_desc->msdu_start_tlv.rx_msdu_start; 385 386 HAL_RX_GET_MSDU_AGGREGATION(rx_desc, rs); 387 388 rs->ant_signal_db = HAL_RX_GET(rx_msdu_start, 389 RX_MSDU_START_5, USER_RSSI); 390 rs->is_stbc = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, STBC); 391 392 reg_value = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, SGI); 393 rs->sgi = sgi_hw_to_cdp[reg_value]; 394 rs->nr_ant = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, NSS); 395 reg_value = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, RECEPTION_TYPE); 396 rs->beamformed = (reg_value == HAL_RX_RECEPTION_TYPE_MU_MIMO) ? 1 : 0; 397 /* TODO: rs->beamformed should be set for SU beamforming also */ 398 } 399 400 #define LINK_DESC_SIZE (NUM_OF_DWORDS_RX_MSDU_LINK << 2) 401 static uint32_t hal_get_link_desc_size_8074(void) 402 { 403 return LINK_DESC_SIZE; 404 } 405 406 /* 407 * hal_rx_get_tlv_8074(): API to get the tlv 408 * 409 * @rx_tlv: TLV data extracted from the rx packet 410 * Return: uint8_t 411 */ 412 static uint8_t hal_rx_get_tlv_8074(void *rx_tlv) 413 { 414 return HAL_RX_GET(rx_tlv, PHYRX_RSSI_LEGACY_35, RECEIVE_BANDWIDTH); 415 } 416 417 /** 418 * hal_rx_proc_phyrx_other_receive_info_tlv_8074() 419 * -process other receive info TLV 420 * @rx_tlv_hdr: pointer to TLV header 421 * @ppdu_info: pointer to ppdu_info 422 * 423 * Return: None 424 */ 425 static 426 void hal_rx_proc_phyrx_other_receive_info_tlv_8074(void *rx_tlv_hdr, 427 void *ppdu_info) 428 { 429 } 430 431 432 /** 433 * hal_rx_dump_msdu_start_tlv_8074() : dump RX msdu_start TLV in structured 434 * human readable format. 435 * @ msdu_start: pointer the msdu_start TLV in pkt. 436 * @ dbg_level: log level. 437 * 438 * Return: void 439 */ 440 static void hal_rx_dump_msdu_start_tlv_8074(void *msdustart, 441 uint8_t dbg_level) 442 { 443 struct rx_msdu_start *msdu_start = (struct rx_msdu_start *)msdustart; 444 445 QDF_TRACE(QDF_MODULE_ID_DP, dbg_level, 446 "rx_msdu_start tlv - " 447 "rxpcu_mpdu_filter_in_category: %d " 448 "sw_frame_group_id: %d " 449 "phy_ppdu_id: %d " 450 "msdu_length: %d " 451 "ipsec_esp: %d " 452 "l3_offset: %d " 453 "ipsec_ah: %d " 454 "l4_offset: %d " 455 "msdu_number: %d " 456 "decap_format: %d " 457 "ipv4_proto: %d " 458 "ipv6_proto: %d " 459 "tcp_proto: %d " 460 "udp_proto: %d " 461 "ip_frag: %d " 462 "tcp_only_ack: %d " 463 "da_is_bcast_mcast: %d " 464 "ip4_protocol_ip6_next_header: %d " 465 "toeplitz_hash_2_or_4: %d " 466 "flow_id_toeplitz: %d " 467 "user_rssi: %d " 468 "pkt_type: %d " 469 "stbc: %d " 470 "sgi: %d " 471 "rate_mcs: %d " 472 "receive_bandwidth: %d " 473 "reception_type: %d " 474 "toeplitz_hash: %d " 475 "nss: %d " 476 "ppdu_start_timestamp: %d " 477 "sw_phy_meta_data: %d ", 478 msdu_start->rxpcu_mpdu_filter_in_category, 479 msdu_start->sw_frame_group_id, 480 msdu_start->phy_ppdu_id, 481 msdu_start->msdu_length, 482 msdu_start->ipsec_esp, 483 msdu_start->l3_offset, 484 msdu_start->ipsec_ah, 485 msdu_start->l4_offset, 486 msdu_start->msdu_number, 487 msdu_start->decap_format, 488 msdu_start->ipv4_proto, 489 msdu_start->ipv6_proto, 490 msdu_start->tcp_proto, 491 msdu_start->udp_proto, 492 msdu_start->ip_frag, 493 msdu_start->tcp_only_ack, 494 msdu_start->da_is_bcast_mcast, 495 msdu_start->ip4_protocol_ip6_next_header, 496 msdu_start->toeplitz_hash_2_or_4, 497 msdu_start->flow_id_toeplitz, 498 msdu_start->user_rssi, 499 msdu_start->pkt_type, 500 msdu_start->stbc, 501 msdu_start->sgi, 502 msdu_start->rate_mcs, 503 msdu_start->receive_bandwidth, 504 msdu_start->reception_type, 505 msdu_start->toeplitz_hash, 506 msdu_start->nss, 507 msdu_start->ppdu_start_timestamp, 508 msdu_start->sw_phy_meta_data); 509 } 510 511 /** 512 * hal_rx_dump_msdu_end_tlv_8074: dump RX msdu_end TLV in structured 513 * human readable format. 514 * @ msdu_end: pointer the msdu_end TLV in pkt. 515 * @ dbg_level: log level. 516 * 517 * Return: void 518 */ 519 static void hal_rx_dump_msdu_end_tlv_8074(void *msduend, 520 uint8_t dbg_level) 521 { 522 struct rx_msdu_end *msdu_end = (struct rx_msdu_end *)msduend; 523 524 QDF_TRACE(QDF_MODULE_ID_DP, dbg_level, 525 "rx_msdu_end tlv - " 526 "rxpcu_mpdu_filter_in_category: %d " 527 "sw_frame_group_id: %d " 528 "phy_ppdu_id: %d " 529 "ip_hdr_chksum: %d " 530 "tcp_udp_chksum: %d " 531 "key_id_octet: %d " 532 "cce_super_rule: %d " 533 "cce_classify_not_done_truncat: %d " 534 "cce_classify_not_done_cce_dis: %d " 535 "ext_wapi_pn_63_48: %d " 536 "ext_wapi_pn_95_64: %d " 537 "ext_wapi_pn_127_96: %d " 538 "reported_mpdu_length: %d " 539 "first_msdu: %d " 540 "last_msdu: %d " 541 "sa_idx_timeout: %d " 542 "da_idx_timeout: %d " 543 "msdu_limit_error: %d " 544 "flow_idx_timeout: %d " 545 "flow_idx_invalid: %d " 546 "wifi_parser_error: %d " 547 "amsdu_parser_error: %d " 548 "sa_is_valid: %d " 549 "da_is_valid: %d " 550 "da_is_mcbc: %d " 551 "l3_header_padding: %d " 552 "ipv6_options_crc: %d " 553 "tcp_seq_number: %d " 554 "tcp_ack_number: %d " 555 "tcp_flag: %d " 556 "lro_eligible: %d " 557 "window_size: %d " 558 "da_offset: %d " 559 "sa_offset: %d " 560 "da_offset_valid: %d " 561 "sa_offset_valid: %d " 562 "rule_indication_31_0: %d " 563 "rule_indication_63_32: %d " 564 "sa_idx: %d " 565 "da_idx: %d " 566 "msdu_drop: %d " 567 "reo_destination_indication: %d " 568 "flow_idx: %d " 569 "fse_metadata: %d " 570 "cce_metadata: %d " 571 "sa_sw_peer_id: %d ", 572 msdu_end->rxpcu_mpdu_filter_in_category, 573 msdu_end->sw_frame_group_id, 574 msdu_end->phy_ppdu_id, 575 msdu_end->ip_hdr_chksum, 576 msdu_end->tcp_udp_chksum, 577 msdu_end->key_id_octet, 578 msdu_end->cce_super_rule, 579 msdu_end->cce_classify_not_done_truncate, 580 msdu_end->cce_classify_not_done_cce_dis, 581 msdu_end->ext_wapi_pn_63_48, 582 msdu_end->ext_wapi_pn_95_64, 583 msdu_end->ext_wapi_pn_127_96, 584 msdu_end->reported_mpdu_length, 585 msdu_end->first_msdu, 586 msdu_end->last_msdu, 587 msdu_end->sa_idx_timeout, 588 msdu_end->da_idx_timeout, 589 msdu_end->msdu_limit_error, 590 msdu_end->flow_idx_timeout, 591 msdu_end->flow_idx_invalid, 592 msdu_end->wifi_parser_error, 593 msdu_end->amsdu_parser_error, 594 msdu_end->sa_is_valid, 595 msdu_end->da_is_valid, 596 msdu_end->da_is_mcbc, 597 msdu_end->l3_header_padding, 598 msdu_end->ipv6_options_crc, 599 msdu_end->tcp_seq_number, 600 msdu_end->tcp_ack_number, 601 msdu_end->tcp_flag, 602 msdu_end->lro_eligible, 603 msdu_end->window_size, 604 msdu_end->da_offset, 605 msdu_end->sa_offset, 606 msdu_end->da_offset_valid, 607 msdu_end->sa_offset_valid, 608 msdu_end->rule_indication_31_0, 609 msdu_end->rule_indication_63_32, 610 msdu_end->sa_idx, 611 msdu_end->da_idx, 612 msdu_end->msdu_drop, 613 msdu_end->reo_destination_indication, 614 msdu_end->flow_idx, 615 msdu_end->fse_metadata, 616 msdu_end->cce_metadata, 617 msdu_end->sa_sw_peer_id); 618 } 619 620 621 /* 622 * Get tid from RX_MPDU_START 623 */ 624 #define HAL_RX_MPDU_INFO_TID_GET(_rx_mpdu_info) \ 625 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_info), \ 626 RX_MPDU_INFO_3_TID_OFFSET)), \ 627 RX_MPDU_INFO_3_TID_MASK, \ 628 RX_MPDU_INFO_3_TID_LSB)) 629 630 static uint32_t hal_rx_mpdu_start_tid_get_8074(uint8_t *buf) 631 { 632 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 633 struct rx_mpdu_start *mpdu_start = 634 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 635 uint32_t tid; 636 637 tid = HAL_RX_MPDU_INFO_TID_GET(&mpdu_start->rx_mpdu_info_details); 638 639 return tid; 640 } 641 642 #define HAL_RX_MSDU_START_RECEPTION_TYPE_GET(_rx_msdu_start) \ 643 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start), \ 644 RX_MSDU_START_5_RECEPTION_TYPE_OFFSET)), \ 645 RX_MSDU_START_5_RECEPTION_TYPE_MASK, \ 646 RX_MSDU_START_5_RECEPTION_TYPE_LSB)) 647 648 /* 649 * hal_rx_msdu_start_reception_type_get(): API to get the reception type 650 * Interval from rx_msdu_start 651 * 652 * @buf: pointer to the start of RX PKT TLV header 653 * Return: uint32_t(reception_type) 654 */ 655 static uint32_t hal_rx_msdu_start_reception_type_get_8074(uint8_t *buf) 656 { 657 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 658 struct rx_msdu_start *msdu_start = 659 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 660 uint32_t reception_type; 661 662 reception_type = HAL_RX_MSDU_START_RECEPTION_TYPE_GET(msdu_start); 663 664 return reception_type; 665 } 666 667 #define HAL_RX_MSDU_END_DA_IDX_GET(_rx_msdu_end) \ 668 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 669 RX_MSDU_END_13_DA_IDX_OFFSET)), \ 670 RX_MSDU_END_13_DA_IDX_MASK, \ 671 RX_MSDU_END_13_DA_IDX_LSB)) 672 673 /** 674 * hal_rx_msdu_end_da_idx_get_8074: API to get da_idx 675 * from rx_msdu_end TLV 676 * 677 * @ buf: pointer to the start of RX PKT TLV headers 678 * Return: da index 679 */ 680 static uint16_t hal_rx_msdu_end_da_idx_get_8074(uint8_t *buf) 681 { 682 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 683 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 684 uint16_t da_idx; 685 686 da_idx = HAL_RX_MSDU_END_DA_IDX_GET(msdu_end); 687 688 return da_idx; 689 } 690