1 /* 2 * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 #include "hal_hw_headers.h" 19 #include "hal_internal.h" 20 #include "cdp_txrx_mon_struct.h" 21 #include "qdf_trace.h" 22 #include "hal_li_rx.h" 23 #include "hal_tx.h" 24 #include "dp_types.h" 25 #include "hal_api_mon.h" 26 27 #define HAL_RX_MPDU_GET_SEQUENCE_NUMBER(_rx_mpdu_info) \ 28 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 29 RX_MPDU_INFO_2_MPDU_SEQUENCE_NUMBER_OFFSET)), \ 30 RX_MPDU_INFO_2_MPDU_SEQUENCE_NUMBER_MASK, \ 31 RX_MPDU_INFO_2_MPDU_SEQUENCE_NUMBER_LSB)) 32 33 #define HAL_RX_MSDU_END_DA_IS_MCBC_GET(_rx_msdu_end) \ 34 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 35 RX_MSDU_END_5_DA_IS_MCBC_OFFSET)), \ 36 RX_MSDU_END_5_DA_IS_MCBC_MASK, \ 37 RX_MSDU_END_5_DA_IS_MCBC_LSB)) 38 39 #define HAL_RX_MSDU_END_SA_IS_VALID_GET(_rx_msdu_end) \ 40 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 41 RX_MSDU_END_5_SA_IS_VALID_OFFSET)), \ 42 RX_MSDU_END_5_SA_IS_VALID_MASK, \ 43 RX_MSDU_END_5_SA_IS_VALID_LSB)) 44 45 #define HAL_RX_MSDU_END_SA_IDX_GET(_rx_msdu_end) \ 46 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 47 RX_MSDU_END_13_SA_IDX_OFFSET)), \ 48 RX_MSDU_END_13_SA_IDX_MASK, \ 49 RX_MSDU_END_13_SA_IDX_LSB)) 50 51 #define HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(_rx_msdu_end) \ 52 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 53 RX_MSDU_END_5_L3_HEADER_PADDING_OFFSET)), \ 54 RX_MSDU_END_5_L3_HEADER_PADDING_MASK, \ 55 RX_MSDU_END_5_L3_HEADER_PADDING_LSB)) 56 57 #define HAL_RX_MPDU_ENCRYPTION_INFO_VALID(_rx_mpdu_info) \ 58 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 59 RX_MPDU_INFO_2_FRAME_ENCRYPTION_INFO_VALID_OFFSET)), \ 60 RX_MPDU_INFO_2_FRAME_ENCRYPTION_INFO_VALID_MASK, \ 61 RX_MPDU_INFO_2_FRAME_ENCRYPTION_INFO_VALID_LSB)) 62 63 #define HAL_RX_MPDU_PN_31_0_GET(_rx_mpdu_info) \ 64 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 65 RX_MPDU_INFO_4_PN_31_0_OFFSET)), \ 66 RX_MPDU_INFO_4_PN_31_0_MASK, \ 67 RX_MPDU_INFO_4_PN_31_0_LSB)) 68 69 #define HAL_RX_MPDU_PN_63_32_GET(_rx_mpdu_info) \ 70 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 71 RX_MPDU_INFO_5_PN_63_32_OFFSET)), \ 72 RX_MPDU_INFO_5_PN_63_32_MASK, \ 73 RX_MPDU_INFO_5_PN_63_32_LSB)) 74 75 #define HAL_RX_MPDU_PN_95_64_GET(_rx_mpdu_info) \ 76 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 77 RX_MPDU_INFO_6_PN_95_64_OFFSET)), \ 78 RX_MPDU_INFO_6_PN_95_64_MASK, \ 79 RX_MPDU_INFO_6_PN_95_64_LSB)) 80 81 #define HAL_RX_MPDU_PN_127_96_GET(_rx_mpdu_info) \ 82 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 83 RX_MPDU_INFO_7_PN_127_96_OFFSET)), \ 84 RX_MPDU_INFO_7_PN_127_96_MASK, \ 85 RX_MPDU_INFO_7_PN_127_96_LSB)) 86 87 #define HAL_RX_MSDU_END_FIRST_MSDU_GET(_rx_msdu_end) \ 88 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 89 RX_MSDU_END_5_FIRST_MSDU_OFFSET)), \ 90 RX_MSDU_END_5_FIRST_MSDU_MASK, \ 91 RX_MSDU_END_5_FIRST_MSDU_LSB)) 92 93 #define HAL_RX_MSDU_END_DA_IS_VALID_GET(_rx_msdu_end) \ 94 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 95 RX_MSDU_END_5_DA_IS_VALID_OFFSET)), \ 96 RX_MSDU_END_5_DA_IS_VALID_MASK, \ 97 RX_MSDU_END_5_DA_IS_VALID_LSB)) 98 99 #define HAL_RX_MSDU_END_LAST_MSDU_GET(_rx_msdu_end) \ 100 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 101 RX_MSDU_END_5_LAST_MSDU_OFFSET)), \ 102 RX_MSDU_END_5_LAST_MSDU_MASK, \ 103 RX_MSDU_END_5_LAST_MSDU_LSB)) 104 105 #define HAL_RX_MPDU_GET_MAC_AD4_VALID(_rx_mpdu_info) \ 106 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 107 RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_OFFSET)), \ 108 RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_MASK, \ 109 RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_LSB)) 110 111 #define HAL_RX_MPDU_INFO_SW_PEER_ID_GET(_rx_mpdu_info) \ 112 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_info), \ 113 RX_MPDU_INFO_1_SW_PEER_ID_OFFSET)), \ 114 RX_MPDU_INFO_1_SW_PEER_ID_MASK, \ 115 RX_MPDU_INFO_1_SW_PEER_ID_LSB)) 116 117 #define HAL_RX_MPDU_GET_TODS(_rx_mpdu_info) \ 118 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 119 RX_MPDU_INFO_2_TO_DS_OFFSET)), \ 120 RX_MPDU_INFO_2_TO_DS_MASK, \ 121 RX_MPDU_INFO_2_TO_DS_LSB)) 122 123 #define HAL_RX_MPDU_GET_FROMDS(_rx_mpdu_info) \ 124 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 125 RX_MPDU_INFO_2_FR_DS_OFFSET)), \ 126 RX_MPDU_INFO_2_FR_DS_MASK, \ 127 RX_MPDU_INFO_2_FR_DS_LSB)) 128 129 #define HAL_RX_MPDU_GET_FRAME_CONTROL_VALID(_rx_mpdu_info) \ 130 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 131 RX_MPDU_INFO_2_MPDU_FRAME_CONTROL_VALID_OFFSET)), \ 132 RX_MPDU_INFO_2_MPDU_FRAME_CONTROL_VALID_MASK, \ 133 RX_MPDU_INFO_2_MPDU_FRAME_CONTROL_VALID_LSB)) 134 135 #define HAL_RX_MPDU_MAC_ADDR_AD1_VALID_GET(_rx_mpdu_info) \ 136 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 137 RX_MPDU_INFO_2_MAC_ADDR_AD1_VALID_OFFSET)), \ 138 RX_MPDU_INFO_2_MAC_ADDR_AD1_VALID_MASK, \ 139 RX_MPDU_INFO_2_MAC_ADDR_AD1_VALID_LSB)) 140 141 #define HAL_RX_MPDU_AD1_31_0_GET(_rx_mpdu_info) \ 142 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 143 RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_OFFSET)), \ 144 RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_MASK, \ 145 RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_LSB)) 146 147 #define HAL_RX_MPDU_AD1_47_32_GET(_rx_mpdu_info) \ 148 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 149 RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_OFFSET)), \ 150 RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_MASK, \ 151 RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_LSB)) 152 153 #define HAL_RX_MPDU_MAC_ADDR_AD2_VALID_GET(_rx_mpdu_info) \ 154 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 155 RX_MPDU_INFO_2_MAC_ADDR_AD2_VALID_OFFSET)), \ 156 RX_MPDU_INFO_2_MAC_ADDR_AD2_VALID_MASK, \ 157 RX_MPDU_INFO_2_MAC_ADDR_AD2_VALID_LSB)) 158 159 #define HAL_RX_MPDU_AD2_15_0_GET(_rx_mpdu_info) \ 160 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 161 RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_OFFSET)), \ 162 RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_MASK, \ 163 RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_LSB)) 164 165 #define HAL_RX_MPDU_AD2_47_16_GET(_rx_mpdu_info) \ 166 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 167 RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_OFFSET)), \ 168 RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_MASK, \ 169 RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_LSB)) 170 171 #define HAL_RX_MPDU_MAC_ADDR_AD3_VALID_GET(_rx_mpdu_info) \ 172 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 173 RX_MPDU_INFO_2_MAC_ADDR_AD3_VALID_OFFSET)), \ 174 RX_MPDU_INFO_2_MAC_ADDR_AD3_VALID_MASK, \ 175 RX_MPDU_INFO_2_MAC_ADDR_AD3_VALID_LSB)) 176 177 #define HAL_RX_MPDU_AD3_31_0_GET(_rx_mpdu_info) \ 178 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 179 RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_OFFSET)), \ 180 RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_MASK, \ 181 RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_LSB)) 182 183 #define HAL_RX_MPDU_AD3_47_32_GET(_rx_mpdu_info) \ 184 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 185 RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_OFFSET)), \ 186 RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_MASK, \ 187 RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_LSB)) 188 189 #define HAL_RX_MPDU_MAC_ADDR_AD4_VALID_GET(_rx_mpdu_info) \ 190 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 191 RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_OFFSET)), \ 192 RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_MASK, \ 193 RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_LSB)) 194 195 #define HAL_RX_MPDU_AD4_31_0_GET(_rx_mpdu_info) \ 196 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 197 RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_OFFSET)), \ 198 RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_MASK, \ 199 RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_LSB)) 200 201 #define HAL_RX_MPDU_AD4_47_32_GET(_rx_mpdu_info) \ 202 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 203 RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_OFFSET)), \ 204 RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_MASK, \ 205 RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_LSB)) 206 207 #define HAL_RX_MPDU_GET_SEQUENCE_CONTROL_VALID(_rx_mpdu_info) \ 208 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 209 RX_MPDU_INFO_2_MPDU_SEQUENCE_CONTROL_VALID_OFFSET)), \ 210 RX_MPDU_INFO_2_MPDU_SEQUENCE_CONTROL_VALID_MASK, \ 211 RX_MPDU_INFO_2_MPDU_SEQUENCE_CONTROL_VALID_LSB)) 212 213 #define HAL_RX_MPDU_INFO_QOS_CONTROL_VALID_GET(_rx_mpdu_info) \ 214 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_info), \ 215 RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_OFFSET)), \ 216 RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_MASK, \ 217 RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_LSB)) 218 219 #define HAL_RX_MSDU_END_SA_SW_PEER_ID_GET(_rx_msdu_end) \ 220 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 221 RX_MSDU_END_16_SA_SW_PEER_ID_OFFSET)), \ 222 RX_MSDU_END_16_SA_SW_PEER_ID_MASK, \ 223 RX_MSDU_END_16_SA_SW_PEER_ID_LSB)) 224 225 #define HAL_RX_MSDU0_BUFFER_ADDR_LSB(link_desc_va) \ 226 (uint8_t *)(link_desc_va) + \ 227 RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET 228 229 #define HAL_RX_MSDU_DESC_INFO_PTR_GET(msdu0) \ 230 (uint8_t *)(msdu0) + \ 231 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET 232 233 #define HAL_ENT_MPDU_DESC_INFO(ent_ring_desc) \ 234 (uint8_t *)(ent_ring_desc) + \ 235 RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET 236 237 #define HAL_DST_MPDU_DESC_INFO(dst_ring_desc) \ 238 (uint8_t *)(dst_ring_desc) + \ 239 REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET 240 241 #define HAL_RX_GET_FC_VALID(rx_mpdu_start) \ 242 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_2, MPDU_FRAME_CONTROL_VALID) 243 244 #define HAL_RX_GET_TO_DS_FLAG(rx_mpdu_start) \ 245 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_2, TO_DS) 246 247 #define HAL_RX_GET_MAC_ADDR1_VALID(rx_mpdu_start) \ 248 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_2, MAC_ADDR_AD1_VALID) 249 250 #define HAL_RX_GET_MAC_ADDR2_VALID(rx_mpdu_start) \ 251 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_2, MAC_ADDR_AD2_VALID) 252 253 #define HAL_RX_GET_FILTER_CATEGORY(rx_mpdu_start) \ 254 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_0, RXPCU_MPDU_FILTER_IN_CATEGORY) 255 256 #define HAL_RX_GET_PPDU_ID(rx_mpdu_start) \ 257 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_0, PHY_PPDU_ID) 258 259 #define HAL_RX_GET_SW_FRAME_GROUP_ID(rx_mpdu_start) \ 260 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_0, SW_FRAME_GROUP_ID) 261 262 #define HAL_RX_GET_SW_PEER_ID(rx_mpdu_start) \ 263 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_1, SW_PEER_ID) 264 265 #define HAL_REO_R0_CONFIG(soc, reg_val, reo_params) \ 266 do { \ 267 reg_val &= \ 268 ~(HWIO_REO_R0_GENERAL_ENABLE_FRAGMENT_DEST_RING_BMSK |\ 269 HWIO_REO_R0_GENERAL_ENABLE_AGING_LIST_ENABLE_BMSK | \ 270 HWIO_REO_R0_GENERAL_ENABLE_AGING_FLUSH_ENABLE_BMSK); \ 271 reg_val |= \ 272 HAL_SM(HWIO_REO_R0_GENERAL_ENABLE, \ 273 FRAGMENT_DEST_RING, \ 274 (reo_params)->frag_dst_ring) | \ 275 HAL_SM(HWIO_REO_R0_GENERAL_ENABLE, \ 276 AGING_LIST_ENABLE, 1) |\ 277 HAL_SM(HWIO_REO_R0_GENERAL_ENABLE, \ 278 AGING_FLUSH_ENABLE, 1);\ 279 HAL_REG_WRITE((soc), \ 280 HWIO_REO_R0_GENERAL_ENABLE_ADDR( \ 281 SEQ_WCSS_UMAC_REO_REG_OFFSET),\ 282 (reg_val)); \ 283 (reg_val) = \ 284 HAL_REG_READ((soc), \ 285 HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_ADDR( \ 286 SEQ_WCSS_UMAC_REO_REG_OFFSET)); \ 287 (reg_val) &= \ 288 ~(HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_0_BMSK); \ 289 (reg_val) |= \ 290 HAL_SM(HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0, \ 291 DEST_RING_ALT_MAPPING_0, \ 292 (reo_params)->alt_dst_ind_0); \ 293 HAL_REG_WRITE((soc), \ 294 HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_ADDR( \ 295 SEQ_WCSS_UMAC_REO_REG_OFFSET), \ 296 (reg_val)); \ 297 } while (0) 298 299 #define HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr) \ 300 ((struct rx_msdu_desc_info *) \ 301 _OFFSET_TO_BYTE_PTR((msdu_details_ptr), \ 302 UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET)) 303 304 #define HAL_RX_LINK_DESC_MSDU0_PTR(link_desc) \ 305 ((struct rx_msdu_details *) \ 306 _OFFSET_TO_BYTE_PTR((link_desc),\ 307 UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET)) 308 309 #define HAL_RX_MSDU_END_FLOW_IDX_GET(_rx_msdu_end) \ 310 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 311 RX_MSDU_END_14_FLOW_IDX_OFFSET)), \ 312 RX_MSDU_END_14_FLOW_IDX_MASK, \ 313 RX_MSDU_END_14_FLOW_IDX_LSB)) 314 315 #define HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(_rx_msdu_end) \ 316 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 317 RX_MSDU_END_5_FLOW_IDX_INVALID_OFFSET)), \ 318 RX_MSDU_END_5_FLOW_IDX_INVALID_MASK, \ 319 RX_MSDU_END_5_FLOW_IDX_INVALID_LSB)) 320 321 #define HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(_rx_msdu_end) \ 322 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 323 RX_MSDU_END_5_FLOW_IDX_TIMEOUT_OFFSET)), \ 324 RX_MSDU_END_5_FLOW_IDX_TIMEOUT_MASK, \ 325 RX_MSDU_END_5_FLOW_IDX_TIMEOUT_LSB)) 326 327 #define HAL_RX_MSDU_END_FSE_METADATA_GET(_rx_msdu_end) \ 328 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 329 RX_MSDU_END_15_FSE_METADATA_OFFSET)), \ 330 RX_MSDU_END_15_FSE_METADATA_MASK, \ 331 RX_MSDU_END_15_FSE_METADATA_LSB)) 332 333 #define HAL_RX_MSDU_END_CCE_METADATA_GET(_rx_msdu_end) \ 334 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 335 RX_MSDU_END_16_CCE_METADATA_OFFSET)), \ 336 RX_MSDU_END_16_CCE_METADATA_MASK, \ 337 RX_MSDU_END_16_CCE_METADATA_LSB)) 338 339 #define HAL_RX_TLV_GET_TCP_CHKSUM(buf) \ 340 (_HAL_MS( \ 341 (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ 342 msdu_end_tlv.rx_msdu_end), \ 343 RX_MSDU_END_1_TCP_UDP_CHKSUM_OFFSET)), \ 344 RX_MSDU_END_1_TCP_UDP_CHKSUM_MASK, \ 345 RX_MSDU_END_1_TCP_UDP_CHKSUM_LSB)) 346 347 /* 348 * hal_rx_msdu_start_nss_get_8074(): API to get the NSS 349 * Interval from rx_msdu_start 350 * 351 * @buf: pointer to the start of RX PKT TLV header 352 * Return: uint32_t(nss) 353 */ 354 static uint32_t 355 hal_rx_msdu_start_nss_get_8074(uint8_t *buf) 356 { 357 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 358 struct rx_msdu_start *msdu_start = 359 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 360 uint32_t nss; 361 362 nss = HAL_RX_MSDU_START_NSS_GET(msdu_start); 363 return nss; 364 } 365 366 /** 367 * hal_rx_mon_hw_desc_get_mpdu_status_8074(): Retrieve MPDU status 368 * 369 * @ hw_desc_addr: Start address of Rx HW TLVs 370 * @ rs: Status for monitor mode 371 * 372 * Return: void 373 */ 374 static void hal_rx_mon_hw_desc_get_mpdu_status_8074(void *hw_desc_addr, 375 struct mon_rx_status *rs) 376 { 377 struct rx_msdu_start *rx_msdu_start; 378 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr; 379 uint32_t reg_value; 380 const uint32_t sgi_hw_to_cdp[] = { 381 CDP_SGI_0_8_US, 382 CDP_SGI_0_4_US, 383 CDP_SGI_1_6_US, 384 CDP_SGI_3_2_US, 385 }; 386 387 rx_msdu_start = &rx_desc->msdu_start_tlv.rx_msdu_start; 388 389 HAL_RX_GET_MSDU_AGGREGATION(rx_desc, rs); 390 391 rs->ant_signal_db = HAL_RX_GET(rx_msdu_start, 392 RX_MSDU_START_5, USER_RSSI); 393 rs->is_stbc = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, STBC); 394 395 reg_value = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, SGI); 396 rs->sgi = sgi_hw_to_cdp[reg_value]; 397 rs->nr_ant = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, NSS); 398 reg_value = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, RECEPTION_TYPE); 399 rs->beamformed = (reg_value == HAL_RX_RECEPTION_TYPE_MU_MIMO) ? 1 : 0; 400 /* TODO: rs->beamformed should be set for SU beamforming also */ 401 } 402 403 #define LINK_DESC_SIZE (NUM_OF_DWORDS_RX_MSDU_LINK << 2) 404 static uint32_t hal_get_link_desc_size_8074(void) 405 { 406 return LINK_DESC_SIZE; 407 } 408 409 /* 410 * hal_rx_get_tlv_8074(): API to get the tlv 411 * 412 * @rx_tlv: TLV data extracted from the rx packet 413 * Return: uint8_t 414 */ 415 static uint8_t hal_rx_get_tlv_8074(void *rx_tlv) 416 { 417 return HAL_RX_GET(rx_tlv, PHYRX_RSSI_LEGACY_35, RECEIVE_BANDWIDTH); 418 } 419 420 /** 421 * hal_rx_proc_phyrx_other_receive_info_tlv_8074() 422 * -process other receive info TLV 423 * @rx_tlv_hdr: pointer to TLV header 424 * @ppdu_info: pointer to ppdu_info 425 * 426 * Return: None 427 */ 428 static 429 void hal_rx_proc_phyrx_other_receive_info_tlv_8074(void *rx_tlv_hdr, 430 void *ppdu_info) 431 { 432 } 433 434 435 /** 436 * hal_rx_dump_msdu_start_tlv_8074() : dump RX msdu_start TLV in structured 437 * human readable format. 438 * @ msdu_start: pointer the msdu_start TLV in pkt. 439 * @ dbg_level: log level. 440 * 441 * Return: void 442 */ 443 static void hal_rx_dump_msdu_start_tlv_8074(void *msdustart, 444 uint8_t dbg_level) 445 { 446 struct rx_msdu_start *msdu_start = (struct rx_msdu_start *)msdustart; 447 448 QDF_TRACE(QDF_MODULE_ID_DP, dbg_level, 449 "rx_msdu_start tlv - " 450 "rxpcu_mpdu_filter_in_category: %d " 451 "sw_frame_group_id: %d " 452 "phy_ppdu_id: %d " 453 "msdu_length: %d " 454 "ipsec_esp: %d " 455 "l3_offset: %d " 456 "ipsec_ah: %d " 457 "l4_offset: %d " 458 "msdu_number: %d " 459 "decap_format: %d " 460 "ipv4_proto: %d " 461 "ipv6_proto: %d " 462 "tcp_proto: %d " 463 "udp_proto: %d " 464 "ip_frag: %d " 465 "tcp_only_ack: %d " 466 "da_is_bcast_mcast: %d " 467 "ip4_protocol_ip6_next_header: %d " 468 "toeplitz_hash_2_or_4: %d " 469 "flow_id_toeplitz: %d " 470 "user_rssi: %d " 471 "pkt_type: %d " 472 "stbc: %d " 473 "sgi: %d " 474 "rate_mcs: %d " 475 "receive_bandwidth: %d " 476 "reception_type: %d " 477 "toeplitz_hash: %d " 478 "nss: %d " 479 "ppdu_start_timestamp: %d " 480 "sw_phy_meta_data: %d ", 481 msdu_start->rxpcu_mpdu_filter_in_category, 482 msdu_start->sw_frame_group_id, 483 msdu_start->phy_ppdu_id, 484 msdu_start->msdu_length, 485 msdu_start->ipsec_esp, 486 msdu_start->l3_offset, 487 msdu_start->ipsec_ah, 488 msdu_start->l4_offset, 489 msdu_start->msdu_number, 490 msdu_start->decap_format, 491 msdu_start->ipv4_proto, 492 msdu_start->ipv6_proto, 493 msdu_start->tcp_proto, 494 msdu_start->udp_proto, 495 msdu_start->ip_frag, 496 msdu_start->tcp_only_ack, 497 msdu_start->da_is_bcast_mcast, 498 msdu_start->ip4_protocol_ip6_next_header, 499 msdu_start->toeplitz_hash_2_or_4, 500 msdu_start->flow_id_toeplitz, 501 msdu_start->user_rssi, 502 msdu_start->pkt_type, 503 msdu_start->stbc, 504 msdu_start->sgi, 505 msdu_start->rate_mcs, 506 msdu_start->receive_bandwidth, 507 msdu_start->reception_type, 508 msdu_start->toeplitz_hash, 509 msdu_start->nss, 510 msdu_start->ppdu_start_timestamp, 511 msdu_start->sw_phy_meta_data); 512 } 513 514 /** 515 * hal_rx_dump_msdu_end_tlv_8074: dump RX msdu_end TLV in structured 516 * human readable format. 517 * @ msdu_end: pointer the msdu_end TLV in pkt. 518 * @ dbg_level: log level. 519 * 520 * Return: void 521 */ 522 static void hal_rx_dump_msdu_end_tlv_8074(void *msduend, 523 uint8_t dbg_level) 524 { 525 struct rx_msdu_end *msdu_end = (struct rx_msdu_end *)msduend; 526 527 QDF_TRACE(QDF_MODULE_ID_DP, dbg_level, 528 "rx_msdu_end tlv - " 529 "rxpcu_mpdu_filter_in_category: %d " 530 "sw_frame_group_id: %d " 531 "phy_ppdu_id: %d " 532 "ip_hdr_chksum: %d " 533 "tcp_udp_chksum: %d " 534 "key_id_octet: %d " 535 "cce_super_rule: %d " 536 "cce_classify_not_done_truncat: %d " 537 "cce_classify_not_done_cce_dis: %d " 538 "ext_wapi_pn_63_48: %d " 539 "ext_wapi_pn_95_64: %d " 540 "ext_wapi_pn_127_96: %d " 541 "reported_mpdu_length: %d " 542 "first_msdu: %d " 543 "last_msdu: %d " 544 "sa_idx_timeout: %d " 545 "da_idx_timeout: %d " 546 "msdu_limit_error: %d " 547 "flow_idx_timeout: %d " 548 "flow_idx_invalid: %d " 549 "wifi_parser_error: %d " 550 "amsdu_parser_error: %d " 551 "sa_is_valid: %d " 552 "da_is_valid: %d " 553 "da_is_mcbc: %d " 554 "l3_header_padding: %d " 555 "ipv6_options_crc: %d " 556 "tcp_seq_number: %d " 557 "tcp_ack_number: %d " 558 "tcp_flag: %d " 559 "lro_eligible: %d " 560 "window_size: %d " 561 "da_offset: %d " 562 "sa_offset: %d " 563 "da_offset_valid: %d " 564 "sa_offset_valid: %d " 565 "rule_indication_31_0: %d " 566 "rule_indication_63_32: %d " 567 "sa_idx: %d " 568 "da_idx: %d " 569 "msdu_drop: %d " 570 "reo_destination_indication: %d " 571 "flow_idx: %d " 572 "fse_metadata: %d " 573 "cce_metadata: %d " 574 "sa_sw_peer_id: %d ", 575 msdu_end->rxpcu_mpdu_filter_in_category, 576 msdu_end->sw_frame_group_id, 577 msdu_end->phy_ppdu_id, 578 msdu_end->ip_hdr_chksum, 579 msdu_end->tcp_udp_chksum, 580 msdu_end->key_id_octet, 581 msdu_end->cce_super_rule, 582 msdu_end->cce_classify_not_done_truncate, 583 msdu_end->cce_classify_not_done_cce_dis, 584 msdu_end->ext_wapi_pn_63_48, 585 msdu_end->ext_wapi_pn_95_64, 586 msdu_end->ext_wapi_pn_127_96, 587 msdu_end->reported_mpdu_length, 588 msdu_end->first_msdu, 589 msdu_end->last_msdu, 590 msdu_end->sa_idx_timeout, 591 msdu_end->da_idx_timeout, 592 msdu_end->msdu_limit_error, 593 msdu_end->flow_idx_timeout, 594 msdu_end->flow_idx_invalid, 595 msdu_end->wifi_parser_error, 596 msdu_end->amsdu_parser_error, 597 msdu_end->sa_is_valid, 598 msdu_end->da_is_valid, 599 msdu_end->da_is_mcbc, 600 msdu_end->l3_header_padding, 601 msdu_end->ipv6_options_crc, 602 msdu_end->tcp_seq_number, 603 msdu_end->tcp_ack_number, 604 msdu_end->tcp_flag, 605 msdu_end->lro_eligible, 606 msdu_end->window_size, 607 msdu_end->da_offset, 608 msdu_end->sa_offset, 609 msdu_end->da_offset_valid, 610 msdu_end->sa_offset_valid, 611 msdu_end->rule_indication_31_0, 612 msdu_end->rule_indication_63_32, 613 msdu_end->sa_idx, 614 msdu_end->da_idx, 615 msdu_end->msdu_drop, 616 msdu_end->reo_destination_indication, 617 msdu_end->flow_idx, 618 msdu_end->fse_metadata, 619 msdu_end->cce_metadata, 620 msdu_end->sa_sw_peer_id); 621 } 622 623 624 /* 625 * Get tid from RX_MPDU_START 626 */ 627 #define HAL_RX_MPDU_INFO_TID_GET(_rx_mpdu_info) \ 628 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_info), \ 629 RX_MPDU_INFO_3_TID_OFFSET)), \ 630 RX_MPDU_INFO_3_TID_MASK, \ 631 RX_MPDU_INFO_3_TID_LSB)) 632 633 static uint32_t hal_rx_mpdu_start_tid_get_8074(uint8_t *buf) 634 { 635 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 636 struct rx_mpdu_start *mpdu_start = 637 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 638 uint32_t tid; 639 640 tid = HAL_RX_MPDU_INFO_TID_GET(&mpdu_start->rx_mpdu_info_details); 641 642 return tid; 643 } 644 645 #define HAL_RX_MSDU_START_RECEPTION_TYPE_GET(_rx_msdu_start) \ 646 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start), \ 647 RX_MSDU_START_5_RECEPTION_TYPE_OFFSET)), \ 648 RX_MSDU_START_5_RECEPTION_TYPE_MASK, \ 649 RX_MSDU_START_5_RECEPTION_TYPE_LSB)) 650 651 /* 652 * hal_rx_msdu_start_reception_type_get(): API to get the reception type 653 * Interval from rx_msdu_start 654 * 655 * @buf: pointer to the start of RX PKT TLV header 656 * Return: uint32_t(reception_type) 657 */ 658 static uint32_t hal_rx_msdu_start_reception_type_get_8074(uint8_t *buf) 659 { 660 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 661 struct rx_msdu_start *msdu_start = 662 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 663 uint32_t reception_type; 664 665 reception_type = HAL_RX_MSDU_START_RECEPTION_TYPE_GET(msdu_start); 666 667 return reception_type; 668 } 669 670 #define HAL_RX_MSDU_END_DA_IDX_GET(_rx_msdu_end) \ 671 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 672 RX_MSDU_END_13_DA_IDX_OFFSET)), \ 673 RX_MSDU_END_13_DA_IDX_MASK, \ 674 RX_MSDU_END_13_DA_IDX_LSB)) 675 676 /** 677 * hal_rx_msdu_end_da_idx_get_8074: API to get da_idx 678 * from rx_msdu_end TLV 679 * 680 * @ buf: pointer to the start of RX PKT TLV headers 681 * Return: da index 682 */ 683 static uint16_t hal_rx_msdu_end_da_idx_get_8074(uint8_t *buf) 684 { 685 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 686 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 687 uint16_t da_idx; 688 689 da_idx = HAL_RX_MSDU_END_DA_IDX_GET(msdu_end); 690 691 return da_idx; 692 } 693