1 /* 2 * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved. 3 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 #include "hal_hw_headers.h" 20 #include "hal_internal.h" 21 #include "cdp_txrx_mon_struct.h" 22 #include "qdf_trace.h" 23 #include "hal_li_rx.h" 24 #include "hal_tx.h" 25 #include "dp_types.h" 26 #include "hal_api_mon.h" 27 28 #define HAL_RX_MPDU_GET_SEQUENCE_NUMBER(_rx_mpdu_info) \ 29 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 30 RX_MPDU_INFO_2_MPDU_SEQUENCE_NUMBER_OFFSET)), \ 31 RX_MPDU_INFO_2_MPDU_SEQUENCE_NUMBER_MASK, \ 32 RX_MPDU_INFO_2_MPDU_SEQUENCE_NUMBER_LSB)) 33 34 #define HAL_RX_MSDU_END_DA_IS_MCBC_GET(_rx_msdu_end) \ 35 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 36 RX_MSDU_END_5_DA_IS_MCBC_OFFSET)), \ 37 RX_MSDU_END_5_DA_IS_MCBC_MASK, \ 38 RX_MSDU_END_5_DA_IS_MCBC_LSB)) 39 40 #define HAL_RX_MSDU_END_SA_IS_VALID_GET(_rx_msdu_end) \ 41 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 42 RX_MSDU_END_5_SA_IS_VALID_OFFSET)), \ 43 RX_MSDU_END_5_SA_IS_VALID_MASK, \ 44 RX_MSDU_END_5_SA_IS_VALID_LSB)) 45 46 #define HAL_RX_MSDU_END_SA_IDX_GET(_rx_msdu_end) \ 47 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 48 RX_MSDU_END_13_SA_IDX_OFFSET)), \ 49 RX_MSDU_END_13_SA_IDX_MASK, \ 50 RX_MSDU_END_13_SA_IDX_LSB)) 51 52 #define HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(_rx_msdu_end) \ 53 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 54 RX_MSDU_END_5_L3_HEADER_PADDING_OFFSET)), \ 55 RX_MSDU_END_5_L3_HEADER_PADDING_MASK, \ 56 RX_MSDU_END_5_L3_HEADER_PADDING_LSB)) 57 58 #define HAL_RX_MPDU_ENCRYPTION_INFO_VALID(_rx_mpdu_info) \ 59 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 60 RX_MPDU_INFO_2_FRAME_ENCRYPTION_INFO_VALID_OFFSET)), \ 61 RX_MPDU_INFO_2_FRAME_ENCRYPTION_INFO_VALID_MASK, \ 62 RX_MPDU_INFO_2_FRAME_ENCRYPTION_INFO_VALID_LSB)) 63 64 #define HAL_RX_MPDU_PN_31_0_GET(_rx_mpdu_info) \ 65 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 66 RX_MPDU_INFO_4_PN_31_0_OFFSET)), \ 67 RX_MPDU_INFO_4_PN_31_0_MASK, \ 68 RX_MPDU_INFO_4_PN_31_0_LSB)) 69 70 #define HAL_RX_MPDU_PN_63_32_GET(_rx_mpdu_info) \ 71 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 72 RX_MPDU_INFO_5_PN_63_32_OFFSET)), \ 73 RX_MPDU_INFO_5_PN_63_32_MASK, \ 74 RX_MPDU_INFO_5_PN_63_32_LSB)) 75 76 #define HAL_RX_MPDU_PN_95_64_GET(_rx_mpdu_info) \ 77 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 78 RX_MPDU_INFO_6_PN_95_64_OFFSET)), \ 79 RX_MPDU_INFO_6_PN_95_64_MASK, \ 80 RX_MPDU_INFO_6_PN_95_64_LSB)) 81 82 #define HAL_RX_MPDU_PN_127_96_GET(_rx_mpdu_info) \ 83 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 84 RX_MPDU_INFO_7_PN_127_96_OFFSET)), \ 85 RX_MPDU_INFO_7_PN_127_96_MASK, \ 86 RX_MPDU_INFO_7_PN_127_96_LSB)) 87 88 #define HAL_RX_MSDU_END_FIRST_MSDU_GET(_rx_msdu_end) \ 89 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 90 RX_MSDU_END_5_FIRST_MSDU_OFFSET)), \ 91 RX_MSDU_END_5_FIRST_MSDU_MASK, \ 92 RX_MSDU_END_5_FIRST_MSDU_LSB)) 93 94 #define HAL_RX_MSDU_END_DA_IS_VALID_GET(_rx_msdu_end) \ 95 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 96 RX_MSDU_END_5_DA_IS_VALID_OFFSET)), \ 97 RX_MSDU_END_5_DA_IS_VALID_MASK, \ 98 RX_MSDU_END_5_DA_IS_VALID_LSB)) 99 100 #define HAL_RX_MSDU_END_LAST_MSDU_GET(_rx_msdu_end) \ 101 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 102 RX_MSDU_END_5_LAST_MSDU_OFFSET)), \ 103 RX_MSDU_END_5_LAST_MSDU_MASK, \ 104 RX_MSDU_END_5_LAST_MSDU_LSB)) 105 106 #define HAL_RX_MPDU_GET_MAC_AD4_VALID(_rx_mpdu_info) \ 107 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 108 RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_OFFSET)), \ 109 RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_MASK, \ 110 RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_LSB)) 111 112 #define HAL_RX_MPDU_INFO_SW_PEER_ID_GET(_rx_mpdu_info) \ 113 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_info), \ 114 RX_MPDU_INFO_1_SW_PEER_ID_OFFSET)), \ 115 RX_MPDU_INFO_1_SW_PEER_ID_MASK, \ 116 RX_MPDU_INFO_1_SW_PEER_ID_LSB)) 117 118 #define HAL_RX_MPDU_GET_TODS(_rx_mpdu_info) \ 119 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 120 RX_MPDU_INFO_2_TO_DS_OFFSET)), \ 121 RX_MPDU_INFO_2_TO_DS_MASK, \ 122 RX_MPDU_INFO_2_TO_DS_LSB)) 123 124 #define HAL_RX_MPDU_GET_FROMDS(_rx_mpdu_info) \ 125 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 126 RX_MPDU_INFO_2_FR_DS_OFFSET)), \ 127 RX_MPDU_INFO_2_FR_DS_MASK, \ 128 RX_MPDU_INFO_2_FR_DS_LSB)) 129 130 #define HAL_RX_MPDU_GET_FRAME_CONTROL_VALID(_rx_mpdu_info) \ 131 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 132 RX_MPDU_INFO_2_MPDU_FRAME_CONTROL_VALID_OFFSET)), \ 133 RX_MPDU_INFO_2_MPDU_FRAME_CONTROL_VALID_MASK, \ 134 RX_MPDU_INFO_2_MPDU_FRAME_CONTROL_VALID_LSB)) 135 136 #define HAL_RX_MPDU_MAC_ADDR_AD1_VALID_GET(_rx_mpdu_info) \ 137 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 138 RX_MPDU_INFO_2_MAC_ADDR_AD1_VALID_OFFSET)), \ 139 RX_MPDU_INFO_2_MAC_ADDR_AD1_VALID_MASK, \ 140 RX_MPDU_INFO_2_MAC_ADDR_AD1_VALID_LSB)) 141 142 #define HAL_RX_MPDU_AD1_31_0_GET(_rx_mpdu_info) \ 143 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 144 RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_OFFSET)), \ 145 RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_MASK, \ 146 RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_LSB)) 147 148 #define HAL_RX_MPDU_AD1_47_32_GET(_rx_mpdu_info) \ 149 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 150 RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_OFFSET)), \ 151 RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_MASK, \ 152 RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_LSB)) 153 154 #define HAL_RX_MPDU_MAC_ADDR_AD2_VALID_GET(_rx_mpdu_info) \ 155 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 156 RX_MPDU_INFO_2_MAC_ADDR_AD2_VALID_OFFSET)), \ 157 RX_MPDU_INFO_2_MAC_ADDR_AD2_VALID_MASK, \ 158 RX_MPDU_INFO_2_MAC_ADDR_AD2_VALID_LSB)) 159 160 #define HAL_RX_MPDU_AD2_15_0_GET(_rx_mpdu_info) \ 161 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 162 RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_OFFSET)), \ 163 RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_MASK, \ 164 RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_LSB)) 165 166 #define HAL_RX_MPDU_AD2_47_16_GET(_rx_mpdu_info) \ 167 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 168 RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_OFFSET)), \ 169 RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_MASK, \ 170 RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_LSB)) 171 172 #define HAL_RX_MPDU_MAC_ADDR_AD3_VALID_GET(_rx_mpdu_info) \ 173 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 174 RX_MPDU_INFO_2_MAC_ADDR_AD3_VALID_OFFSET)), \ 175 RX_MPDU_INFO_2_MAC_ADDR_AD3_VALID_MASK, \ 176 RX_MPDU_INFO_2_MAC_ADDR_AD3_VALID_LSB)) 177 178 #define HAL_RX_MPDU_AD3_31_0_GET(_rx_mpdu_info) \ 179 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 180 RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_OFFSET)), \ 181 RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_MASK, \ 182 RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_LSB)) 183 184 #define HAL_RX_MPDU_AD3_47_32_GET(_rx_mpdu_info) \ 185 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 186 RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_OFFSET)), \ 187 RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_MASK, \ 188 RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_LSB)) 189 190 #define HAL_RX_MPDU_MAC_ADDR_AD4_VALID_GET(_rx_mpdu_info) \ 191 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 192 RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_OFFSET)), \ 193 RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_MASK, \ 194 RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_LSB)) 195 196 #define HAL_RX_MPDU_AD4_31_0_GET(_rx_mpdu_info) \ 197 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 198 RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_OFFSET)), \ 199 RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_MASK, \ 200 RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_LSB)) 201 202 #define HAL_RX_MPDU_AD4_47_32_GET(_rx_mpdu_info) \ 203 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 204 RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_OFFSET)), \ 205 RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_MASK, \ 206 RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_LSB)) 207 208 #define HAL_RX_MPDU_GET_SEQUENCE_CONTROL_VALID(_rx_mpdu_info) \ 209 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 210 RX_MPDU_INFO_2_MPDU_SEQUENCE_CONTROL_VALID_OFFSET)), \ 211 RX_MPDU_INFO_2_MPDU_SEQUENCE_CONTROL_VALID_MASK, \ 212 RX_MPDU_INFO_2_MPDU_SEQUENCE_CONTROL_VALID_LSB)) 213 214 #define HAL_RX_MPDU_INFO_QOS_CONTROL_VALID_GET(_rx_mpdu_info) \ 215 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_info), \ 216 RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_OFFSET)), \ 217 RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_MASK, \ 218 RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_LSB)) 219 220 #define HAL_RX_MSDU_END_SA_SW_PEER_ID_GET(_rx_msdu_end) \ 221 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 222 RX_MSDU_END_16_SA_SW_PEER_ID_OFFSET)), \ 223 RX_MSDU_END_16_SA_SW_PEER_ID_MASK, \ 224 RX_MSDU_END_16_SA_SW_PEER_ID_LSB)) 225 226 #define HAL_RX_MSDU0_BUFFER_ADDR_LSB(link_desc_va) \ 227 (uint8_t *)(link_desc_va) + \ 228 RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET 229 230 #define HAL_RX_MSDU_DESC_INFO_PTR_GET(msdu0) \ 231 (uint8_t *)(msdu0) + \ 232 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET 233 234 #define HAL_ENT_MPDU_DESC_INFO(ent_ring_desc) \ 235 (uint8_t *)(ent_ring_desc) + \ 236 RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET 237 238 #define HAL_DST_MPDU_DESC_INFO(dst_ring_desc) \ 239 (uint8_t *)(dst_ring_desc) + \ 240 REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET 241 242 #define HAL_RX_GET_FC_VALID(rx_mpdu_start) \ 243 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_2, MPDU_FRAME_CONTROL_VALID) 244 245 #define HAL_RX_GET_TO_DS_FLAG(rx_mpdu_start) \ 246 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_2, TO_DS) 247 248 #define HAL_RX_GET_MAC_ADDR1_VALID(rx_mpdu_start) \ 249 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_2, MAC_ADDR_AD1_VALID) 250 251 #define HAL_RX_GET_MAC_ADDR2_VALID(rx_mpdu_start) \ 252 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_2, MAC_ADDR_AD2_VALID) 253 254 #define HAL_RX_GET_FILTER_CATEGORY(rx_mpdu_start) \ 255 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_0, RXPCU_MPDU_FILTER_IN_CATEGORY) 256 257 #define HAL_RX_GET_PPDU_ID(rx_mpdu_start) \ 258 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_0, PHY_PPDU_ID) 259 260 #define HAL_RX_GET_SW_FRAME_GROUP_ID(rx_mpdu_start) \ 261 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_0, SW_FRAME_GROUP_ID) 262 263 #define HAL_RX_GET_SW_PEER_ID(rx_mpdu_start) \ 264 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_1, SW_PEER_ID) 265 266 #define HAL_REO_R0_CONFIG(soc, reg_val, reo_params) \ 267 do { \ 268 reg_val &= \ 269 ~(HWIO_REO_R0_GENERAL_ENABLE_FRAGMENT_DEST_RING_BMSK |\ 270 HWIO_REO_R0_GENERAL_ENABLE_AGING_LIST_ENABLE_BMSK | \ 271 HWIO_REO_R0_GENERAL_ENABLE_AGING_FLUSH_ENABLE_BMSK); \ 272 reg_val |= \ 273 HAL_SM(HWIO_REO_R0_GENERAL_ENABLE, \ 274 FRAGMENT_DEST_RING, \ 275 (reo_params)->frag_dst_ring) | \ 276 HAL_SM(HWIO_REO_R0_GENERAL_ENABLE, \ 277 AGING_LIST_ENABLE, 1) |\ 278 HAL_SM(HWIO_REO_R0_GENERAL_ENABLE, \ 279 AGING_FLUSH_ENABLE, 1);\ 280 HAL_REG_WRITE((soc), \ 281 HWIO_REO_R0_GENERAL_ENABLE_ADDR( \ 282 SEQ_WCSS_UMAC_REO_REG_OFFSET),\ 283 (reg_val)); \ 284 (reg_val) = \ 285 HAL_REG_READ((soc), \ 286 HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_ADDR( \ 287 SEQ_WCSS_UMAC_REO_REG_OFFSET)); \ 288 (reg_val) &= \ 289 ~(HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_0_BMSK); \ 290 (reg_val) |= \ 291 HAL_SM(HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0, \ 292 DEST_RING_ALT_MAPPING_0, \ 293 (reo_params)->alt_dst_ind_0); \ 294 HAL_REG_WRITE((soc), \ 295 HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_ADDR( \ 296 SEQ_WCSS_UMAC_REO_REG_OFFSET), \ 297 (reg_val)); \ 298 } while (0) 299 300 #define HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr) \ 301 ((struct rx_msdu_desc_info *) \ 302 _OFFSET_TO_BYTE_PTR((msdu_details_ptr), \ 303 UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET)) 304 305 #define HAL_RX_LINK_DESC_MSDU0_PTR(link_desc) \ 306 ((struct rx_msdu_details *) \ 307 _OFFSET_TO_BYTE_PTR((link_desc),\ 308 UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET)) 309 310 #define HAL_RX_MSDU_END_FLOW_IDX_GET(_rx_msdu_end) \ 311 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 312 RX_MSDU_END_14_FLOW_IDX_OFFSET)), \ 313 RX_MSDU_END_14_FLOW_IDX_MASK, \ 314 RX_MSDU_END_14_FLOW_IDX_LSB)) 315 316 #define HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(_rx_msdu_end) \ 317 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 318 RX_MSDU_END_5_FLOW_IDX_INVALID_OFFSET)), \ 319 RX_MSDU_END_5_FLOW_IDX_INVALID_MASK, \ 320 RX_MSDU_END_5_FLOW_IDX_INVALID_LSB)) 321 322 #define HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(_rx_msdu_end) \ 323 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 324 RX_MSDU_END_5_FLOW_IDX_TIMEOUT_OFFSET)), \ 325 RX_MSDU_END_5_FLOW_IDX_TIMEOUT_MASK, \ 326 RX_MSDU_END_5_FLOW_IDX_TIMEOUT_LSB)) 327 328 #define HAL_RX_MSDU_END_FSE_METADATA_GET(_rx_msdu_end) \ 329 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 330 RX_MSDU_END_15_FSE_METADATA_OFFSET)), \ 331 RX_MSDU_END_15_FSE_METADATA_MASK, \ 332 RX_MSDU_END_15_FSE_METADATA_LSB)) 333 334 #define HAL_RX_MSDU_END_CCE_METADATA_GET(_rx_msdu_end) \ 335 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 336 RX_MSDU_END_16_CCE_METADATA_OFFSET)), \ 337 RX_MSDU_END_16_CCE_METADATA_MASK, \ 338 RX_MSDU_END_16_CCE_METADATA_LSB)) 339 340 #define HAL_RX_TLV_GET_TCP_CHKSUM(buf) \ 341 (_HAL_MS( \ 342 (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ 343 msdu_end_tlv.rx_msdu_end), \ 344 RX_MSDU_END_1_TCP_UDP_CHKSUM_OFFSET)), \ 345 RX_MSDU_END_1_TCP_UDP_CHKSUM_MASK, \ 346 RX_MSDU_END_1_TCP_UDP_CHKSUM_LSB)) 347 348 /** 349 * hal_rx_msdu_start_nss_get_8074() - API to get the NSS from rx_msdu_start 350 * @buf: pointer to the start of RX PKT TLV header 351 * 352 * Return: uint32_t(nss) 353 */ 354 static uint32_t 355 hal_rx_msdu_start_nss_get_8074(uint8_t *buf) 356 { 357 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 358 struct rx_msdu_start *msdu_start = 359 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 360 uint32_t nss; 361 362 nss = HAL_RX_MSDU_START_NSS_GET(msdu_start); 363 return nss; 364 } 365 366 /** 367 * hal_rx_mon_hw_desc_get_mpdu_status_8074() - Retrieve MPDU status 368 * @hw_desc_addr: Start address of Rx HW TLVs 369 * @rs: Status for monitor mode 370 * 371 * Return: void 372 */ 373 static void hal_rx_mon_hw_desc_get_mpdu_status_8074(void *hw_desc_addr, 374 struct mon_rx_status *rs) 375 { 376 struct rx_msdu_start *rx_msdu_start; 377 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr; 378 uint32_t reg_value; 379 const uint32_t sgi_hw_to_cdp[] = { 380 CDP_SGI_0_8_US, 381 CDP_SGI_0_4_US, 382 CDP_SGI_1_6_US, 383 CDP_SGI_3_2_US, 384 }; 385 386 rx_msdu_start = &rx_desc->msdu_start_tlv.rx_msdu_start; 387 388 HAL_RX_GET_MSDU_AGGREGATION(rx_desc, rs); 389 390 rs->ant_signal_db = HAL_RX_GET(rx_msdu_start, 391 RX_MSDU_START_5, USER_RSSI); 392 rs->is_stbc = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, STBC); 393 394 reg_value = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, SGI); 395 rs->sgi = sgi_hw_to_cdp[reg_value]; 396 rs->nr_ant = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, NSS); 397 reg_value = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, RECEPTION_TYPE); 398 rs->beamformed = (reg_value == HAL_RX_RECEPTION_TYPE_MU_MIMO) ? 1 : 0; 399 /* TODO: rs->beamformed should be set for SU beamforming also */ 400 } 401 402 #define LINK_DESC_SIZE (NUM_OF_DWORDS_RX_MSDU_LINK << 2) 403 static uint32_t hal_get_link_desc_size_8074(void) 404 { 405 return LINK_DESC_SIZE; 406 } 407 408 /** 409 * hal_rx_get_tlv_8074() - API to get the tlv 410 * @rx_tlv: TLV data extracted from the rx packet 411 * 412 * Return: uint8_t 413 */ 414 static uint8_t hal_rx_get_tlv_8074(void *rx_tlv) 415 { 416 return HAL_RX_GET(rx_tlv, PHYRX_RSSI_LEGACY_35, RECEIVE_BANDWIDTH); 417 } 418 419 /** 420 * hal_rx_proc_phyrx_other_receive_info_tlv_8074() 421 * - process other receive info TLV 422 * @rx_tlv_hdr: pointer to TLV header 423 * @ppdu_info: pointer to ppdu_info 424 * 425 * Return: None 426 */ 427 static 428 void hal_rx_proc_phyrx_other_receive_info_tlv_8074(void *rx_tlv_hdr, 429 void *ppdu_info) 430 { 431 } 432 433 434 /** 435 * hal_rx_dump_msdu_start_tlv_8074() : dump RX msdu_start TLV in structured 436 * human readable format. 437 * @msdustart: pointer the msdu_start TLV in pkt. 438 * @dbg_level: log level. 439 * 440 * Return: void 441 */ 442 static void hal_rx_dump_msdu_start_tlv_8074(void *msdustart, 443 uint8_t dbg_level) 444 { 445 struct rx_msdu_start *msdu_start = (struct rx_msdu_start *)msdustart; 446 447 QDF_TRACE(QDF_MODULE_ID_DP, dbg_level, 448 "rx_msdu_start tlv - " 449 "rxpcu_mpdu_filter_in_category: %d " 450 "sw_frame_group_id: %d " 451 "phy_ppdu_id: %d " 452 "msdu_length: %d " 453 "ipsec_esp: %d " 454 "l3_offset: %d " 455 "ipsec_ah: %d " 456 "l4_offset: %d " 457 "msdu_number: %d " 458 "decap_format: %d " 459 "ipv4_proto: %d " 460 "ipv6_proto: %d " 461 "tcp_proto: %d " 462 "udp_proto: %d " 463 "ip_frag: %d " 464 "tcp_only_ack: %d " 465 "da_is_bcast_mcast: %d " 466 "ip4_protocol_ip6_next_header: %d " 467 "toeplitz_hash_2_or_4: %d " 468 "flow_id_toeplitz: %d " 469 "user_rssi: %d " 470 "pkt_type: %d " 471 "stbc: %d " 472 "sgi: %d " 473 "rate_mcs: %d " 474 "receive_bandwidth: %d " 475 "reception_type: %d " 476 "toeplitz_hash: %d " 477 "nss: %d " 478 "ppdu_start_timestamp: %d " 479 "sw_phy_meta_data: %d ", 480 msdu_start->rxpcu_mpdu_filter_in_category, 481 msdu_start->sw_frame_group_id, 482 msdu_start->phy_ppdu_id, 483 msdu_start->msdu_length, 484 msdu_start->ipsec_esp, 485 msdu_start->l3_offset, 486 msdu_start->ipsec_ah, 487 msdu_start->l4_offset, 488 msdu_start->msdu_number, 489 msdu_start->decap_format, 490 msdu_start->ipv4_proto, 491 msdu_start->ipv6_proto, 492 msdu_start->tcp_proto, 493 msdu_start->udp_proto, 494 msdu_start->ip_frag, 495 msdu_start->tcp_only_ack, 496 msdu_start->da_is_bcast_mcast, 497 msdu_start->ip4_protocol_ip6_next_header, 498 msdu_start->toeplitz_hash_2_or_4, 499 msdu_start->flow_id_toeplitz, 500 msdu_start->user_rssi, 501 msdu_start->pkt_type, 502 msdu_start->stbc, 503 msdu_start->sgi, 504 msdu_start->rate_mcs, 505 msdu_start->receive_bandwidth, 506 msdu_start->reception_type, 507 msdu_start->toeplitz_hash, 508 msdu_start->nss, 509 msdu_start->ppdu_start_timestamp, 510 msdu_start->sw_phy_meta_data); 511 } 512 513 /** 514 * hal_rx_dump_msdu_end_tlv_8074() - dump RX msdu_end TLV in structured 515 * human readable format. 516 * @msduend: pointer the msdu_end TLV in pkt. 517 * @dbg_level: log level. 518 * 519 * Return: void 520 */ 521 static void hal_rx_dump_msdu_end_tlv_8074(void *msduend, 522 uint8_t dbg_level) 523 { 524 struct rx_msdu_end *msdu_end = (struct rx_msdu_end *)msduend; 525 526 QDF_TRACE(QDF_MODULE_ID_DP, dbg_level, 527 "rx_msdu_end tlv - " 528 "rxpcu_mpdu_filter_in_category: %d " 529 "sw_frame_group_id: %d " 530 "phy_ppdu_id: %d " 531 "ip_hdr_chksum: %d " 532 "tcp_udp_chksum: %d " 533 "key_id_octet: %d " 534 "cce_super_rule: %d " 535 "cce_classify_not_done_truncat: %d " 536 "cce_classify_not_done_cce_dis: %d " 537 "ext_wapi_pn_63_48: %d " 538 "ext_wapi_pn_95_64: %d " 539 "ext_wapi_pn_127_96: %d " 540 "reported_mpdu_length: %d " 541 "first_msdu: %d " 542 "last_msdu: %d " 543 "sa_idx_timeout: %d " 544 "da_idx_timeout: %d " 545 "msdu_limit_error: %d " 546 "flow_idx_timeout: %d " 547 "flow_idx_invalid: %d " 548 "wifi_parser_error: %d " 549 "amsdu_parser_error: %d " 550 "sa_is_valid: %d " 551 "da_is_valid: %d " 552 "da_is_mcbc: %d " 553 "l3_header_padding: %d " 554 "ipv6_options_crc: %d " 555 "tcp_seq_number: %d " 556 "tcp_ack_number: %d " 557 "tcp_flag: %d " 558 "lro_eligible: %d " 559 "window_size: %d " 560 "da_offset: %d " 561 "sa_offset: %d " 562 "da_offset_valid: %d " 563 "sa_offset_valid: %d " 564 "rule_indication_31_0: %d " 565 "rule_indication_63_32: %d " 566 "sa_idx: %d " 567 "da_idx: %d " 568 "msdu_drop: %d " 569 "reo_destination_indication: %d " 570 "flow_idx: %d " 571 "fse_metadata: %d " 572 "cce_metadata: %d " 573 "sa_sw_peer_id: %d ", 574 msdu_end->rxpcu_mpdu_filter_in_category, 575 msdu_end->sw_frame_group_id, 576 msdu_end->phy_ppdu_id, 577 msdu_end->ip_hdr_chksum, 578 msdu_end->tcp_udp_chksum, 579 msdu_end->key_id_octet, 580 msdu_end->cce_super_rule, 581 msdu_end->cce_classify_not_done_truncate, 582 msdu_end->cce_classify_not_done_cce_dis, 583 msdu_end->ext_wapi_pn_63_48, 584 msdu_end->ext_wapi_pn_95_64, 585 msdu_end->ext_wapi_pn_127_96, 586 msdu_end->reported_mpdu_length, 587 msdu_end->first_msdu, 588 msdu_end->last_msdu, 589 msdu_end->sa_idx_timeout, 590 msdu_end->da_idx_timeout, 591 msdu_end->msdu_limit_error, 592 msdu_end->flow_idx_timeout, 593 msdu_end->flow_idx_invalid, 594 msdu_end->wifi_parser_error, 595 msdu_end->amsdu_parser_error, 596 msdu_end->sa_is_valid, 597 msdu_end->da_is_valid, 598 msdu_end->da_is_mcbc, 599 msdu_end->l3_header_padding, 600 msdu_end->ipv6_options_crc, 601 msdu_end->tcp_seq_number, 602 msdu_end->tcp_ack_number, 603 msdu_end->tcp_flag, 604 msdu_end->lro_eligible, 605 msdu_end->window_size, 606 msdu_end->da_offset, 607 msdu_end->sa_offset, 608 msdu_end->da_offset_valid, 609 msdu_end->sa_offset_valid, 610 msdu_end->rule_indication_31_0, 611 msdu_end->rule_indication_63_32, 612 msdu_end->sa_idx, 613 msdu_end->da_idx, 614 msdu_end->msdu_drop, 615 msdu_end->reo_destination_indication, 616 msdu_end->flow_idx, 617 msdu_end->fse_metadata, 618 msdu_end->cce_metadata, 619 msdu_end->sa_sw_peer_id); 620 } 621 622 623 /* 624 * Get tid from RX_MPDU_START 625 */ 626 #define HAL_RX_MPDU_INFO_TID_GET(_rx_mpdu_info) \ 627 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_info), \ 628 RX_MPDU_INFO_3_TID_OFFSET)), \ 629 RX_MPDU_INFO_3_TID_MASK, \ 630 RX_MPDU_INFO_3_TID_LSB)) 631 632 static uint32_t hal_rx_mpdu_start_tid_get_8074(uint8_t *buf) 633 { 634 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 635 struct rx_mpdu_start *mpdu_start = 636 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 637 uint32_t tid; 638 639 tid = HAL_RX_MPDU_INFO_TID_GET(&mpdu_start->rx_mpdu_info_details); 640 641 return tid; 642 } 643 644 #define HAL_RX_MSDU_START_RECEPTION_TYPE_GET(_rx_msdu_start) \ 645 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start), \ 646 RX_MSDU_START_5_RECEPTION_TYPE_OFFSET)), \ 647 RX_MSDU_START_5_RECEPTION_TYPE_MASK, \ 648 RX_MSDU_START_5_RECEPTION_TYPE_LSB)) 649 650 /** 651 * hal_rx_msdu_start_reception_type_get_8074() - API to get the reception type 652 * Interval from rx_msdu_start 653 * @buf: pointer to the start of RX PKT TLV header 654 * 655 * Return: uint32_t(reception_type) 656 */ 657 static uint32_t hal_rx_msdu_start_reception_type_get_8074(uint8_t *buf) 658 { 659 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 660 struct rx_msdu_start *msdu_start = 661 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 662 uint32_t reception_type; 663 664 reception_type = HAL_RX_MSDU_START_RECEPTION_TYPE_GET(msdu_start); 665 666 return reception_type; 667 } 668 669 #define HAL_RX_MSDU_END_DA_IDX_GET(_rx_msdu_end) \ 670 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 671 RX_MSDU_END_13_DA_IDX_OFFSET)), \ 672 RX_MSDU_END_13_DA_IDX_MASK, \ 673 RX_MSDU_END_13_DA_IDX_LSB)) 674 675 /** 676 * hal_rx_msdu_end_da_idx_get_8074() - API to get da_idx from rx_msdu_end TLV 677 * @buf: pointer to the start of RX PKT TLV headers 678 * 679 * Return: da index 680 */ 681 static uint16_t hal_rx_msdu_end_da_idx_get_8074(uint8_t *buf) 682 { 683 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 684 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 685 uint16_t da_idx; 686 687 da_idx = HAL_RX_MSDU_END_DA_IDX_GET(msdu_end); 688 689 return da_idx; 690 } 691