1 /* 2 * Copyright (c) 2016-2020 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 #include "hal_hw_headers.h" 19 #include "hal_internal.h" 20 #include "hal_api.h" 21 #include "target_type.h" 22 #include "wcss_version.h" 23 #include "qdf_module.h" 24 25 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_OFFSET \ 26 RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_OFFSET 27 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_MASK \ 28 RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_MASK 29 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_LSB \ 30 RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_LSB 31 #define UNIFIED_PHYRX_HT_SIG_0_HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS_OFFSET \ 32 PHYRX_HT_SIG_0_HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS_OFFSET 33 #define UNIFIED_PHYRX_L_SIG_B_0_L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS_OFFSET \ 34 PHYRX_L_SIG_B_0_L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS_OFFSET 35 #define UNIFIED_PHYRX_L_SIG_A_0_L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS_OFFSET \ 36 PHYRX_L_SIG_A_0_L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS_OFFSET 37 #define UNIFIED_PHYRX_VHT_SIG_A_0_VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS_OFFSET \ 38 PHYRX_VHT_SIG_A_0_VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS_OFFSET 39 #define UNIFIED_PHYRX_HE_SIG_A_SU_0_HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS_OFFSET \ 40 PHYRX_HE_SIG_A_SU_0_HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS_OFFSET 41 #define UNIFIED_PHYRX_HE_SIG_A_MU_DL_0_HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_OFFSET \ 42 PHYRX_HE_SIG_A_MU_DL_0_HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_OFFSET 43 #define UNIFIED_PHYRX_HE_SIG_B1_MU_0_HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_OFFSET \ 44 PHYRX_HE_SIG_B1_MU_0_HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_OFFSET 45 #define UNIFIED_PHYRX_HE_SIG_B2_MU_0_HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_OFFSET \ 46 PHYRX_HE_SIG_B2_MU_0_HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_OFFSET 47 #define UNIFIED_PHYRX_HE_SIG_B2_OFDMA_0_HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_OFFSET \ 48 PHYRX_HE_SIG_B2_OFDMA_0_HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_OFFSET 49 #define UNIFIED_PHYRX_RSSI_LEGACY_3_RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS_OFFSET \ 50 PHYRX_RSSI_LEGACY_3_RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS_OFFSET 51 #define UNIFIED_PHYRX_RSSI_LEGACY_19_RECEIVE_RSSI_INFO_PREAMBLE_RSSI_INFO_DETAILS_OFFSET \ 52 PHYRX_RSSI_LEGACY_19_RECEIVE_RSSI_INFO_PREAMBLE_RSSI_INFO_DETAILS_OFFSET 53 #define UNIFIED_RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET \ 54 RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET 55 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 56 RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET 57 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ 58 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET 59 #define UNIFIED_RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 60 RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET 61 #define UNIFIED_REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 62 REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET 63 #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC \ 64 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER 65 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSE \ 66 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET 67 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 68 RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET 69 #define UNIFIED_TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 70 TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET 71 #define UNIFIED_TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 72 TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET 73 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET \ 74 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET 75 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB \ 76 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB 77 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK \ 78 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK 79 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB \ 80 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB 81 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK \ 82 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK 83 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB \ 84 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB 85 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK \ 86 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK 87 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB \ 88 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB 89 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK \ 90 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK 91 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB \ 92 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB 93 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK \ 94 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK 95 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_MASK \ 96 WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_MASK 97 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_OFFSET \ 98 WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_OFFSET 99 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_LSB \ 100 WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_LSB 101 102 #include "hal_8074v1_tx.h" 103 #include "hal_8074v1_rx.h" 104 #include <hal_generic_api.h> 105 #include <hal_wbm.h> 106 107 /** 108 * hal_get_window_address_8074(): Function to get hp/tp address 109 * @hal_soc: Pointer to hal_soc 110 * @addr: address offset of register 111 * 112 * Return: modified address offset of register 113 */ 114 static inline qdf_iomem_t hal_get_window_address_8074(struct hal_soc *hal_soc, 115 qdf_iomem_t addr) 116 { 117 return addr; 118 } 119 120 /** 121 * hal_rx_get_rx_fragment_number_8074v1(): Function to retrieve 122 * rx fragment number 123 * 124 * @nbuf: Network buffer 125 * Returns: rx fragment number 126 */ 127 static 128 uint8_t hal_rx_get_rx_fragment_number_8074v1(uint8_t *buf) 129 { 130 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 131 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 132 133 /* Return first 4 bits as fragment number */ 134 return (HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info) & 135 DOT11_SEQ_FRAG_MASK); 136 } 137 138 /** 139 * hal_rx_msdu_end_da_is_mcbc_get_8074v1(): API to check if 140 * pkt is MCBC from rx_msdu_end TLV 141 * 142 * @ buf: pointer to the start of RX PKT TLV headers 143 * Return: da_is_mcbc 144 */ 145 static uint8_t 146 hal_rx_msdu_end_da_is_mcbc_get_8074v1(uint8_t *buf) 147 { 148 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 149 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 150 151 return HAL_RX_MSDU_END_DA_IS_MCBC_GET(msdu_end); 152 } 153 154 /** 155 * hal_rx_msdu_end_sa_is_valid_get_8074v1(): API to get_8074v1 the 156 * sa_is_valid bit from rx_msdu_end TLV 157 * 158 * @ buf: pointer to the start of RX PKT TLV headers 159 * Return: sa_is_valid bit 160 */ 161 static uint8_t 162 hal_rx_msdu_end_sa_is_valid_get_8074v1(uint8_t *buf) 163 { 164 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 165 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 166 uint8_t sa_is_valid; 167 168 sa_is_valid = HAL_RX_MSDU_END_SA_IS_VALID_GET(msdu_end); 169 170 return sa_is_valid; 171 } 172 173 /** 174 * hal_rx_msdu_end_sa_idx_get_8074v1(): API to get_8074v1 the 175 * sa_idx from rx_msdu_end TLV 176 * 177 * @ buf: pointer to the start of RX PKT TLV headers 178 * Return: sa_idx (SA AST index) 179 */ 180 static uint16_t hal_rx_msdu_end_sa_idx_get_8074v1(uint8_t *buf) 181 { 182 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 183 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 184 uint16_t sa_idx; 185 186 sa_idx = HAL_RX_MSDU_END_SA_IDX_GET(msdu_end); 187 188 return sa_idx; 189 } 190 191 /** 192 * hal_rx_desc_is_first_msdu_8074v1() - Check if first msdu 193 * 194 * @hal_soc_hdl: hal_soc handle 195 * @hw_desc_addr: hardware descriptor address 196 * 197 * Return: 0 - success/ non-zero failure 198 */ 199 static uint32_t hal_rx_desc_is_first_msdu_8074v1(void *hw_desc_addr) 200 { 201 struct rx_pkt_tlvs *rx_tlvs = (struct rx_pkt_tlvs *)hw_desc_addr; 202 struct rx_msdu_end *msdu_end = &rx_tlvs->msdu_end_tlv.rx_msdu_end; 203 204 return HAL_RX_GET(msdu_end, RX_MSDU_END_5, FIRST_MSDU); 205 } 206 207 /** 208 * hal_rx_msdu_end_l3_hdr_padding_get_8074v1(): API to get_8074v1 the 209 * l3_header padding from rx_msdu_end TLV 210 * 211 * @ buf: pointer to the start of RX PKT TLV headers 212 * Return: number of l3 header padding bytes 213 */ 214 static uint32_t hal_rx_msdu_end_l3_hdr_padding_get_8074v1(uint8_t *buf) 215 { 216 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 217 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 218 uint32_t l3_header_padding; 219 220 l3_header_padding = HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(msdu_end); 221 222 return l3_header_padding; 223 } 224 225 /* 226 * @ hal_rx_encryption_info_valid_8074v1: Returns encryption type. 227 * 228 * @ buf: rx_tlv_hdr of the received packet 229 * @ Return: encryption type 230 */ 231 static uint32_t hal_rx_encryption_info_valid_8074v1(uint8_t *buf) 232 { 233 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 234 struct rx_mpdu_start *mpdu_start = 235 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 236 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 237 uint32_t encryption_info = HAL_RX_MPDU_ENCRYPTION_INFO_VALID(mpdu_info); 238 239 return encryption_info; 240 } 241 242 /* 243 * @ hal_rx_print_pn_8074v1: Prints the PN of rx packet. 244 * 245 * @ buf: rx_tlv_hdr of the received packet 246 * @ Return: void 247 */ 248 static void hal_rx_print_pn_8074v1(uint8_t *buf) 249 { 250 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 251 struct rx_mpdu_start *mpdu_start = 252 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 253 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 254 255 uint32_t pn_31_0 = HAL_RX_MPDU_PN_31_0_GET(mpdu_info); 256 uint32_t pn_63_32 = HAL_RX_MPDU_PN_63_32_GET(mpdu_info); 257 uint32_t pn_95_64 = HAL_RX_MPDU_PN_95_64_GET(mpdu_info); 258 uint32_t pn_127_96 = HAL_RX_MPDU_PN_127_96_GET(mpdu_info); 259 260 hal_debug("PN number pn_127_96 0x%x pn_95_64 0x%x pn_63_32 0x%x pn_31_0 0x%x ", 261 pn_127_96, pn_95_64, pn_63_32, pn_31_0); 262 } 263 264 /** 265 * hal_rx_msdu_end_first_msdu_get_8074v1: API to get first msdu status 266 * from rx_msdu_end TLV 267 * 268 * @ buf: pointer to the start of RX PKT TLV headers 269 * Return: first_msdu 270 */ 271 static uint8_t 272 hal_rx_msdu_end_first_msdu_get_8074v1(uint8_t *buf) 273 { 274 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 275 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 276 uint8_t first_msdu; 277 278 first_msdu = HAL_RX_MSDU_END_FIRST_MSDU_GET(msdu_end); 279 280 return first_msdu; 281 } 282 283 /** 284 * hal_rx_msdu_end_da_is_valid_get_8074v1: API to check if da is valid 285 * from rx_msdu_end TLV 286 * 287 * @ buf: pointer to the start of RX PKT TLV headers 288 * Return: da_is_valid 289 */ 290 static uint8_t hal_rx_msdu_end_da_is_valid_get_8074v1(uint8_t *buf) 291 { 292 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 293 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 294 uint8_t da_is_valid; 295 296 da_is_valid = HAL_RX_MSDU_END_DA_IS_VALID_GET(msdu_end); 297 298 return da_is_valid; 299 } 300 301 /** 302 * hal_rx_msdu_end_last_msdu_get_8074v1: API to get last msdu status 303 * from rx_msdu_end TLV 304 * 305 * @ buf: pointer to the start of RX PKT TLV headers 306 * Return: last_msdu 307 */ 308 static uint8_t hal_rx_msdu_end_last_msdu_get_8074v1(uint8_t *buf) 309 { 310 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 311 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 312 uint8_t last_msdu; 313 314 last_msdu = HAL_RX_MSDU_END_LAST_MSDU_GET(msdu_end); 315 316 return last_msdu; 317 } 318 319 /* 320 * hal_rx_get_mpdu_mac_ad4_valid_8074v1(): Retrieves if mpdu 4th addr is valid 321 * 322 * @nbuf: Network buffer 323 * Returns: value of mpdu 4th address valid field 324 */ 325 static bool hal_rx_get_mpdu_mac_ad4_valid_8074v1(uint8_t *buf) 326 { 327 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 328 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 329 bool ad4_valid = 0; 330 331 ad4_valid = HAL_RX_MPDU_GET_MAC_AD4_VALID(rx_mpdu_info); 332 333 return ad4_valid; 334 } 335 336 /** 337 * hal_rx_mpdu_start_sw_peer_id_get_8074v1: Retrieve sw peer_id 338 * @buf: network buffer 339 * 340 * Return: sw peer_id 341 */ 342 static uint32_t hal_rx_mpdu_start_sw_peer_id_get_8074v1(uint8_t *buf) 343 { 344 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 345 struct rx_mpdu_start *mpdu_start = 346 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 347 348 return HAL_RX_MPDU_INFO_SW_PEER_ID_GET( 349 &mpdu_start->rx_mpdu_info_details); 350 } 351 352 /* 353 * hal_rx_mpdu_get_to_ds_8074v1(): API to get the tods info 354 * from rx_mpdu_start 355 * 356 * @buf: pointer to the start of RX PKT TLV header 357 * Return: uint32_t(to_ds) 358 */ 359 360 static uint32_t hal_rx_mpdu_get_to_ds_8074v1(uint8_t *buf) 361 { 362 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 363 struct rx_mpdu_start *mpdu_start = 364 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 365 366 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 367 368 return HAL_RX_MPDU_GET_TODS(mpdu_info); 369 } 370 371 /* 372 * hal_rx_mpdu_get_fr_ds_8074v1(): API to get the from ds info 373 * from rx_mpdu_start 374 * 375 * @buf: pointer to the start of RX PKT TLV header 376 * Return: uint32_t(fr_ds) 377 */ 378 static uint32_t hal_rx_mpdu_get_fr_ds_8074v1(uint8_t *buf) 379 { 380 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 381 struct rx_mpdu_start *mpdu_start = 382 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 383 384 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 385 386 return HAL_RX_MPDU_GET_FROMDS(mpdu_info); 387 } 388 389 /* 390 * hal_rx_get_mpdu_frame_control_valid_8074v1(): Retrieves mpdu 391 * frame control valid 392 * 393 * @nbuf: Network buffer 394 * Returns: value of frame control valid field 395 */ 396 static uint8_t hal_rx_get_mpdu_frame_control_valid_8074v1(uint8_t *buf) 397 { 398 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 399 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 400 401 return HAL_RX_MPDU_GET_FRAME_CONTROL_VALID(rx_mpdu_info); 402 } 403 404 /* 405 * hal_rx_mpdu_get_addr1_8074v1(): API to check get address1 of the mpdu 406 * 407 * @buf: pointer to the start of RX PKT TLV headera 408 * @mac_addr: pointer to mac address 409 * Return: success/failure 410 */ 411 static QDF_STATUS hal_rx_mpdu_get_addr1_8074v1(uint8_t *buf, 412 uint8_t *mac_addr) 413 { 414 struct __attribute__((__packed__)) hal_addr1 { 415 uint32_t ad1_31_0; 416 uint16_t ad1_47_32; 417 }; 418 419 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 420 struct rx_mpdu_start *mpdu_start = 421 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 422 423 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 424 struct hal_addr1 *addr = (struct hal_addr1 *)mac_addr; 425 uint32_t mac_addr_ad1_valid; 426 427 mac_addr_ad1_valid = HAL_RX_MPDU_MAC_ADDR_AD1_VALID_GET(mpdu_info); 428 429 if (mac_addr_ad1_valid) { 430 addr->ad1_31_0 = HAL_RX_MPDU_AD1_31_0_GET(mpdu_info); 431 addr->ad1_47_32 = HAL_RX_MPDU_AD1_47_32_GET(mpdu_info); 432 return QDF_STATUS_SUCCESS; 433 } 434 435 return QDF_STATUS_E_FAILURE; 436 } 437 438 /* 439 * hal_rx_mpdu_get_addr2_8074v1(): API to check get address2 of the mpdu 440 * in the packet 441 * 442 * @buf: pointer to the start of RX PKT TLV header 443 * @mac_addr: pointer to mac address 444 * Return: success/failure 445 */ 446 static QDF_STATUS hal_rx_mpdu_get_addr2_8074v1(uint8_t *buf, uint8_t *mac_addr) 447 { 448 struct __attribute__((__packed__)) hal_addr2 { 449 uint16_t ad2_15_0; 450 uint32_t ad2_47_16; 451 }; 452 453 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 454 struct rx_mpdu_start *mpdu_start = 455 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 456 457 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 458 struct hal_addr2 *addr = (struct hal_addr2 *)mac_addr; 459 uint32_t mac_addr_ad2_valid; 460 461 mac_addr_ad2_valid = HAL_RX_MPDU_MAC_ADDR_AD2_VALID_GET(mpdu_info); 462 463 if (mac_addr_ad2_valid) { 464 addr->ad2_15_0 = HAL_RX_MPDU_AD2_15_0_GET(mpdu_info); 465 addr->ad2_47_16 = HAL_RX_MPDU_AD2_47_16_GET(mpdu_info); 466 return QDF_STATUS_SUCCESS; 467 } 468 469 return QDF_STATUS_E_FAILURE; 470 } 471 472 /* 473 * hal_rx_mpdu_get_addr3_8074v1(): API to get address3 of the mpdu 474 * in the packet 475 * 476 * @buf: pointer to the start of RX PKT TLV header 477 * @mac_addr: pointer to mac address 478 * Return: success/failure 479 */ 480 static QDF_STATUS hal_rx_mpdu_get_addr3_8074v1(uint8_t *buf, uint8_t *mac_addr) 481 { 482 struct __attribute__((__packed__)) hal_addr3 { 483 uint32_t ad3_31_0; 484 uint16_t ad3_47_32; 485 }; 486 487 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 488 struct rx_mpdu_start *mpdu_start = 489 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 490 491 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 492 struct hal_addr3 *addr = (struct hal_addr3 *)mac_addr; 493 uint32_t mac_addr_ad3_valid; 494 495 mac_addr_ad3_valid = HAL_RX_MPDU_MAC_ADDR_AD3_VALID_GET(mpdu_info); 496 497 if (mac_addr_ad3_valid) { 498 addr->ad3_31_0 = HAL_RX_MPDU_AD3_31_0_GET(mpdu_info); 499 addr->ad3_47_32 = HAL_RX_MPDU_AD3_47_32_GET(mpdu_info); 500 return QDF_STATUS_SUCCESS; 501 } 502 503 return QDF_STATUS_E_FAILURE; 504 } 505 506 /* 507 * hal_rx_mpdu_get_addr4_8074v1(): API to get address4 of the mpdu 508 * in the packet 509 * 510 * @buf: pointer to the start of RX PKT TLV header 511 * @mac_addr: pointer to mac address 512 * Return: success/failure 513 */ 514 static QDF_STATUS hal_rx_mpdu_get_addr4_8074v1(uint8_t *buf, uint8_t *mac_addr) 515 { 516 struct __attribute__((__packed__)) hal_addr4 { 517 uint32_t ad4_31_0; 518 uint16_t ad4_47_32; 519 }; 520 521 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 522 struct rx_mpdu_start *mpdu_start = 523 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 524 525 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 526 struct hal_addr4 *addr = (struct hal_addr4 *)mac_addr; 527 uint32_t mac_addr_ad4_valid; 528 529 mac_addr_ad4_valid = HAL_RX_MPDU_MAC_ADDR_AD4_VALID_GET(mpdu_info); 530 531 if (mac_addr_ad4_valid) { 532 addr->ad4_31_0 = HAL_RX_MPDU_AD4_31_0_GET(mpdu_info); 533 addr->ad4_47_32 = HAL_RX_MPDU_AD4_47_32_GET(mpdu_info); 534 return QDF_STATUS_SUCCESS; 535 } 536 537 return QDF_STATUS_E_FAILURE; 538 } 539 540 /* 541 * hal_rx_get_mpdu_sequence_control_valid_8074v1(): Get mpdu 542 * sequence control valid 543 * 544 * @nbuf: Network buffer 545 * Returns: value of sequence control valid field 546 */ 547 static uint8_t hal_rx_get_mpdu_sequence_control_valid_8074v1(uint8_t *buf) 548 { 549 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 550 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 551 552 return HAL_RX_MPDU_GET_SEQUENCE_CONTROL_VALID(rx_mpdu_info); 553 } 554 555 /** 556 * hal_rx_is_unicast_8074v1: check packet is unicast frame or not. 557 * 558 * @ buf: pointer to rx pkt TLV. 559 * 560 * Return: true on unicast. 561 */ 562 static bool hal_rx_is_unicast_8074v1(uint8_t *buf) 563 { 564 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 565 struct rx_mpdu_start *mpdu_start = 566 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 567 uint32_t grp_id; 568 uint8_t *rx_mpdu_info = (uint8_t *)&mpdu_start->rx_mpdu_info_details; 569 570 grp_id = (_HAL_MS((*_OFFSET_TO_WORD_PTR((rx_mpdu_info), 571 RX_MPDU_INFO_0_SW_FRAME_GROUP_ID_OFFSET)), 572 RX_MPDU_INFO_0_SW_FRAME_GROUP_ID_MASK, 573 RX_MPDU_INFO_0_SW_FRAME_GROUP_ID_LSB)); 574 575 return (HAL_MPDU_SW_FRAME_GROUP_UNICAST_DATA == grp_id) ? true : false; 576 } 577 578 /** 579 * hal_rx_tid_get_8074v1: get tid based on qos control valid. 580 * 581 * @ buf: pointer to rx pkt TLV. 582 * 583 * Return: tid 584 */ 585 static uint32_t hal_rx_tid_get_8074v1(hal_soc_handle_t hal_soc_hdl, 586 uint8_t *buf) 587 { 588 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 589 struct rx_mpdu_start *mpdu_start = 590 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 591 uint8_t *rx_mpdu_info = (uint8_t *)&mpdu_start->rx_mpdu_info_details; 592 uint8_t qos_control_valid = 593 (_HAL_MS((*_OFFSET_TO_WORD_PTR((rx_mpdu_info), 594 RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_OFFSET)), 595 RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_MASK, 596 RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_LSB)); 597 598 if (qos_control_valid) 599 return hal_rx_mpdu_start_tid_get_8074(buf); 600 601 return HAL_RX_NON_QOS_TID; 602 } 603 604 /** 605 * hal_rx_hw_desc_get_ppduid_get_8074v1(): retrieve ppdu id 606 * @hw_desc_addr: hw addr 607 * 608 * Return: ppdu id 609 */ 610 static uint32_t hal_rx_hw_desc_get_ppduid_get_8074v1(void *hw_desc_addr) 611 { 612 struct rx_mpdu_info *rx_mpdu_info; 613 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr; 614 615 rx_mpdu_info = 616 &rx_desc->mpdu_start_tlv.rx_mpdu_start.rx_mpdu_info_details; 617 618 return HAL_RX_GET(rx_mpdu_info, RX_MPDU_INFO_0, PHY_PPDU_ID); 619 } 620 621 /** 622 * hal_reo_status_get_header_8074v1 - Process reo desc info 623 * @d - Pointer to reo descriptior 624 * @b - tlv type info 625 * @h1 - Pointer to hal_reo_status_header where info to be stored 626 * 627 * Return - none. 628 * 629 */ 630 static void hal_reo_status_get_header_8074v1(uint32_t *d, int b, void *h1) 631 { 632 uint32_t val1 = 0; 633 struct hal_reo_status_header *h = 634 (struct hal_reo_status_header *)h1; 635 636 switch (b) { 637 case HAL_REO_QUEUE_STATS_STATUS_TLV: 638 val1 = d[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_0, 639 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 640 break; 641 case HAL_REO_FLUSH_QUEUE_STATUS_TLV: 642 val1 = d[HAL_OFFSET_DW(REO_FLUSH_QUEUE_STATUS_0, 643 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 644 break; 645 case HAL_REO_FLUSH_CACHE_STATUS_TLV: 646 val1 = d[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_0, 647 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 648 break; 649 case HAL_REO_UNBLK_CACHE_STATUS_TLV: 650 val1 = d[HAL_OFFSET_DW(REO_UNBLOCK_CACHE_STATUS_0, 651 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 652 break; 653 case HAL_REO_TIMOUT_LIST_STATUS_TLV: 654 val1 = d[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_0, 655 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 656 break; 657 case HAL_REO_DESC_THRES_STATUS_TLV: 658 val1 = 659 d[HAL_OFFSET_DW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0, 660 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 661 break; 662 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: 663 val1 = d[HAL_OFFSET_DW(REO_UPDATE_RX_REO_QUEUE_STATUS_0, 664 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 665 break; 666 default: 667 qdf_nofl_err("ERROR: Unknown tlv\n"); 668 break; 669 } 670 h->cmd_num = 671 HAL_GET_FIELD( 672 UNIFORM_REO_STATUS_HEADER_0, REO_STATUS_NUMBER, 673 val1); 674 h->exec_time = 675 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_0, 676 CMD_EXECUTION_TIME, val1); 677 h->status = 678 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_0, 679 REO_CMD_EXECUTION_STATUS, val1); 680 switch (b) { 681 case HAL_REO_QUEUE_STATS_STATUS_TLV: 682 val1 = d[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_1, 683 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 684 break; 685 case HAL_REO_FLUSH_QUEUE_STATUS_TLV: 686 val1 = d[HAL_OFFSET_DW(REO_FLUSH_QUEUE_STATUS_1, 687 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 688 break; 689 case HAL_REO_FLUSH_CACHE_STATUS_TLV: 690 val1 = d[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_1, 691 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 692 break; 693 case HAL_REO_UNBLK_CACHE_STATUS_TLV: 694 val1 = d[HAL_OFFSET_DW(REO_UNBLOCK_CACHE_STATUS_1, 695 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 696 break; 697 case HAL_REO_TIMOUT_LIST_STATUS_TLV: 698 val1 = d[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_1, 699 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 700 break; 701 case HAL_REO_DESC_THRES_STATUS_TLV: 702 val1 = 703 d[HAL_OFFSET_DW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_1, 704 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 705 break; 706 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: 707 val1 = d[HAL_OFFSET_DW(REO_UPDATE_RX_REO_QUEUE_STATUS_1, 708 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 709 break; 710 default: 711 qdf_nofl_err("ERROR: Unknown tlv\n"); 712 break; 713 } 714 h->tstamp = 715 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_1, TIMESTAMP, val1); 716 } 717 718 /** 719 * hal_rx_mpdu_start_mpdu_qos_control_valid_get_8074v1(): 720 * Retrieve qos control valid bit from the tlv. 721 * @buf: pointer to rx pkt TLV. 722 * 723 * Return: qos control value. 724 */ 725 static inline uint32_t 726 hal_rx_mpdu_start_mpdu_qos_control_valid_get_8074v1(uint8_t *buf) 727 { 728 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 729 struct rx_mpdu_start *mpdu_start = 730 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 731 732 return HAL_RX_MPDU_INFO_QOS_CONTROL_VALID_GET( 733 &mpdu_start->rx_mpdu_info_details); 734 } 735 736 /** 737 * hal_rx_msdu_end_sa_sw_peer_id_get_8074v1(): API to get the 738 * sa_sw_peer_id from rx_msdu_end TLV 739 * @buf: pointer to the start of RX PKT TLV headers 740 * 741 * Return: sa_sw_peer_id index 742 */ 743 static inline uint32_t 744 hal_rx_msdu_end_sa_sw_peer_id_get_8074v1(uint8_t *buf) 745 { 746 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 747 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 748 749 return HAL_RX_MSDU_END_SA_SW_PEER_ID_GET(msdu_end); 750 } 751 752 /** 753 * hal_tx_desc_set_mesh_en_8074v1 - Set mesh_enable flag in Tx descriptor 754 * @desc: Handle to Tx Descriptor 755 * @en: For raw WiFi frames, this indicates transmission to a mesh STA, 756 * enabling the interpretation of the 'Mesh Control Present' bit 757 * (bit 8) of QoS Control (otherwise this bit is ignored), 758 * For native WiFi frames, this indicates that a 'Mesh Control' field 759 * is present between the header and the LLC. 760 * 761 * Return: void 762 */ 763 static inline 764 void hal_tx_desc_set_mesh_en_8074v1(void *desc, uint8_t en) 765 { 766 HAL_SET_FLD(desc, TCL_DATA_CMD_4, MESH_ENABLE) |= 767 HAL_TX_SM(TCL_DATA_CMD_4, MESH_ENABLE, en); 768 } 769 770 static 771 void *hal_rx_msdu0_buffer_addr_lsb_8074v1(void *link_desc_va) 772 { 773 return (void *)HAL_RX_MSDU0_BUFFER_ADDR_LSB(link_desc_va); 774 } 775 776 static 777 void *hal_rx_msdu_desc_info_ptr_get_8074v1(void *msdu0) 778 { 779 return (void *)HAL_RX_MSDU_DESC_INFO_PTR_GET(msdu0); 780 } 781 782 static 783 void *hal_ent_mpdu_desc_info_8074v1(void *ent_ring_desc) 784 { 785 return (void *)HAL_ENT_MPDU_DESC_INFO(ent_ring_desc); 786 } 787 788 static 789 void *hal_dst_mpdu_desc_info_8074v1(void *dst_ring_desc) 790 { 791 return (void *)HAL_DST_MPDU_DESC_INFO(dst_ring_desc); 792 } 793 794 static 795 uint8_t hal_rx_get_fc_valid_8074v1(uint8_t *buf) 796 { 797 return HAL_RX_GET_FC_VALID(buf); 798 } 799 800 static uint8_t hal_rx_get_to_ds_flag_8074v1(uint8_t *buf) 801 { 802 return HAL_RX_GET_TO_DS_FLAG(buf); 803 } 804 805 static uint8_t hal_rx_get_mac_addr2_valid_8074v1(uint8_t *buf) 806 { 807 return HAL_RX_GET_MAC_ADDR2_VALID(buf); 808 } 809 810 static uint8_t hal_rx_get_filter_category_8074v1(uint8_t *buf) 811 { 812 return HAL_RX_GET_FILTER_CATEGORY(buf); 813 } 814 815 static uint32_t 816 hal_rx_get_ppdu_id_8074v1(uint8_t *buf) 817 { 818 return HAL_RX_GET_PPDU_ID(buf); 819 } 820 821 /** 822 * hal_reo_config_8074v1(): Set reo config parameters 823 * @soc: hal soc handle 824 * @reg_val: value to be set 825 * @reo_params: reo parameters 826 * 827 * Return: void 828 */ 829 static void 830 hal_reo_config_8074v1(struct hal_soc *soc, 831 uint32_t reg_val, 832 struct hal_reo_params *reo_params) 833 { 834 HAL_REO_R0_CONFIG(soc, reg_val, reo_params); 835 } 836 837 /** 838 * hal_rx_msdu_desc_info_get_ptr_8074v1() - Get msdu desc info ptr 839 * @msdu_details_ptr - Pointer to msdu_details_ptr 840 * 841 * Return - Pointer to rx_msdu_desc_info structure. 842 * 843 */ 844 static void *hal_rx_msdu_desc_info_get_ptr_8074v1(void *msdu_details_ptr) 845 { 846 return HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr); 847 } 848 849 /** 850 * hal_rx_link_desc_msdu0_ptr_8074v1 - Get pointer to rx_msdu details 851 * @link_desc - Pointer to link desc 852 * 853 * Return - Pointer to rx_msdu_details structure 854 * 855 */ 856 static void *hal_rx_link_desc_msdu0_ptr_8074v1(void *link_desc) 857 { 858 return HAL_RX_LINK_DESC_MSDU0_PTR(link_desc); 859 } 860 861 /** 862 * hal_rx_msdu_flow_idx_get_8074v1: API to get flow index 863 * from rx_msdu_end TLV 864 * @buf: pointer to the start of RX PKT TLV headers 865 * 866 * Return: flow index value from MSDU END TLV 867 */ 868 static inline uint32_t hal_rx_msdu_flow_idx_get_8074v1(uint8_t *buf) 869 { 870 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 871 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 872 873 return HAL_RX_MSDU_END_FLOW_IDX_GET(msdu_end); 874 } 875 876 /** 877 * hal_rx_msdu_flow_idx_invalid_8074v1: API to get flow index invalid 878 * from rx_msdu_end TLV 879 * @buf: pointer to the start of RX PKT TLV headers 880 * 881 * Return: flow index invalid value from MSDU END TLV 882 */ 883 static bool hal_rx_msdu_flow_idx_invalid_8074v1(uint8_t *buf) 884 { 885 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 886 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 887 888 return HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(msdu_end); 889 } 890 891 /** 892 * hal_rx_msdu_flow_idx_timeout_8074v1: API to get flow index timeout 893 * from rx_msdu_end TLV 894 * @buf: pointer to the start of RX PKT TLV headers 895 * 896 * Return: flow index timeout value from MSDU END TLV 897 */ 898 static bool hal_rx_msdu_flow_idx_timeout_8074v1(uint8_t *buf) 899 { 900 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 901 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 902 903 return HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(msdu_end); 904 } 905 906 /** 907 * hal_rx_msdu_fse_metadata_get_8074v1: API to get FSE metadata 908 * from rx_msdu_end TLV 909 * @buf: pointer to the start of RX PKT TLV headers 910 * 911 * Return: fse metadata value from MSDU END TLV 912 */ 913 static uint32_t hal_rx_msdu_fse_metadata_get_8074v1(uint8_t *buf) 914 { 915 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 916 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 917 918 return HAL_RX_MSDU_END_FSE_METADATA_GET(msdu_end); 919 } 920 921 /** 922 * hal_rx_msdu_cce_metadata_get_8074v1: API to get CCE metadata 923 * from rx_msdu_end TLV 924 * @buf: pointer to the start of RX PKT TLV headers 925 * 926 * Return: cce_metadata 927 */ 928 static uint16_t 929 hal_rx_msdu_cce_metadata_get_8074v1(uint8_t *buf) 930 { 931 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 932 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 933 934 return HAL_RX_MSDU_END_CCE_METADATA_GET(msdu_end); 935 } 936 937 /** 938 * hal_rx_msdu_get_flow_params_8074v1: API to get flow index, flow index invalid 939 * and flow index timeout from rx_msdu_end TLV 940 * @buf: pointer to the start of RX PKT TLV headers 941 * @flow_invalid: pointer to return value of flow_idx_valid 942 * @flow_timeout: pointer to return value of flow_idx_timeout 943 * @flow_index: pointer to return value of flow_idx 944 * 945 * Return: none 946 */ 947 static inline void 948 hal_rx_msdu_get_flow_params_8074v1(uint8_t *buf, 949 bool *flow_invalid, 950 bool *flow_timeout, 951 uint32_t *flow_index) 952 { 953 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 954 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 955 956 *flow_invalid = HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(msdu_end); 957 *flow_timeout = HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(msdu_end); 958 *flow_index = HAL_RX_MSDU_END_FLOW_IDX_GET(msdu_end); 959 } 960 961 /** 962 * hal_rx_tlv_get_tcp_chksum_8074v1() - API to get tcp checksum 963 * @buf: rx_tlv_hdr 964 * 965 * Return: tcp checksum 966 */ 967 static uint16_t 968 hal_rx_tlv_get_tcp_chksum_8074v1(uint8_t *buf) 969 { 970 return HAL_RX_TLV_GET_TCP_CHKSUM(buf); 971 } 972 973 /** 974 * hal_rx_get_rx_sequence_8074v1(): Function to retrieve rx sequence number 975 * 976 * @nbuf: Network buffer 977 * Returns: rx sequence number 978 */ 979 static 980 uint16_t hal_rx_get_rx_sequence_8074v1(uint8_t *buf) 981 { 982 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 983 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 984 985 return HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info); 986 } 987 988 struct hal_hw_txrx_ops qca8074_hal_hw_txrx_ops = { 989 990 /* init and setup */ 991 hal_srng_dst_hw_init_generic, 992 hal_srng_src_hw_init_generic, 993 hal_get_hw_hptp_generic, 994 hal_reo_setup_generic, 995 hal_setup_link_idle_list_generic, 996 hal_get_window_address_8074, 997 998 /* tx */ 999 hal_tx_desc_set_dscp_tid_table_id_8074, 1000 hal_tx_set_dscp_tid_map_8074, 1001 hal_tx_update_dscp_tid_8074, 1002 hal_tx_desc_set_lmac_id_8074, 1003 hal_tx_desc_set_buf_addr_generic, 1004 hal_tx_desc_set_search_type_generic, 1005 hal_tx_desc_set_search_index_generic, 1006 hal_tx_desc_set_cache_set_num_generic, 1007 hal_tx_comp_get_status_generic, 1008 hal_tx_comp_get_release_reason_generic, 1009 hal_tx_desc_set_mesh_en_8074v1, 1010 /* rx */ 1011 hal_rx_msdu_start_nss_get_8074, 1012 hal_rx_mon_hw_desc_get_mpdu_status_8074, 1013 hal_rx_get_tlv_8074, 1014 hal_rx_proc_phyrx_other_receive_info_tlv_8074, 1015 hal_rx_dump_msdu_start_tlv_8074, 1016 hal_rx_dump_msdu_end_tlv_8074, 1017 hal_get_link_desc_size_8074, 1018 hal_rx_mpdu_start_tid_get_8074, 1019 hal_rx_msdu_start_reception_type_get_8074, 1020 hal_rx_msdu_end_da_idx_get_8074, 1021 hal_rx_msdu_desc_info_get_ptr_8074v1, 1022 hal_rx_link_desc_msdu0_ptr_8074v1, 1023 hal_reo_status_get_header_8074v1, 1024 hal_rx_status_get_tlv_info_generic, 1025 hal_rx_wbm_err_info_get_generic, 1026 hal_rx_dump_mpdu_start_tlv_generic, 1027 1028 hal_tx_set_pcp_tid_map_generic, 1029 hal_tx_update_pcp_tid_generic, 1030 hal_tx_update_tidmap_prty_generic, 1031 hal_rx_get_rx_fragment_number_8074v1, 1032 hal_rx_msdu_end_da_is_mcbc_get_8074v1, 1033 hal_rx_msdu_end_sa_is_valid_get_8074v1, 1034 hal_rx_msdu_end_sa_idx_get_8074v1, 1035 hal_rx_desc_is_first_msdu_8074v1, 1036 hal_rx_msdu_end_l3_hdr_padding_get_8074v1, 1037 hal_rx_encryption_info_valid_8074v1, 1038 hal_rx_print_pn_8074v1, 1039 hal_rx_msdu_end_first_msdu_get_8074v1, 1040 hal_rx_msdu_end_da_is_valid_get_8074v1, 1041 hal_rx_msdu_end_last_msdu_get_8074v1, 1042 hal_rx_get_mpdu_mac_ad4_valid_8074v1, 1043 hal_rx_mpdu_start_sw_peer_id_get_8074v1, 1044 hal_rx_mpdu_get_to_ds_8074v1, 1045 hal_rx_mpdu_get_fr_ds_8074v1, 1046 hal_rx_get_mpdu_frame_control_valid_8074v1, 1047 hal_rx_mpdu_get_addr1_8074v1, 1048 hal_rx_mpdu_get_addr2_8074v1, 1049 hal_rx_mpdu_get_addr3_8074v1, 1050 hal_rx_mpdu_get_addr4_8074v1, 1051 hal_rx_get_mpdu_sequence_control_valid_8074v1, 1052 hal_rx_is_unicast_8074v1, 1053 hal_rx_tid_get_8074v1, 1054 hal_rx_hw_desc_get_ppduid_get_8074v1, 1055 hal_rx_mpdu_start_mpdu_qos_control_valid_get_8074v1, 1056 hal_rx_msdu_end_sa_sw_peer_id_get_8074v1, 1057 hal_rx_msdu0_buffer_addr_lsb_8074v1, 1058 hal_rx_msdu_desc_info_ptr_get_8074v1, 1059 hal_ent_mpdu_desc_info_8074v1, 1060 hal_dst_mpdu_desc_info_8074v1, 1061 hal_rx_get_fc_valid_8074v1, 1062 hal_rx_get_to_ds_flag_8074v1, 1063 hal_rx_get_mac_addr2_valid_8074v1, 1064 hal_rx_get_filter_category_8074v1, 1065 hal_rx_get_ppdu_id_8074v1, 1066 hal_reo_config_8074v1, 1067 hal_rx_msdu_flow_idx_get_8074v1, 1068 hal_rx_msdu_flow_idx_invalid_8074v1, 1069 hal_rx_msdu_flow_idx_timeout_8074v1, 1070 hal_rx_msdu_fse_metadata_get_8074v1, 1071 hal_rx_msdu_cce_metadata_get_8074v1, 1072 hal_rx_msdu_get_flow_params_8074v1, 1073 hal_rx_tlv_get_tcp_chksum_8074v1, 1074 hal_rx_get_rx_sequence_8074v1, 1075 NULL, 1076 NULL, 1077 }; 1078 1079 struct hal_hw_srng_config hw_srng_table_8074[] = { 1080 /* TODO: max_rings can populated by querying HW capabilities */ 1081 { /* REO_DST */ 1082 .start_ring_id = HAL_SRNG_REO2SW1, 1083 .max_rings = 4, 1084 .entry_size = sizeof(struct reo_destination_ring) >> 2, 1085 .lmac_ring = FALSE, 1086 .ring_dir = HAL_SRNG_DST_RING, 1087 .reg_start = { 1088 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR( 1089 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1090 HWIO_REO_R2_REO2SW1_RING_HP_ADDR( 1091 SEQ_WCSS_UMAC_REO_REG_OFFSET) 1092 }, 1093 .reg_size = { 1094 HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(0) - 1095 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(0), 1096 HWIO_REO_R2_REO2SW2_RING_HP_ADDR(0) - 1097 HWIO_REO_R2_REO2SW1_RING_HP_ADDR(0), 1098 }, 1099 .max_size = 1100 HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_BMSK >> 1101 HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_SHFT, 1102 }, 1103 { /* REO_EXCEPTION */ 1104 /* Designating REO2TCL ring as exception ring. This ring is 1105 * similar to other REO2SW rings though it is named as REO2TCL. 1106 * Any of theREO2SW rings can be used as exception ring. 1107 */ 1108 .start_ring_id = HAL_SRNG_REO2TCL, 1109 .max_rings = 1, 1110 .entry_size = sizeof(struct reo_destination_ring) >> 2, 1111 .lmac_ring = FALSE, 1112 .ring_dir = HAL_SRNG_DST_RING, 1113 .reg_start = { 1114 HWIO_REO_R0_REO2TCL_RING_BASE_LSB_ADDR( 1115 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1116 HWIO_REO_R2_REO2TCL_RING_HP_ADDR( 1117 SEQ_WCSS_UMAC_REO_REG_OFFSET) 1118 }, 1119 /* Single ring - provide ring size if multiple rings of this 1120 * type are supported 1121 */ 1122 .reg_size = {}, 1123 .max_size = 1124 HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_BMSK >> 1125 HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_SHFT, 1126 }, 1127 { /* REO_REINJECT */ 1128 .start_ring_id = HAL_SRNG_SW2REO, 1129 .max_rings = 1, 1130 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 1131 .lmac_ring = FALSE, 1132 .ring_dir = HAL_SRNG_SRC_RING, 1133 .reg_start = { 1134 HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR( 1135 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1136 HWIO_REO_R2_SW2REO_RING_HP_ADDR( 1137 SEQ_WCSS_UMAC_REO_REG_OFFSET) 1138 }, 1139 /* Single ring - provide ring size if multiple rings of this 1140 * type are supported 1141 */ 1142 .reg_size = {}, 1143 .max_size = HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_BMSK >> 1144 HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_SHFT, 1145 }, 1146 { /* REO_CMD */ 1147 .start_ring_id = HAL_SRNG_REO_CMD, 1148 .max_rings = 1, 1149 .entry_size = (sizeof(struct tlv_32_hdr) + 1150 sizeof(struct reo_get_queue_stats)) >> 2, 1151 .lmac_ring = FALSE, 1152 .ring_dir = HAL_SRNG_SRC_RING, 1153 .reg_start = { 1154 HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR( 1155 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1156 HWIO_REO_R2_REO_CMD_RING_HP_ADDR( 1157 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1158 }, 1159 /* Single ring - provide ring size if multiple rings of this 1160 * type are supported 1161 */ 1162 .reg_size = {}, 1163 .max_size = HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_BMSK >> 1164 HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_SHFT, 1165 }, 1166 { /* REO_STATUS */ 1167 .start_ring_id = HAL_SRNG_REO_STATUS, 1168 .max_rings = 1, 1169 .entry_size = (sizeof(struct tlv_32_hdr) + 1170 sizeof(struct reo_get_queue_stats_status)) >> 2, 1171 .lmac_ring = FALSE, 1172 .ring_dir = HAL_SRNG_DST_RING, 1173 .reg_start = { 1174 HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR( 1175 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1176 HWIO_REO_R2_REO_STATUS_RING_HP_ADDR( 1177 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1178 }, 1179 /* Single ring - provide ring size if multiple rings of this 1180 * type are supported 1181 */ 1182 .reg_size = {}, 1183 .max_size = 1184 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> 1185 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, 1186 }, 1187 { /* TCL_DATA */ 1188 .start_ring_id = HAL_SRNG_SW2TCL1, 1189 .max_rings = 3, 1190 .entry_size = (sizeof(struct tlv_32_hdr) + 1191 sizeof(struct tcl_data_cmd)) >> 2, 1192 .lmac_ring = FALSE, 1193 .ring_dir = HAL_SRNG_SRC_RING, 1194 .reg_start = { 1195 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR( 1196 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1197 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR( 1198 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1199 }, 1200 .reg_size = { 1201 HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(0) - 1202 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(0), 1203 HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(0) - 1204 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(0), 1205 }, 1206 .max_size = 1207 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK >> 1208 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT, 1209 }, 1210 { /* TCL_CMD */ 1211 .start_ring_id = HAL_SRNG_SW2TCL_CMD, 1212 .max_rings = 1, 1213 .entry_size = (sizeof(struct tlv_32_hdr) + 1214 sizeof(struct tcl_gse_cmd)) >> 2, 1215 .lmac_ring = FALSE, 1216 .ring_dir = HAL_SRNG_SRC_RING, 1217 .reg_start = { 1218 HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_ADDR( 1219 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1220 HWIO_TCL_R2_SW2TCL_CMD_RING_HP_ADDR( 1221 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1222 }, 1223 /* Single ring - provide ring size if multiple rings of this 1224 * type are supported 1225 */ 1226 .reg_size = {}, 1227 .max_size = 1228 HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RING_SIZE_BMSK >> 1229 HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RING_SIZE_SHFT, 1230 }, 1231 { /* TCL_STATUS */ 1232 .start_ring_id = HAL_SRNG_TCL_STATUS, 1233 .max_rings = 1, 1234 .entry_size = (sizeof(struct tlv_32_hdr) + 1235 sizeof(struct tcl_status_ring)) >> 2, 1236 .lmac_ring = FALSE, 1237 .ring_dir = HAL_SRNG_DST_RING, 1238 .reg_start = { 1239 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR( 1240 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1241 HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR( 1242 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1243 }, 1244 /* Single ring - provide ring size if multiple rings of this 1245 * type are supported 1246 */ 1247 .reg_size = {}, 1248 .max_size = 1249 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_BMSK >> 1250 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_SHFT, 1251 }, 1252 { /* CE_SRC */ 1253 .start_ring_id = HAL_SRNG_CE_0_SRC, 1254 .max_rings = 12, 1255 .entry_size = sizeof(struct ce_src_desc) >> 2, 1256 .lmac_ring = FALSE, 1257 .ring_dir = HAL_SRNG_SRC_RING, 1258 .reg_start = { 1259 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR( 1260 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET), 1261 HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR( 1262 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET), 1263 }, 1264 .reg_size = { 1265 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET - 1266 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET, 1267 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET - 1268 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET, 1269 }, 1270 .max_size = 1271 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >> 1272 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT, 1273 }, 1274 { /* CE_DST */ 1275 .start_ring_id = HAL_SRNG_CE_0_DST, 1276 .max_rings = 12, 1277 .entry_size = 8 >> 2, 1278 /*TODO: entry_size above should actually be 1279 * sizeof(struct ce_dst_desc) >> 2, but couldn't find definition 1280 * of struct ce_dst_desc in HW header files 1281 */ 1282 .lmac_ring = FALSE, 1283 .ring_dir = HAL_SRNG_SRC_RING, 1284 .reg_start = { 1285 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR( 1286 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 1287 HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR( 1288 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 1289 }, 1290 .reg_size = { 1291 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 1292 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 1293 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 1294 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 1295 }, 1296 .max_size = 1297 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >> 1298 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT, 1299 }, 1300 { /* CE_DST_STATUS */ 1301 .start_ring_id = HAL_SRNG_CE_0_DST_STATUS, 1302 .max_rings = 12, 1303 .entry_size = sizeof(struct ce_stat_desc) >> 2, 1304 .lmac_ring = FALSE, 1305 .ring_dir = HAL_SRNG_DST_RING, 1306 .reg_start = { 1307 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR( 1308 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 1309 HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR( 1310 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 1311 }, 1312 /* TODO: check destination status ring registers */ 1313 .reg_size = { 1314 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 1315 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 1316 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 1317 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 1318 }, 1319 .max_size = 1320 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> 1321 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, 1322 }, 1323 { /* WBM_IDLE_LINK */ 1324 .start_ring_id = HAL_SRNG_WBM_IDLE_LINK, 1325 .max_rings = 1, 1326 .entry_size = sizeof(struct wbm_link_descriptor_ring) >> 2, 1327 .lmac_ring = FALSE, 1328 .ring_dir = HAL_SRNG_SRC_RING, 1329 .reg_start = { 1330 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1331 HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1332 }, 1333 /* Single ring - provide ring size if multiple rings of this 1334 * type are supported 1335 */ 1336 .reg_size = {}, 1337 .max_size = 1338 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_BMSK >> 1339 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_SHFT, 1340 }, 1341 { /* SW2WBM_RELEASE */ 1342 .start_ring_id = HAL_SRNG_WBM_SW_RELEASE, 1343 .max_rings = 1, 1344 .entry_size = sizeof(struct wbm_release_ring) >> 2, 1345 .lmac_ring = FALSE, 1346 .ring_dir = HAL_SRNG_SRC_RING, 1347 .reg_start = { 1348 HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1349 HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1350 }, 1351 /* Single ring - provide ring size if multiple rings of this 1352 * type are supported 1353 */ 1354 .reg_size = {}, 1355 .max_size = 1356 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> 1357 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, 1358 }, 1359 { /* WBM2SW_RELEASE */ 1360 .start_ring_id = HAL_SRNG_WBM2SW0_RELEASE, 1361 .max_rings = 4, 1362 .entry_size = sizeof(struct wbm_release_ring) >> 2, 1363 .lmac_ring = FALSE, 1364 .ring_dir = HAL_SRNG_DST_RING, 1365 .reg_start = { 1366 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1367 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1368 }, 1369 .reg_size = { 1370 HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) - 1371 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1372 HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) - 1373 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1374 }, 1375 .max_size = 1376 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> 1377 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, 1378 }, 1379 { /* RXDMA_BUF */ 1380 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA0_BUF0, 1381 #ifdef IPA_OFFLOAD 1382 .max_rings = 3, 1383 #else 1384 .max_rings = 2, 1385 #endif 1386 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 1387 .lmac_ring = TRUE, 1388 .ring_dir = HAL_SRNG_SRC_RING, 1389 /* reg_start is not set because LMAC rings are not accessed 1390 * from host 1391 */ 1392 .reg_start = {}, 1393 .reg_size = {}, 1394 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1395 }, 1396 { /* RXDMA_DST */ 1397 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW0, 1398 .max_rings = 1, 1399 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 1400 .lmac_ring = TRUE, 1401 .ring_dir = HAL_SRNG_DST_RING, 1402 /* reg_start is not set because LMAC rings are not accessed 1403 * from host 1404 */ 1405 .reg_start = {}, 1406 .reg_size = {}, 1407 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1408 }, 1409 { /* RXDMA_MONITOR_BUF */ 1410 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA2_BUF, 1411 .max_rings = 1, 1412 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 1413 .lmac_ring = TRUE, 1414 .ring_dir = HAL_SRNG_SRC_RING, 1415 /* reg_start is not set because LMAC rings are not accessed 1416 * from host 1417 */ 1418 .reg_start = {}, 1419 .reg_size = {}, 1420 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1421 }, 1422 { /* RXDMA_MONITOR_STATUS */ 1423 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_STATBUF, 1424 .max_rings = 1, 1425 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 1426 .lmac_ring = TRUE, 1427 .ring_dir = HAL_SRNG_SRC_RING, 1428 /* reg_start is not set because LMAC rings are not accessed 1429 * from host 1430 */ 1431 .reg_start = {}, 1432 .reg_size = {}, 1433 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1434 }, 1435 { /* RXDMA_MONITOR_DST */ 1436 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW1, 1437 .max_rings = 1, 1438 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 1439 .lmac_ring = TRUE, 1440 .ring_dir = HAL_SRNG_DST_RING, 1441 /* reg_start is not set because LMAC rings are not accessed 1442 * from host 1443 */ 1444 .reg_start = {}, 1445 .reg_size = {}, 1446 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1447 }, 1448 { /* RXDMA_MONITOR_DESC */ 1449 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_DESC, 1450 .max_rings = 1, 1451 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 1452 .lmac_ring = TRUE, 1453 .ring_dir = HAL_SRNG_SRC_RING, 1454 /* reg_start is not set because LMAC rings are not accessed 1455 * from host 1456 */ 1457 .reg_start = {}, 1458 .reg_size = {}, 1459 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1460 }, 1461 { /* DIR_BUF_RX_DMA_SRC */ 1462 .start_ring_id = HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING, 1463 .max_rings = 1, 1464 .entry_size = 2, 1465 .lmac_ring = TRUE, 1466 .ring_dir = HAL_SRNG_SRC_RING, 1467 /* reg_start is not set because LMAC rings are not accessed 1468 * from host 1469 */ 1470 .reg_start = {}, 1471 .reg_size = {}, 1472 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1473 }, 1474 #ifdef WLAN_FEATURE_CIF_CFR 1475 { /* WIFI_POS_SRC */ 1476 .start_ring_id = HAL_SRNG_WIFI_POS_SRC_DMA_RING, 1477 .max_rings = 1, 1478 .entry_size = sizeof(wmi_oem_dma_buf_release_entry) >> 2, 1479 .lmac_ring = TRUE, 1480 .ring_dir = HAL_SRNG_SRC_RING, 1481 /* reg_start is not set because LMAC rings are not accessed 1482 * from host 1483 */ 1484 .reg_start = {}, 1485 .reg_size = {}, 1486 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1487 }, 1488 #endif 1489 }; 1490 1491 int32_t hal_hw_reg_offset_qca8074[] = { 1492 /* dst */ 1493 REG_OFFSET(DST, HP), 1494 REG_OFFSET(DST, TP), 1495 REG_OFFSET(DST, ID), 1496 REG_OFFSET(DST, MISC), 1497 REG_OFFSET(DST, HP_ADDR_LSB), 1498 REG_OFFSET(DST, HP_ADDR_MSB), 1499 REG_OFFSET(DST, MSI1_BASE_LSB), 1500 REG_OFFSET(DST, MSI1_BASE_MSB), 1501 REG_OFFSET(DST, MSI1_DATA), 1502 REG_OFFSET(DST, BASE_LSB), 1503 REG_OFFSET(DST, BASE_MSB), 1504 REG_OFFSET(DST, PRODUCER_INT_SETUP), 1505 /* src */ 1506 REG_OFFSET(SRC, HP), 1507 REG_OFFSET(SRC, TP), 1508 REG_OFFSET(SRC, ID), 1509 REG_OFFSET(SRC, MISC), 1510 REG_OFFSET(SRC, TP_ADDR_LSB), 1511 REG_OFFSET(SRC, TP_ADDR_MSB), 1512 REG_OFFSET(SRC, MSI1_BASE_LSB), 1513 REG_OFFSET(SRC, MSI1_BASE_MSB), 1514 REG_OFFSET(SRC, MSI1_DATA), 1515 REG_OFFSET(SRC, BASE_LSB), 1516 REG_OFFSET(SRC, BASE_MSB), 1517 REG_OFFSET(SRC, CONSUMER_INT_SETUP_IX0), 1518 REG_OFFSET(SRC, CONSUMER_INT_SETUP_IX1), 1519 }; 1520 1521 /** 1522 * hal_qca8074_attach() - Attach 8074 target specific hal_soc ops, 1523 * offset and srng table 1524 */ 1525 void hal_qca8074_attach(struct hal_soc *hal_soc) 1526 { 1527 hal_soc->hw_srng_table = hw_srng_table_8074; 1528 hal_soc->hal_hw_reg_offset = hal_hw_reg_offset_qca8074; 1529 hal_soc->ops = &qca8074_hal_hw_txrx_ops; 1530 } 1531