1 /* 2 * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved. 3 * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 #include "hal_li_hw_headers.h" 20 #include "hal_internal.h" 21 #include "hal_api.h" 22 #include "target_type.h" 23 #include "wcss_version.h" 24 #include "qdf_module.h" 25 #include "hal_flow.h" 26 #include "rx_flow_search_entry.h" 27 #include "hal_rx_flow_info.h" 28 29 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_OFFSET \ 30 RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_OFFSET 31 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_MASK \ 32 RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_MASK 33 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_LSB \ 34 RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_LSB 35 #define UNIFIED_PHYRX_HT_SIG_0_HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS_OFFSET \ 36 PHYRX_HT_SIG_0_HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS_OFFSET 37 #define UNIFIED_PHYRX_L_SIG_B_0_L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS_OFFSET \ 38 PHYRX_L_SIG_B_0_L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS_OFFSET 39 #define UNIFIED_PHYRX_L_SIG_A_0_L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS_OFFSET \ 40 PHYRX_L_SIG_A_0_L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS_OFFSET 41 #define UNIFIED_PHYRX_VHT_SIG_A_0_VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS_OFFSET \ 42 PHYRX_VHT_SIG_A_0_VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS_OFFSET 43 #define UNIFIED_PHYRX_HE_SIG_A_SU_0_HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS_OFFSET \ 44 PHYRX_HE_SIG_A_SU_0_HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS_OFFSET 45 #define UNIFIED_PHYRX_HE_SIG_A_MU_DL_0_HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_OFFSET \ 46 PHYRX_HE_SIG_A_MU_DL_0_HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_OFFSET 47 #define UNIFIED_PHYRX_HE_SIG_B1_MU_0_HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_OFFSET \ 48 PHYRX_HE_SIG_B1_MU_0_HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_OFFSET 49 #define UNIFIED_PHYRX_HE_SIG_B2_MU_0_HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_OFFSET \ 50 PHYRX_HE_SIG_B2_MU_0_HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_OFFSET 51 #define UNIFIED_PHYRX_HE_SIG_B2_OFDMA_0_HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_OFFSET \ 52 PHYRX_HE_SIG_B2_OFDMA_0_HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_OFFSET 53 #define UNIFIED_PHYRX_RSSI_LEGACY_3_RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS_OFFSET \ 54 PHYRX_RSSI_LEGACY_3_RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS_OFFSET 55 #define UNIFIED_PHYRX_RSSI_LEGACY_19_RECEIVE_RSSI_INFO_PREAMBLE_RSSI_INFO_DETAILS_OFFSET \ 56 PHYRX_RSSI_LEGACY_19_RECEIVE_RSSI_INFO_PREAMBLE_RSSI_INFO_DETAILS_OFFSET 57 #define UNIFIED_RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET \ 58 RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET 59 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 60 RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET 61 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ 62 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET 63 #define UNIFIED_RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 64 RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET 65 #define UNIFIED_REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 66 REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET 67 #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC \ 68 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER 69 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSE \ 70 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET 71 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 72 RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET 73 #define UNIFIED_TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 74 TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET 75 #define UNIFIED_TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 76 TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET 77 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET \ 78 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET 79 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB \ 80 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB 81 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK \ 82 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK 83 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB \ 84 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB 85 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK \ 86 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK 87 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB \ 88 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB 89 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK \ 90 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK 91 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB \ 92 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB 93 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK \ 94 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK 95 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB \ 96 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB 97 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK \ 98 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK 99 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_MASK \ 100 WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_MASK 101 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_OFFSET \ 102 WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_OFFSET 103 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_LSB \ 104 WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_LSB 105 106 #include "hal_8074v1_tx.h" 107 #include "hal_8074v1_rx.h" 108 #include <hal_generic_api.h> 109 #include "hal_li_rx.h" 110 #include "hal_li_tx.h" 111 #include "hal_li_api.h" 112 #include "hal_li_generic_api.h" 113 114 /** 115 * hal_get_window_address_8074(): Function to get hp/tp address 116 * @hal_soc: Pointer to hal_soc 117 * @addr: address offset of register 118 * 119 * Return: modified address offset of register 120 */ 121 static inline qdf_iomem_t hal_get_window_address_8074(struct hal_soc *hal_soc, 122 qdf_iomem_t addr) 123 { 124 return addr; 125 } 126 127 /** 128 * hal_rx_get_rx_fragment_number_8074v1(): Function to retrieve 129 * rx fragment number 130 * 131 * @nbuf: Network buffer 132 * Returns: rx fragment number 133 */ 134 static 135 uint8_t hal_rx_get_rx_fragment_number_8074v1(uint8_t *buf) 136 { 137 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 138 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 139 140 /* Return first 4 bits as fragment number */ 141 return (HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info) & 142 DOT11_SEQ_FRAG_MASK); 143 } 144 145 /** 146 * hal_rx_msdu_end_da_is_mcbc_get_8074v1(): API to check if 147 * pkt is MCBC from rx_msdu_end TLV 148 * 149 * @ buf: pointer to the start of RX PKT TLV headers 150 * Return: da_is_mcbc 151 */ 152 static uint8_t 153 hal_rx_msdu_end_da_is_mcbc_get_8074v1(uint8_t *buf) 154 { 155 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 156 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 157 158 return HAL_RX_MSDU_END_DA_IS_MCBC_GET(msdu_end); 159 } 160 161 /** 162 * hal_rx_msdu_end_sa_is_valid_get_8074v1(): API to get_8074v1 the 163 * sa_is_valid bit from rx_msdu_end TLV 164 * 165 * @ buf: pointer to the start of RX PKT TLV headers 166 * Return: sa_is_valid bit 167 */ 168 static uint8_t 169 hal_rx_msdu_end_sa_is_valid_get_8074v1(uint8_t *buf) 170 { 171 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 172 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 173 uint8_t sa_is_valid; 174 175 sa_is_valid = HAL_RX_MSDU_END_SA_IS_VALID_GET(msdu_end); 176 177 return sa_is_valid; 178 } 179 180 /** 181 * hal_rx_msdu_end_sa_idx_get_8074v1(): API to get_8074v1 the 182 * sa_idx from rx_msdu_end TLV 183 * 184 * @ buf: pointer to the start of RX PKT TLV headers 185 * Return: sa_idx (SA AST index) 186 */ 187 static uint16_t hal_rx_msdu_end_sa_idx_get_8074v1(uint8_t *buf) 188 { 189 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 190 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 191 uint16_t sa_idx; 192 193 sa_idx = HAL_RX_MSDU_END_SA_IDX_GET(msdu_end); 194 195 return sa_idx; 196 } 197 198 /** 199 * hal_rx_desc_is_first_msdu_8074v1() - Check if first msdu 200 * 201 * @hal_soc_hdl: hal_soc handle 202 * @hw_desc_addr: hardware descriptor address 203 * 204 * Return: 0 - success/ non-zero failure 205 */ 206 static uint32_t hal_rx_desc_is_first_msdu_8074v1(void *hw_desc_addr) 207 { 208 struct rx_pkt_tlvs *rx_tlvs = (struct rx_pkt_tlvs *)hw_desc_addr; 209 struct rx_msdu_end *msdu_end = &rx_tlvs->msdu_end_tlv.rx_msdu_end; 210 211 return HAL_RX_GET(msdu_end, RX_MSDU_END_5, FIRST_MSDU); 212 } 213 214 /** 215 * hal_rx_msdu_end_l3_hdr_padding_get_8074v1(): API to get_8074v1 the 216 * l3_header padding from rx_msdu_end TLV 217 * 218 * @ buf: pointer to the start of RX PKT TLV headers 219 * Return: number of l3 header padding bytes 220 */ 221 static uint32_t hal_rx_msdu_end_l3_hdr_padding_get_8074v1(uint8_t *buf) 222 { 223 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 224 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 225 uint32_t l3_header_padding; 226 227 l3_header_padding = HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(msdu_end); 228 229 return l3_header_padding; 230 } 231 232 /* 233 * @ hal_rx_encryption_info_valid_8074v1: Returns encryption type. 234 * 235 * @ buf: rx_tlv_hdr of the received packet 236 * @ Return: encryption type 237 */ 238 static uint32_t hal_rx_encryption_info_valid_8074v1(uint8_t *buf) 239 { 240 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 241 struct rx_mpdu_start *mpdu_start = 242 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 243 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 244 uint32_t encryption_info = HAL_RX_MPDU_ENCRYPTION_INFO_VALID(mpdu_info); 245 246 return encryption_info; 247 } 248 249 /* 250 * @ hal_rx_print_pn_8074v1: Prints the PN of rx packet. 251 * 252 * @ buf: rx_tlv_hdr of the received packet 253 * @ Return: void 254 */ 255 static void hal_rx_print_pn_8074v1(uint8_t *buf) 256 { 257 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 258 struct rx_mpdu_start *mpdu_start = 259 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 260 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 261 262 uint32_t pn_31_0 = HAL_RX_MPDU_PN_31_0_GET(mpdu_info); 263 uint32_t pn_63_32 = HAL_RX_MPDU_PN_63_32_GET(mpdu_info); 264 uint32_t pn_95_64 = HAL_RX_MPDU_PN_95_64_GET(mpdu_info); 265 uint32_t pn_127_96 = HAL_RX_MPDU_PN_127_96_GET(mpdu_info); 266 267 hal_debug("PN number pn_127_96 0x%x pn_95_64 0x%x pn_63_32 0x%x pn_31_0 0x%x ", 268 pn_127_96, pn_95_64, pn_63_32, pn_31_0); 269 } 270 271 /** 272 * hal_rx_msdu_end_first_msdu_get_8074v1: API to get first msdu status 273 * from rx_msdu_end TLV 274 * 275 * @ buf: pointer to the start of RX PKT TLV headers 276 * Return: first_msdu 277 */ 278 static uint8_t 279 hal_rx_msdu_end_first_msdu_get_8074v1(uint8_t *buf) 280 { 281 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 282 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 283 uint8_t first_msdu; 284 285 first_msdu = HAL_RX_MSDU_END_FIRST_MSDU_GET(msdu_end); 286 287 return first_msdu; 288 } 289 290 /** 291 * hal_rx_msdu_end_da_is_valid_get_8074v1: API to check if da is valid 292 * from rx_msdu_end TLV 293 * 294 * @ buf: pointer to the start of RX PKT TLV headers 295 * Return: da_is_valid 296 */ 297 static uint8_t hal_rx_msdu_end_da_is_valid_get_8074v1(uint8_t *buf) 298 { 299 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 300 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 301 uint8_t da_is_valid; 302 303 da_is_valid = HAL_RX_MSDU_END_DA_IS_VALID_GET(msdu_end); 304 305 return da_is_valid; 306 } 307 308 /** 309 * hal_rx_msdu_end_last_msdu_get_8074v1: API to get last msdu status 310 * from rx_msdu_end TLV 311 * 312 * @ buf: pointer to the start of RX PKT TLV headers 313 * Return: last_msdu 314 */ 315 static uint8_t hal_rx_msdu_end_last_msdu_get_8074v1(uint8_t *buf) 316 { 317 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 318 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 319 uint8_t last_msdu; 320 321 last_msdu = HAL_RX_MSDU_END_LAST_MSDU_GET(msdu_end); 322 323 return last_msdu; 324 } 325 326 /* 327 * hal_rx_get_mpdu_mac_ad4_valid_8074v1(): Retrieves if mpdu 4th addr is valid 328 * 329 * @nbuf: Network buffer 330 * Returns: value of mpdu 4th address valid field 331 */ 332 static bool hal_rx_get_mpdu_mac_ad4_valid_8074v1(uint8_t *buf) 333 { 334 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 335 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 336 bool ad4_valid = 0; 337 338 ad4_valid = HAL_RX_MPDU_GET_MAC_AD4_VALID(rx_mpdu_info); 339 340 return ad4_valid; 341 } 342 343 /** 344 * hal_rx_mpdu_start_sw_peer_id_get_8074v1: Retrieve sw peer_id 345 * @buf: network buffer 346 * 347 * Return: sw peer_id 348 */ 349 static uint32_t hal_rx_mpdu_start_sw_peer_id_get_8074v1(uint8_t *buf) 350 { 351 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 352 struct rx_mpdu_start *mpdu_start = 353 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 354 355 return HAL_RX_MPDU_INFO_SW_PEER_ID_GET( 356 &mpdu_start->rx_mpdu_info_details); 357 } 358 359 /* 360 * hal_rx_mpdu_get_to_ds_8074v1(): API to get the tods info 361 * from rx_mpdu_start 362 * 363 * @buf: pointer to the start of RX PKT TLV header 364 * Return: uint32_t(to_ds) 365 */ 366 367 static uint32_t hal_rx_mpdu_get_to_ds_8074v1(uint8_t *buf) 368 { 369 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 370 struct rx_mpdu_start *mpdu_start = 371 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 372 373 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 374 375 return HAL_RX_MPDU_GET_TODS(mpdu_info); 376 } 377 378 /* 379 * hal_rx_mpdu_get_fr_ds_8074v1(): API to get the from ds info 380 * from rx_mpdu_start 381 * 382 * @buf: pointer to the start of RX PKT TLV header 383 * Return: uint32_t(fr_ds) 384 */ 385 static uint32_t hal_rx_mpdu_get_fr_ds_8074v1(uint8_t *buf) 386 { 387 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 388 struct rx_mpdu_start *mpdu_start = 389 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 390 391 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 392 393 return HAL_RX_MPDU_GET_FROMDS(mpdu_info); 394 } 395 396 /* 397 * hal_rx_get_mpdu_frame_control_valid_8074v1(): Retrieves mpdu 398 * frame control valid 399 * 400 * @nbuf: Network buffer 401 * Returns: value of frame control valid field 402 */ 403 static uint8_t hal_rx_get_mpdu_frame_control_valid_8074v1(uint8_t *buf) 404 { 405 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 406 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 407 408 return HAL_RX_MPDU_GET_FRAME_CONTROL_VALID(rx_mpdu_info); 409 } 410 411 /* 412 * hal_rx_mpdu_get_addr1_8074v1(): API to check get address1 of the mpdu 413 * 414 * @buf: pointer to the start of RX PKT TLV headera 415 * @mac_addr: pointer to mac address 416 * Return: success/failure 417 */ 418 static QDF_STATUS hal_rx_mpdu_get_addr1_8074v1(uint8_t *buf, 419 uint8_t *mac_addr) 420 { 421 struct __attribute__((__packed__)) hal_addr1 { 422 uint32_t ad1_31_0; 423 uint16_t ad1_47_32; 424 }; 425 426 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 427 struct rx_mpdu_start *mpdu_start = 428 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 429 430 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 431 struct hal_addr1 *addr = (struct hal_addr1 *)mac_addr; 432 uint32_t mac_addr_ad1_valid; 433 434 mac_addr_ad1_valid = HAL_RX_MPDU_MAC_ADDR_AD1_VALID_GET(mpdu_info); 435 436 if (mac_addr_ad1_valid) { 437 addr->ad1_31_0 = HAL_RX_MPDU_AD1_31_0_GET(mpdu_info); 438 addr->ad1_47_32 = HAL_RX_MPDU_AD1_47_32_GET(mpdu_info); 439 return QDF_STATUS_SUCCESS; 440 } 441 442 return QDF_STATUS_E_FAILURE; 443 } 444 445 /* 446 * hal_rx_mpdu_get_addr2_8074v1(): API to check get address2 of the mpdu 447 * in the packet 448 * 449 * @buf: pointer to the start of RX PKT TLV header 450 * @mac_addr: pointer to mac address 451 * Return: success/failure 452 */ 453 static QDF_STATUS hal_rx_mpdu_get_addr2_8074v1(uint8_t *buf, uint8_t *mac_addr) 454 { 455 struct __attribute__((__packed__)) hal_addr2 { 456 uint16_t ad2_15_0; 457 uint32_t ad2_47_16; 458 }; 459 460 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 461 struct rx_mpdu_start *mpdu_start = 462 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 463 464 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 465 struct hal_addr2 *addr = (struct hal_addr2 *)mac_addr; 466 uint32_t mac_addr_ad2_valid; 467 468 mac_addr_ad2_valid = HAL_RX_MPDU_MAC_ADDR_AD2_VALID_GET(mpdu_info); 469 470 if (mac_addr_ad2_valid) { 471 addr->ad2_15_0 = HAL_RX_MPDU_AD2_15_0_GET(mpdu_info); 472 addr->ad2_47_16 = HAL_RX_MPDU_AD2_47_16_GET(mpdu_info); 473 return QDF_STATUS_SUCCESS; 474 } 475 476 return QDF_STATUS_E_FAILURE; 477 } 478 479 /* 480 * hal_rx_mpdu_get_addr3_8074v1(): API to get address3 of the mpdu 481 * in the packet 482 * 483 * @buf: pointer to the start of RX PKT TLV header 484 * @mac_addr: pointer to mac address 485 * Return: success/failure 486 */ 487 static QDF_STATUS hal_rx_mpdu_get_addr3_8074v1(uint8_t *buf, uint8_t *mac_addr) 488 { 489 struct __attribute__((__packed__)) hal_addr3 { 490 uint32_t ad3_31_0; 491 uint16_t ad3_47_32; 492 }; 493 494 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 495 struct rx_mpdu_start *mpdu_start = 496 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 497 498 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 499 struct hal_addr3 *addr = (struct hal_addr3 *)mac_addr; 500 uint32_t mac_addr_ad3_valid; 501 502 mac_addr_ad3_valid = HAL_RX_MPDU_MAC_ADDR_AD3_VALID_GET(mpdu_info); 503 504 if (mac_addr_ad3_valid) { 505 addr->ad3_31_0 = HAL_RX_MPDU_AD3_31_0_GET(mpdu_info); 506 addr->ad3_47_32 = HAL_RX_MPDU_AD3_47_32_GET(mpdu_info); 507 return QDF_STATUS_SUCCESS; 508 } 509 510 return QDF_STATUS_E_FAILURE; 511 } 512 513 /* 514 * hal_rx_mpdu_get_addr4_8074v1(): API to get address4 of the mpdu 515 * in the packet 516 * 517 * @buf: pointer to the start of RX PKT TLV header 518 * @mac_addr: pointer to mac address 519 * Return: success/failure 520 */ 521 static QDF_STATUS hal_rx_mpdu_get_addr4_8074v1(uint8_t *buf, uint8_t *mac_addr) 522 { 523 struct __attribute__((__packed__)) hal_addr4 { 524 uint32_t ad4_31_0; 525 uint16_t ad4_47_32; 526 }; 527 528 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 529 struct rx_mpdu_start *mpdu_start = 530 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 531 532 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 533 struct hal_addr4 *addr = (struct hal_addr4 *)mac_addr; 534 uint32_t mac_addr_ad4_valid; 535 536 mac_addr_ad4_valid = HAL_RX_MPDU_MAC_ADDR_AD4_VALID_GET(mpdu_info); 537 538 if (mac_addr_ad4_valid) { 539 addr->ad4_31_0 = HAL_RX_MPDU_AD4_31_0_GET(mpdu_info); 540 addr->ad4_47_32 = HAL_RX_MPDU_AD4_47_32_GET(mpdu_info); 541 return QDF_STATUS_SUCCESS; 542 } 543 544 return QDF_STATUS_E_FAILURE; 545 } 546 547 /* 548 * hal_rx_get_mpdu_sequence_control_valid_8074v1(): Get mpdu 549 * sequence control valid 550 * 551 * @nbuf: Network buffer 552 * Returns: value of sequence control valid field 553 */ 554 static uint8_t hal_rx_get_mpdu_sequence_control_valid_8074v1(uint8_t *buf) 555 { 556 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 557 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 558 559 return HAL_RX_MPDU_GET_SEQUENCE_CONTROL_VALID(rx_mpdu_info); 560 } 561 562 /** 563 * hal_rx_is_unicast_8074v1: check packet is unicast frame or not. 564 * 565 * @ buf: pointer to rx pkt TLV. 566 * 567 * Return: true on unicast. 568 */ 569 static bool hal_rx_is_unicast_8074v1(uint8_t *buf) 570 { 571 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 572 struct rx_mpdu_start *mpdu_start = 573 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 574 uint32_t grp_id; 575 uint8_t *rx_mpdu_info = (uint8_t *)&mpdu_start->rx_mpdu_info_details; 576 577 grp_id = (_HAL_MS((*_OFFSET_TO_WORD_PTR((rx_mpdu_info), 578 RX_MPDU_INFO_0_SW_FRAME_GROUP_ID_OFFSET)), 579 RX_MPDU_INFO_0_SW_FRAME_GROUP_ID_MASK, 580 RX_MPDU_INFO_0_SW_FRAME_GROUP_ID_LSB)); 581 582 return (HAL_MPDU_SW_FRAME_GROUP_UNICAST_DATA == grp_id) ? true : false; 583 } 584 585 /** 586 * hal_rx_tid_get_8074v1: get tid based on qos control valid. 587 * 588 * @ buf: pointer to rx pkt TLV. 589 * 590 * Return: tid 591 */ 592 static uint32_t hal_rx_tid_get_8074v1(hal_soc_handle_t hal_soc_hdl, 593 uint8_t *buf) 594 { 595 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 596 struct rx_mpdu_start *mpdu_start = 597 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 598 uint8_t *rx_mpdu_info = (uint8_t *)&mpdu_start->rx_mpdu_info_details; 599 uint8_t qos_control_valid = 600 (_HAL_MS((*_OFFSET_TO_WORD_PTR((rx_mpdu_info), 601 RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_OFFSET)), 602 RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_MASK, 603 RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_LSB)); 604 605 if (qos_control_valid) 606 return hal_rx_mpdu_start_tid_get_8074(buf); 607 608 return HAL_RX_NON_QOS_TID; 609 } 610 611 /** 612 * hal_rx_hw_desc_get_ppduid_get_8074v1(): retrieve ppdu id 613 * @rx_tlv_hdr: Rx tlv header 614 * @rxdma_dst_ring_desc: Rx HW descriptor 615 * 616 * Return: ppdu id 617 */ 618 static uint32_t hal_rx_hw_desc_get_ppduid_get_8074v1(void *rx_tlv_hdr, 619 void *rxdma_dst_ring_desc) 620 { 621 struct rx_mpdu_info *rx_mpdu_info; 622 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)rx_tlv_hdr; 623 624 rx_mpdu_info = 625 &rx_desc->mpdu_start_tlv.rx_mpdu_start.rx_mpdu_info_details; 626 627 return HAL_RX_GET(rx_mpdu_info, RX_MPDU_INFO_0, PHY_PPDU_ID); 628 } 629 630 /** 631 * hal_reo_status_get_header_8074v1 - Process reo desc info 632 * @ring_desc: REO status ring descriptor 633 * @b - tlv type info 634 * @h1 - Pointer to hal_reo_status_header where info to be stored 635 * 636 * Return - none. 637 * 638 */ 639 static void hal_reo_status_get_header_8074v1(hal_ring_desc_t ring_desc, int b, 640 void *h1) 641 { 642 uint32_t *d = (uint32_t *)ring_desc; 643 uint32_t val1 = 0; 644 struct hal_reo_status_header *h = 645 (struct hal_reo_status_header *)h1; 646 647 /* Offsets of descriptor fields defined in HW headers start 648 * from the field after TLV header 649 */ 650 d += HAL_GET_NUM_DWORDS(sizeof(struct tlv_32_hdr)); 651 652 switch (b) { 653 case HAL_REO_QUEUE_STATS_STATUS_TLV: 654 val1 = d[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_0, 655 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 656 break; 657 case HAL_REO_FLUSH_QUEUE_STATUS_TLV: 658 val1 = d[HAL_OFFSET_DW(REO_FLUSH_QUEUE_STATUS_0, 659 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 660 break; 661 case HAL_REO_FLUSH_CACHE_STATUS_TLV: 662 val1 = d[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_0, 663 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 664 break; 665 case HAL_REO_UNBLK_CACHE_STATUS_TLV: 666 val1 = d[HAL_OFFSET_DW(REO_UNBLOCK_CACHE_STATUS_0, 667 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 668 break; 669 case HAL_REO_TIMOUT_LIST_STATUS_TLV: 670 val1 = d[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_0, 671 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 672 break; 673 case HAL_REO_DESC_THRES_STATUS_TLV: 674 val1 = 675 d[HAL_OFFSET_DW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0, 676 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 677 break; 678 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: 679 val1 = d[HAL_OFFSET_DW(REO_UPDATE_RX_REO_QUEUE_STATUS_0, 680 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 681 break; 682 default: 683 qdf_nofl_err("ERROR: Unknown tlv\n"); 684 break; 685 } 686 h->cmd_num = 687 HAL_GET_FIELD( 688 UNIFORM_REO_STATUS_HEADER_0, REO_STATUS_NUMBER, 689 val1); 690 h->exec_time = 691 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_0, 692 CMD_EXECUTION_TIME, val1); 693 h->status = 694 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_0, 695 REO_CMD_EXECUTION_STATUS, val1); 696 switch (b) { 697 case HAL_REO_QUEUE_STATS_STATUS_TLV: 698 val1 = d[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_1, 699 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 700 break; 701 case HAL_REO_FLUSH_QUEUE_STATUS_TLV: 702 val1 = d[HAL_OFFSET_DW(REO_FLUSH_QUEUE_STATUS_1, 703 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 704 break; 705 case HAL_REO_FLUSH_CACHE_STATUS_TLV: 706 val1 = d[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_1, 707 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 708 break; 709 case HAL_REO_UNBLK_CACHE_STATUS_TLV: 710 val1 = d[HAL_OFFSET_DW(REO_UNBLOCK_CACHE_STATUS_1, 711 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 712 break; 713 case HAL_REO_TIMOUT_LIST_STATUS_TLV: 714 val1 = d[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_1, 715 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 716 break; 717 case HAL_REO_DESC_THRES_STATUS_TLV: 718 val1 = 719 d[HAL_OFFSET_DW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_1, 720 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 721 break; 722 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: 723 val1 = d[HAL_OFFSET_DW(REO_UPDATE_RX_REO_QUEUE_STATUS_1, 724 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 725 break; 726 default: 727 qdf_nofl_err("ERROR: Unknown tlv\n"); 728 break; 729 } 730 h->tstamp = 731 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_1, TIMESTAMP, val1); 732 } 733 734 /** 735 * hal_rx_mpdu_start_mpdu_qos_control_valid_get_8074v1(): 736 * Retrieve qos control valid bit from the tlv. 737 * @buf: pointer to rx pkt TLV. 738 * 739 * Return: qos control value. 740 */ 741 static inline uint32_t 742 hal_rx_mpdu_start_mpdu_qos_control_valid_get_8074v1(uint8_t *buf) 743 { 744 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 745 struct rx_mpdu_start *mpdu_start = 746 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 747 748 return HAL_RX_MPDU_INFO_QOS_CONTROL_VALID_GET( 749 &mpdu_start->rx_mpdu_info_details); 750 } 751 752 /** 753 * hal_rx_msdu_end_sa_sw_peer_id_get_8074v1(): API to get the 754 * sa_sw_peer_id from rx_msdu_end TLV 755 * @buf: pointer to the start of RX PKT TLV headers 756 * 757 * Return: sa_sw_peer_id index 758 */ 759 static inline uint32_t 760 hal_rx_msdu_end_sa_sw_peer_id_get_8074v1(uint8_t *buf) 761 { 762 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 763 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 764 765 return HAL_RX_MSDU_END_SA_SW_PEER_ID_GET(msdu_end); 766 } 767 768 /** 769 * hal_tx_desc_set_mesh_en_8074v1 - Set mesh_enable flag in Tx descriptor 770 * @desc: Handle to Tx Descriptor 771 * @en: For raw WiFi frames, this indicates transmission to a mesh STA, 772 * enabling the interpretation of the 'Mesh Control Present' bit 773 * (bit 8) of QoS Control (otherwise this bit is ignored), 774 * For native WiFi frames, this indicates that a 'Mesh Control' field 775 * is present between the header and the LLC. 776 * 777 * Return: void 778 */ 779 static inline 780 void hal_tx_desc_set_mesh_en_8074v1(void *desc, uint8_t en) 781 { 782 HAL_SET_FLD(desc, TCL_DATA_CMD_4, MESH_ENABLE) |= 783 HAL_TX_SM(TCL_DATA_CMD_4, MESH_ENABLE, en); 784 } 785 786 static 787 void *hal_rx_msdu0_buffer_addr_lsb_8074v1(void *link_desc_va) 788 { 789 return (void *)HAL_RX_MSDU0_BUFFER_ADDR_LSB(link_desc_va); 790 } 791 792 static 793 void *hal_rx_msdu_desc_info_ptr_get_8074v1(void *msdu0) 794 { 795 return (void *)HAL_RX_MSDU_DESC_INFO_PTR_GET(msdu0); 796 } 797 798 static 799 void *hal_ent_mpdu_desc_info_8074v1(void *ent_ring_desc) 800 { 801 return (void *)HAL_ENT_MPDU_DESC_INFO(ent_ring_desc); 802 } 803 804 static 805 void *hal_dst_mpdu_desc_info_8074v1(void *dst_ring_desc) 806 { 807 return (void *)HAL_DST_MPDU_DESC_INFO(dst_ring_desc); 808 } 809 810 static 811 uint8_t hal_rx_get_fc_valid_8074v1(uint8_t *buf) 812 { 813 return HAL_RX_GET_FC_VALID(buf); 814 } 815 816 static uint8_t hal_rx_get_to_ds_flag_8074v1(uint8_t *buf) 817 { 818 return HAL_RX_GET_TO_DS_FLAG(buf); 819 } 820 821 static uint8_t hal_rx_get_mac_addr2_valid_8074v1(uint8_t *buf) 822 { 823 return HAL_RX_GET_MAC_ADDR2_VALID(buf); 824 } 825 826 static uint8_t hal_rx_get_filter_category_8074v1(uint8_t *buf) 827 { 828 return HAL_RX_GET_FILTER_CATEGORY(buf); 829 } 830 831 static uint32_t 832 hal_rx_get_ppdu_id_8074v1(uint8_t *buf) 833 { 834 struct rx_mpdu_info *rx_mpdu_info; 835 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)buf; 836 837 rx_mpdu_info = 838 &rx_desc->mpdu_start_tlv.rx_mpdu_start.rx_mpdu_info_details; 839 840 return HAL_RX_GET_PPDU_ID(rx_mpdu_info); 841 } 842 843 /** 844 * hal_reo_config_8074v1(): Set reo config parameters 845 * @soc: hal soc handle 846 * @reg_val: value to be set 847 * @reo_params: reo parameters 848 * 849 * Return: void 850 */ 851 static void 852 hal_reo_config_8074v1(struct hal_soc *soc, 853 uint32_t reg_val, 854 struct hal_reo_params *reo_params) 855 { 856 HAL_REO_R0_CONFIG(soc, reg_val, reo_params); 857 } 858 859 /** 860 * hal_rx_msdu_desc_info_get_ptr_8074v1() - Get msdu desc info ptr 861 * @msdu_details_ptr - Pointer to msdu_details_ptr 862 * 863 * Return - Pointer to rx_msdu_desc_info structure. 864 * 865 */ 866 static void *hal_rx_msdu_desc_info_get_ptr_8074v1(void *msdu_details_ptr) 867 { 868 return HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr); 869 } 870 871 /** 872 * hal_rx_link_desc_msdu0_ptr_8074v1 - Get pointer to rx_msdu details 873 * @link_desc - Pointer to link desc 874 * 875 * Return - Pointer to rx_msdu_details structure 876 * 877 */ 878 static void *hal_rx_link_desc_msdu0_ptr_8074v1(void *link_desc) 879 { 880 return HAL_RX_LINK_DESC_MSDU0_PTR(link_desc); 881 } 882 883 /** 884 * hal_rx_msdu_flow_idx_get_8074v1: API to get flow index 885 * from rx_msdu_end TLV 886 * @buf: pointer to the start of RX PKT TLV headers 887 * 888 * Return: flow index value from MSDU END TLV 889 */ 890 static inline uint32_t hal_rx_msdu_flow_idx_get_8074v1(uint8_t *buf) 891 { 892 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 893 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 894 895 return HAL_RX_MSDU_END_FLOW_IDX_GET(msdu_end); 896 } 897 898 /** 899 * hal_rx_msdu_flow_idx_invalid_8074v1: API to get flow index invalid 900 * from rx_msdu_end TLV 901 * @buf: pointer to the start of RX PKT TLV headers 902 * 903 * Return: flow index invalid value from MSDU END TLV 904 */ 905 static bool hal_rx_msdu_flow_idx_invalid_8074v1(uint8_t *buf) 906 { 907 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 908 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 909 910 return HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(msdu_end); 911 } 912 913 /** 914 * hal_rx_msdu_flow_idx_timeout_8074v1: API to get flow index timeout 915 * from rx_msdu_end TLV 916 * @buf: pointer to the start of RX PKT TLV headers 917 * 918 * Return: flow index timeout value from MSDU END TLV 919 */ 920 static bool hal_rx_msdu_flow_idx_timeout_8074v1(uint8_t *buf) 921 { 922 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 923 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 924 925 return HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(msdu_end); 926 } 927 928 /** 929 * hal_rx_msdu_fse_metadata_get_8074v1: API to get FSE metadata 930 * from rx_msdu_end TLV 931 * @buf: pointer to the start of RX PKT TLV headers 932 * 933 * Return: fse metadata value from MSDU END TLV 934 */ 935 static uint32_t hal_rx_msdu_fse_metadata_get_8074v1(uint8_t *buf) 936 { 937 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 938 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 939 940 return HAL_RX_MSDU_END_FSE_METADATA_GET(msdu_end); 941 } 942 943 /** 944 * hal_rx_msdu_cce_metadata_get_8074v1: API to get CCE metadata 945 * from rx_msdu_end TLV 946 * @buf: pointer to the start of RX PKT TLV headers 947 * 948 * Return: cce_metadata 949 */ 950 static uint16_t 951 hal_rx_msdu_cce_metadata_get_8074v1(uint8_t *buf) 952 { 953 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 954 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 955 956 return HAL_RX_MSDU_END_CCE_METADATA_GET(msdu_end); 957 } 958 959 /** 960 * hal_rx_msdu_get_flow_params_8074v1: API to get flow index, flow index invalid 961 * and flow index timeout from rx_msdu_end TLV 962 * @buf: pointer to the start of RX PKT TLV headers 963 * @flow_invalid: pointer to return value of flow_idx_valid 964 * @flow_timeout: pointer to return value of flow_idx_timeout 965 * @flow_index: pointer to return value of flow_idx 966 * 967 * Return: none 968 */ 969 static inline void 970 hal_rx_msdu_get_flow_params_8074v1(uint8_t *buf, 971 bool *flow_invalid, 972 bool *flow_timeout, 973 uint32_t *flow_index) 974 { 975 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 976 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 977 978 *flow_invalid = HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(msdu_end); 979 *flow_timeout = HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(msdu_end); 980 *flow_index = HAL_RX_MSDU_END_FLOW_IDX_GET(msdu_end); 981 } 982 983 /** 984 * hal_rx_tlv_get_tcp_chksum_8074v1() - API to get tcp checksum 985 * @buf: rx_tlv_hdr 986 * 987 * Return: tcp checksum 988 */ 989 static uint16_t 990 hal_rx_tlv_get_tcp_chksum_8074v1(uint8_t *buf) 991 { 992 return HAL_RX_TLV_GET_TCP_CHKSUM(buf); 993 } 994 995 /** 996 * hal_rx_get_rx_sequence_8074v1(): Function to retrieve rx sequence number 997 * 998 * @nbuf: Network buffer 999 * Returns: rx sequence number 1000 */ 1001 static 1002 uint16_t hal_rx_get_rx_sequence_8074v1(uint8_t *buf) 1003 { 1004 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 1005 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 1006 1007 return HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info); 1008 } 1009 1010 /** 1011 * hal_rx_mpdu_start_tlv_tag_valid_8074v1 () - API to check if RX_MPDU_START 1012 * tlv tag is valid 1013 * 1014 * @rx_tlv_hdr: start address of rx_pkt_tlvs 1015 * 1016 * Return: true if RX_MPDU_START is valied, else false. 1017 */ 1018 uint8_t hal_rx_mpdu_start_tlv_tag_valid_8074v1(void *rx_tlv_hdr) 1019 { 1020 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)rx_tlv_hdr; 1021 uint32_t tlv_tag; 1022 1023 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE( 1024 &rx_desc->mpdu_start_tlv); 1025 1026 return tlv_tag == WIFIRX_MPDU_START_E ? true : false; 1027 } 1028 1029 /** 1030 * hal_rx_flow_setup_fse_8074v1() - Setup a flow search entry in HW FST 1031 * @fst: Pointer to the Rx Flow Search Table 1032 * @table_offset: offset into the table where the flow is to be setup 1033 * @flow: Flow Parameters 1034 * 1035 * Return: Success/Failure 1036 */ 1037 static void * 1038 hal_rx_flow_setup_fse_8074v1(uint8_t *rx_fst, uint32_t table_offset, 1039 uint8_t *rx_flow) 1040 { 1041 struct hal_rx_fst *fst = (struct hal_rx_fst *)rx_fst; 1042 struct hal_rx_flow *flow = (struct hal_rx_flow *)rx_flow; 1043 uint8_t *fse; 1044 bool fse_valid; 1045 1046 if (table_offset >= fst->max_entries) { 1047 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR, 1048 "HAL FSE table offset %u exceeds max entries %u", 1049 table_offset, fst->max_entries); 1050 return NULL; 1051 } 1052 1053 fse = (uint8_t *)fst->base_vaddr + 1054 (table_offset * HAL_RX_FST_ENTRY_SIZE); 1055 1056 fse_valid = HAL_GET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, VALID); 1057 1058 if (fse_valid) { 1059 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_DEBUG, 1060 "HAL FSE %pK already valid", fse); 1061 return NULL; 1062 } 1063 1064 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_0, SRC_IP_127_96) = 1065 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_0, SRC_IP_127_96, 1066 qdf_htonl(flow->tuple_info.src_ip_127_96)); 1067 1068 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_1, SRC_IP_95_64) = 1069 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_1, SRC_IP_95_64, 1070 qdf_htonl(flow->tuple_info.src_ip_95_64)); 1071 1072 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_2, SRC_IP_63_32) = 1073 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_2, SRC_IP_63_32, 1074 qdf_htonl(flow->tuple_info.src_ip_63_32)); 1075 1076 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_3, SRC_IP_31_0) = 1077 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_3, SRC_IP_31_0, 1078 qdf_htonl(flow->tuple_info.src_ip_31_0)); 1079 1080 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_4, DEST_IP_127_96) = 1081 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_4, DEST_IP_127_96, 1082 qdf_htonl(flow->tuple_info.dest_ip_127_96)); 1083 1084 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_5, DEST_IP_95_64) = 1085 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_5, DEST_IP_95_64, 1086 qdf_htonl(flow->tuple_info.dest_ip_95_64)); 1087 1088 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_6, DEST_IP_63_32) = 1089 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_6, DEST_IP_63_32, 1090 qdf_htonl(flow->tuple_info.dest_ip_63_32)); 1091 1092 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_7, DEST_IP_31_0) = 1093 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_7, DEST_IP_31_0, 1094 qdf_htonl(flow->tuple_info.dest_ip_31_0)); 1095 1096 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, DEST_PORT); 1097 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, DEST_PORT) |= 1098 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_8, DEST_PORT, 1099 (flow->tuple_info.dest_port)); 1100 1101 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, SRC_PORT); 1102 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, SRC_PORT) |= 1103 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_8, SRC_PORT, 1104 (flow->tuple_info.src_port)); 1105 1106 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, L4_PROTOCOL); 1107 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, L4_PROTOCOL) |= 1108 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, L4_PROTOCOL, 1109 flow->tuple_info.l4_protocol); 1110 1111 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_HANDLER); 1112 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_HANDLER) |= 1113 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_HANDLER, 1114 flow->reo_destination_handler); 1115 1116 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, VALID); 1117 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, VALID) |= 1118 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, VALID, 1); 1119 1120 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_10, METADATA); 1121 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_10, METADATA) = 1122 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_10, METADATA, 1123 flow->fse_metadata); 1124 1125 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_11, REO_DESTINATION_INDICATION); 1126 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_11, REO_DESTINATION_INDICATION) |= 1127 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_11, 1128 REO_DESTINATION_INDICATION, 1129 flow->reo_destination_indication); 1130 1131 /* Reset all the other fields in FSE */ 1132 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, RESERVED_9); 1133 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_11, MSDU_DROP); 1134 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_11, RESERVED_11); 1135 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_11, MSDU_COUNT); 1136 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_12, MSDU_BYTE_COUNT); 1137 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_13, TIMESTAMP); 1138 1139 return fse; 1140 } 1141 1142 static 1143 void hal_compute_reo_remap_ix2_ix3_8074v1(uint32_t *ring, uint32_t num_rings, 1144 uint32_t *remap1, uint32_t *remap2) 1145 { 1146 switch (num_rings) { 1147 case 1: 1148 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 1149 HAL_REO_REMAP_IX2(ring[0], 17) | 1150 HAL_REO_REMAP_IX2(ring[0], 18) | 1151 HAL_REO_REMAP_IX2(ring[0], 19) | 1152 HAL_REO_REMAP_IX2(ring[0], 20) | 1153 HAL_REO_REMAP_IX2(ring[0], 21) | 1154 HAL_REO_REMAP_IX2(ring[0], 22) | 1155 HAL_REO_REMAP_IX2(ring[0], 23); 1156 1157 *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) | 1158 HAL_REO_REMAP_IX3(ring[0], 25) | 1159 HAL_REO_REMAP_IX3(ring[0], 26) | 1160 HAL_REO_REMAP_IX3(ring[0], 27) | 1161 HAL_REO_REMAP_IX3(ring[0], 28) | 1162 HAL_REO_REMAP_IX3(ring[0], 29) | 1163 HAL_REO_REMAP_IX3(ring[0], 30) | 1164 HAL_REO_REMAP_IX3(ring[0], 31); 1165 break; 1166 case 2: 1167 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 1168 HAL_REO_REMAP_IX2(ring[0], 17) | 1169 HAL_REO_REMAP_IX2(ring[1], 18) | 1170 HAL_REO_REMAP_IX2(ring[1], 19) | 1171 HAL_REO_REMAP_IX2(ring[0], 20) | 1172 HAL_REO_REMAP_IX2(ring[0], 21) | 1173 HAL_REO_REMAP_IX2(ring[1], 22) | 1174 HAL_REO_REMAP_IX2(ring[1], 23); 1175 1176 *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) | 1177 HAL_REO_REMAP_IX3(ring[0], 25) | 1178 HAL_REO_REMAP_IX3(ring[1], 26) | 1179 HAL_REO_REMAP_IX3(ring[1], 27) | 1180 HAL_REO_REMAP_IX3(ring[0], 28) | 1181 HAL_REO_REMAP_IX3(ring[0], 29) | 1182 HAL_REO_REMAP_IX3(ring[1], 30) | 1183 HAL_REO_REMAP_IX3(ring[1], 31); 1184 break; 1185 case 3: 1186 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 1187 HAL_REO_REMAP_IX2(ring[1], 17) | 1188 HAL_REO_REMAP_IX2(ring[2], 18) | 1189 HAL_REO_REMAP_IX2(ring[0], 19) | 1190 HAL_REO_REMAP_IX2(ring[1], 20) | 1191 HAL_REO_REMAP_IX2(ring[2], 21) | 1192 HAL_REO_REMAP_IX2(ring[0], 22) | 1193 HAL_REO_REMAP_IX2(ring[1], 23); 1194 1195 *remap2 = HAL_REO_REMAP_IX3(ring[2], 24) | 1196 HAL_REO_REMAP_IX3(ring[0], 25) | 1197 HAL_REO_REMAP_IX3(ring[1], 26) | 1198 HAL_REO_REMAP_IX3(ring[2], 27) | 1199 HAL_REO_REMAP_IX3(ring[0], 28) | 1200 HAL_REO_REMAP_IX3(ring[1], 29) | 1201 HAL_REO_REMAP_IX3(ring[2], 30) | 1202 HAL_REO_REMAP_IX3(ring[0], 31); 1203 break; 1204 case 4: 1205 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 1206 HAL_REO_REMAP_IX2(ring[1], 17) | 1207 HAL_REO_REMAP_IX2(ring[2], 18) | 1208 HAL_REO_REMAP_IX2(ring[3], 19) | 1209 HAL_REO_REMAP_IX2(ring[0], 20) | 1210 HAL_REO_REMAP_IX2(ring[1], 21) | 1211 HAL_REO_REMAP_IX2(ring[2], 22) | 1212 HAL_REO_REMAP_IX2(ring[3], 23); 1213 1214 *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) | 1215 HAL_REO_REMAP_IX3(ring[1], 25) | 1216 HAL_REO_REMAP_IX3(ring[2], 26) | 1217 HAL_REO_REMAP_IX3(ring[3], 27) | 1218 HAL_REO_REMAP_IX3(ring[0], 28) | 1219 HAL_REO_REMAP_IX3(ring[1], 29) | 1220 HAL_REO_REMAP_IX3(ring[2], 30) | 1221 HAL_REO_REMAP_IX3(ring[3], 31); 1222 break; 1223 } 1224 } 1225 1226 static void hal_hw_txrx_ops_attach_qca8074(struct hal_soc *hal_soc) 1227 { 1228 1229 /* init and setup */ 1230 hal_soc->ops->hal_srng_dst_hw_init = hal_srng_dst_hw_init_generic; 1231 hal_soc->ops->hal_srng_src_hw_init = hal_srng_src_hw_init_generic; 1232 hal_soc->ops->hal_get_hw_hptp = hal_get_hw_hptp_generic; 1233 hal_soc->ops->hal_reo_setup = hal_reo_setup_generic_li; 1234 hal_soc->ops->hal_get_window_address = hal_get_window_address_8074; 1235 1236 /* tx */ 1237 hal_soc->ops->hal_tx_desc_set_dscp_tid_table_id = 1238 hal_tx_desc_set_dscp_tid_table_id_8074; 1239 hal_soc->ops->hal_tx_set_dscp_tid_map = hal_tx_set_dscp_tid_map_8074; 1240 hal_soc->ops->hal_tx_update_dscp_tid = hal_tx_update_dscp_tid_8074; 1241 hal_soc->ops->hal_tx_desc_set_lmac_id = hal_tx_desc_set_lmac_id_8074; 1242 hal_soc->ops->hal_tx_desc_set_buf_addr = 1243 hal_tx_desc_set_buf_addr_generic_li; 1244 hal_soc->ops->hal_tx_desc_set_search_type = 1245 hal_tx_desc_set_search_type_generic_li; 1246 hal_soc->ops->hal_tx_desc_set_search_index = 1247 hal_tx_desc_set_search_index_generic_li; 1248 hal_soc->ops->hal_tx_desc_set_cache_set_num = 1249 hal_tx_desc_set_cache_set_num_generic_li; 1250 hal_soc->ops->hal_tx_comp_get_status = 1251 hal_tx_comp_get_status_generic_li; 1252 hal_soc->ops->hal_tx_comp_get_release_reason = 1253 hal_tx_comp_get_release_reason_generic_li; 1254 hal_soc->ops->hal_get_wbm_internal_error = 1255 hal_get_wbm_internal_error_generic_li; 1256 hal_soc->ops->hal_tx_desc_set_mesh_en = hal_tx_desc_set_mesh_en_8074v1; 1257 hal_soc->ops->hal_tx_init_cmd_credit_ring = 1258 hal_tx_init_cmd_credit_ring_8074v1; 1259 1260 /* rx */ 1261 hal_soc->ops->hal_rx_msdu_start_nss_get = 1262 hal_rx_msdu_start_nss_get_8074; 1263 hal_soc->ops->hal_rx_mon_hw_desc_get_mpdu_status = 1264 hal_rx_mon_hw_desc_get_mpdu_status_8074; 1265 hal_soc->ops->hal_rx_get_tlv = hal_rx_get_tlv_8074; 1266 hal_soc->ops->hal_rx_proc_phyrx_other_receive_info_tlv = 1267 hal_rx_proc_phyrx_other_receive_info_tlv_8074; 1268 hal_soc->ops->hal_rx_dump_msdu_start_tlv = 1269 hal_rx_dump_msdu_start_tlv_8074; 1270 hal_soc->ops->hal_rx_dump_msdu_end_tlv = hal_rx_dump_msdu_end_tlv_8074; 1271 hal_soc->ops->hal_get_link_desc_size = hal_get_link_desc_size_8074; 1272 hal_soc->ops->hal_rx_mpdu_start_tid_get = 1273 hal_rx_mpdu_start_tid_get_8074; 1274 hal_soc->ops->hal_rx_msdu_start_reception_type_get = 1275 hal_rx_msdu_start_reception_type_get_8074; 1276 hal_soc->ops->hal_rx_msdu_end_da_idx_get = 1277 hal_rx_msdu_end_da_idx_get_8074; 1278 hal_soc->ops->hal_rx_msdu_desc_info_get_ptr = 1279 hal_rx_msdu_desc_info_get_ptr_8074v1; 1280 hal_soc->ops->hal_rx_link_desc_msdu0_ptr = 1281 hal_rx_link_desc_msdu0_ptr_8074v1; 1282 hal_soc->ops->hal_reo_status_get_header = 1283 hal_reo_status_get_header_8074v1; 1284 hal_soc->ops->hal_rx_status_get_tlv_info = 1285 hal_rx_status_get_tlv_info_generic_li; 1286 hal_soc->ops->hal_rx_wbm_err_info_get = 1287 hal_rx_wbm_err_info_get_generic_li; 1288 hal_soc->ops->hal_rx_dump_mpdu_start_tlv = 1289 hal_rx_dump_mpdu_start_tlv_generic_li; 1290 1291 hal_soc->ops->hal_tx_set_pcp_tid_map = 1292 hal_tx_set_pcp_tid_map_generic_li; 1293 hal_soc->ops->hal_tx_update_pcp_tid_map = 1294 hal_tx_update_pcp_tid_generic_li; 1295 hal_soc->ops->hal_tx_set_tidmap_prty = 1296 hal_tx_update_tidmap_prty_generic_li; 1297 hal_soc->ops->hal_rx_get_rx_fragment_number = 1298 hal_rx_get_rx_fragment_number_8074v1; 1299 hal_soc->ops->hal_rx_msdu_end_da_is_mcbc_get = 1300 hal_rx_msdu_end_da_is_mcbc_get_8074v1; 1301 hal_soc->ops->hal_rx_msdu_end_sa_is_valid_get = 1302 hal_rx_msdu_end_sa_is_valid_get_8074v1; 1303 hal_soc->ops->hal_rx_msdu_end_sa_idx_get = 1304 hal_rx_msdu_end_sa_idx_get_8074v1; 1305 hal_soc->ops->hal_rx_desc_is_first_msdu = 1306 hal_rx_desc_is_first_msdu_8074v1; 1307 hal_soc->ops->hal_rx_msdu_end_l3_hdr_padding_get = 1308 hal_rx_msdu_end_l3_hdr_padding_get_8074v1; 1309 hal_soc->ops->hal_rx_encryption_info_valid = 1310 hal_rx_encryption_info_valid_8074v1; 1311 hal_soc->ops->hal_rx_print_pn = hal_rx_print_pn_8074v1; 1312 hal_soc->ops->hal_rx_msdu_end_first_msdu_get = 1313 hal_rx_msdu_end_first_msdu_get_8074v1; 1314 hal_soc->ops->hal_rx_msdu_end_da_is_valid_get = 1315 hal_rx_msdu_end_da_is_valid_get_8074v1; 1316 hal_soc->ops->hal_rx_msdu_end_last_msdu_get = 1317 hal_rx_msdu_end_last_msdu_get_8074v1; 1318 hal_soc->ops->hal_rx_get_mpdu_mac_ad4_valid = 1319 hal_rx_get_mpdu_mac_ad4_valid_8074v1; 1320 hal_soc->ops->hal_rx_mpdu_start_sw_peer_id_get = 1321 hal_rx_mpdu_start_sw_peer_id_get_8074v1; 1322 hal_soc->ops->hal_rx_mpdu_peer_meta_data_get = 1323 hal_rx_mpdu_peer_meta_data_get_li; 1324 hal_soc->ops->hal_rx_mpdu_get_to_ds = hal_rx_mpdu_get_to_ds_8074v1; 1325 hal_soc->ops->hal_rx_mpdu_get_fr_ds = hal_rx_mpdu_get_fr_ds_8074v1; 1326 hal_soc->ops->hal_rx_get_mpdu_frame_control_valid = 1327 hal_rx_get_mpdu_frame_control_valid_8074v1; 1328 hal_soc->ops->hal_rx_mpdu_get_addr1 = hal_rx_mpdu_get_addr1_8074v1; 1329 hal_soc->ops->hal_rx_mpdu_get_addr2 = hal_rx_mpdu_get_addr2_8074v1; 1330 hal_soc->ops->hal_rx_mpdu_get_addr3 = hal_rx_mpdu_get_addr3_8074v1; 1331 hal_soc->ops->hal_rx_mpdu_get_addr4 = hal_rx_mpdu_get_addr4_8074v1; 1332 hal_soc->ops->hal_rx_get_mpdu_sequence_control_valid = 1333 hal_rx_get_mpdu_sequence_control_valid_8074v1; 1334 hal_soc->ops->hal_rx_is_unicast = hal_rx_is_unicast_8074v1; 1335 hal_soc->ops->hal_rx_tid_get = hal_rx_tid_get_8074v1; 1336 hal_soc->ops->hal_rx_hw_desc_get_ppduid_get = 1337 hal_rx_hw_desc_get_ppduid_get_8074v1; 1338 hal_soc->ops->hal_rx_mpdu_start_mpdu_qos_control_valid_get = 1339 hal_rx_mpdu_start_mpdu_qos_control_valid_get_8074v1; 1340 hal_soc->ops->hal_rx_msdu_end_sa_sw_peer_id_get = 1341 hal_rx_msdu_end_sa_sw_peer_id_get_8074v1; 1342 hal_soc->ops->hal_rx_msdu0_buffer_addr_lsb = 1343 hal_rx_msdu0_buffer_addr_lsb_8074v1; 1344 hal_soc->ops->hal_rx_msdu_desc_info_ptr_get = 1345 hal_rx_msdu_desc_info_ptr_get_8074v1; 1346 hal_soc->ops->hal_ent_mpdu_desc_info = hal_ent_mpdu_desc_info_8074v1; 1347 hal_soc->ops->hal_dst_mpdu_desc_info = hal_dst_mpdu_desc_info_8074v1; 1348 hal_soc->ops->hal_rx_get_fc_valid = hal_rx_get_fc_valid_8074v1; 1349 hal_soc->ops->hal_rx_get_to_ds_flag = hal_rx_get_to_ds_flag_8074v1; 1350 hal_soc->ops->hal_rx_get_mac_addr2_valid = 1351 hal_rx_get_mac_addr2_valid_8074v1; 1352 hal_soc->ops->hal_rx_get_filter_category = 1353 hal_rx_get_filter_category_8074v1; 1354 hal_soc->ops->hal_rx_get_ppdu_id = hal_rx_get_ppdu_id_8074v1; 1355 hal_soc->ops->hal_reo_config = hal_reo_config_8074v1; 1356 hal_soc->ops->hal_rx_msdu_flow_idx_get = 1357 hal_rx_msdu_flow_idx_get_8074v1; 1358 hal_soc->ops->hal_rx_msdu_flow_idx_invalid = 1359 hal_rx_msdu_flow_idx_invalid_8074v1; 1360 hal_soc->ops->hal_rx_msdu_flow_idx_timeout = 1361 hal_rx_msdu_flow_idx_timeout_8074v1; 1362 hal_soc->ops->hal_rx_msdu_fse_metadata_get = 1363 hal_rx_msdu_fse_metadata_get_8074v1; 1364 hal_soc->ops->hal_rx_msdu_cce_match_get = 1365 hal_rx_msdu_cce_match_get_li; 1366 hal_soc->ops->hal_rx_msdu_cce_metadata_get = 1367 hal_rx_msdu_cce_metadata_get_8074v1; 1368 hal_soc->ops->hal_rx_msdu_get_flow_params = 1369 hal_rx_msdu_get_flow_params_8074v1; 1370 hal_soc->ops->hal_rx_tlv_get_tcp_chksum = 1371 hal_rx_tlv_get_tcp_chksum_8074v1; 1372 hal_soc->ops->hal_rx_get_rx_sequence = hal_rx_get_rx_sequence_8074v1; 1373 /* rx - msdu fast path info fields */ 1374 hal_soc->ops->hal_rx_msdu_packet_metadata_get = 1375 hal_rx_msdu_packet_metadata_get_generic_li; 1376 hal_soc->ops->hal_rx_mpdu_start_tlv_tag_valid = 1377 hal_rx_mpdu_start_tlv_tag_valid_8074v1; 1378 1379 /* rx - TLV struct offsets */ 1380 hal_soc->ops->hal_rx_msdu_end_offset_get = 1381 hal_rx_msdu_end_offset_get_generic; 1382 hal_soc->ops->hal_rx_attn_offset_get = hal_rx_attn_offset_get_generic; 1383 hal_soc->ops->hal_rx_msdu_start_offset_get = 1384 hal_rx_msdu_start_offset_get_generic; 1385 hal_soc->ops->hal_rx_mpdu_start_offset_get = 1386 hal_rx_mpdu_start_offset_get_generic; 1387 hal_soc->ops->hal_rx_mpdu_end_offset_get = 1388 hal_rx_mpdu_end_offset_get_generic; 1389 #ifndef NO_RX_PKT_HDR_TLV 1390 hal_soc->ops->hal_rx_pkt_tlv_offset_get = 1391 hal_rx_pkt_tlv_offset_get_generic; 1392 #endif 1393 hal_soc->ops->hal_rx_flow_setup_fse = hal_rx_flow_setup_fse_8074v1; 1394 hal_soc->ops->hal_rx_flow_get_tuple_info = 1395 hal_rx_flow_get_tuple_info_li; 1396 hal_soc->ops->hal_rx_flow_delete_entry = 1397 hal_rx_flow_delete_entry_li; 1398 hal_soc->ops->hal_rx_fst_get_fse_size = hal_rx_fst_get_fse_size_li; 1399 hal_soc->ops->hal_compute_reo_remap_ix2_ix3 = 1400 hal_compute_reo_remap_ix2_ix3_8074v1; 1401 hal_soc->ops->hal_setup_link_idle_list = 1402 hal_setup_link_idle_list_generic_li; 1403 }; 1404 1405 struct hal_hw_srng_config hw_srng_table_8074[] = { 1406 /* TODO: max_rings can populated by querying HW capabilities */ 1407 { /* REO_DST */ 1408 .start_ring_id = HAL_SRNG_REO2SW1, 1409 .max_rings = 4, 1410 .entry_size = sizeof(struct reo_destination_ring) >> 2, 1411 .lmac_ring = FALSE, 1412 .ring_dir = HAL_SRNG_DST_RING, 1413 .reg_start = { 1414 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR( 1415 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1416 HWIO_REO_R2_REO2SW1_RING_HP_ADDR( 1417 SEQ_WCSS_UMAC_REO_REG_OFFSET) 1418 }, 1419 .reg_size = { 1420 HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(0) - 1421 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(0), 1422 HWIO_REO_R2_REO2SW2_RING_HP_ADDR(0) - 1423 HWIO_REO_R2_REO2SW1_RING_HP_ADDR(0), 1424 }, 1425 .max_size = 1426 HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_BMSK >> 1427 HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_SHFT, 1428 }, 1429 { /* REO_EXCEPTION */ 1430 /* Designating REO2TCL ring as exception ring. This ring is 1431 * similar to other REO2SW rings though it is named as REO2TCL. 1432 * Any of theREO2SW rings can be used as exception ring. 1433 */ 1434 .start_ring_id = HAL_SRNG_REO2TCL, 1435 .max_rings = 1, 1436 .entry_size = sizeof(struct reo_destination_ring) >> 2, 1437 .lmac_ring = FALSE, 1438 .ring_dir = HAL_SRNG_DST_RING, 1439 .reg_start = { 1440 HWIO_REO_R0_REO2TCL_RING_BASE_LSB_ADDR( 1441 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1442 HWIO_REO_R2_REO2TCL_RING_HP_ADDR( 1443 SEQ_WCSS_UMAC_REO_REG_OFFSET) 1444 }, 1445 /* Single ring - provide ring size if multiple rings of this 1446 * type are supported 1447 */ 1448 .reg_size = {}, 1449 .max_size = 1450 HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_BMSK >> 1451 HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_SHFT, 1452 }, 1453 { /* REO_REINJECT */ 1454 .start_ring_id = HAL_SRNG_SW2REO, 1455 .max_rings = 1, 1456 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 1457 .lmac_ring = FALSE, 1458 .ring_dir = HAL_SRNG_SRC_RING, 1459 .reg_start = { 1460 HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR( 1461 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1462 HWIO_REO_R2_SW2REO_RING_HP_ADDR( 1463 SEQ_WCSS_UMAC_REO_REG_OFFSET) 1464 }, 1465 /* Single ring - provide ring size if multiple rings of this 1466 * type are supported 1467 */ 1468 .reg_size = {}, 1469 .max_size = HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_BMSK >> 1470 HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_SHFT, 1471 }, 1472 { /* REO_CMD */ 1473 .start_ring_id = HAL_SRNG_REO_CMD, 1474 .max_rings = 1, 1475 .entry_size = (sizeof(struct tlv_32_hdr) + 1476 sizeof(struct reo_get_queue_stats)) >> 2, 1477 .lmac_ring = FALSE, 1478 .ring_dir = HAL_SRNG_SRC_RING, 1479 .reg_start = { 1480 HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR( 1481 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1482 HWIO_REO_R2_REO_CMD_RING_HP_ADDR( 1483 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1484 }, 1485 /* Single ring - provide ring size if multiple rings of this 1486 * type are supported 1487 */ 1488 .reg_size = {}, 1489 .max_size = HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_BMSK >> 1490 HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_SHFT, 1491 }, 1492 { /* REO_STATUS */ 1493 .start_ring_id = HAL_SRNG_REO_STATUS, 1494 .max_rings = 1, 1495 .entry_size = (sizeof(struct tlv_32_hdr) + 1496 sizeof(struct reo_get_queue_stats_status)) >> 2, 1497 .lmac_ring = FALSE, 1498 .ring_dir = HAL_SRNG_DST_RING, 1499 .reg_start = { 1500 HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR( 1501 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1502 HWIO_REO_R2_REO_STATUS_RING_HP_ADDR( 1503 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1504 }, 1505 /* Single ring - provide ring size if multiple rings of this 1506 * type are supported 1507 */ 1508 .reg_size = {}, 1509 .max_size = 1510 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> 1511 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, 1512 }, 1513 { /* TCL_DATA */ 1514 .start_ring_id = HAL_SRNG_SW2TCL1, 1515 .max_rings = 3, 1516 .entry_size = (sizeof(struct tlv_32_hdr) + 1517 sizeof(struct tcl_data_cmd)) >> 2, 1518 .lmac_ring = FALSE, 1519 .ring_dir = HAL_SRNG_SRC_RING, 1520 .reg_start = { 1521 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR( 1522 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1523 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR( 1524 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1525 }, 1526 .reg_size = { 1527 HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(0) - 1528 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(0), 1529 HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(0) - 1530 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(0), 1531 }, 1532 .max_size = 1533 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK >> 1534 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT, 1535 }, 1536 { /* TCL_CMD */ 1537 .start_ring_id = HAL_SRNG_SW2TCL_CMD, 1538 .max_rings = 1, 1539 .entry_size = (sizeof(struct tlv_32_hdr) + 1540 sizeof(struct tcl_data_cmd)) >> 2, 1541 .lmac_ring = FALSE, 1542 .ring_dir = HAL_SRNG_SRC_RING, 1543 .reg_start = { 1544 HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_ADDR( 1545 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1546 HWIO_TCL_R2_SW2TCL_CMD_RING_HP_ADDR( 1547 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1548 }, 1549 /* Single ring - provide ring size if multiple rings of this 1550 * type are supported 1551 */ 1552 .reg_size = {}, 1553 .max_size = 1554 HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RING_SIZE_BMSK >> 1555 HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RING_SIZE_SHFT, 1556 }, 1557 { /* TCL_STATUS */ 1558 .start_ring_id = HAL_SRNG_TCL_STATUS, 1559 .max_rings = 1, 1560 .entry_size = (sizeof(struct tlv_32_hdr) + 1561 sizeof(struct tcl_status_ring)) >> 2, 1562 .lmac_ring = FALSE, 1563 .ring_dir = HAL_SRNG_DST_RING, 1564 .reg_start = { 1565 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR( 1566 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1567 HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR( 1568 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1569 }, 1570 /* Single ring - provide ring size if multiple rings of this 1571 * type are supported 1572 */ 1573 .reg_size = {}, 1574 .max_size = 1575 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_BMSK >> 1576 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_SHFT, 1577 }, 1578 { /* CE_SRC */ 1579 .start_ring_id = HAL_SRNG_CE_0_SRC, 1580 .max_rings = 12, 1581 .entry_size = sizeof(struct ce_src_desc) >> 2, 1582 .lmac_ring = FALSE, 1583 .ring_dir = HAL_SRNG_SRC_RING, 1584 .reg_start = { 1585 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR( 1586 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET), 1587 HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR( 1588 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET), 1589 }, 1590 .reg_size = { 1591 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET - 1592 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET, 1593 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET - 1594 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET, 1595 }, 1596 .max_size = 1597 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >> 1598 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT, 1599 }, 1600 { /* CE_DST */ 1601 .start_ring_id = HAL_SRNG_CE_0_DST, 1602 .max_rings = 12, 1603 .entry_size = 8 >> 2, 1604 /*TODO: entry_size above should actually be 1605 * sizeof(struct ce_dst_desc) >> 2, but couldn't find definition 1606 * of struct ce_dst_desc in HW header files 1607 */ 1608 .lmac_ring = FALSE, 1609 .ring_dir = HAL_SRNG_SRC_RING, 1610 .reg_start = { 1611 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR( 1612 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 1613 HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR( 1614 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 1615 }, 1616 .reg_size = { 1617 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 1618 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 1619 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 1620 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 1621 }, 1622 .max_size = 1623 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >> 1624 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT, 1625 }, 1626 { /* CE_DST_STATUS */ 1627 .start_ring_id = HAL_SRNG_CE_0_DST_STATUS, 1628 .max_rings = 12, 1629 .entry_size = sizeof(struct ce_stat_desc) >> 2, 1630 .lmac_ring = FALSE, 1631 .ring_dir = HAL_SRNG_DST_RING, 1632 .reg_start = { 1633 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR( 1634 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 1635 HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR( 1636 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 1637 }, 1638 /* TODO: check destination status ring registers */ 1639 .reg_size = { 1640 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 1641 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 1642 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 1643 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 1644 }, 1645 .max_size = 1646 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> 1647 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, 1648 }, 1649 { /* WBM_IDLE_LINK */ 1650 .start_ring_id = HAL_SRNG_WBM_IDLE_LINK, 1651 .max_rings = 1, 1652 .entry_size = sizeof(struct wbm_link_descriptor_ring) >> 2, 1653 .lmac_ring = FALSE, 1654 .ring_dir = HAL_SRNG_SRC_RING, 1655 .reg_start = { 1656 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1657 HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1658 }, 1659 /* Single ring - provide ring size if multiple rings of this 1660 * type are supported 1661 */ 1662 .reg_size = {}, 1663 .max_size = 1664 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_BMSK >> 1665 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_SHFT, 1666 }, 1667 { /* SW2WBM_RELEASE */ 1668 .start_ring_id = HAL_SRNG_WBM_SW_RELEASE, 1669 .max_rings = 1, 1670 .entry_size = sizeof(struct wbm_release_ring) >> 2, 1671 .lmac_ring = FALSE, 1672 .ring_dir = HAL_SRNG_SRC_RING, 1673 .reg_start = { 1674 HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1675 HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1676 }, 1677 /* Single ring - provide ring size if multiple rings of this 1678 * type are supported 1679 */ 1680 .reg_size = {}, 1681 .max_size = 1682 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> 1683 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, 1684 }, 1685 { /* WBM2SW_RELEASE */ 1686 .start_ring_id = HAL_SRNG_WBM2SW0_RELEASE, 1687 .max_rings = 4, 1688 .entry_size = sizeof(struct wbm_release_ring) >> 2, 1689 .lmac_ring = FALSE, 1690 .ring_dir = HAL_SRNG_DST_RING, 1691 .reg_start = { 1692 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1693 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1694 }, 1695 .reg_size = { 1696 HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) - 1697 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1698 HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) - 1699 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1700 }, 1701 .max_size = 1702 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> 1703 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, 1704 }, 1705 { /* RXDMA_BUF */ 1706 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA0_BUF0, 1707 #ifdef IPA_OFFLOAD 1708 .max_rings = 3, 1709 #else 1710 .max_rings = 2, 1711 #endif 1712 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 1713 .lmac_ring = TRUE, 1714 .ring_dir = HAL_SRNG_SRC_RING, 1715 /* reg_start is not set because LMAC rings are not accessed 1716 * from host 1717 */ 1718 .reg_start = {}, 1719 .reg_size = {}, 1720 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1721 }, 1722 { /* RXDMA_DST */ 1723 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW0, 1724 .max_rings = 1, 1725 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 1726 .lmac_ring = TRUE, 1727 .ring_dir = HAL_SRNG_DST_RING, 1728 /* reg_start is not set because LMAC rings are not accessed 1729 * from host 1730 */ 1731 .reg_start = {}, 1732 .reg_size = {}, 1733 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1734 }, 1735 { /* RXDMA_MONITOR_BUF */ 1736 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA2_BUF, 1737 .max_rings = 1, 1738 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 1739 .lmac_ring = TRUE, 1740 .ring_dir = HAL_SRNG_SRC_RING, 1741 /* reg_start is not set because LMAC rings are not accessed 1742 * from host 1743 */ 1744 .reg_start = {}, 1745 .reg_size = {}, 1746 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1747 }, 1748 { /* RXDMA_MONITOR_STATUS */ 1749 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_STATBUF, 1750 .max_rings = 1, 1751 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 1752 .lmac_ring = TRUE, 1753 .ring_dir = HAL_SRNG_SRC_RING, 1754 /* reg_start is not set because LMAC rings are not accessed 1755 * from host 1756 */ 1757 .reg_start = {}, 1758 .reg_size = {}, 1759 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1760 }, 1761 { /* RXDMA_MONITOR_DST */ 1762 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW1, 1763 .max_rings = 1, 1764 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 1765 .lmac_ring = TRUE, 1766 .ring_dir = HAL_SRNG_DST_RING, 1767 /* reg_start is not set because LMAC rings are not accessed 1768 * from host 1769 */ 1770 .reg_start = {}, 1771 .reg_size = {}, 1772 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1773 }, 1774 { /* RXDMA_MONITOR_DESC */ 1775 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_DESC, 1776 .max_rings = 1, 1777 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 1778 .lmac_ring = TRUE, 1779 .ring_dir = HAL_SRNG_SRC_RING, 1780 /* reg_start is not set because LMAC rings are not accessed 1781 * from host 1782 */ 1783 .reg_start = {}, 1784 .reg_size = {}, 1785 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1786 }, 1787 { /* DIR_BUF_RX_DMA_SRC */ 1788 .start_ring_id = HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING, 1789 .max_rings = 1, 1790 .entry_size = 2, 1791 .lmac_ring = TRUE, 1792 .ring_dir = HAL_SRNG_SRC_RING, 1793 /* reg_start is not set because LMAC rings are not accessed 1794 * from host 1795 */ 1796 .reg_start = {}, 1797 .reg_size = {}, 1798 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1799 }, 1800 #ifdef WLAN_FEATURE_CIF_CFR 1801 { /* WIFI_POS_SRC */ 1802 .start_ring_id = HAL_SRNG_WIFI_POS_SRC_DMA_RING, 1803 .max_rings = 1, 1804 .entry_size = sizeof(wmi_oem_dma_buf_release_entry) >> 2, 1805 .lmac_ring = TRUE, 1806 .ring_dir = HAL_SRNG_SRC_RING, 1807 /* reg_start is not set because LMAC rings are not accessed 1808 * from host 1809 */ 1810 .reg_start = {}, 1811 .reg_size = {}, 1812 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1813 }, 1814 #endif 1815 { /* REO2PPE */ 0}, 1816 { /* PPE2TCL */ 0}, 1817 { /* PPE_RELEASE */ 0}, 1818 { /* TX_MONITOR_BUF */ 0}, 1819 { /* TX_MONITOR_DST */ 0}, 1820 { /* SW2RXDMA_NEW */ 0}, 1821 }; 1822 1823 /** 1824 * hal_qca8074_attach() - Attach 8074 target specific hal_soc ops, 1825 * offset and srng table 1826 */ 1827 void hal_qca8074_attach(struct hal_soc *hal_soc) 1828 { 1829 hal_soc->hw_srng_table = hw_srng_table_8074; 1830 hal_srng_hw_reg_offset_init_generic(hal_soc); 1831 hal_hw_txrx_default_ops_attach_li(hal_soc); 1832 hal_hw_txrx_ops_attach_qca8074(hal_soc); 1833 } 1834