1 /* 2 * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved. 3 * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 #include "hal_li_hw_headers.h" 20 #include "hal_internal.h" 21 #include "hal_api.h" 22 #include "target_type.h" 23 #include "wcss_version.h" 24 #include "qdf_module.h" 25 #include "hal_flow.h" 26 #include "rx_flow_search_entry.h" 27 #include "hal_rx_flow_info.h" 28 29 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_OFFSET \ 30 RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_OFFSET 31 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_MASK \ 32 RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_MASK 33 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_LSB \ 34 RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_LSB 35 #define UNIFIED_RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_OFFSET \ 36 RXPCU_PPDU_END_INFO_10_PHYRX_ABORT_REQUEST_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_OFFSET 37 #define UNIFIED_RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_MASK \ 38 RXPCU_PPDU_END_INFO_10_PHYRX_ABORT_REQUEST_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_MASK 39 #define UNIFIED_RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_LSB \ 40 RXPCU_PPDU_END_INFO_10_PHYRX_ABORT_REQUEST_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_LSB 41 #define UNIFIED_PHYRX_HT_SIG_0_HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS_OFFSET \ 42 PHYRX_HT_SIG_0_HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS_OFFSET 43 #define UNIFIED_PHYRX_L_SIG_B_0_L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS_OFFSET \ 44 PHYRX_L_SIG_B_0_L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS_OFFSET 45 #define UNIFIED_PHYRX_L_SIG_A_0_L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS_OFFSET \ 46 PHYRX_L_SIG_A_0_L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS_OFFSET 47 #define UNIFIED_PHYRX_VHT_SIG_A_0_VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS_OFFSET \ 48 PHYRX_VHT_SIG_A_0_VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS_OFFSET 49 #define UNIFIED_PHYRX_HE_SIG_A_SU_0_HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS_OFFSET \ 50 PHYRX_HE_SIG_A_SU_0_HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS_OFFSET 51 #define UNIFIED_PHYRX_HE_SIG_A_MU_DL_0_HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_OFFSET \ 52 PHYRX_HE_SIG_A_MU_DL_0_HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_OFFSET 53 #define UNIFIED_PHYRX_HE_SIG_B1_MU_0_HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_OFFSET \ 54 PHYRX_HE_SIG_B1_MU_0_HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_OFFSET 55 #define UNIFIED_PHYRX_HE_SIG_B2_MU_0_HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_OFFSET \ 56 PHYRX_HE_SIG_B2_MU_0_HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_OFFSET 57 #define UNIFIED_PHYRX_HE_SIG_B2_OFDMA_0_HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_OFFSET \ 58 PHYRX_HE_SIG_B2_OFDMA_0_HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_OFFSET 59 #define UNIFIED_PHYRX_RSSI_LEGACY_3_RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS_OFFSET \ 60 PHYRX_RSSI_LEGACY_3_RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS_OFFSET 61 #define UNIFIED_PHYRX_RSSI_LEGACY_19_RECEIVE_RSSI_INFO_PREAMBLE_RSSI_INFO_DETAILS_OFFSET \ 62 PHYRX_RSSI_LEGACY_19_RECEIVE_RSSI_INFO_PREAMBLE_RSSI_INFO_DETAILS_OFFSET 63 #define UNIFIED_RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET \ 64 RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET 65 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 66 RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET 67 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ 68 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET 69 #define UNIFIED_RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 70 RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET 71 #define UNIFIED_REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 72 REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET 73 #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC \ 74 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER 75 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSE \ 76 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET 77 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 78 RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET 79 #define UNIFIED_TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 80 TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET 81 #define UNIFIED_TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 82 TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET 83 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET \ 84 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET 85 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB \ 86 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB 87 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK \ 88 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK 89 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB \ 90 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB 91 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK \ 92 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK 93 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB \ 94 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB 95 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK \ 96 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK 97 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB \ 98 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB 99 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK \ 100 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK 101 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB \ 102 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB 103 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK \ 104 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK 105 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_MASK \ 106 WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_MASK 107 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_OFFSET \ 108 WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_OFFSET 109 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_LSB \ 110 WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_LSB 111 112 #include "hal_8074v1_tx.h" 113 #include "hal_8074v1_rx.h" 114 #include <hal_generic_api.h> 115 #include "hal_li_rx.h" 116 #include "hal_li_tx.h" 117 #include "hal_li_api.h" 118 #include "hal_li_generic_api.h" 119 120 /** 121 * hal_get_window_address_8074(): Function to get hp/tp address 122 * @hal_soc: Pointer to hal_soc 123 * @addr: address offset of register 124 * 125 * Return: modified address offset of register 126 */ 127 static inline qdf_iomem_t hal_get_window_address_8074(struct hal_soc *hal_soc, 128 qdf_iomem_t addr) 129 { 130 return addr; 131 } 132 133 /** 134 * hal_rx_get_rx_fragment_number_8074v1(): Function to retrieve 135 * rx fragment number 136 * 137 * @nbuf: Network buffer 138 * Returns: rx fragment number 139 */ 140 static 141 uint8_t hal_rx_get_rx_fragment_number_8074v1(uint8_t *buf) 142 { 143 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 144 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 145 146 /* Return first 4 bits as fragment number */ 147 return (HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info) & 148 DOT11_SEQ_FRAG_MASK); 149 } 150 151 /** 152 * hal_rx_msdu_end_da_is_mcbc_get_8074v1(): API to check if 153 * pkt is MCBC from rx_msdu_end TLV 154 * 155 * @ buf: pointer to the start of RX PKT TLV headers 156 * Return: da_is_mcbc 157 */ 158 static uint8_t 159 hal_rx_msdu_end_da_is_mcbc_get_8074v1(uint8_t *buf) 160 { 161 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 162 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 163 164 return HAL_RX_MSDU_END_DA_IS_MCBC_GET(msdu_end); 165 } 166 167 /** 168 * hal_rx_msdu_end_sa_is_valid_get_8074v1(): API to get_8074v1 the 169 * sa_is_valid bit from rx_msdu_end TLV 170 * 171 * @ buf: pointer to the start of RX PKT TLV headers 172 * Return: sa_is_valid bit 173 */ 174 static uint8_t 175 hal_rx_msdu_end_sa_is_valid_get_8074v1(uint8_t *buf) 176 { 177 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 178 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 179 uint8_t sa_is_valid; 180 181 sa_is_valid = HAL_RX_MSDU_END_SA_IS_VALID_GET(msdu_end); 182 183 return sa_is_valid; 184 } 185 186 /** 187 * hal_rx_msdu_end_sa_idx_get_8074v1(): API to get_8074v1 the 188 * sa_idx from rx_msdu_end TLV 189 * 190 * @ buf: pointer to the start of RX PKT TLV headers 191 * Return: sa_idx (SA AST index) 192 */ 193 static uint16_t hal_rx_msdu_end_sa_idx_get_8074v1(uint8_t *buf) 194 { 195 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 196 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 197 uint16_t sa_idx; 198 199 sa_idx = HAL_RX_MSDU_END_SA_IDX_GET(msdu_end); 200 201 return sa_idx; 202 } 203 204 /** 205 * hal_rx_desc_is_first_msdu_8074v1() - Check if first msdu 206 * 207 * @hal_soc_hdl: hal_soc handle 208 * @hw_desc_addr: hardware descriptor address 209 * 210 * Return: 0 - success/ non-zero failure 211 */ 212 static uint32_t hal_rx_desc_is_first_msdu_8074v1(void *hw_desc_addr) 213 { 214 struct rx_pkt_tlvs *rx_tlvs = (struct rx_pkt_tlvs *)hw_desc_addr; 215 struct rx_msdu_end *msdu_end = &rx_tlvs->msdu_end_tlv.rx_msdu_end; 216 217 return HAL_RX_GET(msdu_end, RX_MSDU_END_5, FIRST_MSDU); 218 } 219 220 /** 221 * hal_rx_msdu_end_l3_hdr_padding_get_8074v1(): API to get_8074v1 the 222 * l3_header padding from rx_msdu_end TLV 223 * 224 * @ buf: pointer to the start of RX PKT TLV headers 225 * Return: number of l3 header padding bytes 226 */ 227 static uint32_t hal_rx_msdu_end_l3_hdr_padding_get_8074v1(uint8_t *buf) 228 { 229 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 230 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 231 uint32_t l3_header_padding; 232 233 l3_header_padding = HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(msdu_end); 234 235 return l3_header_padding; 236 } 237 238 /* 239 * @ hal_rx_encryption_info_valid_8074v1: Returns encryption type. 240 * 241 * @ buf: rx_tlv_hdr of the received packet 242 * @ Return: encryption type 243 */ 244 static uint32_t hal_rx_encryption_info_valid_8074v1(uint8_t *buf) 245 { 246 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 247 struct rx_mpdu_start *mpdu_start = 248 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 249 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 250 uint32_t encryption_info = HAL_RX_MPDU_ENCRYPTION_INFO_VALID(mpdu_info); 251 252 return encryption_info; 253 } 254 255 /* 256 * @ hal_rx_print_pn_8074v1: Prints the PN of rx packet. 257 * 258 * @ buf: rx_tlv_hdr of the received packet 259 * @ Return: void 260 */ 261 static void hal_rx_print_pn_8074v1(uint8_t *buf) 262 { 263 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 264 struct rx_mpdu_start *mpdu_start = 265 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 266 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 267 268 uint32_t pn_31_0 = HAL_RX_MPDU_PN_31_0_GET(mpdu_info); 269 uint32_t pn_63_32 = HAL_RX_MPDU_PN_63_32_GET(mpdu_info); 270 uint32_t pn_95_64 = HAL_RX_MPDU_PN_95_64_GET(mpdu_info); 271 uint32_t pn_127_96 = HAL_RX_MPDU_PN_127_96_GET(mpdu_info); 272 273 hal_debug("PN number pn_127_96 0x%x pn_95_64 0x%x pn_63_32 0x%x pn_31_0 0x%x ", 274 pn_127_96, pn_95_64, pn_63_32, pn_31_0); 275 } 276 277 /** 278 * hal_rx_msdu_end_first_msdu_get_8074v1: API to get first msdu status 279 * from rx_msdu_end TLV 280 * 281 * @ buf: pointer to the start of RX PKT TLV headers 282 * Return: first_msdu 283 */ 284 static uint8_t 285 hal_rx_msdu_end_first_msdu_get_8074v1(uint8_t *buf) 286 { 287 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 288 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 289 uint8_t first_msdu; 290 291 first_msdu = HAL_RX_MSDU_END_FIRST_MSDU_GET(msdu_end); 292 293 return first_msdu; 294 } 295 296 /** 297 * hal_rx_msdu_end_da_is_valid_get_8074v1: API to check if da is valid 298 * from rx_msdu_end TLV 299 * 300 * @ buf: pointer to the start of RX PKT TLV headers 301 * Return: da_is_valid 302 */ 303 static uint8_t hal_rx_msdu_end_da_is_valid_get_8074v1(uint8_t *buf) 304 { 305 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 306 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 307 uint8_t da_is_valid; 308 309 da_is_valid = HAL_RX_MSDU_END_DA_IS_VALID_GET(msdu_end); 310 311 return da_is_valid; 312 } 313 314 /** 315 * hal_rx_msdu_end_last_msdu_get_8074v1: API to get last msdu status 316 * from rx_msdu_end TLV 317 * 318 * @ buf: pointer to the start of RX PKT TLV headers 319 * Return: last_msdu 320 */ 321 static uint8_t hal_rx_msdu_end_last_msdu_get_8074v1(uint8_t *buf) 322 { 323 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 324 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 325 uint8_t last_msdu; 326 327 last_msdu = HAL_RX_MSDU_END_LAST_MSDU_GET(msdu_end); 328 329 return last_msdu; 330 } 331 332 /* 333 * hal_rx_get_mpdu_mac_ad4_valid_8074v1(): Retrieves if mpdu 4th addr is valid 334 * 335 * @nbuf: Network buffer 336 * Returns: value of mpdu 4th address valid field 337 */ 338 static bool hal_rx_get_mpdu_mac_ad4_valid_8074v1(uint8_t *buf) 339 { 340 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 341 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 342 bool ad4_valid = 0; 343 344 ad4_valid = HAL_RX_MPDU_GET_MAC_AD4_VALID(rx_mpdu_info); 345 346 return ad4_valid; 347 } 348 349 /** 350 * hal_rx_mpdu_start_sw_peer_id_get_8074v1: Retrieve sw peer_id 351 * @buf: network buffer 352 * 353 * Return: sw peer_id 354 */ 355 static uint32_t hal_rx_mpdu_start_sw_peer_id_get_8074v1(uint8_t *buf) 356 { 357 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 358 struct rx_mpdu_start *mpdu_start = 359 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 360 361 return HAL_RX_MPDU_INFO_SW_PEER_ID_GET( 362 &mpdu_start->rx_mpdu_info_details); 363 } 364 365 /* 366 * hal_rx_mpdu_get_to_ds_8074v1(): API to get the tods info 367 * from rx_mpdu_start 368 * 369 * @buf: pointer to the start of RX PKT TLV header 370 * Return: uint32_t(to_ds) 371 */ 372 373 static uint32_t hal_rx_mpdu_get_to_ds_8074v1(uint8_t *buf) 374 { 375 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 376 struct rx_mpdu_start *mpdu_start = 377 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 378 379 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 380 381 return HAL_RX_MPDU_GET_TODS(mpdu_info); 382 } 383 384 /* 385 * hal_rx_mpdu_get_fr_ds_8074v1(): API to get the from ds info 386 * from rx_mpdu_start 387 * 388 * @buf: pointer to the start of RX PKT TLV header 389 * Return: uint32_t(fr_ds) 390 */ 391 static uint32_t hal_rx_mpdu_get_fr_ds_8074v1(uint8_t *buf) 392 { 393 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 394 struct rx_mpdu_start *mpdu_start = 395 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 396 397 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 398 399 return HAL_RX_MPDU_GET_FROMDS(mpdu_info); 400 } 401 402 /* 403 * hal_rx_get_mpdu_frame_control_valid_8074v1(): Retrieves mpdu 404 * frame control valid 405 * 406 * @nbuf: Network buffer 407 * Returns: value of frame control valid field 408 */ 409 static uint8_t hal_rx_get_mpdu_frame_control_valid_8074v1(uint8_t *buf) 410 { 411 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 412 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 413 414 return HAL_RX_MPDU_GET_FRAME_CONTROL_VALID(rx_mpdu_info); 415 } 416 417 /** 418 * hal_rx_get_mpdu_frame_control_field_8074v1(): Function to 419 * retrieve frame control field 420 * 421 * @nbuf: Network buffer 422 * Returns: value of frame control field 423 * 424 */ 425 static uint16_t hal_rx_get_mpdu_frame_control_field_8074v1(uint8_t *buf) 426 { 427 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 428 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 429 uint16_t frame_ctrl = 0; 430 431 frame_ctrl = HAL_RX_MPDU_GET_FRAME_CONTROL_FIELD(rx_mpdu_info); 432 433 return frame_ctrl; 434 } 435 436 /* 437 * hal_rx_mpdu_get_addr1_8074v1(): API to check get address1 of the mpdu 438 * 439 * @buf: pointer to the start of RX PKT TLV headera 440 * @mac_addr: pointer to mac address 441 * Return: success/failure 442 */ 443 static QDF_STATUS hal_rx_mpdu_get_addr1_8074v1(uint8_t *buf, 444 uint8_t *mac_addr) 445 { 446 struct __attribute__((__packed__)) hal_addr1 { 447 uint32_t ad1_31_0; 448 uint16_t ad1_47_32; 449 }; 450 451 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 452 struct rx_mpdu_start *mpdu_start = 453 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 454 455 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 456 struct hal_addr1 *addr = (struct hal_addr1 *)mac_addr; 457 uint32_t mac_addr_ad1_valid; 458 459 mac_addr_ad1_valid = HAL_RX_MPDU_MAC_ADDR_AD1_VALID_GET(mpdu_info); 460 461 if (mac_addr_ad1_valid) { 462 addr->ad1_31_0 = HAL_RX_MPDU_AD1_31_0_GET(mpdu_info); 463 addr->ad1_47_32 = HAL_RX_MPDU_AD1_47_32_GET(mpdu_info); 464 return QDF_STATUS_SUCCESS; 465 } 466 467 return QDF_STATUS_E_FAILURE; 468 } 469 470 /* 471 * hal_rx_mpdu_get_addr2_8074v1(): API to check get address2 of the mpdu 472 * in the packet 473 * 474 * @buf: pointer to the start of RX PKT TLV header 475 * @mac_addr: pointer to mac address 476 * Return: success/failure 477 */ 478 static QDF_STATUS hal_rx_mpdu_get_addr2_8074v1(uint8_t *buf, uint8_t *mac_addr) 479 { 480 struct __attribute__((__packed__)) hal_addr2 { 481 uint16_t ad2_15_0; 482 uint32_t ad2_47_16; 483 }; 484 485 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 486 struct rx_mpdu_start *mpdu_start = 487 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 488 489 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 490 struct hal_addr2 *addr = (struct hal_addr2 *)mac_addr; 491 uint32_t mac_addr_ad2_valid; 492 493 mac_addr_ad2_valid = HAL_RX_MPDU_MAC_ADDR_AD2_VALID_GET(mpdu_info); 494 495 if (mac_addr_ad2_valid) { 496 addr->ad2_15_0 = HAL_RX_MPDU_AD2_15_0_GET(mpdu_info); 497 addr->ad2_47_16 = HAL_RX_MPDU_AD2_47_16_GET(mpdu_info); 498 return QDF_STATUS_SUCCESS; 499 } 500 501 return QDF_STATUS_E_FAILURE; 502 } 503 504 /* 505 * hal_rx_mpdu_get_addr3_8074v1(): API to get address3 of the mpdu 506 * in the packet 507 * 508 * @buf: pointer to the start of RX PKT TLV header 509 * @mac_addr: pointer to mac address 510 * Return: success/failure 511 */ 512 static QDF_STATUS hal_rx_mpdu_get_addr3_8074v1(uint8_t *buf, uint8_t *mac_addr) 513 { 514 struct __attribute__((__packed__)) hal_addr3 { 515 uint32_t ad3_31_0; 516 uint16_t ad3_47_32; 517 }; 518 519 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 520 struct rx_mpdu_start *mpdu_start = 521 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 522 523 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 524 struct hal_addr3 *addr = (struct hal_addr3 *)mac_addr; 525 uint32_t mac_addr_ad3_valid; 526 527 mac_addr_ad3_valid = HAL_RX_MPDU_MAC_ADDR_AD3_VALID_GET(mpdu_info); 528 529 if (mac_addr_ad3_valid) { 530 addr->ad3_31_0 = HAL_RX_MPDU_AD3_31_0_GET(mpdu_info); 531 addr->ad3_47_32 = HAL_RX_MPDU_AD3_47_32_GET(mpdu_info); 532 return QDF_STATUS_SUCCESS; 533 } 534 535 return QDF_STATUS_E_FAILURE; 536 } 537 538 /* 539 * hal_rx_mpdu_get_addr4_8074v1(): API to get address4 of the mpdu 540 * in the packet 541 * 542 * @buf: pointer to the start of RX PKT TLV header 543 * @mac_addr: pointer to mac address 544 * Return: success/failure 545 */ 546 static QDF_STATUS hal_rx_mpdu_get_addr4_8074v1(uint8_t *buf, uint8_t *mac_addr) 547 { 548 struct __attribute__((__packed__)) hal_addr4 { 549 uint32_t ad4_31_0; 550 uint16_t ad4_47_32; 551 }; 552 553 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 554 struct rx_mpdu_start *mpdu_start = 555 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 556 557 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 558 struct hal_addr4 *addr = (struct hal_addr4 *)mac_addr; 559 uint32_t mac_addr_ad4_valid; 560 561 mac_addr_ad4_valid = HAL_RX_MPDU_MAC_ADDR_AD4_VALID_GET(mpdu_info); 562 563 if (mac_addr_ad4_valid) { 564 addr->ad4_31_0 = HAL_RX_MPDU_AD4_31_0_GET(mpdu_info); 565 addr->ad4_47_32 = HAL_RX_MPDU_AD4_47_32_GET(mpdu_info); 566 return QDF_STATUS_SUCCESS; 567 } 568 569 return QDF_STATUS_E_FAILURE; 570 } 571 572 /* 573 * hal_rx_get_mpdu_sequence_control_valid_8074v1(): Get mpdu 574 * sequence control valid 575 * 576 * @nbuf: Network buffer 577 * Returns: value of sequence control valid field 578 */ 579 static uint8_t hal_rx_get_mpdu_sequence_control_valid_8074v1(uint8_t *buf) 580 { 581 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 582 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 583 584 return HAL_RX_MPDU_GET_SEQUENCE_CONTROL_VALID(rx_mpdu_info); 585 } 586 587 /** 588 * hal_rx_is_unicast_8074v1: check packet is unicast frame or not. 589 * 590 * @ buf: pointer to rx pkt TLV. 591 * 592 * Return: true on unicast. 593 */ 594 static bool hal_rx_is_unicast_8074v1(uint8_t *buf) 595 { 596 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 597 struct rx_mpdu_start *mpdu_start = 598 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 599 uint32_t grp_id; 600 uint8_t *rx_mpdu_info = (uint8_t *)&mpdu_start->rx_mpdu_info_details; 601 602 grp_id = (_HAL_MS((*_OFFSET_TO_WORD_PTR((rx_mpdu_info), 603 RX_MPDU_INFO_0_SW_FRAME_GROUP_ID_OFFSET)), 604 RX_MPDU_INFO_0_SW_FRAME_GROUP_ID_MASK, 605 RX_MPDU_INFO_0_SW_FRAME_GROUP_ID_LSB)); 606 607 return (HAL_MPDU_SW_FRAME_GROUP_UNICAST_DATA == grp_id) ? true : false; 608 } 609 610 /** 611 * hal_rx_tid_get_8074v1: get tid based on qos control valid. 612 * 613 * @ buf: pointer to rx pkt TLV. 614 * 615 * Return: tid 616 */ 617 static uint32_t hal_rx_tid_get_8074v1(hal_soc_handle_t hal_soc_hdl, 618 uint8_t *buf) 619 { 620 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 621 struct rx_mpdu_start *mpdu_start = 622 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 623 uint8_t *rx_mpdu_info = (uint8_t *)&mpdu_start->rx_mpdu_info_details; 624 uint8_t qos_control_valid = 625 (_HAL_MS((*_OFFSET_TO_WORD_PTR((rx_mpdu_info), 626 RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_OFFSET)), 627 RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_MASK, 628 RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_LSB)); 629 630 if (qos_control_valid) 631 return hal_rx_mpdu_start_tid_get_8074(buf); 632 633 return HAL_RX_NON_QOS_TID; 634 } 635 636 /** 637 * hal_rx_hw_desc_get_ppduid_get_8074v1(): retrieve ppdu id 638 * @rx_tlv_hdr: Rx tlv header 639 * @rxdma_dst_ring_desc: Rx HW descriptor 640 * 641 * Return: ppdu id 642 */ 643 static uint32_t hal_rx_hw_desc_get_ppduid_get_8074v1(void *rx_tlv_hdr, 644 void *rxdma_dst_ring_desc) 645 { 646 struct rx_mpdu_info *rx_mpdu_info; 647 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)rx_tlv_hdr; 648 649 rx_mpdu_info = 650 &rx_desc->mpdu_start_tlv.rx_mpdu_start.rx_mpdu_info_details; 651 652 return HAL_RX_GET(rx_mpdu_info, RX_MPDU_INFO_0, PHY_PPDU_ID); 653 } 654 655 /** 656 * hal_reo_status_get_header_8074v1 - Process reo desc info 657 * @ring_desc: REO status ring descriptor 658 * @b - tlv type info 659 * @h1 - Pointer to hal_reo_status_header where info to be stored 660 * 661 * Return - none. 662 * 663 */ 664 static void hal_reo_status_get_header_8074v1(hal_ring_desc_t ring_desc, int b, 665 void *h1) 666 { 667 uint32_t *d = (uint32_t *)ring_desc; 668 uint32_t val1 = 0; 669 struct hal_reo_status_header *h = 670 (struct hal_reo_status_header *)h1; 671 672 /* Offsets of descriptor fields defined in HW headers start 673 * from the field after TLV header 674 */ 675 d += HAL_GET_NUM_DWORDS(sizeof(struct tlv_32_hdr)); 676 677 switch (b) { 678 case HAL_REO_QUEUE_STATS_STATUS_TLV: 679 val1 = d[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_0, 680 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 681 break; 682 case HAL_REO_FLUSH_QUEUE_STATUS_TLV: 683 val1 = d[HAL_OFFSET_DW(REO_FLUSH_QUEUE_STATUS_0, 684 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 685 break; 686 case HAL_REO_FLUSH_CACHE_STATUS_TLV: 687 val1 = d[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_0, 688 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 689 break; 690 case HAL_REO_UNBLK_CACHE_STATUS_TLV: 691 val1 = d[HAL_OFFSET_DW(REO_UNBLOCK_CACHE_STATUS_0, 692 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 693 break; 694 case HAL_REO_TIMOUT_LIST_STATUS_TLV: 695 val1 = d[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_0, 696 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 697 break; 698 case HAL_REO_DESC_THRES_STATUS_TLV: 699 val1 = 700 d[HAL_OFFSET_DW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0, 701 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 702 break; 703 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: 704 val1 = d[HAL_OFFSET_DW(REO_UPDATE_RX_REO_QUEUE_STATUS_0, 705 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 706 break; 707 default: 708 qdf_nofl_err("ERROR: Unknown tlv\n"); 709 break; 710 } 711 h->cmd_num = 712 HAL_GET_FIELD( 713 UNIFORM_REO_STATUS_HEADER_0, REO_STATUS_NUMBER, 714 val1); 715 h->exec_time = 716 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_0, 717 CMD_EXECUTION_TIME, val1); 718 h->status = 719 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_0, 720 REO_CMD_EXECUTION_STATUS, val1); 721 switch (b) { 722 case HAL_REO_QUEUE_STATS_STATUS_TLV: 723 val1 = d[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_1, 724 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 725 break; 726 case HAL_REO_FLUSH_QUEUE_STATUS_TLV: 727 val1 = d[HAL_OFFSET_DW(REO_FLUSH_QUEUE_STATUS_1, 728 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 729 break; 730 case HAL_REO_FLUSH_CACHE_STATUS_TLV: 731 val1 = d[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_1, 732 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 733 break; 734 case HAL_REO_UNBLK_CACHE_STATUS_TLV: 735 val1 = d[HAL_OFFSET_DW(REO_UNBLOCK_CACHE_STATUS_1, 736 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 737 break; 738 case HAL_REO_TIMOUT_LIST_STATUS_TLV: 739 val1 = d[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_1, 740 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 741 break; 742 case HAL_REO_DESC_THRES_STATUS_TLV: 743 val1 = 744 d[HAL_OFFSET_DW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_1, 745 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 746 break; 747 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: 748 val1 = d[HAL_OFFSET_DW(REO_UPDATE_RX_REO_QUEUE_STATUS_1, 749 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 750 break; 751 default: 752 qdf_nofl_err("ERROR: Unknown tlv\n"); 753 break; 754 } 755 h->tstamp = 756 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_1, TIMESTAMP, val1); 757 } 758 759 /** 760 * hal_rx_mpdu_start_mpdu_qos_control_valid_get_8074v1(): 761 * Retrieve qos control valid bit from the tlv. 762 * @buf: pointer to rx pkt TLV. 763 * 764 * Return: qos control value. 765 */ 766 static inline uint32_t 767 hal_rx_mpdu_start_mpdu_qos_control_valid_get_8074v1(uint8_t *buf) 768 { 769 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 770 struct rx_mpdu_start *mpdu_start = 771 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 772 773 return HAL_RX_MPDU_INFO_QOS_CONTROL_VALID_GET( 774 &mpdu_start->rx_mpdu_info_details); 775 } 776 777 /** 778 * hal_rx_msdu_end_sa_sw_peer_id_get_8074v1(): API to get the 779 * sa_sw_peer_id from rx_msdu_end TLV 780 * @buf: pointer to the start of RX PKT TLV headers 781 * 782 * Return: sa_sw_peer_id index 783 */ 784 static inline uint32_t 785 hal_rx_msdu_end_sa_sw_peer_id_get_8074v1(uint8_t *buf) 786 { 787 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 788 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 789 790 return HAL_RX_MSDU_END_SA_SW_PEER_ID_GET(msdu_end); 791 } 792 793 /** 794 * hal_tx_desc_set_mesh_en_8074v1 - Set mesh_enable flag in Tx descriptor 795 * @desc: Handle to Tx Descriptor 796 * @en: For raw WiFi frames, this indicates transmission to a mesh STA, 797 * enabling the interpretation of the 'Mesh Control Present' bit 798 * (bit 8) of QoS Control (otherwise this bit is ignored), 799 * For native WiFi frames, this indicates that a 'Mesh Control' field 800 * is present between the header and the LLC. 801 * 802 * Return: void 803 */ 804 static inline 805 void hal_tx_desc_set_mesh_en_8074v1(void *desc, uint8_t en) 806 { 807 HAL_SET_FLD(desc, TCL_DATA_CMD_4, MESH_ENABLE) |= 808 HAL_TX_SM(TCL_DATA_CMD_4, MESH_ENABLE, en); 809 } 810 811 static 812 void *hal_rx_msdu0_buffer_addr_lsb_8074v1(void *link_desc_va) 813 { 814 return (void *)HAL_RX_MSDU0_BUFFER_ADDR_LSB(link_desc_va); 815 } 816 817 static 818 void *hal_rx_msdu_desc_info_ptr_get_8074v1(void *msdu0) 819 { 820 return (void *)HAL_RX_MSDU_DESC_INFO_PTR_GET(msdu0); 821 } 822 823 static 824 void *hal_ent_mpdu_desc_info_8074v1(void *ent_ring_desc) 825 { 826 return (void *)HAL_ENT_MPDU_DESC_INFO(ent_ring_desc); 827 } 828 829 static 830 void *hal_dst_mpdu_desc_info_8074v1(void *dst_ring_desc) 831 { 832 return (void *)HAL_DST_MPDU_DESC_INFO(dst_ring_desc); 833 } 834 835 static 836 uint8_t hal_rx_get_fc_valid_8074v1(uint8_t *buf) 837 { 838 return HAL_RX_GET_FC_VALID(buf); 839 } 840 841 static uint8_t hal_rx_get_to_ds_flag_8074v1(uint8_t *buf) 842 { 843 return HAL_RX_GET_TO_DS_FLAG(buf); 844 } 845 846 static uint8_t hal_rx_get_mac_addr2_valid_8074v1(uint8_t *buf) 847 { 848 return HAL_RX_GET_MAC_ADDR2_VALID(buf); 849 } 850 851 static uint8_t hal_rx_get_filter_category_8074v1(uint8_t *buf) 852 { 853 return HAL_RX_GET_FILTER_CATEGORY(buf); 854 } 855 856 static uint32_t 857 hal_rx_get_ppdu_id_8074v1(uint8_t *buf) 858 { 859 struct rx_mpdu_info *rx_mpdu_info; 860 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)buf; 861 862 rx_mpdu_info = 863 &rx_desc->mpdu_start_tlv.rx_mpdu_start.rx_mpdu_info_details; 864 865 return HAL_RX_GET_PPDU_ID(rx_mpdu_info); 866 } 867 868 /** 869 * hal_reo_config_8074v1(): Set reo config parameters 870 * @soc: hal soc handle 871 * @reg_val: value to be set 872 * @reo_params: reo parameters 873 * 874 * Return: void 875 */ 876 static void 877 hal_reo_config_8074v1(struct hal_soc *soc, 878 uint32_t reg_val, 879 struct hal_reo_params *reo_params) 880 { 881 HAL_REO_R0_CONFIG(soc, reg_val, reo_params); 882 } 883 884 /** 885 * hal_rx_msdu_desc_info_get_ptr_8074v1() - Get msdu desc info ptr 886 * @msdu_details_ptr - Pointer to msdu_details_ptr 887 * 888 * Return - Pointer to rx_msdu_desc_info structure. 889 * 890 */ 891 static void *hal_rx_msdu_desc_info_get_ptr_8074v1(void *msdu_details_ptr) 892 { 893 return HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr); 894 } 895 896 /** 897 * hal_rx_link_desc_msdu0_ptr_8074v1 - Get pointer to rx_msdu details 898 * @link_desc - Pointer to link desc 899 * 900 * Return - Pointer to rx_msdu_details structure 901 * 902 */ 903 static void *hal_rx_link_desc_msdu0_ptr_8074v1(void *link_desc) 904 { 905 return HAL_RX_LINK_DESC_MSDU0_PTR(link_desc); 906 } 907 908 /** 909 * hal_rx_msdu_flow_idx_get_8074v1: API to get flow index 910 * from rx_msdu_end TLV 911 * @buf: pointer to the start of RX PKT TLV headers 912 * 913 * Return: flow index value from MSDU END TLV 914 */ 915 static inline uint32_t hal_rx_msdu_flow_idx_get_8074v1(uint8_t *buf) 916 { 917 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 918 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 919 920 return HAL_RX_MSDU_END_FLOW_IDX_GET(msdu_end); 921 } 922 923 /** 924 * hal_rx_msdu_flow_idx_invalid_8074v1: API to get flow index invalid 925 * from rx_msdu_end TLV 926 * @buf: pointer to the start of RX PKT TLV headers 927 * 928 * Return: flow index invalid value from MSDU END TLV 929 */ 930 static bool hal_rx_msdu_flow_idx_invalid_8074v1(uint8_t *buf) 931 { 932 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 933 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 934 935 return HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(msdu_end); 936 } 937 938 /** 939 * hal_rx_msdu_flow_idx_timeout_8074v1: API to get flow index timeout 940 * from rx_msdu_end TLV 941 * @buf: pointer to the start of RX PKT TLV headers 942 * 943 * Return: flow index timeout value from MSDU END TLV 944 */ 945 static bool hal_rx_msdu_flow_idx_timeout_8074v1(uint8_t *buf) 946 { 947 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 948 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 949 950 return HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(msdu_end); 951 } 952 953 /** 954 * hal_rx_msdu_fse_metadata_get_8074v1: API to get FSE metadata 955 * from rx_msdu_end TLV 956 * @buf: pointer to the start of RX PKT TLV headers 957 * 958 * Return: fse metadata value from MSDU END TLV 959 */ 960 static uint32_t hal_rx_msdu_fse_metadata_get_8074v1(uint8_t *buf) 961 { 962 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 963 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 964 965 return HAL_RX_MSDU_END_FSE_METADATA_GET(msdu_end); 966 } 967 968 /** 969 * hal_rx_msdu_cce_metadata_get_8074v1: API to get CCE metadata 970 * from rx_msdu_end TLV 971 * @buf: pointer to the start of RX PKT TLV headers 972 * 973 * Return: cce_metadata 974 */ 975 static uint16_t 976 hal_rx_msdu_cce_metadata_get_8074v1(uint8_t *buf) 977 { 978 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 979 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 980 981 return HAL_RX_MSDU_END_CCE_METADATA_GET(msdu_end); 982 } 983 984 /** 985 * hal_rx_msdu_get_flow_params_8074v1: API to get flow index, flow index invalid 986 * and flow index timeout from rx_msdu_end TLV 987 * @buf: pointer to the start of RX PKT TLV headers 988 * @flow_invalid: pointer to return value of flow_idx_valid 989 * @flow_timeout: pointer to return value of flow_idx_timeout 990 * @flow_index: pointer to return value of flow_idx 991 * 992 * Return: none 993 */ 994 static inline void 995 hal_rx_msdu_get_flow_params_8074v1(uint8_t *buf, 996 bool *flow_invalid, 997 bool *flow_timeout, 998 uint32_t *flow_index) 999 { 1000 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1001 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1002 1003 *flow_invalid = HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(msdu_end); 1004 *flow_timeout = HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(msdu_end); 1005 *flow_index = HAL_RX_MSDU_END_FLOW_IDX_GET(msdu_end); 1006 } 1007 1008 /** 1009 * hal_rx_tlv_get_tcp_chksum_8074v1() - API to get tcp checksum 1010 * @buf: rx_tlv_hdr 1011 * 1012 * Return: tcp checksum 1013 */ 1014 static uint16_t 1015 hal_rx_tlv_get_tcp_chksum_8074v1(uint8_t *buf) 1016 { 1017 return HAL_RX_TLV_GET_TCP_CHKSUM(buf); 1018 } 1019 1020 /** 1021 * hal_rx_get_rx_sequence_8074v1(): Function to retrieve rx sequence number 1022 * 1023 * @nbuf: Network buffer 1024 * Returns: rx sequence number 1025 */ 1026 static 1027 uint16_t hal_rx_get_rx_sequence_8074v1(uint8_t *buf) 1028 { 1029 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 1030 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 1031 1032 return HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info); 1033 } 1034 1035 /** 1036 * hal_rx_mpdu_start_tlv_tag_valid_8074v1 () - API to check if RX_MPDU_START 1037 * tlv tag is valid 1038 * 1039 * @rx_tlv_hdr: start address of rx_pkt_tlvs 1040 * 1041 * Return: true if RX_MPDU_START is valied, else false. 1042 */ 1043 uint8_t hal_rx_mpdu_start_tlv_tag_valid_8074v1(void *rx_tlv_hdr) 1044 { 1045 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)rx_tlv_hdr; 1046 uint32_t tlv_tag; 1047 1048 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE( 1049 &rx_desc->mpdu_start_tlv); 1050 1051 return tlv_tag == WIFIRX_MPDU_START_E ? true : false; 1052 } 1053 1054 /** 1055 * hal_rx_flow_setup_fse_8074v1() - Setup a flow search entry in HW FST 1056 * @fst: Pointer to the Rx Flow Search Table 1057 * @table_offset: offset into the table where the flow is to be setup 1058 * @flow: Flow Parameters 1059 * 1060 * Return: Success/Failure 1061 */ 1062 static void * 1063 hal_rx_flow_setup_fse_8074v1(uint8_t *rx_fst, uint32_t table_offset, 1064 uint8_t *rx_flow) 1065 { 1066 struct hal_rx_fst *fst = (struct hal_rx_fst *)rx_fst; 1067 struct hal_rx_flow *flow = (struct hal_rx_flow *)rx_flow; 1068 uint8_t *fse; 1069 bool fse_valid; 1070 1071 if (table_offset >= fst->max_entries) { 1072 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR, 1073 "HAL FSE table offset %u exceeds max entries %u", 1074 table_offset, fst->max_entries); 1075 return NULL; 1076 } 1077 1078 fse = (uint8_t *)fst->base_vaddr + 1079 (table_offset * HAL_RX_FST_ENTRY_SIZE); 1080 1081 fse_valid = HAL_GET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, VALID); 1082 1083 if (fse_valid) { 1084 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_DEBUG, 1085 "HAL FSE %pK already valid", fse); 1086 return NULL; 1087 } 1088 1089 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_0, SRC_IP_127_96) = 1090 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_0, SRC_IP_127_96, 1091 qdf_htonl(flow->tuple_info.src_ip_127_96)); 1092 1093 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_1, SRC_IP_95_64) = 1094 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_1, SRC_IP_95_64, 1095 qdf_htonl(flow->tuple_info.src_ip_95_64)); 1096 1097 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_2, SRC_IP_63_32) = 1098 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_2, SRC_IP_63_32, 1099 qdf_htonl(flow->tuple_info.src_ip_63_32)); 1100 1101 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_3, SRC_IP_31_0) = 1102 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_3, SRC_IP_31_0, 1103 qdf_htonl(flow->tuple_info.src_ip_31_0)); 1104 1105 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_4, DEST_IP_127_96) = 1106 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_4, DEST_IP_127_96, 1107 qdf_htonl(flow->tuple_info.dest_ip_127_96)); 1108 1109 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_5, DEST_IP_95_64) = 1110 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_5, DEST_IP_95_64, 1111 qdf_htonl(flow->tuple_info.dest_ip_95_64)); 1112 1113 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_6, DEST_IP_63_32) = 1114 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_6, DEST_IP_63_32, 1115 qdf_htonl(flow->tuple_info.dest_ip_63_32)); 1116 1117 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_7, DEST_IP_31_0) = 1118 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_7, DEST_IP_31_0, 1119 qdf_htonl(flow->tuple_info.dest_ip_31_0)); 1120 1121 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, DEST_PORT); 1122 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, DEST_PORT) |= 1123 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_8, DEST_PORT, 1124 (flow->tuple_info.dest_port)); 1125 1126 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, SRC_PORT); 1127 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, SRC_PORT) |= 1128 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_8, SRC_PORT, 1129 (flow->tuple_info.src_port)); 1130 1131 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, L4_PROTOCOL); 1132 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, L4_PROTOCOL) |= 1133 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, L4_PROTOCOL, 1134 flow->tuple_info.l4_protocol); 1135 1136 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_HANDLER); 1137 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_HANDLER) |= 1138 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_HANDLER, 1139 flow->reo_destination_handler); 1140 1141 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, VALID); 1142 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, VALID) |= 1143 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, VALID, 1); 1144 1145 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_10, METADATA); 1146 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_10, METADATA) = 1147 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_10, METADATA, 1148 flow->fse_metadata); 1149 1150 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_11, REO_DESTINATION_INDICATION); 1151 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_11, REO_DESTINATION_INDICATION) |= 1152 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_11, 1153 REO_DESTINATION_INDICATION, 1154 flow->reo_destination_indication); 1155 1156 /* Reset all the other fields in FSE */ 1157 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, RESERVED_9); 1158 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_11, MSDU_DROP); 1159 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_11, RESERVED_11); 1160 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_11, MSDU_COUNT); 1161 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_12, MSDU_BYTE_COUNT); 1162 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_13, TIMESTAMP); 1163 1164 return fse; 1165 } 1166 1167 static 1168 void hal_compute_reo_remap_ix2_ix3_8074v1(uint32_t *ring, uint32_t num_rings, 1169 uint32_t *remap1, uint32_t *remap2) 1170 { 1171 switch (num_rings) { 1172 case 1: 1173 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 1174 HAL_REO_REMAP_IX2(ring[0], 17) | 1175 HAL_REO_REMAP_IX2(ring[0], 18) | 1176 HAL_REO_REMAP_IX2(ring[0], 19) | 1177 HAL_REO_REMAP_IX2(ring[0], 20) | 1178 HAL_REO_REMAP_IX2(ring[0], 21) | 1179 HAL_REO_REMAP_IX2(ring[0], 22) | 1180 HAL_REO_REMAP_IX2(ring[0], 23); 1181 1182 *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) | 1183 HAL_REO_REMAP_IX3(ring[0], 25) | 1184 HAL_REO_REMAP_IX3(ring[0], 26) | 1185 HAL_REO_REMAP_IX3(ring[0], 27) | 1186 HAL_REO_REMAP_IX3(ring[0], 28) | 1187 HAL_REO_REMAP_IX3(ring[0], 29) | 1188 HAL_REO_REMAP_IX3(ring[0], 30) | 1189 HAL_REO_REMAP_IX3(ring[0], 31); 1190 break; 1191 case 2: 1192 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 1193 HAL_REO_REMAP_IX2(ring[0], 17) | 1194 HAL_REO_REMAP_IX2(ring[1], 18) | 1195 HAL_REO_REMAP_IX2(ring[1], 19) | 1196 HAL_REO_REMAP_IX2(ring[0], 20) | 1197 HAL_REO_REMAP_IX2(ring[0], 21) | 1198 HAL_REO_REMAP_IX2(ring[1], 22) | 1199 HAL_REO_REMAP_IX2(ring[1], 23); 1200 1201 *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) | 1202 HAL_REO_REMAP_IX3(ring[0], 25) | 1203 HAL_REO_REMAP_IX3(ring[1], 26) | 1204 HAL_REO_REMAP_IX3(ring[1], 27) | 1205 HAL_REO_REMAP_IX3(ring[0], 28) | 1206 HAL_REO_REMAP_IX3(ring[0], 29) | 1207 HAL_REO_REMAP_IX3(ring[1], 30) | 1208 HAL_REO_REMAP_IX3(ring[1], 31); 1209 break; 1210 case 3: 1211 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 1212 HAL_REO_REMAP_IX2(ring[1], 17) | 1213 HAL_REO_REMAP_IX2(ring[2], 18) | 1214 HAL_REO_REMAP_IX2(ring[0], 19) | 1215 HAL_REO_REMAP_IX2(ring[1], 20) | 1216 HAL_REO_REMAP_IX2(ring[2], 21) | 1217 HAL_REO_REMAP_IX2(ring[0], 22) | 1218 HAL_REO_REMAP_IX2(ring[1], 23); 1219 1220 *remap2 = HAL_REO_REMAP_IX3(ring[2], 24) | 1221 HAL_REO_REMAP_IX3(ring[0], 25) | 1222 HAL_REO_REMAP_IX3(ring[1], 26) | 1223 HAL_REO_REMAP_IX3(ring[2], 27) | 1224 HAL_REO_REMAP_IX3(ring[0], 28) | 1225 HAL_REO_REMAP_IX3(ring[1], 29) | 1226 HAL_REO_REMAP_IX3(ring[2], 30) | 1227 HAL_REO_REMAP_IX3(ring[0], 31); 1228 break; 1229 case 4: 1230 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 1231 HAL_REO_REMAP_IX2(ring[1], 17) | 1232 HAL_REO_REMAP_IX2(ring[2], 18) | 1233 HAL_REO_REMAP_IX2(ring[3], 19) | 1234 HAL_REO_REMAP_IX2(ring[0], 20) | 1235 HAL_REO_REMAP_IX2(ring[1], 21) | 1236 HAL_REO_REMAP_IX2(ring[2], 22) | 1237 HAL_REO_REMAP_IX2(ring[3], 23); 1238 1239 *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) | 1240 HAL_REO_REMAP_IX3(ring[1], 25) | 1241 HAL_REO_REMAP_IX3(ring[2], 26) | 1242 HAL_REO_REMAP_IX3(ring[3], 27) | 1243 HAL_REO_REMAP_IX3(ring[0], 28) | 1244 HAL_REO_REMAP_IX3(ring[1], 29) | 1245 HAL_REO_REMAP_IX3(ring[2], 30) | 1246 HAL_REO_REMAP_IX3(ring[3], 31); 1247 break; 1248 } 1249 } 1250 1251 static void hal_hw_txrx_ops_attach_qca8074(struct hal_soc *hal_soc) 1252 { 1253 1254 /* init and setup */ 1255 hal_soc->ops->hal_srng_dst_hw_init = hal_srng_dst_hw_init_generic; 1256 hal_soc->ops->hal_srng_src_hw_init = hal_srng_src_hw_init_generic; 1257 hal_soc->ops->hal_get_hw_hptp = hal_get_hw_hptp_generic; 1258 hal_soc->ops->hal_reo_setup = hal_reo_setup_generic_li; 1259 hal_soc->ops->hal_get_window_address = hal_get_window_address_8074; 1260 1261 /* tx */ 1262 hal_soc->ops->hal_tx_desc_set_dscp_tid_table_id = 1263 hal_tx_desc_set_dscp_tid_table_id_8074; 1264 hal_soc->ops->hal_tx_set_dscp_tid_map = hal_tx_set_dscp_tid_map_8074; 1265 hal_soc->ops->hal_tx_update_dscp_tid = hal_tx_update_dscp_tid_8074; 1266 hal_soc->ops->hal_tx_desc_set_lmac_id = hal_tx_desc_set_lmac_id_8074; 1267 hal_soc->ops->hal_tx_desc_set_buf_addr = 1268 hal_tx_desc_set_buf_addr_generic_li; 1269 hal_soc->ops->hal_tx_desc_set_search_type = 1270 hal_tx_desc_set_search_type_generic_li; 1271 hal_soc->ops->hal_tx_desc_set_search_index = 1272 hal_tx_desc_set_search_index_generic_li; 1273 hal_soc->ops->hal_tx_desc_set_cache_set_num = 1274 hal_tx_desc_set_cache_set_num_generic_li; 1275 hal_soc->ops->hal_tx_comp_get_status = 1276 hal_tx_comp_get_status_generic_li; 1277 hal_soc->ops->hal_tx_comp_get_release_reason = 1278 hal_tx_comp_get_release_reason_generic_li; 1279 hal_soc->ops->hal_get_wbm_internal_error = 1280 hal_get_wbm_internal_error_generic_li; 1281 hal_soc->ops->hal_tx_desc_set_mesh_en = hal_tx_desc_set_mesh_en_8074v1; 1282 hal_soc->ops->hal_tx_init_cmd_credit_ring = 1283 hal_tx_init_cmd_credit_ring_8074v1; 1284 1285 /* rx */ 1286 hal_soc->ops->hal_rx_msdu_start_nss_get = 1287 hal_rx_msdu_start_nss_get_8074; 1288 hal_soc->ops->hal_rx_mon_hw_desc_get_mpdu_status = 1289 hal_rx_mon_hw_desc_get_mpdu_status_8074; 1290 hal_soc->ops->hal_rx_get_tlv = hal_rx_get_tlv_8074; 1291 hal_soc->ops->hal_rx_proc_phyrx_other_receive_info_tlv = 1292 hal_rx_proc_phyrx_other_receive_info_tlv_8074; 1293 hal_soc->ops->hal_rx_dump_msdu_start_tlv = 1294 hal_rx_dump_msdu_start_tlv_8074; 1295 hal_soc->ops->hal_rx_dump_msdu_end_tlv = hal_rx_dump_msdu_end_tlv_8074; 1296 hal_soc->ops->hal_get_link_desc_size = hal_get_link_desc_size_8074; 1297 hal_soc->ops->hal_rx_mpdu_start_tid_get = 1298 hal_rx_mpdu_start_tid_get_8074; 1299 hal_soc->ops->hal_rx_msdu_start_reception_type_get = 1300 hal_rx_msdu_start_reception_type_get_8074; 1301 hal_soc->ops->hal_rx_msdu_end_da_idx_get = 1302 hal_rx_msdu_end_da_idx_get_8074; 1303 hal_soc->ops->hal_rx_msdu_desc_info_get_ptr = 1304 hal_rx_msdu_desc_info_get_ptr_8074v1; 1305 hal_soc->ops->hal_rx_link_desc_msdu0_ptr = 1306 hal_rx_link_desc_msdu0_ptr_8074v1; 1307 hal_soc->ops->hal_reo_status_get_header = 1308 hal_reo_status_get_header_8074v1; 1309 hal_soc->ops->hal_rx_status_get_tlv_info = 1310 hal_rx_status_get_tlv_info_generic_li; 1311 hal_soc->ops->hal_rx_wbm_err_info_get = 1312 hal_rx_wbm_err_info_get_generic_li; 1313 hal_soc->ops->hal_rx_dump_mpdu_start_tlv = 1314 hal_rx_dump_mpdu_start_tlv_generic_li; 1315 1316 hal_soc->ops->hal_tx_set_pcp_tid_map = 1317 hal_tx_set_pcp_tid_map_generic_li; 1318 hal_soc->ops->hal_tx_update_pcp_tid_map = 1319 hal_tx_update_pcp_tid_generic_li; 1320 hal_soc->ops->hal_tx_set_tidmap_prty = 1321 hal_tx_update_tidmap_prty_generic_li; 1322 hal_soc->ops->hal_rx_get_rx_fragment_number = 1323 hal_rx_get_rx_fragment_number_8074v1; 1324 hal_soc->ops->hal_rx_msdu_end_da_is_mcbc_get = 1325 hal_rx_msdu_end_da_is_mcbc_get_8074v1; 1326 hal_soc->ops->hal_rx_msdu_end_sa_is_valid_get = 1327 hal_rx_msdu_end_sa_is_valid_get_8074v1; 1328 hal_soc->ops->hal_rx_msdu_end_sa_idx_get = 1329 hal_rx_msdu_end_sa_idx_get_8074v1; 1330 hal_soc->ops->hal_rx_desc_is_first_msdu = 1331 hal_rx_desc_is_first_msdu_8074v1; 1332 hal_soc->ops->hal_rx_msdu_end_l3_hdr_padding_get = 1333 hal_rx_msdu_end_l3_hdr_padding_get_8074v1; 1334 hal_soc->ops->hal_rx_encryption_info_valid = 1335 hal_rx_encryption_info_valid_8074v1; 1336 hal_soc->ops->hal_rx_print_pn = hal_rx_print_pn_8074v1; 1337 hal_soc->ops->hal_rx_msdu_end_first_msdu_get = 1338 hal_rx_msdu_end_first_msdu_get_8074v1; 1339 hal_soc->ops->hal_rx_msdu_end_da_is_valid_get = 1340 hal_rx_msdu_end_da_is_valid_get_8074v1; 1341 hal_soc->ops->hal_rx_msdu_end_last_msdu_get = 1342 hal_rx_msdu_end_last_msdu_get_8074v1; 1343 hal_soc->ops->hal_rx_get_mpdu_mac_ad4_valid = 1344 hal_rx_get_mpdu_mac_ad4_valid_8074v1; 1345 hal_soc->ops->hal_rx_mpdu_start_sw_peer_id_get = 1346 hal_rx_mpdu_start_sw_peer_id_get_8074v1; 1347 hal_soc->ops->hal_rx_tlv_peer_meta_data_get = 1348 hal_rx_mpdu_peer_meta_data_get_li; 1349 hal_soc->ops->hal_rx_mpdu_get_to_ds = hal_rx_mpdu_get_to_ds_8074v1; 1350 hal_soc->ops->hal_rx_mpdu_get_fr_ds = hal_rx_mpdu_get_fr_ds_8074v1; 1351 hal_soc->ops->hal_rx_get_mpdu_frame_control_valid = 1352 hal_rx_get_mpdu_frame_control_valid_8074v1; 1353 hal_soc->ops->hal_rx_get_frame_ctrl_field = 1354 hal_rx_get_mpdu_frame_control_field_8074v1; 1355 hal_soc->ops->hal_rx_mpdu_get_addr1 = hal_rx_mpdu_get_addr1_8074v1; 1356 hal_soc->ops->hal_rx_mpdu_get_addr2 = hal_rx_mpdu_get_addr2_8074v1; 1357 hal_soc->ops->hal_rx_mpdu_get_addr3 = hal_rx_mpdu_get_addr3_8074v1; 1358 hal_soc->ops->hal_rx_mpdu_get_addr4 = hal_rx_mpdu_get_addr4_8074v1; 1359 hal_soc->ops->hal_rx_get_mpdu_sequence_control_valid = 1360 hal_rx_get_mpdu_sequence_control_valid_8074v1; 1361 hal_soc->ops->hal_rx_is_unicast = hal_rx_is_unicast_8074v1; 1362 hal_soc->ops->hal_rx_tid_get = hal_rx_tid_get_8074v1; 1363 hal_soc->ops->hal_rx_hw_desc_get_ppduid_get = 1364 hal_rx_hw_desc_get_ppduid_get_8074v1; 1365 hal_soc->ops->hal_rx_mpdu_start_mpdu_qos_control_valid_get = 1366 hal_rx_mpdu_start_mpdu_qos_control_valid_get_8074v1; 1367 hal_soc->ops->hal_rx_msdu_end_sa_sw_peer_id_get = 1368 hal_rx_msdu_end_sa_sw_peer_id_get_8074v1; 1369 hal_soc->ops->hal_rx_msdu0_buffer_addr_lsb = 1370 hal_rx_msdu0_buffer_addr_lsb_8074v1; 1371 hal_soc->ops->hal_rx_msdu_desc_info_ptr_get = 1372 hal_rx_msdu_desc_info_ptr_get_8074v1; 1373 hal_soc->ops->hal_ent_mpdu_desc_info = hal_ent_mpdu_desc_info_8074v1; 1374 hal_soc->ops->hal_dst_mpdu_desc_info = hal_dst_mpdu_desc_info_8074v1; 1375 hal_soc->ops->hal_rx_get_fc_valid = hal_rx_get_fc_valid_8074v1; 1376 hal_soc->ops->hal_rx_get_to_ds_flag = hal_rx_get_to_ds_flag_8074v1; 1377 hal_soc->ops->hal_rx_get_mac_addr2_valid = 1378 hal_rx_get_mac_addr2_valid_8074v1; 1379 hal_soc->ops->hal_rx_get_filter_category = 1380 hal_rx_get_filter_category_8074v1; 1381 hal_soc->ops->hal_rx_get_ppdu_id = hal_rx_get_ppdu_id_8074v1; 1382 hal_soc->ops->hal_reo_config = hal_reo_config_8074v1; 1383 hal_soc->ops->hal_rx_msdu_flow_idx_get = 1384 hal_rx_msdu_flow_idx_get_8074v1; 1385 hal_soc->ops->hal_rx_msdu_flow_idx_invalid = 1386 hal_rx_msdu_flow_idx_invalid_8074v1; 1387 hal_soc->ops->hal_rx_msdu_flow_idx_timeout = 1388 hal_rx_msdu_flow_idx_timeout_8074v1; 1389 hal_soc->ops->hal_rx_msdu_fse_metadata_get = 1390 hal_rx_msdu_fse_metadata_get_8074v1; 1391 hal_soc->ops->hal_rx_msdu_cce_match_get = 1392 hal_rx_msdu_cce_match_get_li; 1393 hal_soc->ops->hal_rx_msdu_cce_metadata_get = 1394 hal_rx_msdu_cce_metadata_get_8074v1; 1395 hal_soc->ops->hal_rx_msdu_get_flow_params = 1396 hal_rx_msdu_get_flow_params_8074v1; 1397 hal_soc->ops->hal_rx_tlv_get_tcp_chksum = 1398 hal_rx_tlv_get_tcp_chksum_8074v1; 1399 hal_soc->ops->hal_rx_get_rx_sequence = hal_rx_get_rx_sequence_8074v1; 1400 /* rx - msdu fast path info fields */ 1401 hal_soc->ops->hal_rx_msdu_packet_metadata_get = 1402 hal_rx_msdu_packet_metadata_get_generic_li; 1403 hal_soc->ops->hal_rx_mpdu_start_tlv_tag_valid = 1404 hal_rx_mpdu_start_tlv_tag_valid_8074v1; 1405 1406 /* rx - TLV struct offsets */ 1407 hal_soc->ops->hal_rx_msdu_end_offset_get = 1408 hal_rx_msdu_end_offset_get_generic; 1409 hal_soc->ops->hal_rx_attn_offset_get = hal_rx_attn_offset_get_generic; 1410 hal_soc->ops->hal_rx_msdu_start_offset_get = 1411 hal_rx_msdu_start_offset_get_generic; 1412 hal_soc->ops->hal_rx_mpdu_start_offset_get = 1413 hal_rx_mpdu_start_offset_get_generic; 1414 hal_soc->ops->hal_rx_mpdu_end_offset_get = 1415 hal_rx_mpdu_end_offset_get_generic; 1416 #ifndef NO_RX_PKT_HDR_TLV 1417 hal_soc->ops->hal_rx_pkt_tlv_offset_get = 1418 hal_rx_pkt_tlv_offset_get_generic; 1419 #endif 1420 hal_soc->ops->hal_rx_flow_setup_fse = hal_rx_flow_setup_fse_8074v1; 1421 hal_soc->ops->hal_rx_flow_get_tuple_info = 1422 hal_rx_flow_get_tuple_info_li; 1423 hal_soc->ops->hal_rx_flow_delete_entry = 1424 hal_rx_flow_delete_entry_li; 1425 hal_soc->ops->hal_rx_fst_get_fse_size = hal_rx_fst_get_fse_size_li; 1426 hal_soc->ops->hal_compute_reo_remap_ix2_ix3 = 1427 hal_compute_reo_remap_ix2_ix3_8074v1; 1428 hal_soc->ops->hal_setup_link_idle_list = 1429 hal_setup_link_idle_list_generic_li; 1430 hal_soc->ops->hal_compute_reo_remap_ix0 = NULL; 1431 }; 1432 1433 struct hal_hw_srng_config hw_srng_table_8074[] = { 1434 /* TODO: max_rings can populated by querying HW capabilities */ 1435 { /* REO_DST */ 1436 .start_ring_id = HAL_SRNG_REO2SW1, 1437 .max_rings = 4, 1438 .entry_size = sizeof(struct reo_destination_ring) >> 2, 1439 .lmac_ring = FALSE, 1440 .ring_dir = HAL_SRNG_DST_RING, 1441 .reg_start = { 1442 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR( 1443 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1444 HWIO_REO_R2_REO2SW1_RING_HP_ADDR( 1445 SEQ_WCSS_UMAC_REO_REG_OFFSET) 1446 }, 1447 .reg_size = { 1448 HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(0) - 1449 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(0), 1450 HWIO_REO_R2_REO2SW2_RING_HP_ADDR(0) - 1451 HWIO_REO_R2_REO2SW1_RING_HP_ADDR(0), 1452 }, 1453 .max_size = 1454 HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_BMSK >> 1455 HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_SHFT, 1456 }, 1457 { /* REO_EXCEPTION */ 1458 /* Designating REO2TCL ring as exception ring. This ring is 1459 * similar to other REO2SW rings though it is named as REO2TCL. 1460 * Any of theREO2SW rings can be used as exception ring. 1461 */ 1462 .start_ring_id = HAL_SRNG_REO2TCL, 1463 .max_rings = 1, 1464 .entry_size = sizeof(struct reo_destination_ring) >> 2, 1465 .lmac_ring = FALSE, 1466 .ring_dir = HAL_SRNG_DST_RING, 1467 .reg_start = { 1468 HWIO_REO_R0_REO2TCL_RING_BASE_LSB_ADDR( 1469 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1470 HWIO_REO_R2_REO2TCL_RING_HP_ADDR( 1471 SEQ_WCSS_UMAC_REO_REG_OFFSET) 1472 }, 1473 /* Single ring - provide ring size if multiple rings of this 1474 * type are supported 1475 */ 1476 .reg_size = {}, 1477 .max_size = 1478 HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_BMSK >> 1479 HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_SHFT, 1480 }, 1481 { /* REO_REINJECT */ 1482 .start_ring_id = HAL_SRNG_SW2REO, 1483 .max_rings = 1, 1484 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 1485 .lmac_ring = FALSE, 1486 .ring_dir = HAL_SRNG_SRC_RING, 1487 .reg_start = { 1488 HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR( 1489 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1490 HWIO_REO_R2_SW2REO_RING_HP_ADDR( 1491 SEQ_WCSS_UMAC_REO_REG_OFFSET) 1492 }, 1493 /* Single ring - provide ring size if multiple rings of this 1494 * type are supported 1495 */ 1496 .reg_size = {}, 1497 .max_size = HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_BMSK >> 1498 HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_SHFT, 1499 }, 1500 { /* REO_CMD */ 1501 .start_ring_id = HAL_SRNG_REO_CMD, 1502 .max_rings = 1, 1503 .entry_size = (sizeof(struct tlv_32_hdr) + 1504 sizeof(struct reo_get_queue_stats)) >> 2, 1505 .lmac_ring = FALSE, 1506 .ring_dir = HAL_SRNG_SRC_RING, 1507 .reg_start = { 1508 HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR( 1509 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1510 HWIO_REO_R2_REO_CMD_RING_HP_ADDR( 1511 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1512 }, 1513 /* Single ring - provide ring size if multiple rings of this 1514 * type are supported 1515 */ 1516 .reg_size = {}, 1517 .max_size = HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_BMSK >> 1518 HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_SHFT, 1519 }, 1520 { /* REO_STATUS */ 1521 .start_ring_id = HAL_SRNG_REO_STATUS, 1522 .max_rings = 1, 1523 .entry_size = (sizeof(struct tlv_32_hdr) + 1524 sizeof(struct reo_get_queue_stats_status)) >> 2, 1525 .lmac_ring = FALSE, 1526 .ring_dir = HAL_SRNG_DST_RING, 1527 .reg_start = { 1528 HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR( 1529 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1530 HWIO_REO_R2_REO_STATUS_RING_HP_ADDR( 1531 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1532 }, 1533 /* Single ring - provide ring size if multiple rings of this 1534 * type are supported 1535 */ 1536 .reg_size = {}, 1537 .max_size = 1538 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> 1539 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, 1540 }, 1541 { /* TCL_DATA */ 1542 .start_ring_id = HAL_SRNG_SW2TCL1, 1543 .max_rings = 3, 1544 .entry_size = (sizeof(struct tlv_32_hdr) + 1545 sizeof(struct tcl_data_cmd)) >> 2, 1546 .lmac_ring = FALSE, 1547 .ring_dir = HAL_SRNG_SRC_RING, 1548 .reg_start = { 1549 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR( 1550 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1551 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR( 1552 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1553 }, 1554 .reg_size = { 1555 HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(0) - 1556 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(0), 1557 HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(0) - 1558 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(0), 1559 }, 1560 .max_size = 1561 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK >> 1562 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT, 1563 }, 1564 { /* TCL_CMD */ 1565 .start_ring_id = HAL_SRNG_SW2TCL_CMD, 1566 .max_rings = 1, 1567 .entry_size = (sizeof(struct tlv_32_hdr) + 1568 sizeof(struct tcl_data_cmd)) >> 2, 1569 .lmac_ring = FALSE, 1570 .ring_dir = HAL_SRNG_SRC_RING, 1571 .reg_start = { 1572 HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_ADDR( 1573 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1574 HWIO_TCL_R2_SW2TCL_CMD_RING_HP_ADDR( 1575 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1576 }, 1577 /* Single ring - provide ring size if multiple rings of this 1578 * type are supported 1579 */ 1580 .reg_size = {}, 1581 .max_size = 1582 HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RING_SIZE_BMSK >> 1583 HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RING_SIZE_SHFT, 1584 }, 1585 { /* TCL_STATUS */ 1586 .start_ring_id = HAL_SRNG_TCL_STATUS, 1587 .max_rings = 1, 1588 .entry_size = (sizeof(struct tlv_32_hdr) + 1589 sizeof(struct tcl_status_ring)) >> 2, 1590 .lmac_ring = FALSE, 1591 .ring_dir = HAL_SRNG_DST_RING, 1592 .reg_start = { 1593 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR( 1594 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1595 HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR( 1596 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1597 }, 1598 /* Single ring - provide ring size if multiple rings of this 1599 * type are supported 1600 */ 1601 .reg_size = {}, 1602 .max_size = 1603 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_BMSK >> 1604 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_SHFT, 1605 }, 1606 { /* CE_SRC */ 1607 .start_ring_id = HAL_SRNG_CE_0_SRC, 1608 .max_rings = 12, 1609 .entry_size = sizeof(struct ce_src_desc) >> 2, 1610 .lmac_ring = FALSE, 1611 .ring_dir = HAL_SRNG_SRC_RING, 1612 .reg_start = { 1613 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR( 1614 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET), 1615 HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR( 1616 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET), 1617 }, 1618 .reg_size = { 1619 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET - 1620 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET, 1621 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET - 1622 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET, 1623 }, 1624 .max_size = 1625 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >> 1626 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT, 1627 }, 1628 { /* CE_DST */ 1629 .start_ring_id = HAL_SRNG_CE_0_DST, 1630 .max_rings = 12, 1631 .entry_size = 8 >> 2, 1632 /*TODO: entry_size above should actually be 1633 * sizeof(struct ce_dst_desc) >> 2, but couldn't find definition 1634 * of struct ce_dst_desc in HW header files 1635 */ 1636 .lmac_ring = FALSE, 1637 .ring_dir = HAL_SRNG_SRC_RING, 1638 .reg_start = { 1639 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR( 1640 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 1641 HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR( 1642 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 1643 }, 1644 .reg_size = { 1645 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 1646 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 1647 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 1648 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 1649 }, 1650 .max_size = 1651 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >> 1652 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT, 1653 }, 1654 { /* CE_DST_STATUS */ 1655 .start_ring_id = HAL_SRNG_CE_0_DST_STATUS, 1656 .max_rings = 12, 1657 .entry_size = sizeof(struct ce_stat_desc) >> 2, 1658 .lmac_ring = FALSE, 1659 .ring_dir = HAL_SRNG_DST_RING, 1660 .reg_start = { 1661 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR( 1662 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 1663 HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR( 1664 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 1665 }, 1666 /* TODO: check destination status ring registers */ 1667 .reg_size = { 1668 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 1669 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 1670 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 1671 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 1672 }, 1673 .max_size = 1674 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> 1675 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, 1676 }, 1677 { /* WBM_IDLE_LINK */ 1678 .start_ring_id = HAL_SRNG_WBM_IDLE_LINK, 1679 .max_rings = 1, 1680 .entry_size = sizeof(struct wbm_link_descriptor_ring) >> 2, 1681 .lmac_ring = FALSE, 1682 .ring_dir = HAL_SRNG_SRC_RING, 1683 .reg_start = { 1684 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1685 HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1686 }, 1687 /* Single ring - provide ring size if multiple rings of this 1688 * type are supported 1689 */ 1690 .reg_size = {}, 1691 .max_size = 1692 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_BMSK >> 1693 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_SHFT, 1694 }, 1695 { /* SW2WBM_RELEASE */ 1696 .start_ring_id = HAL_SRNG_WBM_SW_RELEASE, 1697 .max_rings = 1, 1698 .entry_size = sizeof(struct wbm_release_ring) >> 2, 1699 .lmac_ring = FALSE, 1700 .ring_dir = HAL_SRNG_SRC_RING, 1701 .reg_start = { 1702 HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1703 HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1704 }, 1705 /* Single ring - provide ring size if multiple rings of this 1706 * type are supported 1707 */ 1708 .reg_size = {}, 1709 .max_size = 1710 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> 1711 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, 1712 }, 1713 { /* WBM2SW_RELEASE */ 1714 .start_ring_id = HAL_SRNG_WBM2SW0_RELEASE, 1715 .max_rings = 4, 1716 .entry_size = sizeof(struct wbm_release_ring) >> 2, 1717 .lmac_ring = FALSE, 1718 .ring_dir = HAL_SRNG_DST_RING, 1719 .reg_start = { 1720 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1721 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1722 }, 1723 .reg_size = { 1724 HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) - 1725 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1726 HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) - 1727 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1728 }, 1729 .max_size = 1730 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> 1731 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, 1732 }, 1733 { /* RXDMA_BUF */ 1734 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA0_BUF0, 1735 #ifdef IPA_OFFLOAD 1736 .max_rings = 3, 1737 #else 1738 .max_rings = 2, 1739 #endif 1740 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 1741 .lmac_ring = TRUE, 1742 .ring_dir = HAL_SRNG_SRC_RING, 1743 /* reg_start is not set because LMAC rings are not accessed 1744 * from host 1745 */ 1746 .reg_start = {}, 1747 .reg_size = {}, 1748 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1749 }, 1750 { /* RXDMA_DST */ 1751 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW0, 1752 .max_rings = 1, 1753 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 1754 .lmac_ring = TRUE, 1755 .ring_dir = HAL_SRNG_DST_RING, 1756 /* reg_start is not set because LMAC rings are not accessed 1757 * from host 1758 */ 1759 .reg_start = {}, 1760 .reg_size = {}, 1761 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1762 }, 1763 { /* RXDMA_MONITOR_BUF */ 1764 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA2_BUF, 1765 .max_rings = 1, 1766 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 1767 .lmac_ring = TRUE, 1768 .ring_dir = HAL_SRNG_SRC_RING, 1769 /* reg_start is not set because LMAC rings are not accessed 1770 * from host 1771 */ 1772 .reg_start = {}, 1773 .reg_size = {}, 1774 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1775 }, 1776 { /* RXDMA_MONITOR_STATUS */ 1777 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_STATBUF, 1778 .max_rings = 1, 1779 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 1780 .lmac_ring = TRUE, 1781 .ring_dir = HAL_SRNG_SRC_RING, 1782 /* reg_start is not set because LMAC rings are not accessed 1783 * from host 1784 */ 1785 .reg_start = {}, 1786 .reg_size = {}, 1787 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1788 }, 1789 { /* RXDMA_MONITOR_DST */ 1790 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW1, 1791 .max_rings = 1, 1792 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 1793 .lmac_ring = TRUE, 1794 .ring_dir = HAL_SRNG_DST_RING, 1795 /* reg_start is not set because LMAC rings are not accessed 1796 * from host 1797 */ 1798 .reg_start = {}, 1799 .reg_size = {}, 1800 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1801 }, 1802 { /* RXDMA_MONITOR_DESC */ 1803 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_DESC, 1804 .max_rings = 1, 1805 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 1806 .lmac_ring = TRUE, 1807 .ring_dir = HAL_SRNG_SRC_RING, 1808 /* reg_start is not set because LMAC rings are not accessed 1809 * from host 1810 */ 1811 .reg_start = {}, 1812 .reg_size = {}, 1813 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1814 }, 1815 { /* DIR_BUF_RX_DMA_SRC */ 1816 .start_ring_id = HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING, 1817 .max_rings = 1, 1818 .entry_size = 2, 1819 .lmac_ring = TRUE, 1820 .ring_dir = HAL_SRNG_SRC_RING, 1821 /* reg_start is not set because LMAC rings are not accessed 1822 * from host 1823 */ 1824 .reg_start = {}, 1825 .reg_size = {}, 1826 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1827 }, 1828 #ifdef WLAN_FEATURE_CIF_CFR 1829 { /* WIFI_POS_SRC */ 1830 .start_ring_id = HAL_SRNG_WIFI_POS_SRC_DMA_RING, 1831 .max_rings = 1, 1832 .entry_size = sizeof(wmi_oem_dma_buf_release_entry) >> 2, 1833 .lmac_ring = TRUE, 1834 .ring_dir = HAL_SRNG_SRC_RING, 1835 /* reg_start is not set because LMAC rings are not accessed 1836 * from host 1837 */ 1838 .reg_start = {}, 1839 .reg_size = {}, 1840 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1841 }, 1842 #endif 1843 { /* REO2PPE */ 0}, 1844 { /* PPE2TCL */ 0}, 1845 { /* PPE_RELEASE */ 0}, 1846 { /* TX_MONITOR_BUF */ 0}, 1847 { /* TX_MONITOR_DST */ 0}, 1848 { /* SW2RXDMA_NEW */ 0}, 1849 }; 1850 1851 /** 1852 * hal_qca8074_attach() - Attach 8074 target specific hal_soc ops, 1853 * offset and srng table 1854 */ 1855 void hal_qca8074_attach(struct hal_soc *hal_soc) 1856 { 1857 hal_soc->hw_srng_table = hw_srng_table_8074; 1858 hal_srng_hw_reg_offset_init_generic(hal_soc); 1859 hal_hw_txrx_default_ops_attach_li(hal_soc); 1860 hal_hw_txrx_ops_attach_qca8074(hal_soc); 1861 } 1862