1 /* 2 * Copyright (c) 2016-2020 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 #include "hal_hw_headers.h" 19 #include "hal_internal.h" 20 #include "hal_api.h" 21 #include "target_type.h" 22 #include "wcss_version.h" 23 #include "qdf_module.h" 24 #include "hal_flow.h" 25 #include "rx_flow_search_entry.h" 26 #include "hal_rx_flow_info.h" 27 28 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_OFFSET \ 29 RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_OFFSET 30 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_MASK \ 31 RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_MASK 32 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_LSB \ 33 RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_LSB 34 #define UNIFIED_PHYRX_HT_SIG_0_HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS_OFFSET \ 35 PHYRX_HT_SIG_0_HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS_OFFSET 36 #define UNIFIED_PHYRX_L_SIG_B_0_L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS_OFFSET \ 37 PHYRX_L_SIG_B_0_L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS_OFFSET 38 #define UNIFIED_PHYRX_L_SIG_A_0_L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS_OFFSET \ 39 PHYRX_L_SIG_A_0_L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS_OFFSET 40 #define UNIFIED_PHYRX_VHT_SIG_A_0_VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS_OFFSET \ 41 PHYRX_VHT_SIG_A_0_VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS_OFFSET 42 #define UNIFIED_PHYRX_HE_SIG_A_SU_0_HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS_OFFSET \ 43 PHYRX_HE_SIG_A_SU_0_HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS_OFFSET 44 #define UNIFIED_PHYRX_HE_SIG_A_MU_DL_0_HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_OFFSET \ 45 PHYRX_HE_SIG_A_MU_DL_0_HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_OFFSET 46 #define UNIFIED_PHYRX_HE_SIG_B1_MU_0_HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_OFFSET \ 47 PHYRX_HE_SIG_B1_MU_0_HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_OFFSET 48 #define UNIFIED_PHYRX_HE_SIG_B2_MU_0_HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_OFFSET \ 49 PHYRX_HE_SIG_B2_MU_0_HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_OFFSET 50 #define UNIFIED_PHYRX_HE_SIG_B2_OFDMA_0_HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_OFFSET \ 51 PHYRX_HE_SIG_B2_OFDMA_0_HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_OFFSET 52 #define UNIFIED_PHYRX_RSSI_LEGACY_3_RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS_OFFSET \ 53 PHYRX_RSSI_LEGACY_3_RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS_OFFSET 54 #define UNIFIED_PHYRX_RSSI_LEGACY_19_RECEIVE_RSSI_INFO_PREAMBLE_RSSI_INFO_DETAILS_OFFSET \ 55 PHYRX_RSSI_LEGACY_19_RECEIVE_RSSI_INFO_PREAMBLE_RSSI_INFO_DETAILS_OFFSET 56 #define UNIFIED_RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET \ 57 RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET 58 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 59 RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET 60 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ 61 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET 62 #define UNIFIED_RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 63 RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET 64 #define UNIFIED_REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 65 REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET 66 #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC \ 67 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER 68 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSE \ 69 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET 70 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 71 RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET 72 #define UNIFIED_TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 73 TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET 74 #define UNIFIED_TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 75 TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET 76 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET \ 77 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET 78 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB \ 79 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB 80 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK \ 81 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK 82 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB \ 83 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB 84 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK \ 85 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK 86 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB \ 87 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB 88 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK \ 89 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK 90 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB \ 91 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB 92 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK \ 93 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK 94 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB \ 95 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB 96 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK \ 97 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK 98 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_MASK \ 99 WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_MASK 100 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_OFFSET \ 101 WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_OFFSET 102 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_LSB \ 103 WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_LSB 104 105 #include "hal_8074v1_tx.h" 106 #include "hal_8074v1_rx.h" 107 #include <hal_generic_api.h> 108 #include <hal_wbm.h> 109 110 /** 111 * hal_get_window_address_8074(): Function to get hp/tp address 112 * @hal_soc: Pointer to hal_soc 113 * @addr: address offset of register 114 * 115 * Return: modified address offset of register 116 */ 117 static inline qdf_iomem_t hal_get_window_address_8074(struct hal_soc *hal_soc, 118 qdf_iomem_t addr) 119 { 120 return addr; 121 } 122 123 /** 124 * hal_rx_get_rx_fragment_number_8074v1(): Function to retrieve 125 * rx fragment number 126 * 127 * @nbuf: Network buffer 128 * Returns: rx fragment number 129 */ 130 static 131 uint8_t hal_rx_get_rx_fragment_number_8074v1(uint8_t *buf) 132 { 133 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 134 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 135 136 /* Return first 4 bits as fragment number */ 137 return (HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info) & 138 DOT11_SEQ_FRAG_MASK); 139 } 140 141 /** 142 * hal_rx_msdu_end_da_is_mcbc_get_8074v1(): API to check if 143 * pkt is MCBC from rx_msdu_end TLV 144 * 145 * @ buf: pointer to the start of RX PKT TLV headers 146 * Return: da_is_mcbc 147 */ 148 static uint8_t 149 hal_rx_msdu_end_da_is_mcbc_get_8074v1(uint8_t *buf) 150 { 151 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 152 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 153 154 return HAL_RX_MSDU_END_DA_IS_MCBC_GET(msdu_end); 155 } 156 157 /** 158 * hal_rx_msdu_end_sa_is_valid_get_8074v1(): API to get_8074v1 the 159 * sa_is_valid bit from rx_msdu_end TLV 160 * 161 * @ buf: pointer to the start of RX PKT TLV headers 162 * Return: sa_is_valid bit 163 */ 164 static uint8_t 165 hal_rx_msdu_end_sa_is_valid_get_8074v1(uint8_t *buf) 166 { 167 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 168 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 169 uint8_t sa_is_valid; 170 171 sa_is_valid = HAL_RX_MSDU_END_SA_IS_VALID_GET(msdu_end); 172 173 return sa_is_valid; 174 } 175 176 /** 177 * hal_rx_msdu_end_sa_idx_get_8074v1(): API to get_8074v1 the 178 * sa_idx from rx_msdu_end TLV 179 * 180 * @ buf: pointer to the start of RX PKT TLV headers 181 * Return: sa_idx (SA AST index) 182 */ 183 static uint16_t hal_rx_msdu_end_sa_idx_get_8074v1(uint8_t *buf) 184 { 185 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 186 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 187 uint16_t sa_idx; 188 189 sa_idx = HAL_RX_MSDU_END_SA_IDX_GET(msdu_end); 190 191 return sa_idx; 192 } 193 194 /** 195 * hal_rx_desc_is_first_msdu_8074v1() - Check if first msdu 196 * 197 * @hal_soc_hdl: hal_soc handle 198 * @hw_desc_addr: hardware descriptor address 199 * 200 * Return: 0 - success/ non-zero failure 201 */ 202 static uint32_t hal_rx_desc_is_first_msdu_8074v1(void *hw_desc_addr) 203 { 204 struct rx_pkt_tlvs *rx_tlvs = (struct rx_pkt_tlvs *)hw_desc_addr; 205 struct rx_msdu_end *msdu_end = &rx_tlvs->msdu_end_tlv.rx_msdu_end; 206 207 return HAL_RX_GET(msdu_end, RX_MSDU_END_5, FIRST_MSDU); 208 } 209 210 /** 211 * hal_rx_msdu_end_l3_hdr_padding_get_8074v1(): API to get_8074v1 the 212 * l3_header padding from rx_msdu_end TLV 213 * 214 * @ buf: pointer to the start of RX PKT TLV headers 215 * Return: number of l3 header padding bytes 216 */ 217 static uint32_t hal_rx_msdu_end_l3_hdr_padding_get_8074v1(uint8_t *buf) 218 { 219 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 220 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 221 uint32_t l3_header_padding; 222 223 l3_header_padding = HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(msdu_end); 224 225 return l3_header_padding; 226 } 227 228 /* 229 * @ hal_rx_encryption_info_valid_8074v1: Returns encryption type. 230 * 231 * @ buf: rx_tlv_hdr of the received packet 232 * @ Return: encryption type 233 */ 234 static uint32_t hal_rx_encryption_info_valid_8074v1(uint8_t *buf) 235 { 236 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 237 struct rx_mpdu_start *mpdu_start = 238 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 239 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 240 uint32_t encryption_info = HAL_RX_MPDU_ENCRYPTION_INFO_VALID(mpdu_info); 241 242 return encryption_info; 243 } 244 245 /* 246 * @ hal_rx_print_pn_8074v1: Prints the PN of rx packet. 247 * 248 * @ buf: rx_tlv_hdr of the received packet 249 * @ Return: void 250 */ 251 static void hal_rx_print_pn_8074v1(uint8_t *buf) 252 { 253 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 254 struct rx_mpdu_start *mpdu_start = 255 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 256 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 257 258 uint32_t pn_31_0 = HAL_RX_MPDU_PN_31_0_GET(mpdu_info); 259 uint32_t pn_63_32 = HAL_RX_MPDU_PN_63_32_GET(mpdu_info); 260 uint32_t pn_95_64 = HAL_RX_MPDU_PN_95_64_GET(mpdu_info); 261 uint32_t pn_127_96 = HAL_RX_MPDU_PN_127_96_GET(mpdu_info); 262 263 hal_debug("PN number pn_127_96 0x%x pn_95_64 0x%x pn_63_32 0x%x pn_31_0 0x%x ", 264 pn_127_96, pn_95_64, pn_63_32, pn_31_0); 265 } 266 267 /** 268 * hal_rx_msdu_end_first_msdu_get_8074v1: API to get first msdu status 269 * from rx_msdu_end TLV 270 * 271 * @ buf: pointer to the start of RX PKT TLV headers 272 * Return: first_msdu 273 */ 274 static uint8_t 275 hal_rx_msdu_end_first_msdu_get_8074v1(uint8_t *buf) 276 { 277 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 278 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 279 uint8_t first_msdu; 280 281 first_msdu = HAL_RX_MSDU_END_FIRST_MSDU_GET(msdu_end); 282 283 return first_msdu; 284 } 285 286 /** 287 * hal_rx_msdu_end_da_is_valid_get_8074v1: API to check if da is valid 288 * from rx_msdu_end TLV 289 * 290 * @ buf: pointer to the start of RX PKT TLV headers 291 * Return: da_is_valid 292 */ 293 static uint8_t hal_rx_msdu_end_da_is_valid_get_8074v1(uint8_t *buf) 294 { 295 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 296 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 297 uint8_t da_is_valid; 298 299 da_is_valid = HAL_RX_MSDU_END_DA_IS_VALID_GET(msdu_end); 300 301 return da_is_valid; 302 } 303 304 /** 305 * hal_rx_msdu_end_last_msdu_get_8074v1: API to get last msdu status 306 * from rx_msdu_end TLV 307 * 308 * @ buf: pointer to the start of RX PKT TLV headers 309 * Return: last_msdu 310 */ 311 static uint8_t hal_rx_msdu_end_last_msdu_get_8074v1(uint8_t *buf) 312 { 313 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 314 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 315 uint8_t last_msdu; 316 317 last_msdu = HAL_RX_MSDU_END_LAST_MSDU_GET(msdu_end); 318 319 return last_msdu; 320 } 321 322 /* 323 * hal_rx_get_mpdu_mac_ad4_valid_8074v1(): Retrieves if mpdu 4th addr is valid 324 * 325 * @nbuf: Network buffer 326 * Returns: value of mpdu 4th address valid field 327 */ 328 static bool hal_rx_get_mpdu_mac_ad4_valid_8074v1(uint8_t *buf) 329 { 330 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 331 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 332 bool ad4_valid = 0; 333 334 ad4_valid = HAL_RX_MPDU_GET_MAC_AD4_VALID(rx_mpdu_info); 335 336 return ad4_valid; 337 } 338 339 /** 340 * hal_rx_mpdu_start_sw_peer_id_get_8074v1: Retrieve sw peer_id 341 * @buf: network buffer 342 * 343 * Return: sw peer_id 344 */ 345 static uint32_t hal_rx_mpdu_start_sw_peer_id_get_8074v1(uint8_t *buf) 346 { 347 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 348 struct rx_mpdu_start *mpdu_start = 349 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 350 351 return HAL_RX_MPDU_INFO_SW_PEER_ID_GET( 352 &mpdu_start->rx_mpdu_info_details); 353 } 354 355 /* 356 * hal_rx_mpdu_get_to_ds_8074v1(): API to get the tods info 357 * from rx_mpdu_start 358 * 359 * @buf: pointer to the start of RX PKT TLV header 360 * Return: uint32_t(to_ds) 361 */ 362 363 static uint32_t hal_rx_mpdu_get_to_ds_8074v1(uint8_t *buf) 364 { 365 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 366 struct rx_mpdu_start *mpdu_start = 367 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 368 369 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 370 371 return HAL_RX_MPDU_GET_TODS(mpdu_info); 372 } 373 374 /* 375 * hal_rx_mpdu_get_fr_ds_8074v1(): API to get the from ds info 376 * from rx_mpdu_start 377 * 378 * @buf: pointer to the start of RX PKT TLV header 379 * Return: uint32_t(fr_ds) 380 */ 381 static uint32_t hal_rx_mpdu_get_fr_ds_8074v1(uint8_t *buf) 382 { 383 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 384 struct rx_mpdu_start *mpdu_start = 385 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 386 387 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 388 389 return HAL_RX_MPDU_GET_FROMDS(mpdu_info); 390 } 391 392 /* 393 * hal_rx_get_mpdu_frame_control_valid_8074v1(): Retrieves mpdu 394 * frame control valid 395 * 396 * @nbuf: Network buffer 397 * Returns: value of frame control valid field 398 */ 399 static uint8_t hal_rx_get_mpdu_frame_control_valid_8074v1(uint8_t *buf) 400 { 401 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 402 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 403 404 return HAL_RX_MPDU_GET_FRAME_CONTROL_VALID(rx_mpdu_info); 405 } 406 407 /* 408 * hal_rx_mpdu_get_addr1_8074v1(): API to check get address1 of the mpdu 409 * 410 * @buf: pointer to the start of RX PKT TLV headera 411 * @mac_addr: pointer to mac address 412 * Return: success/failure 413 */ 414 static QDF_STATUS hal_rx_mpdu_get_addr1_8074v1(uint8_t *buf, 415 uint8_t *mac_addr) 416 { 417 struct __attribute__((__packed__)) hal_addr1 { 418 uint32_t ad1_31_0; 419 uint16_t ad1_47_32; 420 }; 421 422 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 423 struct rx_mpdu_start *mpdu_start = 424 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 425 426 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 427 struct hal_addr1 *addr = (struct hal_addr1 *)mac_addr; 428 uint32_t mac_addr_ad1_valid; 429 430 mac_addr_ad1_valid = HAL_RX_MPDU_MAC_ADDR_AD1_VALID_GET(mpdu_info); 431 432 if (mac_addr_ad1_valid) { 433 addr->ad1_31_0 = HAL_RX_MPDU_AD1_31_0_GET(mpdu_info); 434 addr->ad1_47_32 = HAL_RX_MPDU_AD1_47_32_GET(mpdu_info); 435 return QDF_STATUS_SUCCESS; 436 } 437 438 return QDF_STATUS_E_FAILURE; 439 } 440 441 /* 442 * hal_rx_mpdu_get_addr2_8074v1(): API to check get address2 of the mpdu 443 * in the packet 444 * 445 * @buf: pointer to the start of RX PKT TLV header 446 * @mac_addr: pointer to mac address 447 * Return: success/failure 448 */ 449 static QDF_STATUS hal_rx_mpdu_get_addr2_8074v1(uint8_t *buf, uint8_t *mac_addr) 450 { 451 struct __attribute__((__packed__)) hal_addr2 { 452 uint16_t ad2_15_0; 453 uint32_t ad2_47_16; 454 }; 455 456 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 457 struct rx_mpdu_start *mpdu_start = 458 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 459 460 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 461 struct hal_addr2 *addr = (struct hal_addr2 *)mac_addr; 462 uint32_t mac_addr_ad2_valid; 463 464 mac_addr_ad2_valid = HAL_RX_MPDU_MAC_ADDR_AD2_VALID_GET(mpdu_info); 465 466 if (mac_addr_ad2_valid) { 467 addr->ad2_15_0 = HAL_RX_MPDU_AD2_15_0_GET(mpdu_info); 468 addr->ad2_47_16 = HAL_RX_MPDU_AD2_47_16_GET(mpdu_info); 469 return QDF_STATUS_SUCCESS; 470 } 471 472 return QDF_STATUS_E_FAILURE; 473 } 474 475 /* 476 * hal_rx_mpdu_get_addr3_8074v1(): API to get address3 of the mpdu 477 * in the packet 478 * 479 * @buf: pointer to the start of RX PKT TLV header 480 * @mac_addr: pointer to mac address 481 * Return: success/failure 482 */ 483 static QDF_STATUS hal_rx_mpdu_get_addr3_8074v1(uint8_t *buf, uint8_t *mac_addr) 484 { 485 struct __attribute__((__packed__)) hal_addr3 { 486 uint32_t ad3_31_0; 487 uint16_t ad3_47_32; 488 }; 489 490 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 491 struct rx_mpdu_start *mpdu_start = 492 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 493 494 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 495 struct hal_addr3 *addr = (struct hal_addr3 *)mac_addr; 496 uint32_t mac_addr_ad3_valid; 497 498 mac_addr_ad3_valid = HAL_RX_MPDU_MAC_ADDR_AD3_VALID_GET(mpdu_info); 499 500 if (mac_addr_ad3_valid) { 501 addr->ad3_31_0 = HAL_RX_MPDU_AD3_31_0_GET(mpdu_info); 502 addr->ad3_47_32 = HAL_RX_MPDU_AD3_47_32_GET(mpdu_info); 503 return QDF_STATUS_SUCCESS; 504 } 505 506 return QDF_STATUS_E_FAILURE; 507 } 508 509 /* 510 * hal_rx_mpdu_get_addr4_8074v1(): API to get address4 of the mpdu 511 * in the packet 512 * 513 * @buf: pointer to the start of RX PKT TLV header 514 * @mac_addr: pointer to mac address 515 * Return: success/failure 516 */ 517 static QDF_STATUS hal_rx_mpdu_get_addr4_8074v1(uint8_t *buf, uint8_t *mac_addr) 518 { 519 struct __attribute__((__packed__)) hal_addr4 { 520 uint32_t ad4_31_0; 521 uint16_t ad4_47_32; 522 }; 523 524 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 525 struct rx_mpdu_start *mpdu_start = 526 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 527 528 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 529 struct hal_addr4 *addr = (struct hal_addr4 *)mac_addr; 530 uint32_t mac_addr_ad4_valid; 531 532 mac_addr_ad4_valid = HAL_RX_MPDU_MAC_ADDR_AD4_VALID_GET(mpdu_info); 533 534 if (mac_addr_ad4_valid) { 535 addr->ad4_31_0 = HAL_RX_MPDU_AD4_31_0_GET(mpdu_info); 536 addr->ad4_47_32 = HAL_RX_MPDU_AD4_47_32_GET(mpdu_info); 537 return QDF_STATUS_SUCCESS; 538 } 539 540 return QDF_STATUS_E_FAILURE; 541 } 542 543 /* 544 * hal_rx_get_mpdu_sequence_control_valid_8074v1(): Get mpdu 545 * sequence control valid 546 * 547 * @nbuf: Network buffer 548 * Returns: value of sequence control valid field 549 */ 550 static uint8_t hal_rx_get_mpdu_sequence_control_valid_8074v1(uint8_t *buf) 551 { 552 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 553 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 554 555 return HAL_RX_MPDU_GET_SEQUENCE_CONTROL_VALID(rx_mpdu_info); 556 } 557 558 /** 559 * hal_rx_is_unicast_8074v1: check packet is unicast frame or not. 560 * 561 * @ buf: pointer to rx pkt TLV. 562 * 563 * Return: true on unicast. 564 */ 565 static bool hal_rx_is_unicast_8074v1(uint8_t *buf) 566 { 567 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 568 struct rx_mpdu_start *mpdu_start = 569 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 570 uint32_t grp_id; 571 uint8_t *rx_mpdu_info = (uint8_t *)&mpdu_start->rx_mpdu_info_details; 572 573 grp_id = (_HAL_MS((*_OFFSET_TO_WORD_PTR((rx_mpdu_info), 574 RX_MPDU_INFO_0_SW_FRAME_GROUP_ID_OFFSET)), 575 RX_MPDU_INFO_0_SW_FRAME_GROUP_ID_MASK, 576 RX_MPDU_INFO_0_SW_FRAME_GROUP_ID_LSB)); 577 578 return (HAL_MPDU_SW_FRAME_GROUP_UNICAST_DATA == grp_id) ? true : false; 579 } 580 581 /** 582 * hal_rx_tid_get_8074v1: get tid based on qos control valid. 583 * 584 * @ buf: pointer to rx pkt TLV. 585 * 586 * Return: tid 587 */ 588 static uint32_t hal_rx_tid_get_8074v1(hal_soc_handle_t hal_soc_hdl, 589 uint8_t *buf) 590 { 591 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 592 struct rx_mpdu_start *mpdu_start = 593 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 594 uint8_t *rx_mpdu_info = (uint8_t *)&mpdu_start->rx_mpdu_info_details; 595 uint8_t qos_control_valid = 596 (_HAL_MS((*_OFFSET_TO_WORD_PTR((rx_mpdu_info), 597 RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_OFFSET)), 598 RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_MASK, 599 RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_LSB)); 600 601 if (qos_control_valid) 602 return hal_rx_mpdu_start_tid_get_8074(buf); 603 604 return HAL_RX_NON_QOS_TID; 605 } 606 607 /** 608 * hal_rx_hw_desc_get_ppduid_get_8074v1(): retrieve ppdu id 609 * @rx_tlv_hdr: Rx tlv header 610 * @rxdma_dst_ring_desc: Rx HW descriptor 611 * 612 * Return: ppdu id 613 */ 614 static uint32_t hal_rx_hw_desc_get_ppduid_get_8074v1(void *rx_tlv_hdr, 615 void *rxdma_dst_ring_desc) 616 { 617 struct rx_mpdu_info *rx_mpdu_info; 618 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)rx_tlv_hdr; 619 620 rx_mpdu_info = 621 &rx_desc->mpdu_start_tlv.rx_mpdu_start.rx_mpdu_info_details; 622 623 return HAL_RX_GET(rx_mpdu_info, RX_MPDU_INFO_0, PHY_PPDU_ID); 624 } 625 626 /** 627 * hal_reo_status_get_header_8074v1 - Process reo desc info 628 * @d - Pointer to reo descriptior 629 * @b - tlv type info 630 * @h1 - Pointer to hal_reo_status_header where info to be stored 631 * 632 * Return - none. 633 * 634 */ 635 static void hal_reo_status_get_header_8074v1(uint32_t *d, int b, void *h1) 636 { 637 uint32_t val1 = 0; 638 struct hal_reo_status_header *h = 639 (struct hal_reo_status_header *)h1; 640 641 switch (b) { 642 case HAL_REO_QUEUE_STATS_STATUS_TLV: 643 val1 = d[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_0, 644 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 645 break; 646 case HAL_REO_FLUSH_QUEUE_STATUS_TLV: 647 val1 = d[HAL_OFFSET_DW(REO_FLUSH_QUEUE_STATUS_0, 648 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 649 break; 650 case HAL_REO_FLUSH_CACHE_STATUS_TLV: 651 val1 = d[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_0, 652 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 653 break; 654 case HAL_REO_UNBLK_CACHE_STATUS_TLV: 655 val1 = d[HAL_OFFSET_DW(REO_UNBLOCK_CACHE_STATUS_0, 656 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 657 break; 658 case HAL_REO_TIMOUT_LIST_STATUS_TLV: 659 val1 = d[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_0, 660 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 661 break; 662 case HAL_REO_DESC_THRES_STATUS_TLV: 663 val1 = 664 d[HAL_OFFSET_DW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0, 665 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 666 break; 667 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: 668 val1 = d[HAL_OFFSET_DW(REO_UPDATE_RX_REO_QUEUE_STATUS_0, 669 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 670 break; 671 default: 672 qdf_nofl_err("ERROR: Unknown tlv\n"); 673 break; 674 } 675 h->cmd_num = 676 HAL_GET_FIELD( 677 UNIFORM_REO_STATUS_HEADER_0, REO_STATUS_NUMBER, 678 val1); 679 h->exec_time = 680 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_0, 681 CMD_EXECUTION_TIME, val1); 682 h->status = 683 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_0, 684 REO_CMD_EXECUTION_STATUS, val1); 685 switch (b) { 686 case HAL_REO_QUEUE_STATS_STATUS_TLV: 687 val1 = d[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_1, 688 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 689 break; 690 case HAL_REO_FLUSH_QUEUE_STATUS_TLV: 691 val1 = d[HAL_OFFSET_DW(REO_FLUSH_QUEUE_STATUS_1, 692 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 693 break; 694 case HAL_REO_FLUSH_CACHE_STATUS_TLV: 695 val1 = d[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_1, 696 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 697 break; 698 case HAL_REO_UNBLK_CACHE_STATUS_TLV: 699 val1 = d[HAL_OFFSET_DW(REO_UNBLOCK_CACHE_STATUS_1, 700 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 701 break; 702 case HAL_REO_TIMOUT_LIST_STATUS_TLV: 703 val1 = d[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_1, 704 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 705 break; 706 case HAL_REO_DESC_THRES_STATUS_TLV: 707 val1 = 708 d[HAL_OFFSET_DW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_1, 709 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 710 break; 711 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: 712 val1 = d[HAL_OFFSET_DW(REO_UPDATE_RX_REO_QUEUE_STATUS_1, 713 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 714 break; 715 default: 716 qdf_nofl_err("ERROR: Unknown tlv\n"); 717 break; 718 } 719 h->tstamp = 720 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_1, TIMESTAMP, val1); 721 } 722 723 /** 724 * hal_rx_mpdu_start_mpdu_qos_control_valid_get_8074v1(): 725 * Retrieve qos control valid bit from the tlv. 726 * @buf: pointer to rx pkt TLV. 727 * 728 * Return: qos control value. 729 */ 730 static inline uint32_t 731 hal_rx_mpdu_start_mpdu_qos_control_valid_get_8074v1(uint8_t *buf) 732 { 733 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 734 struct rx_mpdu_start *mpdu_start = 735 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 736 737 return HAL_RX_MPDU_INFO_QOS_CONTROL_VALID_GET( 738 &mpdu_start->rx_mpdu_info_details); 739 } 740 741 /** 742 * hal_rx_msdu_end_sa_sw_peer_id_get_8074v1(): API to get the 743 * sa_sw_peer_id from rx_msdu_end TLV 744 * @buf: pointer to the start of RX PKT TLV headers 745 * 746 * Return: sa_sw_peer_id index 747 */ 748 static inline uint32_t 749 hal_rx_msdu_end_sa_sw_peer_id_get_8074v1(uint8_t *buf) 750 { 751 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 752 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 753 754 return HAL_RX_MSDU_END_SA_SW_PEER_ID_GET(msdu_end); 755 } 756 757 /** 758 * hal_tx_desc_set_mesh_en_8074v1 - Set mesh_enable flag in Tx descriptor 759 * @desc: Handle to Tx Descriptor 760 * @en: For raw WiFi frames, this indicates transmission to a mesh STA, 761 * enabling the interpretation of the 'Mesh Control Present' bit 762 * (bit 8) of QoS Control (otherwise this bit is ignored), 763 * For native WiFi frames, this indicates that a 'Mesh Control' field 764 * is present between the header and the LLC. 765 * 766 * Return: void 767 */ 768 static inline 769 void hal_tx_desc_set_mesh_en_8074v1(void *desc, uint8_t en) 770 { 771 HAL_SET_FLD(desc, TCL_DATA_CMD_4, MESH_ENABLE) |= 772 HAL_TX_SM(TCL_DATA_CMD_4, MESH_ENABLE, en); 773 } 774 775 static 776 void *hal_rx_msdu0_buffer_addr_lsb_8074v1(void *link_desc_va) 777 { 778 return (void *)HAL_RX_MSDU0_BUFFER_ADDR_LSB(link_desc_va); 779 } 780 781 static 782 void *hal_rx_msdu_desc_info_ptr_get_8074v1(void *msdu0) 783 { 784 return (void *)HAL_RX_MSDU_DESC_INFO_PTR_GET(msdu0); 785 } 786 787 static 788 void *hal_ent_mpdu_desc_info_8074v1(void *ent_ring_desc) 789 { 790 return (void *)HAL_ENT_MPDU_DESC_INFO(ent_ring_desc); 791 } 792 793 static 794 void *hal_dst_mpdu_desc_info_8074v1(void *dst_ring_desc) 795 { 796 return (void *)HAL_DST_MPDU_DESC_INFO(dst_ring_desc); 797 } 798 799 static 800 uint8_t hal_rx_get_fc_valid_8074v1(uint8_t *buf) 801 { 802 return HAL_RX_GET_FC_VALID(buf); 803 } 804 805 static uint8_t hal_rx_get_to_ds_flag_8074v1(uint8_t *buf) 806 { 807 return HAL_RX_GET_TO_DS_FLAG(buf); 808 } 809 810 static uint8_t hal_rx_get_mac_addr2_valid_8074v1(uint8_t *buf) 811 { 812 return HAL_RX_GET_MAC_ADDR2_VALID(buf); 813 } 814 815 static uint8_t hal_rx_get_filter_category_8074v1(uint8_t *buf) 816 { 817 return HAL_RX_GET_FILTER_CATEGORY(buf); 818 } 819 820 static uint32_t 821 hal_rx_get_ppdu_id_8074v1(uint8_t *buf) 822 { 823 struct rx_mpdu_info *rx_mpdu_info; 824 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)buf; 825 826 rx_mpdu_info = 827 &rx_desc->mpdu_start_tlv.rx_mpdu_start.rx_mpdu_info_details; 828 829 return HAL_RX_GET_PPDU_ID(rx_mpdu_info); 830 } 831 832 /** 833 * hal_reo_config_8074v1(): Set reo config parameters 834 * @soc: hal soc handle 835 * @reg_val: value to be set 836 * @reo_params: reo parameters 837 * 838 * Return: void 839 */ 840 static void 841 hal_reo_config_8074v1(struct hal_soc *soc, 842 uint32_t reg_val, 843 struct hal_reo_params *reo_params) 844 { 845 HAL_REO_R0_CONFIG(soc, reg_val, reo_params); 846 } 847 848 /** 849 * hal_rx_msdu_desc_info_get_ptr_8074v1() - Get msdu desc info ptr 850 * @msdu_details_ptr - Pointer to msdu_details_ptr 851 * 852 * Return - Pointer to rx_msdu_desc_info structure. 853 * 854 */ 855 static void *hal_rx_msdu_desc_info_get_ptr_8074v1(void *msdu_details_ptr) 856 { 857 return HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr); 858 } 859 860 /** 861 * hal_rx_link_desc_msdu0_ptr_8074v1 - Get pointer to rx_msdu details 862 * @link_desc - Pointer to link desc 863 * 864 * Return - Pointer to rx_msdu_details structure 865 * 866 */ 867 static void *hal_rx_link_desc_msdu0_ptr_8074v1(void *link_desc) 868 { 869 return HAL_RX_LINK_DESC_MSDU0_PTR(link_desc); 870 } 871 872 /** 873 * hal_rx_msdu_flow_idx_get_8074v1: API to get flow index 874 * from rx_msdu_end TLV 875 * @buf: pointer to the start of RX PKT TLV headers 876 * 877 * Return: flow index value from MSDU END TLV 878 */ 879 static inline uint32_t hal_rx_msdu_flow_idx_get_8074v1(uint8_t *buf) 880 { 881 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 882 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 883 884 return HAL_RX_MSDU_END_FLOW_IDX_GET(msdu_end); 885 } 886 887 /** 888 * hal_rx_msdu_flow_idx_invalid_8074v1: API to get flow index invalid 889 * from rx_msdu_end TLV 890 * @buf: pointer to the start of RX PKT TLV headers 891 * 892 * Return: flow index invalid value from MSDU END TLV 893 */ 894 static bool hal_rx_msdu_flow_idx_invalid_8074v1(uint8_t *buf) 895 { 896 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 897 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 898 899 return HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(msdu_end); 900 } 901 902 /** 903 * hal_rx_msdu_flow_idx_timeout_8074v1: API to get flow index timeout 904 * from rx_msdu_end TLV 905 * @buf: pointer to the start of RX PKT TLV headers 906 * 907 * Return: flow index timeout value from MSDU END TLV 908 */ 909 static bool hal_rx_msdu_flow_idx_timeout_8074v1(uint8_t *buf) 910 { 911 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 912 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 913 914 return HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(msdu_end); 915 } 916 917 /** 918 * hal_rx_msdu_fse_metadata_get_8074v1: API to get FSE metadata 919 * from rx_msdu_end TLV 920 * @buf: pointer to the start of RX PKT TLV headers 921 * 922 * Return: fse metadata value from MSDU END TLV 923 */ 924 static uint32_t hal_rx_msdu_fse_metadata_get_8074v1(uint8_t *buf) 925 { 926 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 927 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 928 929 return HAL_RX_MSDU_END_FSE_METADATA_GET(msdu_end); 930 } 931 932 /** 933 * hal_rx_msdu_cce_metadata_get_8074v1: API to get CCE metadata 934 * from rx_msdu_end TLV 935 * @buf: pointer to the start of RX PKT TLV headers 936 * 937 * Return: cce_metadata 938 */ 939 static uint16_t 940 hal_rx_msdu_cce_metadata_get_8074v1(uint8_t *buf) 941 { 942 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 943 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 944 945 return HAL_RX_MSDU_END_CCE_METADATA_GET(msdu_end); 946 } 947 948 /** 949 * hal_rx_msdu_get_flow_params_8074v1: API to get flow index, flow index invalid 950 * and flow index timeout from rx_msdu_end TLV 951 * @buf: pointer to the start of RX PKT TLV headers 952 * @flow_invalid: pointer to return value of flow_idx_valid 953 * @flow_timeout: pointer to return value of flow_idx_timeout 954 * @flow_index: pointer to return value of flow_idx 955 * 956 * Return: none 957 */ 958 static inline void 959 hal_rx_msdu_get_flow_params_8074v1(uint8_t *buf, 960 bool *flow_invalid, 961 bool *flow_timeout, 962 uint32_t *flow_index) 963 { 964 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 965 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 966 967 *flow_invalid = HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(msdu_end); 968 *flow_timeout = HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(msdu_end); 969 *flow_index = HAL_RX_MSDU_END_FLOW_IDX_GET(msdu_end); 970 } 971 972 /** 973 * hal_rx_tlv_get_tcp_chksum_8074v1() - API to get tcp checksum 974 * @buf: rx_tlv_hdr 975 * 976 * Return: tcp checksum 977 */ 978 static uint16_t 979 hal_rx_tlv_get_tcp_chksum_8074v1(uint8_t *buf) 980 { 981 return HAL_RX_TLV_GET_TCP_CHKSUM(buf); 982 } 983 984 /** 985 * hal_rx_get_rx_sequence_8074v1(): Function to retrieve rx sequence number 986 * 987 * @nbuf: Network buffer 988 * Returns: rx sequence number 989 */ 990 static 991 uint16_t hal_rx_get_rx_sequence_8074v1(uint8_t *buf) 992 { 993 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 994 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 995 996 return HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info); 997 } 998 999 /** 1000 * hal_rx_mpdu_start_tlv_tag_valid_8074v1 () - API to check if RX_MPDU_START 1001 * tlv tag is valid 1002 * 1003 * @rx_tlv_hdr: start address of rx_pkt_tlvs 1004 * 1005 * Return: true if RX_MPDU_START is valied, else false. 1006 */ 1007 uint8_t hal_rx_mpdu_start_tlv_tag_valid_8074v1(void *rx_tlv_hdr) 1008 { 1009 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)rx_tlv_hdr; 1010 uint32_t tlv_tag; 1011 1012 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE( 1013 &rx_desc->mpdu_start_tlv); 1014 1015 return tlv_tag == WIFIRX_MPDU_START_E ? true : false; 1016 } 1017 1018 /** 1019 * hal_rx_flow_setup_fse_8074v1() - Setup a flow search entry in HW FST 1020 * @fst: Pointer to the Rx Flow Search Table 1021 * @table_offset: offset into the table where the flow is to be setup 1022 * @flow: Flow Parameters 1023 * 1024 * Return: Success/Failure 1025 */ 1026 static void * 1027 hal_rx_flow_setup_fse_8074v1(uint8_t *rx_fst, uint32_t table_offset, 1028 uint8_t *rx_flow) 1029 { 1030 struct hal_rx_fst *fst = (struct hal_rx_fst *)rx_fst; 1031 struct hal_rx_flow *flow = (struct hal_rx_flow *)rx_flow; 1032 uint8_t *fse; 1033 bool fse_valid; 1034 1035 if (table_offset >= fst->max_entries) { 1036 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR, 1037 "HAL FSE table offset %u exceeds max entries %u", 1038 table_offset, fst->max_entries); 1039 return NULL; 1040 } 1041 1042 fse = (uint8_t *)fst->base_vaddr + 1043 (table_offset * HAL_RX_FST_ENTRY_SIZE); 1044 1045 fse_valid = HAL_GET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, VALID); 1046 1047 if (fse_valid) { 1048 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_DEBUG, 1049 "HAL FSE %pK already valid", fse); 1050 return NULL; 1051 } 1052 1053 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_0, SRC_IP_127_96) = 1054 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_0, SRC_IP_127_96, 1055 qdf_htonl(flow->tuple_info.src_ip_127_96)); 1056 1057 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_1, SRC_IP_95_64) = 1058 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_1, SRC_IP_95_64, 1059 qdf_htonl(flow->tuple_info.src_ip_95_64)); 1060 1061 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_2, SRC_IP_63_32) = 1062 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_2, SRC_IP_63_32, 1063 qdf_htonl(flow->tuple_info.src_ip_63_32)); 1064 1065 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_3, SRC_IP_31_0) = 1066 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_3, SRC_IP_31_0, 1067 qdf_htonl(flow->tuple_info.src_ip_31_0)); 1068 1069 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_4, DEST_IP_127_96) = 1070 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_4, DEST_IP_127_96, 1071 qdf_htonl(flow->tuple_info.dest_ip_127_96)); 1072 1073 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_5, DEST_IP_95_64) = 1074 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_5, DEST_IP_95_64, 1075 qdf_htonl(flow->tuple_info.dest_ip_95_64)); 1076 1077 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_6, DEST_IP_63_32) = 1078 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_6, DEST_IP_63_32, 1079 qdf_htonl(flow->tuple_info.dest_ip_63_32)); 1080 1081 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_7, DEST_IP_31_0) = 1082 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_7, DEST_IP_31_0, 1083 qdf_htonl(flow->tuple_info.dest_ip_31_0)); 1084 1085 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, DEST_PORT); 1086 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, DEST_PORT) |= 1087 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_8, DEST_PORT, 1088 (flow->tuple_info.dest_port)); 1089 1090 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, SRC_PORT); 1091 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, SRC_PORT) |= 1092 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_8, SRC_PORT, 1093 (flow->tuple_info.src_port)); 1094 1095 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, L4_PROTOCOL); 1096 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, L4_PROTOCOL) |= 1097 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, L4_PROTOCOL, 1098 flow->tuple_info.l4_protocol); 1099 1100 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_HANDLER); 1101 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_HANDLER) |= 1102 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_HANDLER, 1103 flow->reo_destination_handler); 1104 1105 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, VALID); 1106 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, VALID) |= 1107 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, VALID, 1); 1108 1109 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_10, METADATA); 1110 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_10, METADATA) = 1111 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_10, METADATA, 1112 flow->fse_metadata); 1113 1114 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_11, REO_DESTINATION_INDICATION); 1115 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_11, REO_DESTINATION_INDICATION) |= 1116 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_11, 1117 REO_DESTINATION_INDICATION, 1118 flow->reo_destination_indication); 1119 1120 /* Reset all the other fields in FSE */ 1121 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, RESERVED_9); 1122 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_11, MSDU_DROP); 1123 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_11, RESERVED_11); 1124 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_11, MSDU_COUNT); 1125 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_12, MSDU_BYTE_COUNT); 1126 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_13, TIMESTAMP); 1127 1128 return fse; 1129 } 1130 1131 static 1132 void hal_compute_reo_remap_ix2_ix3_8074v1(uint32_t *ring, uint32_t num_rings, 1133 uint32_t *remap1, uint32_t *remap2) 1134 { 1135 switch (num_rings) { 1136 case 3: 1137 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 1138 HAL_REO_REMAP_IX2(ring[1], 17) | 1139 HAL_REO_REMAP_IX2(ring[2], 18) | 1140 HAL_REO_REMAP_IX2(ring[0], 19) | 1141 HAL_REO_REMAP_IX2(ring[1], 20) | 1142 HAL_REO_REMAP_IX2(ring[2], 21) | 1143 HAL_REO_REMAP_IX2(ring[0], 22) | 1144 HAL_REO_REMAP_IX2(ring[1], 23); 1145 1146 *remap2 = HAL_REO_REMAP_IX3(ring[2], 24) | 1147 HAL_REO_REMAP_IX3(ring[0], 25) | 1148 HAL_REO_REMAP_IX3(ring[1], 26) | 1149 HAL_REO_REMAP_IX3(ring[2], 27) | 1150 HAL_REO_REMAP_IX3(ring[0], 28) | 1151 HAL_REO_REMAP_IX3(ring[1], 29) | 1152 HAL_REO_REMAP_IX3(ring[2], 30) | 1153 HAL_REO_REMAP_IX3(ring[0], 31); 1154 break; 1155 case 4: 1156 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 1157 HAL_REO_REMAP_IX2(ring[1], 17) | 1158 HAL_REO_REMAP_IX2(ring[2], 18) | 1159 HAL_REO_REMAP_IX2(ring[3], 19) | 1160 HAL_REO_REMAP_IX2(ring[0], 20) | 1161 HAL_REO_REMAP_IX2(ring[1], 21) | 1162 HAL_REO_REMAP_IX2(ring[2], 22) | 1163 HAL_REO_REMAP_IX2(ring[3], 23); 1164 1165 *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) | 1166 HAL_REO_REMAP_IX3(ring[1], 25) | 1167 HAL_REO_REMAP_IX3(ring[2], 26) | 1168 HAL_REO_REMAP_IX3(ring[3], 27) | 1169 HAL_REO_REMAP_IX3(ring[0], 28) | 1170 HAL_REO_REMAP_IX3(ring[1], 29) | 1171 HAL_REO_REMAP_IX3(ring[2], 30) | 1172 HAL_REO_REMAP_IX3(ring[3], 31); 1173 break; 1174 } 1175 } 1176 1177 struct hal_hw_txrx_ops qca8074_hal_hw_txrx_ops = { 1178 1179 /* init and setup */ 1180 hal_srng_dst_hw_init_generic, 1181 hal_srng_src_hw_init_generic, 1182 hal_get_hw_hptp_generic, 1183 hal_reo_setup_generic, 1184 hal_setup_link_idle_list_generic, 1185 hal_get_window_address_8074, 1186 NULL, 1187 1188 /* tx */ 1189 hal_tx_desc_set_dscp_tid_table_id_8074, 1190 hal_tx_set_dscp_tid_map_8074, 1191 hal_tx_update_dscp_tid_8074, 1192 hal_tx_desc_set_lmac_id_8074, 1193 hal_tx_desc_set_buf_addr_generic, 1194 hal_tx_desc_set_search_type_generic, 1195 hal_tx_desc_set_search_index_generic, 1196 hal_tx_desc_set_cache_set_num_generic, 1197 hal_tx_comp_get_status_generic, 1198 hal_tx_comp_get_release_reason_generic, 1199 hal_get_wbm_internal_error_generic, 1200 hal_tx_desc_set_mesh_en_8074v1, 1201 hal_tx_init_cmd_credit_ring_8074v1, 1202 1203 /* rx */ 1204 hal_rx_msdu_start_nss_get_8074, 1205 hal_rx_mon_hw_desc_get_mpdu_status_8074, 1206 hal_rx_get_tlv_8074, 1207 hal_rx_proc_phyrx_other_receive_info_tlv_8074, 1208 hal_rx_dump_msdu_start_tlv_8074, 1209 hal_rx_dump_msdu_end_tlv_8074, 1210 hal_get_link_desc_size_8074, 1211 hal_rx_mpdu_start_tid_get_8074, 1212 hal_rx_msdu_start_reception_type_get_8074, 1213 hal_rx_msdu_end_da_idx_get_8074, 1214 hal_rx_msdu_desc_info_get_ptr_8074v1, 1215 hal_rx_link_desc_msdu0_ptr_8074v1, 1216 hal_reo_status_get_header_8074v1, 1217 hal_rx_status_get_tlv_info_generic, 1218 hal_rx_wbm_err_info_get_generic, 1219 hal_rx_dump_mpdu_start_tlv_generic, 1220 1221 hal_tx_set_pcp_tid_map_generic, 1222 hal_tx_update_pcp_tid_generic, 1223 hal_tx_update_tidmap_prty_generic, 1224 hal_rx_get_rx_fragment_number_8074v1, 1225 hal_rx_msdu_end_da_is_mcbc_get_8074v1, 1226 hal_rx_msdu_end_sa_is_valid_get_8074v1, 1227 hal_rx_msdu_end_sa_idx_get_8074v1, 1228 hal_rx_desc_is_first_msdu_8074v1, 1229 hal_rx_msdu_end_l3_hdr_padding_get_8074v1, 1230 hal_rx_encryption_info_valid_8074v1, 1231 hal_rx_print_pn_8074v1, 1232 hal_rx_msdu_end_first_msdu_get_8074v1, 1233 hal_rx_msdu_end_da_is_valid_get_8074v1, 1234 hal_rx_msdu_end_last_msdu_get_8074v1, 1235 hal_rx_get_mpdu_mac_ad4_valid_8074v1, 1236 hal_rx_mpdu_start_sw_peer_id_get_8074v1, 1237 hal_rx_mpdu_get_to_ds_8074v1, 1238 hal_rx_mpdu_get_fr_ds_8074v1, 1239 hal_rx_get_mpdu_frame_control_valid_8074v1, 1240 hal_rx_mpdu_get_addr1_8074v1, 1241 hal_rx_mpdu_get_addr2_8074v1, 1242 hal_rx_mpdu_get_addr3_8074v1, 1243 hal_rx_mpdu_get_addr4_8074v1, 1244 hal_rx_get_mpdu_sequence_control_valid_8074v1, 1245 hal_rx_is_unicast_8074v1, 1246 hal_rx_tid_get_8074v1, 1247 hal_rx_hw_desc_get_ppduid_get_8074v1, 1248 hal_rx_mpdu_start_mpdu_qos_control_valid_get_8074v1, 1249 hal_rx_msdu_end_sa_sw_peer_id_get_8074v1, 1250 hal_rx_msdu0_buffer_addr_lsb_8074v1, 1251 hal_rx_msdu_desc_info_ptr_get_8074v1, 1252 hal_ent_mpdu_desc_info_8074v1, 1253 hal_dst_mpdu_desc_info_8074v1, 1254 hal_rx_get_fc_valid_8074v1, 1255 hal_rx_get_to_ds_flag_8074v1, 1256 hal_rx_get_mac_addr2_valid_8074v1, 1257 hal_rx_get_filter_category_8074v1, 1258 hal_rx_get_ppdu_id_8074v1, 1259 hal_reo_config_8074v1, 1260 hal_rx_msdu_flow_idx_get_8074v1, 1261 hal_rx_msdu_flow_idx_invalid_8074v1, 1262 hal_rx_msdu_flow_idx_timeout_8074v1, 1263 hal_rx_msdu_fse_metadata_get_8074v1, 1264 hal_rx_msdu_cce_metadata_get_8074v1, 1265 hal_rx_msdu_get_flow_params_8074v1, 1266 hal_rx_tlv_get_tcp_chksum_8074v1, 1267 hal_rx_get_rx_sequence_8074v1, 1268 NULL, 1269 NULL, 1270 /* rx - msdu fast path info fields */ 1271 hal_rx_msdu_packet_metadata_get_generic, 1272 NULL, 1273 NULL, 1274 NULL, 1275 NULL, 1276 NULL, 1277 NULL, 1278 hal_rx_mpdu_start_tlv_tag_valid_8074v1, 1279 NULL, 1280 NULL, 1281 1282 /* rx - TLV struct offsets */ 1283 hal_rx_msdu_end_offset_get_generic, 1284 hal_rx_attn_offset_get_generic, 1285 hal_rx_msdu_start_offset_get_generic, 1286 hal_rx_mpdu_start_offset_get_generic, 1287 hal_rx_mpdu_end_offset_get_generic, 1288 hal_rx_flow_setup_fse_8074v1, 1289 hal_compute_reo_remap_ix2_ix3_8074v1 1290 }; 1291 1292 struct hal_hw_srng_config hw_srng_table_8074[] = { 1293 /* TODO: max_rings can populated by querying HW capabilities */ 1294 { /* REO_DST */ 1295 .start_ring_id = HAL_SRNG_REO2SW1, 1296 .max_rings = 4, 1297 .entry_size = sizeof(struct reo_destination_ring) >> 2, 1298 .lmac_ring = FALSE, 1299 .ring_dir = HAL_SRNG_DST_RING, 1300 .reg_start = { 1301 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR( 1302 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1303 HWIO_REO_R2_REO2SW1_RING_HP_ADDR( 1304 SEQ_WCSS_UMAC_REO_REG_OFFSET) 1305 }, 1306 .reg_size = { 1307 HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(0) - 1308 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(0), 1309 HWIO_REO_R2_REO2SW2_RING_HP_ADDR(0) - 1310 HWIO_REO_R2_REO2SW1_RING_HP_ADDR(0), 1311 }, 1312 .max_size = 1313 HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_BMSK >> 1314 HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_SHFT, 1315 }, 1316 { /* REO_EXCEPTION */ 1317 /* Designating REO2TCL ring as exception ring. This ring is 1318 * similar to other REO2SW rings though it is named as REO2TCL. 1319 * Any of theREO2SW rings can be used as exception ring. 1320 */ 1321 .start_ring_id = HAL_SRNG_REO2TCL, 1322 .max_rings = 1, 1323 .entry_size = sizeof(struct reo_destination_ring) >> 2, 1324 .lmac_ring = FALSE, 1325 .ring_dir = HAL_SRNG_DST_RING, 1326 .reg_start = { 1327 HWIO_REO_R0_REO2TCL_RING_BASE_LSB_ADDR( 1328 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1329 HWIO_REO_R2_REO2TCL_RING_HP_ADDR( 1330 SEQ_WCSS_UMAC_REO_REG_OFFSET) 1331 }, 1332 /* Single ring - provide ring size if multiple rings of this 1333 * type are supported 1334 */ 1335 .reg_size = {}, 1336 .max_size = 1337 HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_BMSK >> 1338 HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_SHFT, 1339 }, 1340 { /* REO_REINJECT */ 1341 .start_ring_id = HAL_SRNG_SW2REO, 1342 .max_rings = 1, 1343 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 1344 .lmac_ring = FALSE, 1345 .ring_dir = HAL_SRNG_SRC_RING, 1346 .reg_start = { 1347 HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR( 1348 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1349 HWIO_REO_R2_SW2REO_RING_HP_ADDR( 1350 SEQ_WCSS_UMAC_REO_REG_OFFSET) 1351 }, 1352 /* Single ring - provide ring size if multiple rings of this 1353 * type are supported 1354 */ 1355 .reg_size = {}, 1356 .max_size = HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_BMSK >> 1357 HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_SHFT, 1358 }, 1359 { /* REO_CMD */ 1360 .start_ring_id = HAL_SRNG_REO_CMD, 1361 .max_rings = 1, 1362 .entry_size = (sizeof(struct tlv_32_hdr) + 1363 sizeof(struct reo_get_queue_stats)) >> 2, 1364 .lmac_ring = FALSE, 1365 .ring_dir = HAL_SRNG_SRC_RING, 1366 .reg_start = { 1367 HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR( 1368 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1369 HWIO_REO_R2_REO_CMD_RING_HP_ADDR( 1370 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1371 }, 1372 /* Single ring - provide ring size if multiple rings of this 1373 * type are supported 1374 */ 1375 .reg_size = {}, 1376 .max_size = HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_BMSK >> 1377 HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_SHFT, 1378 }, 1379 { /* REO_STATUS */ 1380 .start_ring_id = HAL_SRNG_REO_STATUS, 1381 .max_rings = 1, 1382 .entry_size = (sizeof(struct tlv_32_hdr) + 1383 sizeof(struct reo_get_queue_stats_status)) >> 2, 1384 .lmac_ring = FALSE, 1385 .ring_dir = HAL_SRNG_DST_RING, 1386 .reg_start = { 1387 HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR( 1388 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1389 HWIO_REO_R2_REO_STATUS_RING_HP_ADDR( 1390 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1391 }, 1392 /* Single ring - provide ring size if multiple rings of this 1393 * type are supported 1394 */ 1395 .reg_size = {}, 1396 .max_size = 1397 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> 1398 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, 1399 }, 1400 { /* TCL_DATA */ 1401 .start_ring_id = HAL_SRNG_SW2TCL1, 1402 .max_rings = 3, 1403 .entry_size = (sizeof(struct tlv_32_hdr) + 1404 sizeof(struct tcl_data_cmd)) >> 2, 1405 .lmac_ring = FALSE, 1406 .ring_dir = HAL_SRNG_SRC_RING, 1407 .reg_start = { 1408 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR( 1409 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1410 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR( 1411 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1412 }, 1413 .reg_size = { 1414 HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(0) - 1415 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(0), 1416 HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(0) - 1417 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(0), 1418 }, 1419 .max_size = 1420 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK >> 1421 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT, 1422 }, 1423 { /* TCL_CMD */ 1424 .start_ring_id = HAL_SRNG_SW2TCL_CMD, 1425 .max_rings = 1, 1426 .entry_size = (sizeof(struct tlv_32_hdr) + 1427 sizeof(struct tcl_data_cmd)) >> 2, 1428 .lmac_ring = FALSE, 1429 .ring_dir = HAL_SRNG_SRC_RING, 1430 .reg_start = { 1431 HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_ADDR( 1432 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1433 HWIO_TCL_R2_SW2TCL_CMD_RING_HP_ADDR( 1434 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1435 }, 1436 /* Single ring - provide ring size if multiple rings of this 1437 * type are supported 1438 */ 1439 .reg_size = {}, 1440 .max_size = 1441 HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RING_SIZE_BMSK >> 1442 HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RING_SIZE_SHFT, 1443 }, 1444 { /* TCL_STATUS */ 1445 .start_ring_id = HAL_SRNG_TCL_STATUS, 1446 .max_rings = 1, 1447 .entry_size = (sizeof(struct tlv_32_hdr) + 1448 sizeof(struct tcl_status_ring)) >> 2, 1449 .lmac_ring = FALSE, 1450 .ring_dir = HAL_SRNG_DST_RING, 1451 .reg_start = { 1452 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR( 1453 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1454 HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR( 1455 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1456 }, 1457 /* Single ring - provide ring size if multiple rings of this 1458 * type are supported 1459 */ 1460 .reg_size = {}, 1461 .max_size = 1462 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_BMSK >> 1463 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_SHFT, 1464 }, 1465 { /* CE_SRC */ 1466 .start_ring_id = HAL_SRNG_CE_0_SRC, 1467 .max_rings = 12, 1468 .entry_size = sizeof(struct ce_src_desc) >> 2, 1469 .lmac_ring = FALSE, 1470 .ring_dir = HAL_SRNG_SRC_RING, 1471 .reg_start = { 1472 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR( 1473 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET), 1474 HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR( 1475 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET), 1476 }, 1477 .reg_size = { 1478 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET - 1479 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET, 1480 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET - 1481 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET, 1482 }, 1483 .max_size = 1484 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >> 1485 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT, 1486 }, 1487 { /* CE_DST */ 1488 .start_ring_id = HAL_SRNG_CE_0_DST, 1489 .max_rings = 12, 1490 .entry_size = 8 >> 2, 1491 /*TODO: entry_size above should actually be 1492 * sizeof(struct ce_dst_desc) >> 2, but couldn't find definition 1493 * of struct ce_dst_desc in HW header files 1494 */ 1495 .lmac_ring = FALSE, 1496 .ring_dir = HAL_SRNG_SRC_RING, 1497 .reg_start = { 1498 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR( 1499 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 1500 HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR( 1501 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 1502 }, 1503 .reg_size = { 1504 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 1505 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 1506 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 1507 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 1508 }, 1509 .max_size = 1510 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >> 1511 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT, 1512 }, 1513 { /* CE_DST_STATUS */ 1514 .start_ring_id = HAL_SRNG_CE_0_DST_STATUS, 1515 .max_rings = 12, 1516 .entry_size = sizeof(struct ce_stat_desc) >> 2, 1517 .lmac_ring = FALSE, 1518 .ring_dir = HAL_SRNG_DST_RING, 1519 .reg_start = { 1520 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR( 1521 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 1522 HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR( 1523 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 1524 }, 1525 /* TODO: check destination status ring registers */ 1526 .reg_size = { 1527 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 1528 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 1529 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 1530 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 1531 }, 1532 .max_size = 1533 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> 1534 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, 1535 }, 1536 { /* WBM_IDLE_LINK */ 1537 .start_ring_id = HAL_SRNG_WBM_IDLE_LINK, 1538 .max_rings = 1, 1539 .entry_size = sizeof(struct wbm_link_descriptor_ring) >> 2, 1540 .lmac_ring = FALSE, 1541 .ring_dir = HAL_SRNG_SRC_RING, 1542 .reg_start = { 1543 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1544 HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1545 }, 1546 /* Single ring - provide ring size if multiple rings of this 1547 * type are supported 1548 */ 1549 .reg_size = {}, 1550 .max_size = 1551 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_BMSK >> 1552 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_SHFT, 1553 }, 1554 { /* SW2WBM_RELEASE */ 1555 .start_ring_id = HAL_SRNG_WBM_SW_RELEASE, 1556 .max_rings = 1, 1557 .entry_size = sizeof(struct wbm_release_ring) >> 2, 1558 .lmac_ring = FALSE, 1559 .ring_dir = HAL_SRNG_SRC_RING, 1560 .reg_start = { 1561 HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1562 HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1563 }, 1564 /* Single ring - provide ring size if multiple rings of this 1565 * type are supported 1566 */ 1567 .reg_size = {}, 1568 .max_size = 1569 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> 1570 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, 1571 }, 1572 { /* WBM2SW_RELEASE */ 1573 .start_ring_id = HAL_SRNG_WBM2SW0_RELEASE, 1574 .max_rings = 4, 1575 .entry_size = sizeof(struct wbm_release_ring) >> 2, 1576 .lmac_ring = FALSE, 1577 .ring_dir = HAL_SRNG_DST_RING, 1578 .reg_start = { 1579 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1580 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1581 }, 1582 .reg_size = { 1583 HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) - 1584 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1585 HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) - 1586 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1587 }, 1588 .max_size = 1589 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> 1590 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, 1591 }, 1592 { /* RXDMA_BUF */ 1593 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA0_BUF0, 1594 #ifdef IPA_OFFLOAD 1595 .max_rings = 3, 1596 #else 1597 .max_rings = 2, 1598 #endif 1599 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 1600 .lmac_ring = TRUE, 1601 .ring_dir = HAL_SRNG_SRC_RING, 1602 /* reg_start is not set because LMAC rings are not accessed 1603 * from host 1604 */ 1605 .reg_start = {}, 1606 .reg_size = {}, 1607 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1608 }, 1609 { /* RXDMA_DST */ 1610 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW0, 1611 .max_rings = 1, 1612 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 1613 .lmac_ring = TRUE, 1614 .ring_dir = HAL_SRNG_DST_RING, 1615 /* reg_start is not set because LMAC rings are not accessed 1616 * from host 1617 */ 1618 .reg_start = {}, 1619 .reg_size = {}, 1620 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1621 }, 1622 { /* RXDMA_MONITOR_BUF */ 1623 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA2_BUF, 1624 .max_rings = 1, 1625 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 1626 .lmac_ring = TRUE, 1627 .ring_dir = HAL_SRNG_SRC_RING, 1628 /* reg_start is not set because LMAC rings are not accessed 1629 * from host 1630 */ 1631 .reg_start = {}, 1632 .reg_size = {}, 1633 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1634 }, 1635 { /* RXDMA_MONITOR_STATUS */ 1636 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_STATBUF, 1637 .max_rings = 1, 1638 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 1639 .lmac_ring = TRUE, 1640 .ring_dir = HAL_SRNG_SRC_RING, 1641 /* reg_start is not set because LMAC rings are not accessed 1642 * from host 1643 */ 1644 .reg_start = {}, 1645 .reg_size = {}, 1646 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1647 }, 1648 { /* RXDMA_MONITOR_DST */ 1649 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW1, 1650 .max_rings = 1, 1651 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 1652 .lmac_ring = TRUE, 1653 .ring_dir = HAL_SRNG_DST_RING, 1654 /* reg_start is not set because LMAC rings are not accessed 1655 * from host 1656 */ 1657 .reg_start = {}, 1658 .reg_size = {}, 1659 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1660 }, 1661 { /* RXDMA_MONITOR_DESC */ 1662 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_DESC, 1663 .max_rings = 1, 1664 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 1665 .lmac_ring = TRUE, 1666 .ring_dir = HAL_SRNG_SRC_RING, 1667 /* reg_start is not set because LMAC rings are not accessed 1668 * from host 1669 */ 1670 .reg_start = {}, 1671 .reg_size = {}, 1672 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1673 }, 1674 { /* DIR_BUF_RX_DMA_SRC */ 1675 .start_ring_id = HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING, 1676 .max_rings = 1, 1677 .entry_size = 2, 1678 .lmac_ring = TRUE, 1679 .ring_dir = HAL_SRNG_SRC_RING, 1680 /* reg_start is not set because LMAC rings are not accessed 1681 * from host 1682 */ 1683 .reg_start = {}, 1684 .reg_size = {}, 1685 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1686 }, 1687 #ifdef WLAN_FEATURE_CIF_CFR 1688 { /* WIFI_POS_SRC */ 1689 .start_ring_id = HAL_SRNG_WIFI_POS_SRC_DMA_RING, 1690 .max_rings = 1, 1691 .entry_size = sizeof(wmi_oem_dma_buf_release_entry) >> 2, 1692 .lmac_ring = TRUE, 1693 .ring_dir = HAL_SRNG_SRC_RING, 1694 /* reg_start is not set because LMAC rings are not accessed 1695 * from host 1696 */ 1697 .reg_start = {}, 1698 .reg_size = {}, 1699 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1700 }, 1701 #endif 1702 }; 1703 1704 int32_t hal_hw_reg_offset_qca8074[] = { 1705 /* dst */ 1706 REG_OFFSET(DST, HP), 1707 REG_OFFSET(DST, TP), 1708 REG_OFFSET(DST, ID), 1709 REG_OFFSET(DST, MISC), 1710 REG_OFFSET(DST, HP_ADDR_LSB), 1711 REG_OFFSET(DST, HP_ADDR_MSB), 1712 REG_OFFSET(DST, MSI1_BASE_LSB), 1713 REG_OFFSET(DST, MSI1_BASE_MSB), 1714 REG_OFFSET(DST, MSI1_DATA), 1715 REG_OFFSET(DST, BASE_LSB), 1716 REG_OFFSET(DST, BASE_MSB), 1717 REG_OFFSET(DST, PRODUCER_INT_SETUP), 1718 /* src */ 1719 REG_OFFSET(SRC, HP), 1720 REG_OFFSET(SRC, TP), 1721 REG_OFFSET(SRC, ID), 1722 REG_OFFSET(SRC, MISC), 1723 REG_OFFSET(SRC, TP_ADDR_LSB), 1724 REG_OFFSET(SRC, TP_ADDR_MSB), 1725 REG_OFFSET(SRC, MSI1_BASE_LSB), 1726 REG_OFFSET(SRC, MSI1_BASE_MSB), 1727 REG_OFFSET(SRC, MSI1_DATA), 1728 REG_OFFSET(SRC, BASE_LSB), 1729 REG_OFFSET(SRC, BASE_MSB), 1730 REG_OFFSET(SRC, CONSUMER_INT_SETUP_IX0), 1731 REG_OFFSET(SRC, CONSUMER_INT_SETUP_IX1), 1732 }; 1733 1734 /** 1735 * hal_qca8074_attach() - Attach 8074 target specific hal_soc ops, 1736 * offset and srng table 1737 */ 1738 void hal_qca8074_attach(struct hal_soc *hal_soc) 1739 { 1740 hal_soc->hw_srng_table = hw_srng_table_8074; 1741 hal_soc->hal_hw_reg_offset = hal_hw_reg_offset_qca8074; 1742 hal_soc->ops = &qca8074_hal_hw_txrx_ops; 1743 } 1744