1 /* 2 * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 #include "hal_li_hw_headers.h" 19 #include "hal_internal.h" 20 #include "hal_api.h" 21 #include "target_type.h" 22 #include "wcss_version.h" 23 #include "qdf_module.h" 24 #include "hal_flow.h" 25 #include "rx_flow_search_entry.h" 26 #include "hal_rx_flow_info.h" 27 28 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_OFFSET \ 29 RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_OFFSET 30 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_MASK \ 31 RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_MASK 32 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_LSB \ 33 RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_LSB 34 #define UNIFIED_PHYRX_HT_SIG_0_HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS_OFFSET \ 35 PHYRX_HT_SIG_0_HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS_OFFSET 36 #define UNIFIED_PHYRX_L_SIG_B_0_L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS_OFFSET \ 37 PHYRX_L_SIG_B_0_L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS_OFFSET 38 #define UNIFIED_PHYRX_L_SIG_A_0_L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS_OFFSET \ 39 PHYRX_L_SIG_A_0_L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS_OFFSET 40 #define UNIFIED_PHYRX_VHT_SIG_A_0_VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS_OFFSET \ 41 PHYRX_VHT_SIG_A_0_VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS_OFFSET 42 #define UNIFIED_PHYRX_HE_SIG_A_SU_0_HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS_OFFSET \ 43 PHYRX_HE_SIG_A_SU_0_HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS_OFFSET 44 #define UNIFIED_PHYRX_HE_SIG_A_MU_DL_0_HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_OFFSET \ 45 PHYRX_HE_SIG_A_MU_DL_0_HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_OFFSET 46 #define UNIFIED_PHYRX_HE_SIG_B1_MU_0_HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_OFFSET \ 47 PHYRX_HE_SIG_B1_MU_0_HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_OFFSET 48 #define UNIFIED_PHYRX_HE_SIG_B2_MU_0_HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_OFFSET \ 49 PHYRX_HE_SIG_B2_MU_0_HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_OFFSET 50 #define UNIFIED_PHYRX_HE_SIG_B2_OFDMA_0_HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_OFFSET \ 51 PHYRX_HE_SIG_B2_OFDMA_0_HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_OFFSET 52 #define UNIFIED_PHYRX_RSSI_LEGACY_3_RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS_OFFSET \ 53 PHYRX_RSSI_LEGACY_3_RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS_OFFSET 54 #define UNIFIED_PHYRX_RSSI_LEGACY_19_RECEIVE_RSSI_INFO_PREAMBLE_RSSI_INFO_DETAILS_OFFSET \ 55 PHYRX_RSSI_LEGACY_19_RECEIVE_RSSI_INFO_PREAMBLE_RSSI_INFO_DETAILS_OFFSET 56 #define UNIFIED_RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET \ 57 RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET 58 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 59 RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET 60 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ 61 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET 62 #define UNIFIED_RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 63 RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET 64 #define UNIFIED_REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 65 REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET 66 #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC \ 67 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER 68 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSE \ 69 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET 70 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 71 RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET 72 #define UNIFIED_TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 73 TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET 74 #define UNIFIED_TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 75 TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET 76 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET \ 77 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET 78 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB \ 79 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB 80 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK \ 81 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK 82 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB \ 83 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB 84 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK \ 85 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK 86 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB \ 87 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB 88 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK \ 89 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK 90 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB \ 91 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB 92 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK \ 93 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK 94 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB \ 95 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB 96 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK \ 97 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK 98 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_MASK \ 99 WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_MASK 100 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_OFFSET \ 101 WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_OFFSET 102 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_LSB \ 103 WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_LSB 104 105 #include "hal_8074v1_tx.h" 106 #include "hal_8074v1_rx.h" 107 #include <hal_generic_api.h> 108 #include "hal_li_rx.h" 109 #include "hal_li_tx.h" 110 #include "hal_li_api.h" 111 #include "hal_li_generic_api.h" 112 113 /** 114 * hal_get_window_address_8074(): Function to get hp/tp address 115 * @hal_soc: Pointer to hal_soc 116 * @addr: address offset of register 117 * 118 * Return: modified address offset of register 119 */ 120 static inline qdf_iomem_t hal_get_window_address_8074(struct hal_soc *hal_soc, 121 qdf_iomem_t addr) 122 { 123 return addr; 124 } 125 126 /** 127 * hal_rx_get_rx_fragment_number_8074v1(): Function to retrieve 128 * rx fragment number 129 * 130 * @nbuf: Network buffer 131 * Returns: rx fragment number 132 */ 133 static 134 uint8_t hal_rx_get_rx_fragment_number_8074v1(uint8_t *buf) 135 { 136 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 137 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 138 139 /* Return first 4 bits as fragment number */ 140 return (HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info) & 141 DOT11_SEQ_FRAG_MASK); 142 } 143 144 /** 145 * hal_rx_msdu_end_da_is_mcbc_get_8074v1(): API to check if 146 * pkt is MCBC from rx_msdu_end TLV 147 * 148 * @ buf: pointer to the start of RX PKT TLV headers 149 * Return: da_is_mcbc 150 */ 151 static uint8_t 152 hal_rx_msdu_end_da_is_mcbc_get_8074v1(uint8_t *buf) 153 { 154 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 155 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 156 157 return HAL_RX_MSDU_END_DA_IS_MCBC_GET(msdu_end); 158 } 159 160 /** 161 * hal_rx_msdu_end_sa_is_valid_get_8074v1(): API to get_8074v1 the 162 * sa_is_valid bit from rx_msdu_end TLV 163 * 164 * @ buf: pointer to the start of RX PKT TLV headers 165 * Return: sa_is_valid bit 166 */ 167 static uint8_t 168 hal_rx_msdu_end_sa_is_valid_get_8074v1(uint8_t *buf) 169 { 170 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 171 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 172 uint8_t sa_is_valid; 173 174 sa_is_valid = HAL_RX_MSDU_END_SA_IS_VALID_GET(msdu_end); 175 176 return sa_is_valid; 177 } 178 179 /** 180 * hal_rx_msdu_end_sa_idx_get_8074v1(): API to get_8074v1 the 181 * sa_idx from rx_msdu_end TLV 182 * 183 * @ buf: pointer to the start of RX PKT TLV headers 184 * Return: sa_idx (SA AST index) 185 */ 186 static uint16_t hal_rx_msdu_end_sa_idx_get_8074v1(uint8_t *buf) 187 { 188 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 189 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 190 uint16_t sa_idx; 191 192 sa_idx = HAL_RX_MSDU_END_SA_IDX_GET(msdu_end); 193 194 return sa_idx; 195 } 196 197 /** 198 * hal_rx_desc_is_first_msdu_8074v1() - Check if first msdu 199 * 200 * @hal_soc_hdl: hal_soc handle 201 * @hw_desc_addr: hardware descriptor address 202 * 203 * Return: 0 - success/ non-zero failure 204 */ 205 static uint32_t hal_rx_desc_is_first_msdu_8074v1(void *hw_desc_addr) 206 { 207 struct rx_pkt_tlvs *rx_tlvs = (struct rx_pkt_tlvs *)hw_desc_addr; 208 struct rx_msdu_end *msdu_end = &rx_tlvs->msdu_end_tlv.rx_msdu_end; 209 210 return HAL_RX_GET(msdu_end, RX_MSDU_END_5, FIRST_MSDU); 211 } 212 213 /** 214 * hal_rx_msdu_end_l3_hdr_padding_get_8074v1(): API to get_8074v1 the 215 * l3_header padding from rx_msdu_end TLV 216 * 217 * @ buf: pointer to the start of RX PKT TLV headers 218 * Return: number of l3 header padding bytes 219 */ 220 static uint32_t hal_rx_msdu_end_l3_hdr_padding_get_8074v1(uint8_t *buf) 221 { 222 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 223 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 224 uint32_t l3_header_padding; 225 226 l3_header_padding = HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(msdu_end); 227 228 return l3_header_padding; 229 } 230 231 /* 232 * @ hal_rx_encryption_info_valid_8074v1: Returns encryption type. 233 * 234 * @ buf: rx_tlv_hdr of the received packet 235 * @ Return: encryption type 236 */ 237 static uint32_t hal_rx_encryption_info_valid_8074v1(uint8_t *buf) 238 { 239 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 240 struct rx_mpdu_start *mpdu_start = 241 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 242 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 243 uint32_t encryption_info = HAL_RX_MPDU_ENCRYPTION_INFO_VALID(mpdu_info); 244 245 return encryption_info; 246 } 247 248 /* 249 * @ hal_rx_print_pn_8074v1: Prints the PN of rx packet. 250 * 251 * @ buf: rx_tlv_hdr of the received packet 252 * @ Return: void 253 */ 254 static void hal_rx_print_pn_8074v1(uint8_t *buf) 255 { 256 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 257 struct rx_mpdu_start *mpdu_start = 258 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 259 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 260 261 uint32_t pn_31_0 = HAL_RX_MPDU_PN_31_0_GET(mpdu_info); 262 uint32_t pn_63_32 = HAL_RX_MPDU_PN_63_32_GET(mpdu_info); 263 uint32_t pn_95_64 = HAL_RX_MPDU_PN_95_64_GET(mpdu_info); 264 uint32_t pn_127_96 = HAL_RX_MPDU_PN_127_96_GET(mpdu_info); 265 266 hal_debug("PN number pn_127_96 0x%x pn_95_64 0x%x pn_63_32 0x%x pn_31_0 0x%x ", 267 pn_127_96, pn_95_64, pn_63_32, pn_31_0); 268 } 269 270 /** 271 * hal_rx_msdu_end_first_msdu_get_8074v1: API to get first msdu status 272 * from rx_msdu_end TLV 273 * 274 * @ buf: pointer to the start of RX PKT TLV headers 275 * Return: first_msdu 276 */ 277 static uint8_t 278 hal_rx_msdu_end_first_msdu_get_8074v1(uint8_t *buf) 279 { 280 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 281 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 282 uint8_t first_msdu; 283 284 first_msdu = HAL_RX_MSDU_END_FIRST_MSDU_GET(msdu_end); 285 286 return first_msdu; 287 } 288 289 /** 290 * hal_rx_msdu_end_da_is_valid_get_8074v1: API to check if da is valid 291 * from rx_msdu_end TLV 292 * 293 * @ buf: pointer to the start of RX PKT TLV headers 294 * Return: da_is_valid 295 */ 296 static uint8_t hal_rx_msdu_end_da_is_valid_get_8074v1(uint8_t *buf) 297 { 298 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 299 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 300 uint8_t da_is_valid; 301 302 da_is_valid = HAL_RX_MSDU_END_DA_IS_VALID_GET(msdu_end); 303 304 return da_is_valid; 305 } 306 307 /** 308 * hal_rx_msdu_end_last_msdu_get_8074v1: API to get last msdu status 309 * from rx_msdu_end TLV 310 * 311 * @ buf: pointer to the start of RX PKT TLV headers 312 * Return: last_msdu 313 */ 314 static uint8_t hal_rx_msdu_end_last_msdu_get_8074v1(uint8_t *buf) 315 { 316 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 317 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 318 uint8_t last_msdu; 319 320 last_msdu = HAL_RX_MSDU_END_LAST_MSDU_GET(msdu_end); 321 322 return last_msdu; 323 } 324 325 /* 326 * hal_rx_get_mpdu_mac_ad4_valid_8074v1(): Retrieves if mpdu 4th addr is valid 327 * 328 * @nbuf: Network buffer 329 * Returns: value of mpdu 4th address valid field 330 */ 331 static bool hal_rx_get_mpdu_mac_ad4_valid_8074v1(uint8_t *buf) 332 { 333 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 334 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 335 bool ad4_valid = 0; 336 337 ad4_valid = HAL_RX_MPDU_GET_MAC_AD4_VALID(rx_mpdu_info); 338 339 return ad4_valid; 340 } 341 342 /** 343 * hal_rx_mpdu_start_sw_peer_id_get_8074v1: Retrieve sw peer_id 344 * @buf: network buffer 345 * 346 * Return: sw peer_id 347 */ 348 static uint32_t hal_rx_mpdu_start_sw_peer_id_get_8074v1(uint8_t *buf) 349 { 350 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 351 struct rx_mpdu_start *mpdu_start = 352 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 353 354 return HAL_RX_MPDU_INFO_SW_PEER_ID_GET( 355 &mpdu_start->rx_mpdu_info_details); 356 } 357 358 /* 359 * hal_rx_mpdu_get_to_ds_8074v1(): API to get the tods info 360 * from rx_mpdu_start 361 * 362 * @buf: pointer to the start of RX PKT TLV header 363 * Return: uint32_t(to_ds) 364 */ 365 366 static uint32_t hal_rx_mpdu_get_to_ds_8074v1(uint8_t *buf) 367 { 368 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 369 struct rx_mpdu_start *mpdu_start = 370 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 371 372 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 373 374 return HAL_RX_MPDU_GET_TODS(mpdu_info); 375 } 376 377 /* 378 * hal_rx_mpdu_get_fr_ds_8074v1(): API to get the from ds info 379 * from rx_mpdu_start 380 * 381 * @buf: pointer to the start of RX PKT TLV header 382 * Return: uint32_t(fr_ds) 383 */ 384 static uint32_t hal_rx_mpdu_get_fr_ds_8074v1(uint8_t *buf) 385 { 386 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 387 struct rx_mpdu_start *mpdu_start = 388 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 389 390 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 391 392 return HAL_RX_MPDU_GET_FROMDS(mpdu_info); 393 } 394 395 /* 396 * hal_rx_get_mpdu_frame_control_valid_8074v1(): Retrieves mpdu 397 * frame control valid 398 * 399 * @nbuf: Network buffer 400 * Returns: value of frame control valid field 401 */ 402 static uint8_t hal_rx_get_mpdu_frame_control_valid_8074v1(uint8_t *buf) 403 { 404 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 405 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 406 407 return HAL_RX_MPDU_GET_FRAME_CONTROL_VALID(rx_mpdu_info); 408 } 409 410 /* 411 * hal_rx_mpdu_get_addr1_8074v1(): API to check get address1 of the mpdu 412 * 413 * @buf: pointer to the start of RX PKT TLV headera 414 * @mac_addr: pointer to mac address 415 * Return: success/failure 416 */ 417 static QDF_STATUS hal_rx_mpdu_get_addr1_8074v1(uint8_t *buf, 418 uint8_t *mac_addr) 419 { 420 struct __attribute__((__packed__)) hal_addr1 { 421 uint32_t ad1_31_0; 422 uint16_t ad1_47_32; 423 }; 424 425 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 426 struct rx_mpdu_start *mpdu_start = 427 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 428 429 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 430 struct hal_addr1 *addr = (struct hal_addr1 *)mac_addr; 431 uint32_t mac_addr_ad1_valid; 432 433 mac_addr_ad1_valid = HAL_RX_MPDU_MAC_ADDR_AD1_VALID_GET(mpdu_info); 434 435 if (mac_addr_ad1_valid) { 436 addr->ad1_31_0 = HAL_RX_MPDU_AD1_31_0_GET(mpdu_info); 437 addr->ad1_47_32 = HAL_RX_MPDU_AD1_47_32_GET(mpdu_info); 438 return QDF_STATUS_SUCCESS; 439 } 440 441 return QDF_STATUS_E_FAILURE; 442 } 443 444 /* 445 * hal_rx_mpdu_get_addr2_8074v1(): API to check get address2 of the mpdu 446 * in the packet 447 * 448 * @buf: pointer to the start of RX PKT TLV header 449 * @mac_addr: pointer to mac address 450 * Return: success/failure 451 */ 452 static QDF_STATUS hal_rx_mpdu_get_addr2_8074v1(uint8_t *buf, uint8_t *mac_addr) 453 { 454 struct __attribute__((__packed__)) hal_addr2 { 455 uint16_t ad2_15_0; 456 uint32_t ad2_47_16; 457 }; 458 459 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 460 struct rx_mpdu_start *mpdu_start = 461 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 462 463 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 464 struct hal_addr2 *addr = (struct hal_addr2 *)mac_addr; 465 uint32_t mac_addr_ad2_valid; 466 467 mac_addr_ad2_valid = HAL_RX_MPDU_MAC_ADDR_AD2_VALID_GET(mpdu_info); 468 469 if (mac_addr_ad2_valid) { 470 addr->ad2_15_0 = HAL_RX_MPDU_AD2_15_0_GET(mpdu_info); 471 addr->ad2_47_16 = HAL_RX_MPDU_AD2_47_16_GET(mpdu_info); 472 return QDF_STATUS_SUCCESS; 473 } 474 475 return QDF_STATUS_E_FAILURE; 476 } 477 478 /* 479 * hal_rx_mpdu_get_addr3_8074v1(): API to get address3 of the mpdu 480 * in the packet 481 * 482 * @buf: pointer to the start of RX PKT TLV header 483 * @mac_addr: pointer to mac address 484 * Return: success/failure 485 */ 486 static QDF_STATUS hal_rx_mpdu_get_addr3_8074v1(uint8_t *buf, uint8_t *mac_addr) 487 { 488 struct __attribute__((__packed__)) hal_addr3 { 489 uint32_t ad3_31_0; 490 uint16_t ad3_47_32; 491 }; 492 493 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 494 struct rx_mpdu_start *mpdu_start = 495 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 496 497 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 498 struct hal_addr3 *addr = (struct hal_addr3 *)mac_addr; 499 uint32_t mac_addr_ad3_valid; 500 501 mac_addr_ad3_valid = HAL_RX_MPDU_MAC_ADDR_AD3_VALID_GET(mpdu_info); 502 503 if (mac_addr_ad3_valid) { 504 addr->ad3_31_0 = HAL_RX_MPDU_AD3_31_0_GET(mpdu_info); 505 addr->ad3_47_32 = HAL_RX_MPDU_AD3_47_32_GET(mpdu_info); 506 return QDF_STATUS_SUCCESS; 507 } 508 509 return QDF_STATUS_E_FAILURE; 510 } 511 512 /* 513 * hal_rx_mpdu_get_addr4_8074v1(): API to get address4 of the mpdu 514 * in the packet 515 * 516 * @buf: pointer to the start of RX PKT TLV header 517 * @mac_addr: pointer to mac address 518 * Return: success/failure 519 */ 520 static QDF_STATUS hal_rx_mpdu_get_addr4_8074v1(uint8_t *buf, uint8_t *mac_addr) 521 { 522 struct __attribute__((__packed__)) hal_addr4 { 523 uint32_t ad4_31_0; 524 uint16_t ad4_47_32; 525 }; 526 527 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 528 struct rx_mpdu_start *mpdu_start = 529 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 530 531 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 532 struct hal_addr4 *addr = (struct hal_addr4 *)mac_addr; 533 uint32_t mac_addr_ad4_valid; 534 535 mac_addr_ad4_valid = HAL_RX_MPDU_MAC_ADDR_AD4_VALID_GET(mpdu_info); 536 537 if (mac_addr_ad4_valid) { 538 addr->ad4_31_0 = HAL_RX_MPDU_AD4_31_0_GET(mpdu_info); 539 addr->ad4_47_32 = HAL_RX_MPDU_AD4_47_32_GET(mpdu_info); 540 return QDF_STATUS_SUCCESS; 541 } 542 543 return QDF_STATUS_E_FAILURE; 544 } 545 546 /* 547 * hal_rx_get_mpdu_sequence_control_valid_8074v1(): Get mpdu 548 * sequence control valid 549 * 550 * @nbuf: Network buffer 551 * Returns: value of sequence control valid field 552 */ 553 static uint8_t hal_rx_get_mpdu_sequence_control_valid_8074v1(uint8_t *buf) 554 { 555 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 556 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 557 558 return HAL_RX_MPDU_GET_SEQUENCE_CONTROL_VALID(rx_mpdu_info); 559 } 560 561 /** 562 * hal_rx_is_unicast_8074v1: check packet is unicast frame or not. 563 * 564 * @ buf: pointer to rx pkt TLV. 565 * 566 * Return: true on unicast. 567 */ 568 static bool hal_rx_is_unicast_8074v1(uint8_t *buf) 569 { 570 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 571 struct rx_mpdu_start *mpdu_start = 572 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 573 uint32_t grp_id; 574 uint8_t *rx_mpdu_info = (uint8_t *)&mpdu_start->rx_mpdu_info_details; 575 576 grp_id = (_HAL_MS((*_OFFSET_TO_WORD_PTR((rx_mpdu_info), 577 RX_MPDU_INFO_0_SW_FRAME_GROUP_ID_OFFSET)), 578 RX_MPDU_INFO_0_SW_FRAME_GROUP_ID_MASK, 579 RX_MPDU_INFO_0_SW_FRAME_GROUP_ID_LSB)); 580 581 return (HAL_MPDU_SW_FRAME_GROUP_UNICAST_DATA == grp_id) ? true : false; 582 } 583 584 /** 585 * hal_rx_tid_get_8074v1: get tid based on qos control valid. 586 * 587 * @ buf: pointer to rx pkt TLV. 588 * 589 * Return: tid 590 */ 591 static uint32_t hal_rx_tid_get_8074v1(hal_soc_handle_t hal_soc_hdl, 592 uint8_t *buf) 593 { 594 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 595 struct rx_mpdu_start *mpdu_start = 596 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 597 uint8_t *rx_mpdu_info = (uint8_t *)&mpdu_start->rx_mpdu_info_details; 598 uint8_t qos_control_valid = 599 (_HAL_MS((*_OFFSET_TO_WORD_PTR((rx_mpdu_info), 600 RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_OFFSET)), 601 RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_MASK, 602 RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_LSB)); 603 604 if (qos_control_valid) 605 return hal_rx_mpdu_start_tid_get_8074(buf); 606 607 return HAL_RX_NON_QOS_TID; 608 } 609 610 /** 611 * hal_rx_hw_desc_get_ppduid_get_8074v1(): retrieve ppdu id 612 * @rx_tlv_hdr: Rx tlv header 613 * @rxdma_dst_ring_desc: Rx HW descriptor 614 * 615 * Return: ppdu id 616 */ 617 static uint32_t hal_rx_hw_desc_get_ppduid_get_8074v1(void *rx_tlv_hdr, 618 void *rxdma_dst_ring_desc) 619 { 620 struct rx_mpdu_info *rx_mpdu_info; 621 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)rx_tlv_hdr; 622 623 rx_mpdu_info = 624 &rx_desc->mpdu_start_tlv.rx_mpdu_start.rx_mpdu_info_details; 625 626 return HAL_RX_GET(rx_mpdu_info, RX_MPDU_INFO_0, PHY_PPDU_ID); 627 } 628 629 /** 630 * hal_reo_status_get_header_8074v1 - Process reo desc info 631 * @ring_desc: REO status ring descriptor 632 * @b - tlv type info 633 * @h1 - Pointer to hal_reo_status_header where info to be stored 634 * 635 * Return - none. 636 * 637 */ 638 static void hal_reo_status_get_header_8074v1(hal_ring_desc_t ring_desc, int b, 639 void *h1) 640 { 641 uint32_t *d = (uint32_t *)ring_desc; 642 uint32_t val1 = 0; 643 struct hal_reo_status_header *h = 644 (struct hal_reo_status_header *)h1; 645 646 /* Offsets of descriptor fields defined in HW headers start 647 * from the field after TLV header 648 */ 649 d += HAL_GET_NUM_DWORDS(sizeof(struct tlv_32_hdr)); 650 651 switch (b) { 652 case HAL_REO_QUEUE_STATS_STATUS_TLV: 653 val1 = d[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_0, 654 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 655 break; 656 case HAL_REO_FLUSH_QUEUE_STATUS_TLV: 657 val1 = d[HAL_OFFSET_DW(REO_FLUSH_QUEUE_STATUS_0, 658 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 659 break; 660 case HAL_REO_FLUSH_CACHE_STATUS_TLV: 661 val1 = d[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_0, 662 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 663 break; 664 case HAL_REO_UNBLK_CACHE_STATUS_TLV: 665 val1 = d[HAL_OFFSET_DW(REO_UNBLOCK_CACHE_STATUS_0, 666 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 667 break; 668 case HAL_REO_TIMOUT_LIST_STATUS_TLV: 669 val1 = d[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_0, 670 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 671 break; 672 case HAL_REO_DESC_THRES_STATUS_TLV: 673 val1 = 674 d[HAL_OFFSET_DW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0, 675 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 676 break; 677 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: 678 val1 = d[HAL_OFFSET_DW(REO_UPDATE_RX_REO_QUEUE_STATUS_0, 679 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 680 break; 681 default: 682 qdf_nofl_err("ERROR: Unknown tlv\n"); 683 break; 684 } 685 h->cmd_num = 686 HAL_GET_FIELD( 687 UNIFORM_REO_STATUS_HEADER_0, REO_STATUS_NUMBER, 688 val1); 689 h->exec_time = 690 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_0, 691 CMD_EXECUTION_TIME, val1); 692 h->status = 693 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_0, 694 REO_CMD_EXECUTION_STATUS, val1); 695 switch (b) { 696 case HAL_REO_QUEUE_STATS_STATUS_TLV: 697 val1 = d[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_1, 698 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 699 break; 700 case HAL_REO_FLUSH_QUEUE_STATUS_TLV: 701 val1 = d[HAL_OFFSET_DW(REO_FLUSH_QUEUE_STATUS_1, 702 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 703 break; 704 case HAL_REO_FLUSH_CACHE_STATUS_TLV: 705 val1 = d[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_1, 706 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 707 break; 708 case HAL_REO_UNBLK_CACHE_STATUS_TLV: 709 val1 = d[HAL_OFFSET_DW(REO_UNBLOCK_CACHE_STATUS_1, 710 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 711 break; 712 case HAL_REO_TIMOUT_LIST_STATUS_TLV: 713 val1 = d[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_1, 714 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 715 break; 716 case HAL_REO_DESC_THRES_STATUS_TLV: 717 val1 = 718 d[HAL_OFFSET_DW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_1, 719 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 720 break; 721 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: 722 val1 = d[HAL_OFFSET_DW(REO_UPDATE_RX_REO_QUEUE_STATUS_1, 723 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 724 break; 725 default: 726 qdf_nofl_err("ERROR: Unknown tlv\n"); 727 break; 728 } 729 h->tstamp = 730 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_1, TIMESTAMP, val1); 731 } 732 733 /** 734 * hal_rx_mpdu_start_mpdu_qos_control_valid_get_8074v1(): 735 * Retrieve qos control valid bit from the tlv. 736 * @buf: pointer to rx pkt TLV. 737 * 738 * Return: qos control value. 739 */ 740 static inline uint32_t 741 hal_rx_mpdu_start_mpdu_qos_control_valid_get_8074v1(uint8_t *buf) 742 { 743 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 744 struct rx_mpdu_start *mpdu_start = 745 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 746 747 return HAL_RX_MPDU_INFO_QOS_CONTROL_VALID_GET( 748 &mpdu_start->rx_mpdu_info_details); 749 } 750 751 /** 752 * hal_rx_msdu_end_sa_sw_peer_id_get_8074v1(): API to get the 753 * sa_sw_peer_id from rx_msdu_end TLV 754 * @buf: pointer to the start of RX PKT TLV headers 755 * 756 * Return: sa_sw_peer_id index 757 */ 758 static inline uint32_t 759 hal_rx_msdu_end_sa_sw_peer_id_get_8074v1(uint8_t *buf) 760 { 761 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 762 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 763 764 return HAL_RX_MSDU_END_SA_SW_PEER_ID_GET(msdu_end); 765 } 766 767 /** 768 * hal_tx_desc_set_mesh_en_8074v1 - Set mesh_enable flag in Tx descriptor 769 * @desc: Handle to Tx Descriptor 770 * @en: For raw WiFi frames, this indicates transmission to a mesh STA, 771 * enabling the interpretation of the 'Mesh Control Present' bit 772 * (bit 8) of QoS Control (otherwise this bit is ignored), 773 * For native WiFi frames, this indicates that a 'Mesh Control' field 774 * is present between the header and the LLC. 775 * 776 * Return: void 777 */ 778 static inline 779 void hal_tx_desc_set_mesh_en_8074v1(void *desc, uint8_t en) 780 { 781 HAL_SET_FLD(desc, TCL_DATA_CMD_4, MESH_ENABLE) |= 782 HAL_TX_SM(TCL_DATA_CMD_4, MESH_ENABLE, en); 783 } 784 785 static 786 void *hal_rx_msdu0_buffer_addr_lsb_8074v1(void *link_desc_va) 787 { 788 return (void *)HAL_RX_MSDU0_BUFFER_ADDR_LSB(link_desc_va); 789 } 790 791 static 792 void *hal_rx_msdu_desc_info_ptr_get_8074v1(void *msdu0) 793 { 794 return (void *)HAL_RX_MSDU_DESC_INFO_PTR_GET(msdu0); 795 } 796 797 static 798 void *hal_ent_mpdu_desc_info_8074v1(void *ent_ring_desc) 799 { 800 return (void *)HAL_ENT_MPDU_DESC_INFO(ent_ring_desc); 801 } 802 803 static 804 void *hal_dst_mpdu_desc_info_8074v1(void *dst_ring_desc) 805 { 806 return (void *)HAL_DST_MPDU_DESC_INFO(dst_ring_desc); 807 } 808 809 static 810 uint8_t hal_rx_get_fc_valid_8074v1(uint8_t *buf) 811 { 812 return HAL_RX_GET_FC_VALID(buf); 813 } 814 815 static uint8_t hal_rx_get_to_ds_flag_8074v1(uint8_t *buf) 816 { 817 return HAL_RX_GET_TO_DS_FLAG(buf); 818 } 819 820 static uint8_t hal_rx_get_mac_addr2_valid_8074v1(uint8_t *buf) 821 { 822 return HAL_RX_GET_MAC_ADDR2_VALID(buf); 823 } 824 825 static uint8_t hal_rx_get_filter_category_8074v1(uint8_t *buf) 826 { 827 return HAL_RX_GET_FILTER_CATEGORY(buf); 828 } 829 830 static uint32_t 831 hal_rx_get_ppdu_id_8074v1(uint8_t *buf) 832 { 833 struct rx_mpdu_info *rx_mpdu_info; 834 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)buf; 835 836 rx_mpdu_info = 837 &rx_desc->mpdu_start_tlv.rx_mpdu_start.rx_mpdu_info_details; 838 839 return HAL_RX_GET_PPDU_ID(rx_mpdu_info); 840 } 841 842 /** 843 * hal_reo_config_8074v1(): Set reo config parameters 844 * @soc: hal soc handle 845 * @reg_val: value to be set 846 * @reo_params: reo parameters 847 * 848 * Return: void 849 */ 850 static void 851 hal_reo_config_8074v1(struct hal_soc *soc, 852 uint32_t reg_val, 853 struct hal_reo_params *reo_params) 854 { 855 HAL_REO_R0_CONFIG(soc, reg_val, reo_params); 856 } 857 858 /** 859 * hal_rx_msdu_desc_info_get_ptr_8074v1() - Get msdu desc info ptr 860 * @msdu_details_ptr - Pointer to msdu_details_ptr 861 * 862 * Return - Pointer to rx_msdu_desc_info structure. 863 * 864 */ 865 static void *hal_rx_msdu_desc_info_get_ptr_8074v1(void *msdu_details_ptr) 866 { 867 return HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr); 868 } 869 870 /** 871 * hal_rx_link_desc_msdu0_ptr_8074v1 - Get pointer to rx_msdu details 872 * @link_desc - Pointer to link desc 873 * 874 * Return - Pointer to rx_msdu_details structure 875 * 876 */ 877 static void *hal_rx_link_desc_msdu0_ptr_8074v1(void *link_desc) 878 { 879 return HAL_RX_LINK_DESC_MSDU0_PTR(link_desc); 880 } 881 882 /** 883 * hal_rx_msdu_flow_idx_get_8074v1: API to get flow index 884 * from rx_msdu_end TLV 885 * @buf: pointer to the start of RX PKT TLV headers 886 * 887 * Return: flow index value from MSDU END TLV 888 */ 889 static inline uint32_t hal_rx_msdu_flow_idx_get_8074v1(uint8_t *buf) 890 { 891 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 892 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 893 894 return HAL_RX_MSDU_END_FLOW_IDX_GET(msdu_end); 895 } 896 897 /** 898 * hal_rx_msdu_flow_idx_invalid_8074v1: API to get flow index invalid 899 * from rx_msdu_end TLV 900 * @buf: pointer to the start of RX PKT TLV headers 901 * 902 * Return: flow index invalid value from MSDU END TLV 903 */ 904 static bool hal_rx_msdu_flow_idx_invalid_8074v1(uint8_t *buf) 905 { 906 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 907 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 908 909 return HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(msdu_end); 910 } 911 912 /** 913 * hal_rx_msdu_flow_idx_timeout_8074v1: API to get flow index timeout 914 * from rx_msdu_end TLV 915 * @buf: pointer to the start of RX PKT TLV headers 916 * 917 * Return: flow index timeout value from MSDU END TLV 918 */ 919 static bool hal_rx_msdu_flow_idx_timeout_8074v1(uint8_t *buf) 920 { 921 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 922 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 923 924 return HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(msdu_end); 925 } 926 927 /** 928 * hal_rx_msdu_fse_metadata_get_8074v1: API to get FSE metadata 929 * from rx_msdu_end TLV 930 * @buf: pointer to the start of RX PKT TLV headers 931 * 932 * Return: fse metadata value from MSDU END TLV 933 */ 934 static uint32_t hal_rx_msdu_fse_metadata_get_8074v1(uint8_t *buf) 935 { 936 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 937 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 938 939 return HAL_RX_MSDU_END_FSE_METADATA_GET(msdu_end); 940 } 941 942 /** 943 * hal_rx_msdu_cce_metadata_get_8074v1: API to get CCE metadata 944 * from rx_msdu_end TLV 945 * @buf: pointer to the start of RX PKT TLV headers 946 * 947 * Return: cce_metadata 948 */ 949 static uint16_t 950 hal_rx_msdu_cce_metadata_get_8074v1(uint8_t *buf) 951 { 952 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 953 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 954 955 return HAL_RX_MSDU_END_CCE_METADATA_GET(msdu_end); 956 } 957 958 /** 959 * hal_rx_msdu_get_flow_params_8074v1: API to get flow index, flow index invalid 960 * and flow index timeout from rx_msdu_end TLV 961 * @buf: pointer to the start of RX PKT TLV headers 962 * @flow_invalid: pointer to return value of flow_idx_valid 963 * @flow_timeout: pointer to return value of flow_idx_timeout 964 * @flow_index: pointer to return value of flow_idx 965 * 966 * Return: none 967 */ 968 static inline void 969 hal_rx_msdu_get_flow_params_8074v1(uint8_t *buf, 970 bool *flow_invalid, 971 bool *flow_timeout, 972 uint32_t *flow_index) 973 { 974 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 975 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 976 977 *flow_invalid = HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(msdu_end); 978 *flow_timeout = HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(msdu_end); 979 *flow_index = HAL_RX_MSDU_END_FLOW_IDX_GET(msdu_end); 980 } 981 982 /** 983 * hal_rx_tlv_get_tcp_chksum_8074v1() - API to get tcp checksum 984 * @buf: rx_tlv_hdr 985 * 986 * Return: tcp checksum 987 */ 988 static uint16_t 989 hal_rx_tlv_get_tcp_chksum_8074v1(uint8_t *buf) 990 { 991 return HAL_RX_TLV_GET_TCP_CHKSUM(buf); 992 } 993 994 /** 995 * hal_rx_get_rx_sequence_8074v1(): Function to retrieve rx sequence number 996 * 997 * @nbuf: Network buffer 998 * Returns: rx sequence number 999 */ 1000 static 1001 uint16_t hal_rx_get_rx_sequence_8074v1(uint8_t *buf) 1002 { 1003 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 1004 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 1005 1006 return HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info); 1007 } 1008 1009 /** 1010 * hal_rx_mpdu_start_tlv_tag_valid_8074v1 () - API to check if RX_MPDU_START 1011 * tlv tag is valid 1012 * 1013 * @rx_tlv_hdr: start address of rx_pkt_tlvs 1014 * 1015 * Return: true if RX_MPDU_START is valied, else false. 1016 */ 1017 uint8_t hal_rx_mpdu_start_tlv_tag_valid_8074v1(void *rx_tlv_hdr) 1018 { 1019 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)rx_tlv_hdr; 1020 uint32_t tlv_tag; 1021 1022 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE( 1023 &rx_desc->mpdu_start_tlv); 1024 1025 return tlv_tag == WIFIRX_MPDU_START_E ? true : false; 1026 } 1027 1028 /** 1029 * hal_rx_flow_setup_fse_8074v1() - Setup a flow search entry in HW FST 1030 * @fst: Pointer to the Rx Flow Search Table 1031 * @table_offset: offset into the table where the flow is to be setup 1032 * @flow: Flow Parameters 1033 * 1034 * Return: Success/Failure 1035 */ 1036 static void * 1037 hal_rx_flow_setup_fse_8074v1(uint8_t *rx_fst, uint32_t table_offset, 1038 uint8_t *rx_flow) 1039 { 1040 struct hal_rx_fst *fst = (struct hal_rx_fst *)rx_fst; 1041 struct hal_rx_flow *flow = (struct hal_rx_flow *)rx_flow; 1042 uint8_t *fse; 1043 bool fse_valid; 1044 1045 if (table_offset >= fst->max_entries) { 1046 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR, 1047 "HAL FSE table offset %u exceeds max entries %u", 1048 table_offset, fst->max_entries); 1049 return NULL; 1050 } 1051 1052 fse = (uint8_t *)fst->base_vaddr + 1053 (table_offset * HAL_RX_FST_ENTRY_SIZE); 1054 1055 fse_valid = HAL_GET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, VALID); 1056 1057 if (fse_valid) { 1058 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_DEBUG, 1059 "HAL FSE %pK already valid", fse); 1060 return NULL; 1061 } 1062 1063 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_0, SRC_IP_127_96) = 1064 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_0, SRC_IP_127_96, 1065 qdf_htonl(flow->tuple_info.src_ip_127_96)); 1066 1067 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_1, SRC_IP_95_64) = 1068 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_1, SRC_IP_95_64, 1069 qdf_htonl(flow->tuple_info.src_ip_95_64)); 1070 1071 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_2, SRC_IP_63_32) = 1072 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_2, SRC_IP_63_32, 1073 qdf_htonl(flow->tuple_info.src_ip_63_32)); 1074 1075 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_3, SRC_IP_31_0) = 1076 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_3, SRC_IP_31_0, 1077 qdf_htonl(flow->tuple_info.src_ip_31_0)); 1078 1079 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_4, DEST_IP_127_96) = 1080 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_4, DEST_IP_127_96, 1081 qdf_htonl(flow->tuple_info.dest_ip_127_96)); 1082 1083 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_5, DEST_IP_95_64) = 1084 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_5, DEST_IP_95_64, 1085 qdf_htonl(flow->tuple_info.dest_ip_95_64)); 1086 1087 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_6, DEST_IP_63_32) = 1088 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_6, DEST_IP_63_32, 1089 qdf_htonl(flow->tuple_info.dest_ip_63_32)); 1090 1091 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_7, DEST_IP_31_0) = 1092 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_7, DEST_IP_31_0, 1093 qdf_htonl(flow->tuple_info.dest_ip_31_0)); 1094 1095 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, DEST_PORT); 1096 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, DEST_PORT) |= 1097 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_8, DEST_PORT, 1098 (flow->tuple_info.dest_port)); 1099 1100 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, SRC_PORT); 1101 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, SRC_PORT) |= 1102 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_8, SRC_PORT, 1103 (flow->tuple_info.src_port)); 1104 1105 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, L4_PROTOCOL); 1106 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, L4_PROTOCOL) |= 1107 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, L4_PROTOCOL, 1108 flow->tuple_info.l4_protocol); 1109 1110 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_HANDLER); 1111 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_HANDLER) |= 1112 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_HANDLER, 1113 flow->reo_destination_handler); 1114 1115 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, VALID); 1116 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, VALID) |= 1117 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, VALID, 1); 1118 1119 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_10, METADATA); 1120 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_10, METADATA) = 1121 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_10, METADATA, 1122 flow->fse_metadata); 1123 1124 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_11, REO_DESTINATION_INDICATION); 1125 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_11, REO_DESTINATION_INDICATION) |= 1126 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_11, 1127 REO_DESTINATION_INDICATION, 1128 flow->reo_destination_indication); 1129 1130 /* Reset all the other fields in FSE */ 1131 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, RESERVED_9); 1132 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_11, MSDU_DROP); 1133 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_11, RESERVED_11); 1134 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_11, MSDU_COUNT); 1135 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_12, MSDU_BYTE_COUNT); 1136 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_13, TIMESTAMP); 1137 1138 return fse; 1139 } 1140 1141 static 1142 void hal_compute_reo_remap_ix2_ix3_8074v1(uint32_t *ring, uint32_t num_rings, 1143 uint32_t *remap1, uint32_t *remap2) 1144 { 1145 switch (num_rings) { 1146 case 1: 1147 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 1148 HAL_REO_REMAP_IX2(ring[0], 17) | 1149 HAL_REO_REMAP_IX2(ring[0], 18) | 1150 HAL_REO_REMAP_IX2(ring[0], 19) | 1151 HAL_REO_REMAP_IX2(ring[0], 20) | 1152 HAL_REO_REMAP_IX2(ring[0], 21) | 1153 HAL_REO_REMAP_IX2(ring[0], 22) | 1154 HAL_REO_REMAP_IX2(ring[0], 23); 1155 1156 *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) | 1157 HAL_REO_REMAP_IX3(ring[0], 25) | 1158 HAL_REO_REMAP_IX3(ring[0], 26) | 1159 HAL_REO_REMAP_IX3(ring[0], 27) | 1160 HAL_REO_REMAP_IX3(ring[0], 28) | 1161 HAL_REO_REMAP_IX3(ring[0], 29) | 1162 HAL_REO_REMAP_IX3(ring[0], 30) | 1163 HAL_REO_REMAP_IX3(ring[0], 31); 1164 break; 1165 case 2: 1166 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 1167 HAL_REO_REMAP_IX2(ring[0], 17) | 1168 HAL_REO_REMAP_IX2(ring[1], 18) | 1169 HAL_REO_REMAP_IX2(ring[1], 19) | 1170 HAL_REO_REMAP_IX2(ring[0], 20) | 1171 HAL_REO_REMAP_IX2(ring[0], 21) | 1172 HAL_REO_REMAP_IX2(ring[1], 22) | 1173 HAL_REO_REMAP_IX2(ring[1], 23); 1174 1175 *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) | 1176 HAL_REO_REMAP_IX3(ring[0], 25) | 1177 HAL_REO_REMAP_IX3(ring[1], 26) | 1178 HAL_REO_REMAP_IX3(ring[1], 27) | 1179 HAL_REO_REMAP_IX3(ring[0], 28) | 1180 HAL_REO_REMAP_IX3(ring[0], 29) | 1181 HAL_REO_REMAP_IX3(ring[1], 30) | 1182 HAL_REO_REMAP_IX3(ring[1], 31); 1183 break; 1184 case 3: 1185 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 1186 HAL_REO_REMAP_IX2(ring[1], 17) | 1187 HAL_REO_REMAP_IX2(ring[2], 18) | 1188 HAL_REO_REMAP_IX2(ring[0], 19) | 1189 HAL_REO_REMAP_IX2(ring[1], 20) | 1190 HAL_REO_REMAP_IX2(ring[2], 21) | 1191 HAL_REO_REMAP_IX2(ring[0], 22) | 1192 HAL_REO_REMAP_IX2(ring[1], 23); 1193 1194 *remap2 = HAL_REO_REMAP_IX3(ring[2], 24) | 1195 HAL_REO_REMAP_IX3(ring[0], 25) | 1196 HAL_REO_REMAP_IX3(ring[1], 26) | 1197 HAL_REO_REMAP_IX3(ring[2], 27) | 1198 HAL_REO_REMAP_IX3(ring[0], 28) | 1199 HAL_REO_REMAP_IX3(ring[1], 29) | 1200 HAL_REO_REMAP_IX3(ring[2], 30) | 1201 HAL_REO_REMAP_IX3(ring[0], 31); 1202 break; 1203 case 4: 1204 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 1205 HAL_REO_REMAP_IX2(ring[1], 17) | 1206 HAL_REO_REMAP_IX2(ring[2], 18) | 1207 HAL_REO_REMAP_IX2(ring[3], 19) | 1208 HAL_REO_REMAP_IX2(ring[0], 20) | 1209 HAL_REO_REMAP_IX2(ring[1], 21) | 1210 HAL_REO_REMAP_IX2(ring[2], 22) | 1211 HAL_REO_REMAP_IX2(ring[3], 23); 1212 1213 *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) | 1214 HAL_REO_REMAP_IX3(ring[1], 25) | 1215 HAL_REO_REMAP_IX3(ring[2], 26) | 1216 HAL_REO_REMAP_IX3(ring[3], 27) | 1217 HAL_REO_REMAP_IX3(ring[0], 28) | 1218 HAL_REO_REMAP_IX3(ring[1], 29) | 1219 HAL_REO_REMAP_IX3(ring[2], 30) | 1220 HAL_REO_REMAP_IX3(ring[3], 31); 1221 break; 1222 } 1223 } 1224 1225 static void hal_hw_txrx_ops_attach_qca8074(struct hal_soc *hal_soc) 1226 { 1227 1228 /* init and setup */ 1229 hal_soc->ops->hal_srng_dst_hw_init = hal_srng_dst_hw_init_generic; 1230 hal_soc->ops->hal_srng_src_hw_init = hal_srng_src_hw_init_generic; 1231 hal_soc->ops->hal_get_hw_hptp = hal_get_hw_hptp_generic; 1232 hal_soc->ops->hal_reo_setup = hal_reo_setup_generic_li; 1233 hal_soc->ops->hal_get_window_address = hal_get_window_address_8074; 1234 1235 /* tx */ 1236 hal_soc->ops->hal_tx_desc_set_dscp_tid_table_id = 1237 hal_tx_desc_set_dscp_tid_table_id_8074; 1238 hal_soc->ops->hal_tx_set_dscp_tid_map = hal_tx_set_dscp_tid_map_8074; 1239 hal_soc->ops->hal_tx_update_dscp_tid = hal_tx_update_dscp_tid_8074; 1240 hal_soc->ops->hal_tx_desc_set_lmac_id = hal_tx_desc_set_lmac_id_8074; 1241 hal_soc->ops->hal_tx_desc_set_buf_addr = 1242 hal_tx_desc_set_buf_addr_generic_li; 1243 hal_soc->ops->hal_tx_desc_set_search_type = 1244 hal_tx_desc_set_search_type_generic_li; 1245 hal_soc->ops->hal_tx_desc_set_search_index = 1246 hal_tx_desc_set_search_index_generic_li; 1247 hal_soc->ops->hal_tx_desc_set_cache_set_num = 1248 hal_tx_desc_set_cache_set_num_generic_li; 1249 hal_soc->ops->hal_tx_comp_get_status = 1250 hal_tx_comp_get_status_generic_li; 1251 hal_soc->ops->hal_tx_comp_get_release_reason = 1252 hal_tx_comp_get_release_reason_generic_li; 1253 hal_soc->ops->hal_get_wbm_internal_error = 1254 hal_get_wbm_internal_error_generic_li; 1255 hal_soc->ops->hal_tx_desc_set_mesh_en = hal_tx_desc_set_mesh_en_8074v1; 1256 hal_soc->ops->hal_tx_init_cmd_credit_ring = 1257 hal_tx_init_cmd_credit_ring_8074v1; 1258 1259 /* rx */ 1260 hal_soc->ops->hal_rx_msdu_start_nss_get = 1261 hal_rx_msdu_start_nss_get_8074; 1262 hal_soc->ops->hal_rx_mon_hw_desc_get_mpdu_status = 1263 hal_rx_mon_hw_desc_get_mpdu_status_8074; 1264 hal_soc->ops->hal_rx_get_tlv = hal_rx_get_tlv_8074; 1265 hal_soc->ops->hal_rx_proc_phyrx_other_receive_info_tlv = 1266 hal_rx_proc_phyrx_other_receive_info_tlv_8074; 1267 hal_soc->ops->hal_rx_dump_msdu_start_tlv = 1268 hal_rx_dump_msdu_start_tlv_8074; 1269 hal_soc->ops->hal_rx_dump_msdu_end_tlv = hal_rx_dump_msdu_end_tlv_8074; 1270 hal_soc->ops->hal_get_link_desc_size = hal_get_link_desc_size_8074; 1271 hal_soc->ops->hal_rx_mpdu_start_tid_get = 1272 hal_rx_mpdu_start_tid_get_8074; 1273 hal_soc->ops->hal_rx_msdu_start_reception_type_get = 1274 hal_rx_msdu_start_reception_type_get_8074; 1275 hal_soc->ops->hal_rx_msdu_end_da_idx_get = 1276 hal_rx_msdu_end_da_idx_get_8074; 1277 hal_soc->ops->hal_rx_msdu_desc_info_get_ptr = 1278 hal_rx_msdu_desc_info_get_ptr_8074v1; 1279 hal_soc->ops->hal_rx_link_desc_msdu0_ptr = 1280 hal_rx_link_desc_msdu0_ptr_8074v1; 1281 hal_soc->ops->hal_reo_status_get_header = 1282 hal_reo_status_get_header_8074v1; 1283 hal_soc->ops->hal_rx_status_get_tlv_info = 1284 hal_rx_status_get_tlv_info_generic_li; 1285 hal_soc->ops->hal_rx_wbm_err_info_get = 1286 hal_rx_wbm_err_info_get_generic_li; 1287 hal_soc->ops->hal_rx_dump_mpdu_start_tlv = 1288 hal_rx_dump_mpdu_start_tlv_generic_li; 1289 1290 hal_soc->ops->hal_tx_set_pcp_tid_map = 1291 hal_tx_set_pcp_tid_map_generic_li; 1292 hal_soc->ops->hal_tx_update_pcp_tid_map = 1293 hal_tx_update_pcp_tid_generic_li; 1294 hal_soc->ops->hal_tx_set_tidmap_prty = 1295 hal_tx_update_tidmap_prty_generic_li; 1296 hal_soc->ops->hal_rx_get_rx_fragment_number = 1297 hal_rx_get_rx_fragment_number_8074v1; 1298 hal_soc->ops->hal_rx_msdu_end_da_is_mcbc_get = 1299 hal_rx_msdu_end_da_is_mcbc_get_8074v1; 1300 hal_soc->ops->hal_rx_msdu_end_sa_is_valid_get = 1301 hal_rx_msdu_end_sa_is_valid_get_8074v1; 1302 hal_soc->ops->hal_rx_msdu_end_sa_idx_get = 1303 hal_rx_msdu_end_sa_idx_get_8074v1; 1304 hal_soc->ops->hal_rx_desc_is_first_msdu = 1305 hal_rx_desc_is_first_msdu_8074v1; 1306 hal_soc->ops->hal_rx_msdu_end_l3_hdr_padding_get = 1307 hal_rx_msdu_end_l3_hdr_padding_get_8074v1; 1308 hal_soc->ops->hal_rx_encryption_info_valid = 1309 hal_rx_encryption_info_valid_8074v1; 1310 hal_soc->ops->hal_rx_print_pn = hal_rx_print_pn_8074v1; 1311 hal_soc->ops->hal_rx_msdu_end_first_msdu_get = 1312 hal_rx_msdu_end_first_msdu_get_8074v1; 1313 hal_soc->ops->hal_rx_msdu_end_da_is_valid_get = 1314 hal_rx_msdu_end_da_is_valid_get_8074v1; 1315 hal_soc->ops->hal_rx_msdu_end_last_msdu_get = 1316 hal_rx_msdu_end_last_msdu_get_8074v1; 1317 hal_soc->ops->hal_rx_get_mpdu_mac_ad4_valid = 1318 hal_rx_get_mpdu_mac_ad4_valid_8074v1; 1319 hal_soc->ops->hal_rx_mpdu_start_sw_peer_id_get = 1320 hal_rx_mpdu_start_sw_peer_id_get_8074v1; 1321 hal_soc->ops->hal_rx_mpdu_get_to_ds = hal_rx_mpdu_get_to_ds_8074v1; 1322 hal_soc->ops->hal_rx_mpdu_get_fr_ds = hal_rx_mpdu_get_fr_ds_8074v1; 1323 hal_soc->ops->hal_rx_get_mpdu_frame_control_valid = 1324 hal_rx_get_mpdu_frame_control_valid_8074v1; 1325 hal_soc->ops->hal_rx_mpdu_get_addr1 = hal_rx_mpdu_get_addr1_8074v1; 1326 hal_soc->ops->hal_rx_mpdu_get_addr2 = hal_rx_mpdu_get_addr2_8074v1; 1327 hal_soc->ops->hal_rx_mpdu_get_addr3 = hal_rx_mpdu_get_addr3_8074v1; 1328 hal_soc->ops->hal_rx_mpdu_get_addr4 = hal_rx_mpdu_get_addr4_8074v1; 1329 hal_soc->ops->hal_rx_get_mpdu_sequence_control_valid = 1330 hal_rx_get_mpdu_sequence_control_valid_8074v1; 1331 hal_soc->ops->hal_rx_is_unicast = hal_rx_is_unicast_8074v1; 1332 hal_soc->ops->hal_rx_tid_get = hal_rx_tid_get_8074v1; 1333 hal_soc->ops->hal_rx_hw_desc_get_ppduid_get = 1334 hal_rx_hw_desc_get_ppduid_get_8074v1; 1335 hal_soc->ops->hal_rx_mpdu_start_mpdu_qos_control_valid_get = 1336 hal_rx_mpdu_start_mpdu_qos_control_valid_get_8074v1; 1337 hal_soc->ops->hal_rx_msdu_end_sa_sw_peer_id_get = 1338 hal_rx_msdu_end_sa_sw_peer_id_get_8074v1; 1339 hal_soc->ops->hal_rx_msdu0_buffer_addr_lsb = 1340 hal_rx_msdu0_buffer_addr_lsb_8074v1; 1341 hal_soc->ops->hal_rx_msdu_desc_info_ptr_get = 1342 hal_rx_msdu_desc_info_ptr_get_8074v1; 1343 hal_soc->ops->hal_ent_mpdu_desc_info = hal_ent_mpdu_desc_info_8074v1; 1344 hal_soc->ops->hal_dst_mpdu_desc_info = hal_dst_mpdu_desc_info_8074v1; 1345 hal_soc->ops->hal_rx_get_fc_valid = hal_rx_get_fc_valid_8074v1; 1346 hal_soc->ops->hal_rx_get_to_ds_flag = hal_rx_get_to_ds_flag_8074v1; 1347 hal_soc->ops->hal_rx_get_mac_addr2_valid = 1348 hal_rx_get_mac_addr2_valid_8074v1; 1349 hal_soc->ops->hal_rx_get_filter_category = 1350 hal_rx_get_filter_category_8074v1; 1351 hal_soc->ops->hal_rx_get_ppdu_id = hal_rx_get_ppdu_id_8074v1; 1352 hal_soc->ops->hal_reo_config = hal_reo_config_8074v1; 1353 hal_soc->ops->hal_rx_msdu_flow_idx_get = 1354 hal_rx_msdu_flow_idx_get_8074v1; 1355 hal_soc->ops->hal_rx_msdu_flow_idx_invalid = 1356 hal_rx_msdu_flow_idx_invalid_8074v1; 1357 hal_soc->ops->hal_rx_msdu_flow_idx_timeout = 1358 hal_rx_msdu_flow_idx_timeout_8074v1; 1359 hal_soc->ops->hal_rx_msdu_fse_metadata_get = 1360 hal_rx_msdu_fse_metadata_get_8074v1; 1361 hal_soc->ops->hal_rx_msdu_cce_metadata_get = 1362 hal_rx_msdu_cce_metadata_get_8074v1; 1363 hal_soc->ops->hal_rx_msdu_get_flow_params = 1364 hal_rx_msdu_get_flow_params_8074v1; 1365 hal_soc->ops->hal_rx_tlv_get_tcp_chksum = 1366 hal_rx_tlv_get_tcp_chksum_8074v1; 1367 hal_soc->ops->hal_rx_get_rx_sequence = hal_rx_get_rx_sequence_8074v1; 1368 /* rx - msdu fast path info fields */ 1369 hal_soc->ops->hal_rx_msdu_packet_metadata_get = 1370 hal_rx_msdu_packet_metadata_get_generic_li; 1371 hal_soc->ops->hal_rx_mpdu_start_tlv_tag_valid = 1372 hal_rx_mpdu_start_tlv_tag_valid_8074v1; 1373 1374 /* rx - TLV struct offsets */ 1375 hal_soc->ops->hal_rx_msdu_end_offset_get = 1376 hal_rx_msdu_end_offset_get_generic; 1377 hal_soc->ops->hal_rx_attn_offset_get = hal_rx_attn_offset_get_generic; 1378 hal_soc->ops->hal_rx_msdu_start_offset_get = 1379 hal_rx_msdu_start_offset_get_generic; 1380 hal_soc->ops->hal_rx_mpdu_start_offset_get = 1381 hal_rx_mpdu_start_offset_get_generic; 1382 hal_soc->ops->hal_rx_mpdu_end_offset_get = 1383 hal_rx_mpdu_end_offset_get_generic; 1384 #ifndef NO_RX_PKT_HDR_TLV 1385 hal_soc->ops->hal_rx_pkt_tlv_offset_get = 1386 hal_rx_pkt_tlv_offset_get_generic; 1387 #endif 1388 hal_soc->ops->hal_rx_flow_setup_fse = hal_rx_flow_setup_fse_8074v1; 1389 hal_soc->ops->hal_compute_reo_remap_ix2_ix3 = 1390 hal_compute_reo_remap_ix2_ix3_8074v1; 1391 hal_soc->ops->hal_setup_link_idle_list = 1392 hal_setup_link_idle_list_generic_li; 1393 }; 1394 1395 struct hal_hw_srng_config hw_srng_table_8074[] = { 1396 /* TODO: max_rings can populated by querying HW capabilities */ 1397 { /* REO_DST */ 1398 .start_ring_id = HAL_SRNG_REO2SW1, 1399 .max_rings = 4, 1400 .entry_size = sizeof(struct reo_destination_ring) >> 2, 1401 .lmac_ring = FALSE, 1402 .ring_dir = HAL_SRNG_DST_RING, 1403 .reg_start = { 1404 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR( 1405 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1406 HWIO_REO_R2_REO2SW1_RING_HP_ADDR( 1407 SEQ_WCSS_UMAC_REO_REG_OFFSET) 1408 }, 1409 .reg_size = { 1410 HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(0) - 1411 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(0), 1412 HWIO_REO_R2_REO2SW2_RING_HP_ADDR(0) - 1413 HWIO_REO_R2_REO2SW1_RING_HP_ADDR(0), 1414 }, 1415 .max_size = 1416 HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_BMSK >> 1417 HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_SHFT, 1418 }, 1419 { /* REO_EXCEPTION */ 1420 /* Designating REO2TCL ring as exception ring. This ring is 1421 * similar to other REO2SW rings though it is named as REO2TCL. 1422 * Any of theREO2SW rings can be used as exception ring. 1423 */ 1424 .start_ring_id = HAL_SRNG_REO2TCL, 1425 .max_rings = 1, 1426 .entry_size = sizeof(struct reo_destination_ring) >> 2, 1427 .lmac_ring = FALSE, 1428 .ring_dir = HAL_SRNG_DST_RING, 1429 .reg_start = { 1430 HWIO_REO_R0_REO2TCL_RING_BASE_LSB_ADDR( 1431 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1432 HWIO_REO_R2_REO2TCL_RING_HP_ADDR( 1433 SEQ_WCSS_UMAC_REO_REG_OFFSET) 1434 }, 1435 /* Single ring - provide ring size if multiple rings of this 1436 * type are supported 1437 */ 1438 .reg_size = {}, 1439 .max_size = 1440 HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_BMSK >> 1441 HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_SHFT, 1442 }, 1443 { /* REO_REINJECT */ 1444 .start_ring_id = HAL_SRNG_SW2REO, 1445 .max_rings = 1, 1446 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 1447 .lmac_ring = FALSE, 1448 .ring_dir = HAL_SRNG_SRC_RING, 1449 .reg_start = { 1450 HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR( 1451 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1452 HWIO_REO_R2_SW2REO_RING_HP_ADDR( 1453 SEQ_WCSS_UMAC_REO_REG_OFFSET) 1454 }, 1455 /* Single ring - provide ring size if multiple rings of this 1456 * type are supported 1457 */ 1458 .reg_size = {}, 1459 .max_size = HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_BMSK >> 1460 HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_SHFT, 1461 }, 1462 { /* REO_CMD */ 1463 .start_ring_id = HAL_SRNG_REO_CMD, 1464 .max_rings = 1, 1465 .entry_size = (sizeof(struct tlv_32_hdr) + 1466 sizeof(struct reo_get_queue_stats)) >> 2, 1467 .lmac_ring = FALSE, 1468 .ring_dir = HAL_SRNG_SRC_RING, 1469 .reg_start = { 1470 HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR( 1471 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1472 HWIO_REO_R2_REO_CMD_RING_HP_ADDR( 1473 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1474 }, 1475 /* Single ring - provide ring size if multiple rings of this 1476 * type are supported 1477 */ 1478 .reg_size = {}, 1479 .max_size = HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_BMSK >> 1480 HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_SHFT, 1481 }, 1482 { /* REO_STATUS */ 1483 .start_ring_id = HAL_SRNG_REO_STATUS, 1484 .max_rings = 1, 1485 .entry_size = (sizeof(struct tlv_32_hdr) + 1486 sizeof(struct reo_get_queue_stats_status)) >> 2, 1487 .lmac_ring = FALSE, 1488 .ring_dir = HAL_SRNG_DST_RING, 1489 .reg_start = { 1490 HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR( 1491 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1492 HWIO_REO_R2_REO_STATUS_RING_HP_ADDR( 1493 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1494 }, 1495 /* Single ring - provide ring size if multiple rings of this 1496 * type are supported 1497 */ 1498 .reg_size = {}, 1499 .max_size = 1500 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> 1501 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, 1502 }, 1503 { /* TCL_DATA */ 1504 .start_ring_id = HAL_SRNG_SW2TCL1, 1505 .max_rings = 3, 1506 .entry_size = (sizeof(struct tlv_32_hdr) + 1507 sizeof(struct tcl_data_cmd)) >> 2, 1508 .lmac_ring = FALSE, 1509 .ring_dir = HAL_SRNG_SRC_RING, 1510 .reg_start = { 1511 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR( 1512 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1513 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR( 1514 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1515 }, 1516 .reg_size = { 1517 HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(0) - 1518 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(0), 1519 HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(0) - 1520 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(0), 1521 }, 1522 .max_size = 1523 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK >> 1524 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT, 1525 }, 1526 { /* TCL_CMD */ 1527 .start_ring_id = HAL_SRNG_SW2TCL_CMD, 1528 .max_rings = 1, 1529 .entry_size = (sizeof(struct tlv_32_hdr) + 1530 sizeof(struct tcl_data_cmd)) >> 2, 1531 .lmac_ring = FALSE, 1532 .ring_dir = HAL_SRNG_SRC_RING, 1533 .reg_start = { 1534 HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_ADDR( 1535 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1536 HWIO_TCL_R2_SW2TCL_CMD_RING_HP_ADDR( 1537 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1538 }, 1539 /* Single ring - provide ring size if multiple rings of this 1540 * type are supported 1541 */ 1542 .reg_size = {}, 1543 .max_size = 1544 HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RING_SIZE_BMSK >> 1545 HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RING_SIZE_SHFT, 1546 }, 1547 { /* TCL_STATUS */ 1548 .start_ring_id = HAL_SRNG_TCL_STATUS, 1549 .max_rings = 1, 1550 .entry_size = (sizeof(struct tlv_32_hdr) + 1551 sizeof(struct tcl_status_ring)) >> 2, 1552 .lmac_ring = FALSE, 1553 .ring_dir = HAL_SRNG_DST_RING, 1554 .reg_start = { 1555 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR( 1556 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1557 HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR( 1558 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1559 }, 1560 /* Single ring - provide ring size if multiple rings of this 1561 * type are supported 1562 */ 1563 .reg_size = {}, 1564 .max_size = 1565 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_BMSK >> 1566 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_SHFT, 1567 }, 1568 { /* CE_SRC */ 1569 .start_ring_id = HAL_SRNG_CE_0_SRC, 1570 .max_rings = 12, 1571 .entry_size = sizeof(struct ce_src_desc) >> 2, 1572 .lmac_ring = FALSE, 1573 .ring_dir = HAL_SRNG_SRC_RING, 1574 .reg_start = { 1575 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR( 1576 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET), 1577 HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR( 1578 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET), 1579 }, 1580 .reg_size = { 1581 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET - 1582 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET, 1583 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET - 1584 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET, 1585 }, 1586 .max_size = 1587 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >> 1588 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT, 1589 }, 1590 { /* CE_DST */ 1591 .start_ring_id = HAL_SRNG_CE_0_DST, 1592 .max_rings = 12, 1593 .entry_size = 8 >> 2, 1594 /*TODO: entry_size above should actually be 1595 * sizeof(struct ce_dst_desc) >> 2, but couldn't find definition 1596 * of struct ce_dst_desc in HW header files 1597 */ 1598 .lmac_ring = FALSE, 1599 .ring_dir = HAL_SRNG_SRC_RING, 1600 .reg_start = { 1601 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR( 1602 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 1603 HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR( 1604 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 1605 }, 1606 .reg_size = { 1607 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 1608 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 1609 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 1610 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 1611 }, 1612 .max_size = 1613 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >> 1614 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT, 1615 }, 1616 { /* CE_DST_STATUS */ 1617 .start_ring_id = HAL_SRNG_CE_0_DST_STATUS, 1618 .max_rings = 12, 1619 .entry_size = sizeof(struct ce_stat_desc) >> 2, 1620 .lmac_ring = FALSE, 1621 .ring_dir = HAL_SRNG_DST_RING, 1622 .reg_start = { 1623 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR( 1624 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 1625 HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR( 1626 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 1627 }, 1628 /* TODO: check destination status ring registers */ 1629 .reg_size = { 1630 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 1631 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 1632 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 1633 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 1634 }, 1635 .max_size = 1636 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> 1637 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, 1638 }, 1639 { /* WBM_IDLE_LINK */ 1640 .start_ring_id = HAL_SRNG_WBM_IDLE_LINK, 1641 .max_rings = 1, 1642 .entry_size = sizeof(struct wbm_link_descriptor_ring) >> 2, 1643 .lmac_ring = FALSE, 1644 .ring_dir = HAL_SRNG_SRC_RING, 1645 .reg_start = { 1646 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1647 HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1648 }, 1649 /* Single ring - provide ring size if multiple rings of this 1650 * type are supported 1651 */ 1652 .reg_size = {}, 1653 .max_size = 1654 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_BMSK >> 1655 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_SHFT, 1656 }, 1657 { /* SW2WBM_RELEASE */ 1658 .start_ring_id = HAL_SRNG_WBM_SW_RELEASE, 1659 .max_rings = 1, 1660 .entry_size = sizeof(struct wbm_release_ring) >> 2, 1661 .lmac_ring = FALSE, 1662 .ring_dir = HAL_SRNG_SRC_RING, 1663 .reg_start = { 1664 HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1665 HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1666 }, 1667 /* Single ring - provide ring size if multiple rings of this 1668 * type are supported 1669 */ 1670 .reg_size = {}, 1671 .max_size = 1672 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> 1673 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, 1674 }, 1675 { /* WBM2SW_RELEASE */ 1676 .start_ring_id = HAL_SRNG_WBM2SW0_RELEASE, 1677 .max_rings = 4, 1678 .entry_size = sizeof(struct wbm_release_ring) >> 2, 1679 .lmac_ring = FALSE, 1680 .ring_dir = HAL_SRNG_DST_RING, 1681 .reg_start = { 1682 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1683 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1684 }, 1685 .reg_size = { 1686 HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) - 1687 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1688 HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) - 1689 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1690 }, 1691 .max_size = 1692 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> 1693 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, 1694 }, 1695 { /* RXDMA_BUF */ 1696 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA0_BUF0, 1697 #ifdef IPA_OFFLOAD 1698 .max_rings = 3, 1699 #else 1700 .max_rings = 2, 1701 #endif 1702 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 1703 .lmac_ring = TRUE, 1704 .ring_dir = HAL_SRNG_SRC_RING, 1705 /* reg_start is not set because LMAC rings are not accessed 1706 * from host 1707 */ 1708 .reg_start = {}, 1709 .reg_size = {}, 1710 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1711 }, 1712 { /* RXDMA_DST */ 1713 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW0, 1714 .max_rings = 1, 1715 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 1716 .lmac_ring = TRUE, 1717 .ring_dir = HAL_SRNG_DST_RING, 1718 /* reg_start is not set because LMAC rings are not accessed 1719 * from host 1720 */ 1721 .reg_start = {}, 1722 .reg_size = {}, 1723 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1724 }, 1725 { /* RXDMA_MONITOR_BUF */ 1726 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA2_BUF, 1727 .max_rings = 1, 1728 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 1729 .lmac_ring = TRUE, 1730 .ring_dir = HAL_SRNG_SRC_RING, 1731 /* reg_start is not set because LMAC rings are not accessed 1732 * from host 1733 */ 1734 .reg_start = {}, 1735 .reg_size = {}, 1736 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1737 }, 1738 { /* RXDMA_MONITOR_STATUS */ 1739 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_STATBUF, 1740 .max_rings = 1, 1741 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 1742 .lmac_ring = TRUE, 1743 .ring_dir = HAL_SRNG_SRC_RING, 1744 /* reg_start is not set because LMAC rings are not accessed 1745 * from host 1746 */ 1747 .reg_start = {}, 1748 .reg_size = {}, 1749 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1750 }, 1751 { /* RXDMA_MONITOR_DST */ 1752 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW1, 1753 .max_rings = 1, 1754 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 1755 .lmac_ring = TRUE, 1756 .ring_dir = HAL_SRNG_DST_RING, 1757 /* reg_start is not set because LMAC rings are not accessed 1758 * from host 1759 */ 1760 .reg_start = {}, 1761 .reg_size = {}, 1762 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1763 }, 1764 { /* RXDMA_MONITOR_DESC */ 1765 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_DESC, 1766 .max_rings = 1, 1767 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 1768 .lmac_ring = TRUE, 1769 .ring_dir = HAL_SRNG_SRC_RING, 1770 /* reg_start is not set because LMAC rings are not accessed 1771 * from host 1772 */ 1773 .reg_start = {}, 1774 .reg_size = {}, 1775 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1776 }, 1777 { /* DIR_BUF_RX_DMA_SRC */ 1778 .start_ring_id = HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING, 1779 .max_rings = 1, 1780 .entry_size = 2, 1781 .lmac_ring = TRUE, 1782 .ring_dir = HAL_SRNG_SRC_RING, 1783 /* reg_start is not set because LMAC rings are not accessed 1784 * from host 1785 */ 1786 .reg_start = {}, 1787 .reg_size = {}, 1788 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1789 }, 1790 #ifdef WLAN_FEATURE_CIF_CFR 1791 { /* WIFI_POS_SRC */ 1792 .start_ring_id = HAL_SRNG_WIFI_POS_SRC_DMA_RING, 1793 .max_rings = 1, 1794 .entry_size = sizeof(wmi_oem_dma_buf_release_entry) >> 2, 1795 .lmac_ring = TRUE, 1796 .ring_dir = HAL_SRNG_SRC_RING, 1797 /* reg_start is not set because LMAC rings are not accessed 1798 * from host 1799 */ 1800 .reg_start = {}, 1801 .reg_size = {}, 1802 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1803 }, 1804 #endif 1805 { /* REO2PPE */ 0}, 1806 { /* PPE2TCL */ 0}, 1807 { /* PPE_RELEASE */ 0}, 1808 { /* TX_MONITOR_BUF */ 0}, 1809 { /* TX_MONITOR_DST */ 0}, 1810 { /* SW2RXDMA_NEW */ 0}, 1811 }; 1812 1813 /** 1814 * hal_qca8074_attach() - Attach 8074 target specific hal_soc ops, 1815 * offset and srng table 1816 */ 1817 void hal_qca8074_attach(struct hal_soc *hal_soc) 1818 { 1819 hal_soc->hw_srng_table = hw_srng_table_8074; 1820 hal_srng_hw_reg_offset_init_generic(hal_soc); 1821 hal_hw_txrx_default_ops_attach_li(hal_soc); 1822 hal_hw_txrx_ops_attach_qca8074(hal_soc); 1823 } 1824