1 /* 2 * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved. 3 * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 #include "hal_li_hw_headers.h" 20 #include "hal_internal.h" 21 #include "hal_api.h" 22 #include "target_type.h" 23 #include "wcss_version.h" 24 #include "qdf_module.h" 25 #include "hal_flow.h" 26 #include "rx_flow_search_entry.h" 27 #include "hal_rx_flow_info.h" 28 29 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_OFFSET \ 30 RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_OFFSET 31 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_MASK \ 32 RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_MASK 33 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_LSB \ 34 RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_LSB 35 #define UNIFIED_RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_OFFSET \ 36 RXPCU_PPDU_END_INFO_10_PHYRX_ABORT_REQUEST_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_OFFSET 37 #define UNIFIED_RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_MASK \ 38 RXPCU_PPDU_END_INFO_10_PHYRX_ABORT_REQUEST_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_MASK 39 #define UNIFIED_RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_LSB \ 40 RXPCU_PPDU_END_INFO_10_PHYRX_ABORT_REQUEST_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_LSB 41 #define UNIFIED_PHYRX_HT_SIG_0_HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS_OFFSET \ 42 PHYRX_HT_SIG_0_HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS_OFFSET 43 #define UNIFIED_PHYRX_L_SIG_B_0_L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS_OFFSET \ 44 PHYRX_L_SIG_B_0_L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS_OFFSET 45 #define UNIFIED_PHYRX_L_SIG_A_0_L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS_OFFSET \ 46 PHYRX_L_SIG_A_0_L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS_OFFSET 47 #define UNIFIED_PHYRX_VHT_SIG_A_0_VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS_OFFSET \ 48 PHYRX_VHT_SIG_A_0_VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS_OFFSET 49 #define UNIFIED_PHYRX_HE_SIG_A_SU_0_HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS_OFFSET \ 50 PHYRX_HE_SIG_A_SU_0_HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS_OFFSET 51 #define UNIFIED_PHYRX_HE_SIG_A_MU_DL_0_HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_OFFSET \ 52 PHYRX_HE_SIG_A_MU_DL_0_HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_OFFSET 53 #define UNIFIED_PHYRX_HE_SIG_B1_MU_0_HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_OFFSET \ 54 PHYRX_HE_SIG_B1_MU_0_HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_OFFSET 55 #define UNIFIED_PHYRX_HE_SIG_B2_MU_0_HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_OFFSET \ 56 PHYRX_HE_SIG_B2_MU_0_HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_OFFSET 57 #define UNIFIED_PHYRX_HE_SIG_B2_OFDMA_0_HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_OFFSET \ 58 PHYRX_HE_SIG_B2_OFDMA_0_HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_OFFSET 59 #define UNIFIED_PHYRX_RSSI_LEGACY_3_RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS_OFFSET \ 60 PHYRX_RSSI_LEGACY_3_RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS_OFFSET 61 #define UNIFIED_PHYRX_RSSI_LEGACY_19_RECEIVE_RSSI_INFO_PREAMBLE_RSSI_INFO_DETAILS_OFFSET \ 62 PHYRX_RSSI_LEGACY_19_RECEIVE_RSSI_INFO_PREAMBLE_RSSI_INFO_DETAILS_OFFSET 63 #define UNIFIED_RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET \ 64 RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET 65 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 66 RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET 67 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ 68 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET 69 #define UNIFIED_RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 70 RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET 71 #define UNIFIED_REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 72 REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET 73 #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC \ 74 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER 75 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSE \ 76 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET 77 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 78 RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET 79 #define UNIFIED_TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 80 TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET 81 #define UNIFIED_TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 82 TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET 83 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET \ 84 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET 85 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB \ 86 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB 87 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK \ 88 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK 89 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB \ 90 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB 91 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK \ 92 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK 93 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB \ 94 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB 95 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK \ 96 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK 97 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB \ 98 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB 99 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK \ 100 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK 101 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB \ 102 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB 103 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK \ 104 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK 105 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_MASK \ 106 WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_MASK 107 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_OFFSET \ 108 WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_OFFSET 109 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_LSB \ 110 WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_LSB 111 112 #include "hal_8074v1_tx.h" 113 #include "hal_8074v1_rx.h" 114 #include <hal_generic_api.h> 115 #include "hal_li_rx.h" 116 #include "hal_li_tx.h" 117 #include "hal_li_api.h" 118 #include "hal_li_generic_api.h" 119 120 /** 121 * hal_get_window_address_8074(): Function to get hp/tp address 122 * @hal_soc: Pointer to hal_soc 123 * @addr: address offset of register 124 * 125 * Return: modified address offset of register 126 */ 127 static inline qdf_iomem_t hal_get_window_address_8074(struct hal_soc *hal_soc, 128 qdf_iomem_t addr) 129 { 130 return addr; 131 } 132 133 /** 134 * hal_rx_get_rx_fragment_number_8074v1(): Function to retrieve 135 * rx fragment number 136 * 137 * @nbuf: Network buffer 138 * Returns: rx fragment number 139 */ 140 static 141 uint8_t hal_rx_get_rx_fragment_number_8074v1(uint8_t *buf) 142 { 143 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 144 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 145 146 /* Return first 4 bits as fragment number */ 147 return (HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info) & 148 DOT11_SEQ_FRAG_MASK); 149 } 150 151 /** 152 * hal_rx_msdu_end_da_is_mcbc_get_8074v1(): API to check if 153 * pkt is MCBC from rx_msdu_end TLV 154 * 155 * @ buf: pointer to the start of RX PKT TLV headers 156 * Return: da_is_mcbc 157 */ 158 static uint8_t 159 hal_rx_msdu_end_da_is_mcbc_get_8074v1(uint8_t *buf) 160 { 161 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 162 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 163 164 return HAL_RX_MSDU_END_DA_IS_MCBC_GET(msdu_end); 165 } 166 167 /** 168 * hal_rx_msdu_end_sa_is_valid_get_8074v1(): API to get_8074v1 the 169 * sa_is_valid bit from rx_msdu_end TLV 170 * 171 * @ buf: pointer to the start of RX PKT TLV headers 172 * Return: sa_is_valid bit 173 */ 174 static uint8_t 175 hal_rx_msdu_end_sa_is_valid_get_8074v1(uint8_t *buf) 176 { 177 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 178 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 179 uint8_t sa_is_valid; 180 181 sa_is_valid = HAL_RX_MSDU_END_SA_IS_VALID_GET(msdu_end); 182 183 return sa_is_valid; 184 } 185 186 /** 187 * hal_rx_msdu_end_sa_idx_get_8074v1(): API to get_8074v1 the 188 * sa_idx from rx_msdu_end TLV 189 * 190 * @ buf: pointer to the start of RX PKT TLV headers 191 * Return: sa_idx (SA AST index) 192 */ 193 static uint16_t hal_rx_msdu_end_sa_idx_get_8074v1(uint8_t *buf) 194 { 195 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 196 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 197 uint16_t sa_idx; 198 199 sa_idx = HAL_RX_MSDU_END_SA_IDX_GET(msdu_end); 200 201 return sa_idx; 202 } 203 204 /** 205 * hal_rx_desc_is_first_msdu_8074v1() - Check if first msdu 206 * 207 * @hal_soc_hdl: hal_soc handle 208 * @hw_desc_addr: hardware descriptor address 209 * 210 * Return: 0 - success/ non-zero failure 211 */ 212 static uint32_t hal_rx_desc_is_first_msdu_8074v1(void *hw_desc_addr) 213 { 214 struct rx_pkt_tlvs *rx_tlvs = (struct rx_pkt_tlvs *)hw_desc_addr; 215 struct rx_msdu_end *msdu_end = &rx_tlvs->msdu_end_tlv.rx_msdu_end; 216 217 return HAL_RX_GET(msdu_end, RX_MSDU_END_5, FIRST_MSDU); 218 } 219 220 /** 221 * hal_rx_msdu_end_l3_hdr_padding_get_8074v1(): API to get_8074v1 the 222 * l3_header padding from rx_msdu_end TLV 223 * 224 * @ buf: pointer to the start of RX PKT TLV headers 225 * Return: number of l3 header padding bytes 226 */ 227 static uint32_t hal_rx_msdu_end_l3_hdr_padding_get_8074v1(uint8_t *buf) 228 { 229 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 230 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 231 uint32_t l3_header_padding; 232 233 l3_header_padding = HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(msdu_end); 234 235 return l3_header_padding; 236 } 237 238 /* 239 * @ hal_rx_encryption_info_valid_8074v1: Returns encryption type. 240 * 241 * @ buf: rx_tlv_hdr of the received packet 242 * @ Return: encryption type 243 */ 244 static uint32_t hal_rx_encryption_info_valid_8074v1(uint8_t *buf) 245 { 246 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 247 struct rx_mpdu_start *mpdu_start = 248 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 249 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 250 uint32_t encryption_info = HAL_RX_MPDU_ENCRYPTION_INFO_VALID(mpdu_info); 251 252 return encryption_info; 253 } 254 255 /* 256 * @ hal_rx_print_pn_8074v1: Prints the PN of rx packet. 257 * 258 * @ buf: rx_tlv_hdr of the received packet 259 * @ Return: void 260 */ 261 static void hal_rx_print_pn_8074v1(uint8_t *buf) 262 { 263 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 264 struct rx_mpdu_start *mpdu_start = 265 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 266 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 267 268 uint32_t pn_31_0 = HAL_RX_MPDU_PN_31_0_GET(mpdu_info); 269 uint32_t pn_63_32 = HAL_RX_MPDU_PN_63_32_GET(mpdu_info); 270 uint32_t pn_95_64 = HAL_RX_MPDU_PN_95_64_GET(mpdu_info); 271 uint32_t pn_127_96 = HAL_RX_MPDU_PN_127_96_GET(mpdu_info); 272 273 hal_debug("PN number pn_127_96 0x%x pn_95_64 0x%x pn_63_32 0x%x pn_31_0 0x%x ", 274 pn_127_96, pn_95_64, pn_63_32, pn_31_0); 275 } 276 277 /** 278 * hal_rx_msdu_end_first_msdu_get_8074v1: API to get first msdu status 279 * from rx_msdu_end TLV 280 * 281 * @ buf: pointer to the start of RX PKT TLV headers 282 * Return: first_msdu 283 */ 284 static uint8_t 285 hal_rx_msdu_end_first_msdu_get_8074v1(uint8_t *buf) 286 { 287 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 288 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 289 uint8_t first_msdu; 290 291 first_msdu = HAL_RX_MSDU_END_FIRST_MSDU_GET(msdu_end); 292 293 return first_msdu; 294 } 295 296 /** 297 * hal_rx_msdu_end_da_is_valid_get_8074v1: API to check if da is valid 298 * from rx_msdu_end TLV 299 * 300 * @ buf: pointer to the start of RX PKT TLV headers 301 * Return: da_is_valid 302 */ 303 static uint8_t hal_rx_msdu_end_da_is_valid_get_8074v1(uint8_t *buf) 304 { 305 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 306 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 307 uint8_t da_is_valid; 308 309 da_is_valid = HAL_RX_MSDU_END_DA_IS_VALID_GET(msdu_end); 310 311 return da_is_valid; 312 } 313 314 /** 315 * hal_rx_msdu_end_last_msdu_get_8074v1: API to get last msdu status 316 * from rx_msdu_end TLV 317 * 318 * @ buf: pointer to the start of RX PKT TLV headers 319 * Return: last_msdu 320 */ 321 static uint8_t hal_rx_msdu_end_last_msdu_get_8074v1(uint8_t *buf) 322 { 323 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 324 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 325 uint8_t last_msdu; 326 327 last_msdu = HAL_RX_MSDU_END_LAST_MSDU_GET(msdu_end); 328 329 return last_msdu; 330 } 331 332 /* 333 * hal_rx_get_mpdu_mac_ad4_valid_8074v1(): Retrieves if mpdu 4th addr is valid 334 * 335 * @nbuf: Network buffer 336 * Returns: value of mpdu 4th address valid field 337 */ 338 static bool hal_rx_get_mpdu_mac_ad4_valid_8074v1(uint8_t *buf) 339 { 340 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 341 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 342 bool ad4_valid = 0; 343 344 ad4_valid = HAL_RX_MPDU_GET_MAC_AD4_VALID(rx_mpdu_info); 345 346 return ad4_valid; 347 } 348 349 /** 350 * hal_rx_mpdu_start_sw_peer_id_get_8074v1: Retrieve sw peer_id 351 * @buf: network buffer 352 * 353 * Return: sw peer_id 354 */ 355 static uint32_t hal_rx_mpdu_start_sw_peer_id_get_8074v1(uint8_t *buf) 356 { 357 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 358 struct rx_mpdu_start *mpdu_start = 359 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 360 361 return HAL_RX_MPDU_INFO_SW_PEER_ID_GET( 362 &mpdu_start->rx_mpdu_info_details); 363 } 364 365 /* 366 * hal_rx_mpdu_get_to_ds_8074v1(): API to get the tods info 367 * from rx_mpdu_start 368 * 369 * @buf: pointer to the start of RX PKT TLV header 370 * Return: uint32_t(to_ds) 371 */ 372 373 static uint32_t hal_rx_mpdu_get_to_ds_8074v1(uint8_t *buf) 374 { 375 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 376 struct rx_mpdu_start *mpdu_start = 377 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 378 379 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 380 381 return HAL_RX_MPDU_GET_TODS(mpdu_info); 382 } 383 384 /* 385 * hal_rx_mpdu_get_fr_ds_8074v1(): API to get the from ds info 386 * from rx_mpdu_start 387 * 388 * @buf: pointer to the start of RX PKT TLV header 389 * Return: uint32_t(fr_ds) 390 */ 391 static uint32_t hal_rx_mpdu_get_fr_ds_8074v1(uint8_t *buf) 392 { 393 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 394 struct rx_mpdu_start *mpdu_start = 395 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 396 397 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 398 399 return HAL_RX_MPDU_GET_FROMDS(mpdu_info); 400 } 401 402 /* 403 * hal_rx_get_mpdu_frame_control_valid_8074v1(): Retrieves mpdu 404 * frame control valid 405 * 406 * @nbuf: Network buffer 407 * Returns: value of frame control valid field 408 */ 409 static uint8_t hal_rx_get_mpdu_frame_control_valid_8074v1(uint8_t *buf) 410 { 411 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 412 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 413 414 return HAL_RX_MPDU_GET_FRAME_CONTROL_VALID(rx_mpdu_info); 415 } 416 417 /* 418 * hal_rx_mpdu_get_addr1_8074v1(): API to check get address1 of the mpdu 419 * 420 * @buf: pointer to the start of RX PKT TLV headera 421 * @mac_addr: pointer to mac address 422 * Return: success/failure 423 */ 424 static QDF_STATUS hal_rx_mpdu_get_addr1_8074v1(uint8_t *buf, 425 uint8_t *mac_addr) 426 { 427 struct __attribute__((__packed__)) hal_addr1 { 428 uint32_t ad1_31_0; 429 uint16_t ad1_47_32; 430 }; 431 432 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 433 struct rx_mpdu_start *mpdu_start = 434 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 435 436 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 437 struct hal_addr1 *addr = (struct hal_addr1 *)mac_addr; 438 uint32_t mac_addr_ad1_valid; 439 440 mac_addr_ad1_valid = HAL_RX_MPDU_MAC_ADDR_AD1_VALID_GET(mpdu_info); 441 442 if (mac_addr_ad1_valid) { 443 addr->ad1_31_0 = HAL_RX_MPDU_AD1_31_0_GET(mpdu_info); 444 addr->ad1_47_32 = HAL_RX_MPDU_AD1_47_32_GET(mpdu_info); 445 return QDF_STATUS_SUCCESS; 446 } 447 448 return QDF_STATUS_E_FAILURE; 449 } 450 451 /* 452 * hal_rx_mpdu_get_addr2_8074v1(): API to check get address2 of the mpdu 453 * in the packet 454 * 455 * @buf: pointer to the start of RX PKT TLV header 456 * @mac_addr: pointer to mac address 457 * Return: success/failure 458 */ 459 static QDF_STATUS hal_rx_mpdu_get_addr2_8074v1(uint8_t *buf, uint8_t *mac_addr) 460 { 461 struct __attribute__((__packed__)) hal_addr2 { 462 uint16_t ad2_15_0; 463 uint32_t ad2_47_16; 464 }; 465 466 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 467 struct rx_mpdu_start *mpdu_start = 468 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 469 470 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 471 struct hal_addr2 *addr = (struct hal_addr2 *)mac_addr; 472 uint32_t mac_addr_ad2_valid; 473 474 mac_addr_ad2_valid = HAL_RX_MPDU_MAC_ADDR_AD2_VALID_GET(mpdu_info); 475 476 if (mac_addr_ad2_valid) { 477 addr->ad2_15_0 = HAL_RX_MPDU_AD2_15_0_GET(mpdu_info); 478 addr->ad2_47_16 = HAL_RX_MPDU_AD2_47_16_GET(mpdu_info); 479 return QDF_STATUS_SUCCESS; 480 } 481 482 return QDF_STATUS_E_FAILURE; 483 } 484 485 /* 486 * hal_rx_mpdu_get_addr3_8074v1(): API to get address3 of the mpdu 487 * in the packet 488 * 489 * @buf: pointer to the start of RX PKT TLV header 490 * @mac_addr: pointer to mac address 491 * Return: success/failure 492 */ 493 static QDF_STATUS hal_rx_mpdu_get_addr3_8074v1(uint8_t *buf, uint8_t *mac_addr) 494 { 495 struct __attribute__((__packed__)) hal_addr3 { 496 uint32_t ad3_31_0; 497 uint16_t ad3_47_32; 498 }; 499 500 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 501 struct rx_mpdu_start *mpdu_start = 502 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 503 504 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 505 struct hal_addr3 *addr = (struct hal_addr3 *)mac_addr; 506 uint32_t mac_addr_ad3_valid; 507 508 mac_addr_ad3_valid = HAL_RX_MPDU_MAC_ADDR_AD3_VALID_GET(mpdu_info); 509 510 if (mac_addr_ad3_valid) { 511 addr->ad3_31_0 = HAL_RX_MPDU_AD3_31_0_GET(mpdu_info); 512 addr->ad3_47_32 = HAL_RX_MPDU_AD3_47_32_GET(mpdu_info); 513 return QDF_STATUS_SUCCESS; 514 } 515 516 return QDF_STATUS_E_FAILURE; 517 } 518 519 /* 520 * hal_rx_mpdu_get_addr4_8074v1(): API to get address4 of the mpdu 521 * in the packet 522 * 523 * @buf: pointer to the start of RX PKT TLV header 524 * @mac_addr: pointer to mac address 525 * Return: success/failure 526 */ 527 static QDF_STATUS hal_rx_mpdu_get_addr4_8074v1(uint8_t *buf, uint8_t *mac_addr) 528 { 529 struct __attribute__((__packed__)) hal_addr4 { 530 uint32_t ad4_31_0; 531 uint16_t ad4_47_32; 532 }; 533 534 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 535 struct rx_mpdu_start *mpdu_start = 536 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 537 538 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 539 struct hal_addr4 *addr = (struct hal_addr4 *)mac_addr; 540 uint32_t mac_addr_ad4_valid; 541 542 mac_addr_ad4_valid = HAL_RX_MPDU_MAC_ADDR_AD4_VALID_GET(mpdu_info); 543 544 if (mac_addr_ad4_valid) { 545 addr->ad4_31_0 = HAL_RX_MPDU_AD4_31_0_GET(mpdu_info); 546 addr->ad4_47_32 = HAL_RX_MPDU_AD4_47_32_GET(mpdu_info); 547 return QDF_STATUS_SUCCESS; 548 } 549 550 return QDF_STATUS_E_FAILURE; 551 } 552 553 /* 554 * hal_rx_get_mpdu_sequence_control_valid_8074v1(): Get mpdu 555 * sequence control valid 556 * 557 * @nbuf: Network buffer 558 * Returns: value of sequence control valid field 559 */ 560 static uint8_t hal_rx_get_mpdu_sequence_control_valid_8074v1(uint8_t *buf) 561 { 562 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 563 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 564 565 return HAL_RX_MPDU_GET_SEQUENCE_CONTROL_VALID(rx_mpdu_info); 566 } 567 568 /** 569 * hal_rx_is_unicast_8074v1: check packet is unicast frame or not. 570 * 571 * @ buf: pointer to rx pkt TLV. 572 * 573 * Return: true on unicast. 574 */ 575 static bool hal_rx_is_unicast_8074v1(uint8_t *buf) 576 { 577 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 578 struct rx_mpdu_start *mpdu_start = 579 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 580 uint32_t grp_id; 581 uint8_t *rx_mpdu_info = (uint8_t *)&mpdu_start->rx_mpdu_info_details; 582 583 grp_id = (_HAL_MS((*_OFFSET_TO_WORD_PTR((rx_mpdu_info), 584 RX_MPDU_INFO_0_SW_FRAME_GROUP_ID_OFFSET)), 585 RX_MPDU_INFO_0_SW_FRAME_GROUP_ID_MASK, 586 RX_MPDU_INFO_0_SW_FRAME_GROUP_ID_LSB)); 587 588 return (HAL_MPDU_SW_FRAME_GROUP_UNICAST_DATA == grp_id) ? true : false; 589 } 590 591 /** 592 * hal_rx_tid_get_8074v1: get tid based on qos control valid. 593 * 594 * @ buf: pointer to rx pkt TLV. 595 * 596 * Return: tid 597 */ 598 static uint32_t hal_rx_tid_get_8074v1(hal_soc_handle_t hal_soc_hdl, 599 uint8_t *buf) 600 { 601 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 602 struct rx_mpdu_start *mpdu_start = 603 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 604 uint8_t *rx_mpdu_info = (uint8_t *)&mpdu_start->rx_mpdu_info_details; 605 uint8_t qos_control_valid = 606 (_HAL_MS((*_OFFSET_TO_WORD_PTR((rx_mpdu_info), 607 RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_OFFSET)), 608 RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_MASK, 609 RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_LSB)); 610 611 if (qos_control_valid) 612 return hal_rx_mpdu_start_tid_get_8074(buf); 613 614 return HAL_RX_NON_QOS_TID; 615 } 616 617 /** 618 * hal_rx_hw_desc_get_ppduid_get_8074v1(): retrieve ppdu id 619 * @rx_tlv_hdr: Rx tlv header 620 * @rxdma_dst_ring_desc: Rx HW descriptor 621 * 622 * Return: ppdu id 623 */ 624 static uint32_t hal_rx_hw_desc_get_ppduid_get_8074v1(void *rx_tlv_hdr, 625 void *rxdma_dst_ring_desc) 626 { 627 struct rx_mpdu_info *rx_mpdu_info; 628 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)rx_tlv_hdr; 629 630 rx_mpdu_info = 631 &rx_desc->mpdu_start_tlv.rx_mpdu_start.rx_mpdu_info_details; 632 633 return HAL_RX_GET(rx_mpdu_info, RX_MPDU_INFO_0, PHY_PPDU_ID); 634 } 635 636 /** 637 * hal_reo_status_get_header_8074v1 - Process reo desc info 638 * @ring_desc: REO status ring descriptor 639 * @b - tlv type info 640 * @h1 - Pointer to hal_reo_status_header where info to be stored 641 * 642 * Return - none. 643 * 644 */ 645 static void hal_reo_status_get_header_8074v1(hal_ring_desc_t ring_desc, int b, 646 void *h1) 647 { 648 uint32_t *d = (uint32_t *)ring_desc; 649 uint32_t val1 = 0; 650 struct hal_reo_status_header *h = 651 (struct hal_reo_status_header *)h1; 652 653 /* Offsets of descriptor fields defined in HW headers start 654 * from the field after TLV header 655 */ 656 d += HAL_GET_NUM_DWORDS(sizeof(struct tlv_32_hdr)); 657 658 switch (b) { 659 case HAL_REO_QUEUE_STATS_STATUS_TLV: 660 val1 = d[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_0, 661 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 662 break; 663 case HAL_REO_FLUSH_QUEUE_STATUS_TLV: 664 val1 = d[HAL_OFFSET_DW(REO_FLUSH_QUEUE_STATUS_0, 665 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 666 break; 667 case HAL_REO_FLUSH_CACHE_STATUS_TLV: 668 val1 = d[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_0, 669 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 670 break; 671 case HAL_REO_UNBLK_CACHE_STATUS_TLV: 672 val1 = d[HAL_OFFSET_DW(REO_UNBLOCK_CACHE_STATUS_0, 673 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 674 break; 675 case HAL_REO_TIMOUT_LIST_STATUS_TLV: 676 val1 = d[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_0, 677 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 678 break; 679 case HAL_REO_DESC_THRES_STATUS_TLV: 680 val1 = 681 d[HAL_OFFSET_DW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0, 682 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 683 break; 684 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: 685 val1 = d[HAL_OFFSET_DW(REO_UPDATE_RX_REO_QUEUE_STATUS_0, 686 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 687 break; 688 default: 689 qdf_nofl_err("ERROR: Unknown tlv\n"); 690 break; 691 } 692 h->cmd_num = 693 HAL_GET_FIELD( 694 UNIFORM_REO_STATUS_HEADER_0, REO_STATUS_NUMBER, 695 val1); 696 h->exec_time = 697 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_0, 698 CMD_EXECUTION_TIME, val1); 699 h->status = 700 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_0, 701 REO_CMD_EXECUTION_STATUS, val1); 702 switch (b) { 703 case HAL_REO_QUEUE_STATS_STATUS_TLV: 704 val1 = d[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_1, 705 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 706 break; 707 case HAL_REO_FLUSH_QUEUE_STATUS_TLV: 708 val1 = d[HAL_OFFSET_DW(REO_FLUSH_QUEUE_STATUS_1, 709 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 710 break; 711 case HAL_REO_FLUSH_CACHE_STATUS_TLV: 712 val1 = d[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_1, 713 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 714 break; 715 case HAL_REO_UNBLK_CACHE_STATUS_TLV: 716 val1 = d[HAL_OFFSET_DW(REO_UNBLOCK_CACHE_STATUS_1, 717 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 718 break; 719 case HAL_REO_TIMOUT_LIST_STATUS_TLV: 720 val1 = d[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_1, 721 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 722 break; 723 case HAL_REO_DESC_THRES_STATUS_TLV: 724 val1 = 725 d[HAL_OFFSET_DW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_1, 726 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 727 break; 728 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: 729 val1 = d[HAL_OFFSET_DW(REO_UPDATE_RX_REO_QUEUE_STATUS_1, 730 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 731 break; 732 default: 733 qdf_nofl_err("ERROR: Unknown tlv\n"); 734 break; 735 } 736 h->tstamp = 737 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_1, TIMESTAMP, val1); 738 } 739 740 /** 741 * hal_rx_mpdu_start_mpdu_qos_control_valid_get_8074v1(): 742 * Retrieve qos control valid bit from the tlv. 743 * @buf: pointer to rx pkt TLV. 744 * 745 * Return: qos control value. 746 */ 747 static inline uint32_t 748 hal_rx_mpdu_start_mpdu_qos_control_valid_get_8074v1(uint8_t *buf) 749 { 750 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 751 struct rx_mpdu_start *mpdu_start = 752 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 753 754 return HAL_RX_MPDU_INFO_QOS_CONTROL_VALID_GET( 755 &mpdu_start->rx_mpdu_info_details); 756 } 757 758 /** 759 * hal_rx_msdu_end_sa_sw_peer_id_get_8074v1(): API to get the 760 * sa_sw_peer_id from rx_msdu_end TLV 761 * @buf: pointer to the start of RX PKT TLV headers 762 * 763 * Return: sa_sw_peer_id index 764 */ 765 static inline uint32_t 766 hal_rx_msdu_end_sa_sw_peer_id_get_8074v1(uint8_t *buf) 767 { 768 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 769 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 770 771 return HAL_RX_MSDU_END_SA_SW_PEER_ID_GET(msdu_end); 772 } 773 774 /** 775 * hal_tx_desc_set_mesh_en_8074v1 - Set mesh_enable flag in Tx descriptor 776 * @desc: Handle to Tx Descriptor 777 * @en: For raw WiFi frames, this indicates transmission to a mesh STA, 778 * enabling the interpretation of the 'Mesh Control Present' bit 779 * (bit 8) of QoS Control (otherwise this bit is ignored), 780 * For native WiFi frames, this indicates that a 'Mesh Control' field 781 * is present between the header and the LLC. 782 * 783 * Return: void 784 */ 785 static inline 786 void hal_tx_desc_set_mesh_en_8074v1(void *desc, uint8_t en) 787 { 788 HAL_SET_FLD(desc, TCL_DATA_CMD_4, MESH_ENABLE) |= 789 HAL_TX_SM(TCL_DATA_CMD_4, MESH_ENABLE, en); 790 } 791 792 static 793 void *hal_rx_msdu0_buffer_addr_lsb_8074v1(void *link_desc_va) 794 { 795 return (void *)HAL_RX_MSDU0_BUFFER_ADDR_LSB(link_desc_va); 796 } 797 798 static 799 void *hal_rx_msdu_desc_info_ptr_get_8074v1(void *msdu0) 800 { 801 return (void *)HAL_RX_MSDU_DESC_INFO_PTR_GET(msdu0); 802 } 803 804 static 805 void *hal_ent_mpdu_desc_info_8074v1(void *ent_ring_desc) 806 { 807 return (void *)HAL_ENT_MPDU_DESC_INFO(ent_ring_desc); 808 } 809 810 static 811 void *hal_dst_mpdu_desc_info_8074v1(void *dst_ring_desc) 812 { 813 return (void *)HAL_DST_MPDU_DESC_INFO(dst_ring_desc); 814 } 815 816 static 817 uint8_t hal_rx_get_fc_valid_8074v1(uint8_t *buf) 818 { 819 return HAL_RX_GET_FC_VALID(buf); 820 } 821 822 static uint8_t hal_rx_get_to_ds_flag_8074v1(uint8_t *buf) 823 { 824 return HAL_RX_GET_TO_DS_FLAG(buf); 825 } 826 827 static uint8_t hal_rx_get_mac_addr2_valid_8074v1(uint8_t *buf) 828 { 829 return HAL_RX_GET_MAC_ADDR2_VALID(buf); 830 } 831 832 static uint8_t hal_rx_get_filter_category_8074v1(uint8_t *buf) 833 { 834 return HAL_RX_GET_FILTER_CATEGORY(buf); 835 } 836 837 static uint32_t 838 hal_rx_get_ppdu_id_8074v1(uint8_t *buf) 839 { 840 struct rx_mpdu_info *rx_mpdu_info; 841 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)buf; 842 843 rx_mpdu_info = 844 &rx_desc->mpdu_start_tlv.rx_mpdu_start.rx_mpdu_info_details; 845 846 return HAL_RX_GET_PPDU_ID(rx_mpdu_info); 847 } 848 849 /** 850 * hal_reo_config_8074v1(): Set reo config parameters 851 * @soc: hal soc handle 852 * @reg_val: value to be set 853 * @reo_params: reo parameters 854 * 855 * Return: void 856 */ 857 static void 858 hal_reo_config_8074v1(struct hal_soc *soc, 859 uint32_t reg_val, 860 struct hal_reo_params *reo_params) 861 { 862 HAL_REO_R0_CONFIG(soc, reg_val, reo_params); 863 } 864 865 /** 866 * hal_rx_msdu_desc_info_get_ptr_8074v1() - Get msdu desc info ptr 867 * @msdu_details_ptr - Pointer to msdu_details_ptr 868 * 869 * Return - Pointer to rx_msdu_desc_info structure. 870 * 871 */ 872 static void *hal_rx_msdu_desc_info_get_ptr_8074v1(void *msdu_details_ptr) 873 { 874 return HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr); 875 } 876 877 /** 878 * hal_rx_link_desc_msdu0_ptr_8074v1 - Get pointer to rx_msdu details 879 * @link_desc - Pointer to link desc 880 * 881 * Return - Pointer to rx_msdu_details structure 882 * 883 */ 884 static void *hal_rx_link_desc_msdu0_ptr_8074v1(void *link_desc) 885 { 886 return HAL_RX_LINK_DESC_MSDU0_PTR(link_desc); 887 } 888 889 /** 890 * hal_rx_msdu_flow_idx_get_8074v1: API to get flow index 891 * from rx_msdu_end TLV 892 * @buf: pointer to the start of RX PKT TLV headers 893 * 894 * Return: flow index value from MSDU END TLV 895 */ 896 static inline uint32_t hal_rx_msdu_flow_idx_get_8074v1(uint8_t *buf) 897 { 898 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 899 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 900 901 return HAL_RX_MSDU_END_FLOW_IDX_GET(msdu_end); 902 } 903 904 /** 905 * hal_rx_msdu_flow_idx_invalid_8074v1: API to get flow index invalid 906 * from rx_msdu_end TLV 907 * @buf: pointer to the start of RX PKT TLV headers 908 * 909 * Return: flow index invalid value from MSDU END TLV 910 */ 911 static bool hal_rx_msdu_flow_idx_invalid_8074v1(uint8_t *buf) 912 { 913 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 914 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 915 916 return HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(msdu_end); 917 } 918 919 /** 920 * hal_rx_msdu_flow_idx_timeout_8074v1: API to get flow index timeout 921 * from rx_msdu_end TLV 922 * @buf: pointer to the start of RX PKT TLV headers 923 * 924 * Return: flow index timeout value from MSDU END TLV 925 */ 926 static bool hal_rx_msdu_flow_idx_timeout_8074v1(uint8_t *buf) 927 { 928 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 929 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 930 931 return HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(msdu_end); 932 } 933 934 /** 935 * hal_rx_msdu_fse_metadata_get_8074v1: API to get FSE metadata 936 * from rx_msdu_end TLV 937 * @buf: pointer to the start of RX PKT TLV headers 938 * 939 * Return: fse metadata value from MSDU END TLV 940 */ 941 static uint32_t hal_rx_msdu_fse_metadata_get_8074v1(uint8_t *buf) 942 { 943 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 944 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 945 946 return HAL_RX_MSDU_END_FSE_METADATA_GET(msdu_end); 947 } 948 949 /** 950 * hal_rx_msdu_cce_metadata_get_8074v1: API to get CCE metadata 951 * from rx_msdu_end TLV 952 * @buf: pointer to the start of RX PKT TLV headers 953 * 954 * Return: cce_metadata 955 */ 956 static uint16_t 957 hal_rx_msdu_cce_metadata_get_8074v1(uint8_t *buf) 958 { 959 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 960 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 961 962 return HAL_RX_MSDU_END_CCE_METADATA_GET(msdu_end); 963 } 964 965 /** 966 * hal_rx_msdu_get_flow_params_8074v1: API to get flow index, flow index invalid 967 * and flow index timeout from rx_msdu_end TLV 968 * @buf: pointer to the start of RX PKT TLV headers 969 * @flow_invalid: pointer to return value of flow_idx_valid 970 * @flow_timeout: pointer to return value of flow_idx_timeout 971 * @flow_index: pointer to return value of flow_idx 972 * 973 * Return: none 974 */ 975 static inline void 976 hal_rx_msdu_get_flow_params_8074v1(uint8_t *buf, 977 bool *flow_invalid, 978 bool *flow_timeout, 979 uint32_t *flow_index) 980 { 981 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 982 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 983 984 *flow_invalid = HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(msdu_end); 985 *flow_timeout = HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(msdu_end); 986 *flow_index = HAL_RX_MSDU_END_FLOW_IDX_GET(msdu_end); 987 } 988 989 /** 990 * hal_rx_tlv_get_tcp_chksum_8074v1() - API to get tcp checksum 991 * @buf: rx_tlv_hdr 992 * 993 * Return: tcp checksum 994 */ 995 static uint16_t 996 hal_rx_tlv_get_tcp_chksum_8074v1(uint8_t *buf) 997 { 998 return HAL_RX_TLV_GET_TCP_CHKSUM(buf); 999 } 1000 1001 /** 1002 * hal_rx_get_rx_sequence_8074v1(): Function to retrieve rx sequence number 1003 * 1004 * @nbuf: Network buffer 1005 * Returns: rx sequence number 1006 */ 1007 static 1008 uint16_t hal_rx_get_rx_sequence_8074v1(uint8_t *buf) 1009 { 1010 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 1011 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 1012 1013 return HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info); 1014 } 1015 1016 /** 1017 * hal_rx_mpdu_start_tlv_tag_valid_8074v1 () - API to check if RX_MPDU_START 1018 * tlv tag is valid 1019 * 1020 * @rx_tlv_hdr: start address of rx_pkt_tlvs 1021 * 1022 * Return: true if RX_MPDU_START is valied, else false. 1023 */ 1024 uint8_t hal_rx_mpdu_start_tlv_tag_valid_8074v1(void *rx_tlv_hdr) 1025 { 1026 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)rx_tlv_hdr; 1027 uint32_t tlv_tag; 1028 1029 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE( 1030 &rx_desc->mpdu_start_tlv); 1031 1032 return tlv_tag == WIFIRX_MPDU_START_E ? true : false; 1033 } 1034 1035 /** 1036 * hal_rx_flow_setup_fse_8074v1() - Setup a flow search entry in HW FST 1037 * @fst: Pointer to the Rx Flow Search Table 1038 * @table_offset: offset into the table where the flow is to be setup 1039 * @flow: Flow Parameters 1040 * 1041 * Return: Success/Failure 1042 */ 1043 static void * 1044 hal_rx_flow_setup_fse_8074v1(uint8_t *rx_fst, uint32_t table_offset, 1045 uint8_t *rx_flow) 1046 { 1047 struct hal_rx_fst *fst = (struct hal_rx_fst *)rx_fst; 1048 struct hal_rx_flow *flow = (struct hal_rx_flow *)rx_flow; 1049 uint8_t *fse; 1050 bool fse_valid; 1051 1052 if (table_offset >= fst->max_entries) { 1053 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR, 1054 "HAL FSE table offset %u exceeds max entries %u", 1055 table_offset, fst->max_entries); 1056 return NULL; 1057 } 1058 1059 fse = (uint8_t *)fst->base_vaddr + 1060 (table_offset * HAL_RX_FST_ENTRY_SIZE); 1061 1062 fse_valid = HAL_GET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, VALID); 1063 1064 if (fse_valid) { 1065 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_DEBUG, 1066 "HAL FSE %pK already valid", fse); 1067 return NULL; 1068 } 1069 1070 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_0, SRC_IP_127_96) = 1071 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_0, SRC_IP_127_96, 1072 qdf_htonl(flow->tuple_info.src_ip_127_96)); 1073 1074 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_1, SRC_IP_95_64) = 1075 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_1, SRC_IP_95_64, 1076 qdf_htonl(flow->tuple_info.src_ip_95_64)); 1077 1078 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_2, SRC_IP_63_32) = 1079 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_2, SRC_IP_63_32, 1080 qdf_htonl(flow->tuple_info.src_ip_63_32)); 1081 1082 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_3, SRC_IP_31_0) = 1083 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_3, SRC_IP_31_0, 1084 qdf_htonl(flow->tuple_info.src_ip_31_0)); 1085 1086 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_4, DEST_IP_127_96) = 1087 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_4, DEST_IP_127_96, 1088 qdf_htonl(flow->tuple_info.dest_ip_127_96)); 1089 1090 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_5, DEST_IP_95_64) = 1091 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_5, DEST_IP_95_64, 1092 qdf_htonl(flow->tuple_info.dest_ip_95_64)); 1093 1094 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_6, DEST_IP_63_32) = 1095 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_6, DEST_IP_63_32, 1096 qdf_htonl(flow->tuple_info.dest_ip_63_32)); 1097 1098 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_7, DEST_IP_31_0) = 1099 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_7, DEST_IP_31_0, 1100 qdf_htonl(flow->tuple_info.dest_ip_31_0)); 1101 1102 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, DEST_PORT); 1103 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, DEST_PORT) |= 1104 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_8, DEST_PORT, 1105 (flow->tuple_info.dest_port)); 1106 1107 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, SRC_PORT); 1108 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, SRC_PORT) |= 1109 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_8, SRC_PORT, 1110 (flow->tuple_info.src_port)); 1111 1112 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, L4_PROTOCOL); 1113 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, L4_PROTOCOL) |= 1114 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, L4_PROTOCOL, 1115 flow->tuple_info.l4_protocol); 1116 1117 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_HANDLER); 1118 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_HANDLER) |= 1119 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_HANDLER, 1120 flow->reo_destination_handler); 1121 1122 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, VALID); 1123 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, VALID) |= 1124 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, VALID, 1); 1125 1126 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_10, METADATA); 1127 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_10, METADATA) = 1128 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_10, METADATA, 1129 flow->fse_metadata); 1130 1131 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_11, REO_DESTINATION_INDICATION); 1132 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_11, REO_DESTINATION_INDICATION) |= 1133 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_11, 1134 REO_DESTINATION_INDICATION, 1135 flow->reo_destination_indication); 1136 1137 /* Reset all the other fields in FSE */ 1138 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, RESERVED_9); 1139 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_11, MSDU_DROP); 1140 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_11, RESERVED_11); 1141 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_11, MSDU_COUNT); 1142 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_12, MSDU_BYTE_COUNT); 1143 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_13, TIMESTAMP); 1144 1145 return fse; 1146 } 1147 1148 static 1149 void hal_compute_reo_remap_ix2_ix3_8074v1(uint32_t *ring, uint32_t num_rings, 1150 uint32_t *remap1, uint32_t *remap2) 1151 { 1152 switch (num_rings) { 1153 case 1: 1154 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 1155 HAL_REO_REMAP_IX2(ring[0], 17) | 1156 HAL_REO_REMAP_IX2(ring[0], 18) | 1157 HAL_REO_REMAP_IX2(ring[0], 19) | 1158 HAL_REO_REMAP_IX2(ring[0], 20) | 1159 HAL_REO_REMAP_IX2(ring[0], 21) | 1160 HAL_REO_REMAP_IX2(ring[0], 22) | 1161 HAL_REO_REMAP_IX2(ring[0], 23); 1162 1163 *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) | 1164 HAL_REO_REMAP_IX3(ring[0], 25) | 1165 HAL_REO_REMAP_IX3(ring[0], 26) | 1166 HAL_REO_REMAP_IX3(ring[0], 27) | 1167 HAL_REO_REMAP_IX3(ring[0], 28) | 1168 HAL_REO_REMAP_IX3(ring[0], 29) | 1169 HAL_REO_REMAP_IX3(ring[0], 30) | 1170 HAL_REO_REMAP_IX3(ring[0], 31); 1171 break; 1172 case 2: 1173 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 1174 HAL_REO_REMAP_IX2(ring[0], 17) | 1175 HAL_REO_REMAP_IX2(ring[1], 18) | 1176 HAL_REO_REMAP_IX2(ring[1], 19) | 1177 HAL_REO_REMAP_IX2(ring[0], 20) | 1178 HAL_REO_REMAP_IX2(ring[0], 21) | 1179 HAL_REO_REMAP_IX2(ring[1], 22) | 1180 HAL_REO_REMAP_IX2(ring[1], 23); 1181 1182 *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) | 1183 HAL_REO_REMAP_IX3(ring[0], 25) | 1184 HAL_REO_REMAP_IX3(ring[1], 26) | 1185 HAL_REO_REMAP_IX3(ring[1], 27) | 1186 HAL_REO_REMAP_IX3(ring[0], 28) | 1187 HAL_REO_REMAP_IX3(ring[0], 29) | 1188 HAL_REO_REMAP_IX3(ring[1], 30) | 1189 HAL_REO_REMAP_IX3(ring[1], 31); 1190 break; 1191 case 3: 1192 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 1193 HAL_REO_REMAP_IX2(ring[1], 17) | 1194 HAL_REO_REMAP_IX2(ring[2], 18) | 1195 HAL_REO_REMAP_IX2(ring[0], 19) | 1196 HAL_REO_REMAP_IX2(ring[1], 20) | 1197 HAL_REO_REMAP_IX2(ring[2], 21) | 1198 HAL_REO_REMAP_IX2(ring[0], 22) | 1199 HAL_REO_REMAP_IX2(ring[1], 23); 1200 1201 *remap2 = HAL_REO_REMAP_IX3(ring[2], 24) | 1202 HAL_REO_REMAP_IX3(ring[0], 25) | 1203 HAL_REO_REMAP_IX3(ring[1], 26) | 1204 HAL_REO_REMAP_IX3(ring[2], 27) | 1205 HAL_REO_REMAP_IX3(ring[0], 28) | 1206 HAL_REO_REMAP_IX3(ring[1], 29) | 1207 HAL_REO_REMAP_IX3(ring[2], 30) | 1208 HAL_REO_REMAP_IX3(ring[0], 31); 1209 break; 1210 case 4: 1211 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 1212 HAL_REO_REMAP_IX2(ring[1], 17) | 1213 HAL_REO_REMAP_IX2(ring[2], 18) | 1214 HAL_REO_REMAP_IX2(ring[3], 19) | 1215 HAL_REO_REMAP_IX2(ring[0], 20) | 1216 HAL_REO_REMAP_IX2(ring[1], 21) | 1217 HAL_REO_REMAP_IX2(ring[2], 22) | 1218 HAL_REO_REMAP_IX2(ring[3], 23); 1219 1220 *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) | 1221 HAL_REO_REMAP_IX3(ring[1], 25) | 1222 HAL_REO_REMAP_IX3(ring[2], 26) | 1223 HAL_REO_REMAP_IX3(ring[3], 27) | 1224 HAL_REO_REMAP_IX3(ring[0], 28) | 1225 HAL_REO_REMAP_IX3(ring[1], 29) | 1226 HAL_REO_REMAP_IX3(ring[2], 30) | 1227 HAL_REO_REMAP_IX3(ring[3], 31); 1228 break; 1229 } 1230 } 1231 1232 static void hal_hw_txrx_ops_attach_qca8074(struct hal_soc *hal_soc) 1233 { 1234 1235 /* init and setup */ 1236 hal_soc->ops->hal_srng_dst_hw_init = hal_srng_dst_hw_init_generic; 1237 hal_soc->ops->hal_srng_src_hw_init = hal_srng_src_hw_init_generic; 1238 hal_soc->ops->hal_get_hw_hptp = hal_get_hw_hptp_generic; 1239 hal_soc->ops->hal_reo_setup = hal_reo_setup_generic_li; 1240 hal_soc->ops->hal_get_window_address = hal_get_window_address_8074; 1241 1242 /* tx */ 1243 hal_soc->ops->hal_tx_desc_set_dscp_tid_table_id = 1244 hal_tx_desc_set_dscp_tid_table_id_8074; 1245 hal_soc->ops->hal_tx_set_dscp_tid_map = hal_tx_set_dscp_tid_map_8074; 1246 hal_soc->ops->hal_tx_update_dscp_tid = hal_tx_update_dscp_tid_8074; 1247 hal_soc->ops->hal_tx_desc_set_lmac_id = hal_tx_desc_set_lmac_id_8074; 1248 hal_soc->ops->hal_tx_desc_set_buf_addr = 1249 hal_tx_desc_set_buf_addr_generic_li; 1250 hal_soc->ops->hal_tx_desc_set_search_type = 1251 hal_tx_desc_set_search_type_generic_li; 1252 hal_soc->ops->hal_tx_desc_set_search_index = 1253 hal_tx_desc_set_search_index_generic_li; 1254 hal_soc->ops->hal_tx_desc_set_cache_set_num = 1255 hal_tx_desc_set_cache_set_num_generic_li; 1256 hal_soc->ops->hal_tx_comp_get_status = 1257 hal_tx_comp_get_status_generic_li; 1258 hal_soc->ops->hal_tx_comp_get_release_reason = 1259 hal_tx_comp_get_release_reason_generic_li; 1260 hal_soc->ops->hal_get_wbm_internal_error = 1261 hal_get_wbm_internal_error_generic_li; 1262 hal_soc->ops->hal_tx_desc_set_mesh_en = hal_tx_desc_set_mesh_en_8074v1; 1263 hal_soc->ops->hal_tx_init_cmd_credit_ring = 1264 hal_tx_init_cmd_credit_ring_8074v1; 1265 1266 /* rx */ 1267 hal_soc->ops->hal_rx_msdu_start_nss_get = 1268 hal_rx_msdu_start_nss_get_8074; 1269 hal_soc->ops->hal_rx_mon_hw_desc_get_mpdu_status = 1270 hal_rx_mon_hw_desc_get_mpdu_status_8074; 1271 hal_soc->ops->hal_rx_get_tlv = hal_rx_get_tlv_8074; 1272 hal_soc->ops->hal_rx_proc_phyrx_other_receive_info_tlv = 1273 hal_rx_proc_phyrx_other_receive_info_tlv_8074; 1274 hal_soc->ops->hal_rx_dump_msdu_start_tlv = 1275 hal_rx_dump_msdu_start_tlv_8074; 1276 hal_soc->ops->hal_rx_dump_msdu_end_tlv = hal_rx_dump_msdu_end_tlv_8074; 1277 hal_soc->ops->hal_get_link_desc_size = hal_get_link_desc_size_8074; 1278 hal_soc->ops->hal_rx_mpdu_start_tid_get = 1279 hal_rx_mpdu_start_tid_get_8074; 1280 hal_soc->ops->hal_rx_msdu_start_reception_type_get = 1281 hal_rx_msdu_start_reception_type_get_8074; 1282 hal_soc->ops->hal_rx_msdu_end_da_idx_get = 1283 hal_rx_msdu_end_da_idx_get_8074; 1284 hal_soc->ops->hal_rx_msdu_desc_info_get_ptr = 1285 hal_rx_msdu_desc_info_get_ptr_8074v1; 1286 hal_soc->ops->hal_rx_link_desc_msdu0_ptr = 1287 hal_rx_link_desc_msdu0_ptr_8074v1; 1288 hal_soc->ops->hal_reo_status_get_header = 1289 hal_reo_status_get_header_8074v1; 1290 hal_soc->ops->hal_rx_status_get_tlv_info = 1291 hal_rx_status_get_tlv_info_generic_li; 1292 hal_soc->ops->hal_rx_wbm_err_info_get = 1293 hal_rx_wbm_err_info_get_generic_li; 1294 hal_soc->ops->hal_rx_dump_mpdu_start_tlv = 1295 hal_rx_dump_mpdu_start_tlv_generic_li; 1296 1297 hal_soc->ops->hal_tx_set_pcp_tid_map = 1298 hal_tx_set_pcp_tid_map_generic_li; 1299 hal_soc->ops->hal_tx_update_pcp_tid_map = 1300 hal_tx_update_pcp_tid_generic_li; 1301 hal_soc->ops->hal_tx_set_tidmap_prty = 1302 hal_tx_update_tidmap_prty_generic_li; 1303 hal_soc->ops->hal_rx_get_rx_fragment_number = 1304 hal_rx_get_rx_fragment_number_8074v1; 1305 hal_soc->ops->hal_rx_msdu_end_da_is_mcbc_get = 1306 hal_rx_msdu_end_da_is_mcbc_get_8074v1; 1307 hal_soc->ops->hal_rx_msdu_end_sa_is_valid_get = 1308 hal_rx_msdu_end_sa_is_valid_get_8074v1; 1309 hal_soc->ops->hal_rx_msdu_end_sa_idx_get = 1310 hal_rx_msdu_end_sa_idx_get_8074v1; 1311 hal_soc->ops->hal_rx_desc_is_first_msdu = 1312 hal_rx_desc_is_first_msdu_8074v1; 1313 hal_soc->ops->hal_rx_msdu_end_l3_hdr_padding_get = 1314 hal_rx_msdu_end_l3_hdr_padding_get_8074v1; 1315 hal_soc->ops->hal_rx_encryption_info_valid = 1316 hal_rx_encryption_info_valid_8074v1; 1317 hal_soc->ops->hal_rx_print_pn = hal_rx_print_pn_8074v1; 1318 hal_soc->ops->hal_rx_msdu_end_first_msdu_get = 1319 hal_rx_msdu_end_first_msdu_get_8074v1; 1320 hal_soc->ops->hal_rx_msdu_end_da_is_valid_get = 1321 hal_rx_msdu_end_da_is_valid_get_8074v1; 1322 hal_soc->ops->hal_rx_msdu_end_last_msdu_get = 1323 hal_rx_msdu_end_last_msdu_get_8074v1; 1324 hal_soc->ops->hal_rx_get_mpdu_mac_ad4_valid = 1325 hal_rx_get_mpdu_mac_ad4_valid_8074v1; 1326 hal_soc->ops->hal_rx_mpdu_start_sw_peer_id_get = 1327 hal_rx_mpdu_start_sw_peer_id_get_8074v1; 1328 hal_soc->ops->hal_rx_tlv_peer_meta_data_get = 1329 hal_rx_mpdu_peer_meta_data_get_li; 1330 hal_soc->ops->hal_rx_mpdu_get_to_ds = hal_rx_mpdu_get_to_ds_8074v1; 1331 hal_soc->ops->hal_rx_mpdu_get_fr_ds = hal_rx_mpdu_get_fr_ds_8074v1; 1332 hal_soc->ops->hal_rx_get_mpdu_frame_control_valid = 1333 hal_rx_get_mpdu_frame_control_valid_8074v1; 1334 hal_soc->ops->hal_rx_mpdu_get_addr1 = hal_rx_mpdu_get_addr1_8074v1; 1335 hal_soc->ops->hal_rx_mpdu_get_addr2 = hal_rx_mpdu_get_addr2_8074v1; 1336 hal_soc->ops->hal_rx_mpdu_get_addr3 = hal_rx_mpdu_get_addr3_8074v1; 1337 hal_soc->ops->hal_rx_mpdu_get_addr4 = hal_rx_mpdu_get_addr4_8074v1; 1338 hal_soc->ops->hal_rx_get_mpdu_sequence_control_valid = 1339 hal_rx_get_mpdu_sequence_control_valid_8074v1; 1340 hal_soc->ops->hal_rx_is_unicast = hal_rx_is_unicast_8074v1; 1341 hal_soc->ops->hal_rx_tid_get = hal_rx_tid_get_8074v1; 1342 hal_soc->ops->hal_rx_hw_desc_get_ppduid_get = 1343 hal_rx_hw_desc_get_ppduid_get_8074v1; 1344 hal_soc->ops->hal_rx_mpdu_start_mpdu_qos_control_valid_get = 1345 hal_rx_mpdu_start_mpdu_qos_control_valid_get_8074v1; 1346 hal_soc->ops->hal_rx_msdu_end_sa_sw_peer_id_get = 1347 hal_rx_msdu_end_sa_sw_peer_id_get_8074v1; 1348 hal_soc->ops->hal_rx_msdu0_buffer_addr_lsb = 1349 hal_rx_msdu0_buffer_addr_lsb_8074v1; 1350 hal_soc->ops->hal_rx_msdu_desc_info_ptr_get = 1351 hal_rx_msdu_desc_info_ptr_get_8074v1; 1352 hal_soc->ops->hal_ent_mpdu_desc_info = hal_ent_mpdu_desc_info_8074v1; 1353 hal_soc->ops->hal_dst_mpdu_desc_info = hal_dst_mpdu_desc_info_8074v1; 1354 hal_soc->ops->hal_rx_get_fc_valid = hal_rx_get_fc_valid_8074v1; 1355 hal_soc->ops->hal_rx_get_to_ds_flag = hal_rx_get_to_ds_flag_8074v1; 1356 hal_soc->ops->hal_rx_get_mac_addr2_valid = 1357 hal_rx_get_mac_addr2_valid_8074v1; 1358 hal_soc->ops->hal_rx_get_filter_category = 1359 hal_rx_get_filter_category_8074v1; 1360 hal_soc->ops->hal_rx_get_ppdu_id = hal_rx_get_ppdu_id_8074v1; 1361 hal_soc->ops->hal_reo_config = hal_reo_config_8074v1; 1362 hal_soc->ops->hal_rx_msdu_flow_idx_get = 1363 hal_rx_msdu_flow_idx_get_8074v1; 1364 hal_soc->ops->hal_rx_msdu_flow_idx_invalid = 1365 hal_rx_msdu_flow_idx_invalid_8074v1; 1366 hal_soc->ops->hal_rx_msdu_flow_idx_timeout = 1367 hal_rx_msdu_flow_idx_timeout_8074v1; 1368 hal_soc->ops->hal_rx_msdu_fse_metadata_get = 1369 hal_rx_msdu_fse_metadata_get_8074v1; 1370 hal_soc->ops->hal_rx_msdu_cce_match_get = 1371 hal_rx_msdu_cce_match_get_li; 1372 hal_soc->ops->hal_rx_msdu_cce_metadata_get = 1373 hal_rx_msdu_cce_metadata_get_8074v1; 1374 hal_soc->ops->hal_rx_msdu_get_flow_params = 1375 hal_rx_msdu_get_flow_params_8074v1; 1376 hal_soc->ops->hal_rx_tlv_get_tcp_chksum = 1377 hal_rx_tlv_get_tcp_chksum_8074v1; 1378 hal_soc->ops->hal_rx_get_rx_sequence = hal_rx_get_rx_sequence_8074v1; 1379 /* rx - msdu fast path info fields */ 1380 hal_soc->ops->hal_rx_msdu_packet_metadata_get = 1381 hal_rx_msdu_packet_metadata_get_generic_li; 1382 hal_soc->ops->hal_rx_mpdu_start_tlv_tag_valid = 1383 hal_rx_mpdu_start_tlv_tag_valid_8074v1; 1384 1385 /* rx - TLV struct offsets */ 1386 hal_soc->ops->hal_rx_msdu_end_offset_get = 1387 hal_rx_msdu_end_offset_get_generic; 1388 hal_soc->ops->hal_rx_attn_offset_get = hal_rx_attn_offset_get_generic; 1389 hal_soc->ops->hal_rx_msdu_start_offset_get = 1390 hal_rx_msdu_start_offset_get_generic; 1391 hal_soc->ops->hal_rx_mpdu_start_offset_get = 1392 hal_rx_mpdu_start_offset_get_generic; 1393 hal_soc->ops->hal_rx_mpdu_end_offset_get = 1394 hal_rx_mpdu_end_offset_get_generic; 1395 #ifndef NO_RX_PKT_HDR_TLV 1396 hal_soc->ops->hal_rx_pkt_tlv_offset_get = 1397 hal_rx_pkt_tlv_offset_get_generic; 1398 #endif 1399 hal_soc->ops->hal_rx_flow_setup_fse = hal_rx_flow_setup_fse_8074v1; 1400 hal_soc->ops->hal_rx_flow_get_tuple_info = 1401 hal_rx_flow_get_tuple_info_li; 1402 hal_soc->ops->hal_rx_flow_delete_entry = 1403 hal_rx_flow_delete_entry_li; 1404 hal_soc->ops->hal_rx_fst_get_fse_size = hal_rx_fst_get_fse_size_li; 1405 hal_soc->ops->hal_compute_reo_remap_ix2_ix3 = 1406 hal_compute_reo_remap_ix2_ix3_8074v1; 1407 hal_soc->ops->hal_setup_link_idle_list = 1408 hal_setup_link_idle_list_generic_li; 1409 hal_soc->ops->hal_compute_reo_remap_ix0 = NULL; 1410 }; 1411 1412 struct hal_hw_srng_config hw_srng_table_8074[] = { 1413 /* TODO: max_rings can populated by querying HW capabilities */ 1414 { /* REO_DST */ 1415 .start_ring_id = HAL_SRNG_REO2SW1, 1416 .max_rings = 4, 1417 .entry_size = sizeof(struct reo_destination_ring) >> 2, 1418 .lmac_ring = FALSE, 1419 .ring_dir = HAL_SRNG_DST_RING, 1420 .reg_start = { 1421 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR( 1422 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1423 HWIO_REO_R2_REO2SW1_RING_HP_ADDR( 1424 SEQ_WCSS_UMAC_REO_REG_OFFSET) 1425 }, 1426 .reg_size = { 1427 HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(0) - 1428 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(0), 1429 HWIO_REO_R2_REO2SW2_RING_HP_ADDR(0) - 1430 HWIO_REO_R2_REO2SW1_RING_HP_ADDR(0), 1431 }, 1432 .max_size = 1433 HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_BMSK >> 1434 HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_SHFT, 1435 }, 1436 { /* REO_EXCEPTION */ 1437 /* Designating REO2TCL ring as exception ring. This ring is 1438 * similar to other REO2SW rings though it is named as REO2TCL. 1439 * Any of theREO2SW rings can be used as exception ring. 1440 */ 1441 .start_ring_id = HAL_SRNG_REO2TCL, 1442 .max_rings = 1, 1443 .entry_size = sizeof(struct reo_destination_ring) >> 2, 1444 .lmac_ring = FALSE, 1445 .ring_dir = HAL_SRNG_DST_RING, 1446 .reg_start = { 1447 HWIO_REO_R0_REO2TCL_RING_BASE_LSB_ADDR( 1448 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1449 HWIO_REO_R2_REO2TCL_RING_HP_ADDR( 1450 SEQ_WCSS_UMAC_REO_REG_OFFSET) 1451 }, 1452 /* Single ring - provide ring size if multiple rings of this 1453 * type are supported 1454 */ 1455 .reg_size = {}, 1456 .max_size = 1457 HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_BMSK >> 1458 HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_SHFT, 1459 }, 1460 { /* REO_REINJECT */ 1461 .start_ring_id = HAL_SRNG_SW2REO, 1462 .max_rings = 1, 1463 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 1464 .lmac_ring = FALSE, 1465 .ring_dir = HAL_SRNG_SRC_RING, 1466 .reg_start = { 1467 HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR( 1468 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1469 HWIO_REO_R2_SW2REO_RING_HP_ADDR( 1470 SEQ_WCSS_UMAC_REO_REG_OFFSET) 1471 }, 1472 /* Single ring - provide ring size if multiple rings of this 1473 * type are supported 1474 */ 1475 .reg_size = {}, 1476 .max_size = HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_BMSK >> 1477 HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_SHFT, 1478 }, 1479 { /* REO_CMD */ 1480 .start_ring_id = HAL_SRNG_REO_CMD, 1481 .max_rings = 1, 1482 .entry_size = (sizeof(struct tlv_32_hdr) + 1483 sizeof(struct reo_get_queue_stats)) >> 2, 1484 .lmac_ring = FALSE, 1485 .ring_dir = HAL_SRNG_SRC_RING, 1486 .reg_start = { 1487 HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR( 1488 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1489 HWIO_REO_R2_REO_CMD_RING_HP_ADDR( 1490 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1491 }, 1492 /* Single ring - provide ring size if multiple rings of this 1493 * type are supported 1494 */ 1495 .reg_size = {}, 1496 .max_size = HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_BMSK >> 1497 HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_SHFT, 1498 }, 1499 { /* REO_STATUS */ 1500 .start_ring_id = HAL_SRNG_REO_STATUS, 1501 .max_rings = 1, 1502 .entry_size = (sizeof(struct tlv_32_hdr) + 1503 sizeof(struct reo_get_queue_stats_status)) >> 2, 1504 .lmac_ring = FALSE, 1505 .ring_dir = HAL_SRNG_DST_RING, 1506 .reg_start = { 1507 HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR( 1508 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1509 HWIO_REO_R2_REO_STATUS_RING_HP_ADDR( 1510 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1511 }, 1512 /* Single ring - provide ring size if multiple rings of this 1513 * type are supported 1514 */ 1515 .reg_size = {}, 1516 .max_size = 1517 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> 1518 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, 1519 }, 1520 { /* TCL_DATA */ 1521 .start_ring_id = HAL_SRNG_SW2TCL1, 1522 .max_rings = 3, 1523 .entry_size = (sizeof(struct tlv_32_hdr) + 1524 sizeof(struct tcl_data_cmd)) >> 2, 1525 .lmac_ring = FALSE, 1526 .ring_dir = HAL_SRNG_SRC_RING, 1527 .reg_start = { 1528 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR( 1529 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1530 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR( 1531 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1532 }, 1533 .reg_size = { 1534 HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(0) - 1535 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(0), 1536 HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(0) - 1537 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(0), 1538 }, 1539 .max_size = 1540 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK >> 1541 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT, 1542 }, 1543 { /* TCL_CMD */ 1544 .start_ring_id = HAL_SRNG_SW2TCL_CMD, 1545 .max_rings = 1, 1546 .entry_size = (sizeof(struct tlv_32_hdr) + 1547 sizeof(struct tcl_data_cmd)) >> 2, 1548 .lmac_ring = FALSE, 1549 .ring_dir = HAL_SRNG_SRC_RING, 1550 .reg_start = { 1551 HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_ADDR( 1552 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1553 HWIO_TCL_R2_SW2TCL_CMD_RING_HP_ADDR( 1554 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1555 }, 1556 /* Single ring - provide ring size if multiple rings of this 1557 * type are supported 1558 */ 1559 .reg_size = {}, 1560 .max_size = 1561 HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RING_SIZE_BMSK >> 1562 HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RING_SIZE_SHFT, 1563 }, 1564 { /* TCL_STATUS */ 1565 .start_ring_id = HAL_SRNG_TCL_STATUS, 1566 .max_rings = 1, 1567 .entry_size = (sizeof(struct tlv_32_hdr) + 1568 sizeof(struct tcl_status_ring)) >> 2, 1569 .lmac_ring = FALSE, 1570 .ring_dir = HAL_SRNG_DST_RING, 1571 .reg_start = { 1572 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR( 1573 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1574 HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR( 1575 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1576 }, 1577 /* Single ring - provide ring size if multiple rings of this 1578 * type are supported 1579 */ 1580 .reg_size = {}, 1581 .max_size = 1582 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_BMSK >> 1583 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_SHFT, 1584 }, 1585 { /* CE_SRC */ 1586 .start_ring_id = HAL_SRNG_CE_0_SRC, 1587 .max_rings = 12, 1588 .entry_size = sizeof(struct ce_src_desc) >> 2, 1589 .lmac_ring = FALSE, 1590 .ring_dir = HAL_SRNG_SRC_RING, 1591 .reg_start = { 1592 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR( 1593 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET), 1594 HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR( 1595 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET), 1596 }, 1597 .reg_size = { 1598 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET - 1599 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET, 1600 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET - 1601 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET, 1602 }, 1603 .max_size = 1604 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >> 1605 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT, 1606 }, 1607 { /* CE_DST */ 1608 .start_ring_id = HAL_SRNG_CE_0_DST, 1609 .max_rings = 12, 1610 .entry_size = 8 >> 2, 1611 /*TODO: entry_size above should actually be 1612 * sizeof(struct ce_dst_desc) >> 2, but couldn't find definition 1613 * of struct ce_dst_desc in HW header files 1614 */ 1615 .lmac_ring = FALSE, 1616 .ring_dir = HAL_SRNG_SRC_RING, 1617 .reg_start = { 1618 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR( 1619 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 1620 HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR( 1621 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 1622 }, 1623 .reg_size = { 1624 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 1625 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 1626 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 1627 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 1628 }, 1629 .max_size = 1630 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >> 1631 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT, 1632 }, 1633 { /* CE_DST_STATUS */ 1634 .start_ring_id = HAL_SRNG_CE_0_DST_STATUS, 1635 .max_rings = 12, 1636 .entry_size = sizeof(struct ce_stat_desc) >> 2, 1637 .lmac_ring = FALSE, 1638 .ring_dir = HAL_SRNG_DST_RING, 1639 .reg_start = { 1640 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR( 1641 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 1642 HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR( 1643 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 1644 }, 1645 /* TODO: check destination status ring registers */ 1646 .reg_size = { 1647 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 1648 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 1649 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 1650 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 1651 }, 1652 .max_size = 1653 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> 1654 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, 1655 }, 1656 { /* WBM_IDLE_LINK */ 1657 .start_ring_id = HAL_SRNG_WBM_IDLE_LINK, 1658 .max_rings = 1, 1659 .entry_size = sizeof(struct wbm_link_descriptor_ring) >> 2, 1660 .lmac_ring = FALSE, 1661 .ring_dir = HAL_SRNG_SRC_RING, 1662 .reg_start = { 1663 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1664 HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1665 }, 1666 /* Single ring - provide ring size if multiple rings of this 1667 * type are supported 1668 */ 1669 .reg_size = {}, 1670 .max_size = 1671 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_BMSK >> 1672 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_SHFT, 1673 }, 1674 { /* SW2WBM_RELEASE */ 1675 .start_ring_id = HAL_SRNG_WBM_SW_RELEASE, 1676 .max_rings = 1, 1677 .entry_size = sizeof(struct wbm_release_ring) >> 2, 1678 .lmac_ring = FALSE, 1679 .ring_dir = HAL_SRNG_SRC_RING, 1680 .reg_start = { 1681 HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1682 HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1683 }, 1684 /* Single ring - provide ring size if multiple rings of this 1685 * type are supported 1686 */ 1687 .reg_size = {}, 1688 .max_size = 1689 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> 1690 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, 1691 }, 1692 { /* WBM2SW_RELEASE */ 1693 .start_ring_id = HAL_SRNG_WBM2SW0_RELEASE, 1694 .max_rings = 4, 1695 .entry_size = sizeof(struct wbm_release_ring) >> 2, 1696 .lmac_ring = FALSE, 1697 .ring_dir = HAL_SRNG_DST_RING, 1698 .reg_start = { 1699 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1700 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1701 }, 1702 .reg_size = { 1703 HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) - 1704 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1705 HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) - 1706 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1707 }, 1708 .max_size = 1709 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> 1710 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, 1711 }, 1712 { /* RXDMA_BUF */ 1713 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA0_BUF0, 1714 #ifdef IPA_OFFLOAD 1715 .max_rings = 3, 1716 #else 1717 .max_rings = 2, 1718 #endif 1719 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 1720 .lmac_ring = TRUE, 1721 .ring_dir = HAL_SRNG_SRC_RING, 1722 /* reg_start is not set because LMAC rings are not accessed 1723 * from host 1724 */ 1725 .reg_start = {}, 1726 .reg_size = {}, 1727 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1728 }, 1729 { /* RXDMA_DST */ 1730 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW0, 1731 .max_rings = 1, 1732 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 1733 .lmac_ring = TRUE, 1734 .ring_dir = HAL_SRNG_DST_RING, 1735 /* reg_start is not set because LMAC rings are not accessed 1736 * from host 1737 */ 1738 .reg_start = {}, 1739 .reg_size = {}, 1740 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1741 }, 1742 { /* RXDMA_MONITOR_BUF */ 1743 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA2_BUF, 1744 .max_rings = 1, 1745 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 1746 .lmac_ring = TRUE, 1747 .ring_dir = HAL_SRNG_SRC_RING, 1748 /* reg_start is not set because LMAC rings are not accessed 1749 * from host 1750 */ 1751 .reg_start = {}, 1752 .reg_size = {}, 1753 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1754 }, 1755 { /* RXDMA_MONITOR_STATUS */ 1756 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_STATBUF, 1757 .max_rings = 1, 1758 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 1759 .lmac_ring = TRUE, 1760 .ring_dir = HAL_SRNG_SRC_RING, 1761 /* reg_start is not set because LMAC rings are not accessed 1762 * from host 1763 */ 1764 .reg_start = {}, 1765 .reg_size = {}, 1766 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1767 }, 1768 { /* RXDMA_MONITOR_DST */ 1769 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW1, 1770 .max_rings = 1, 1771 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 1772 .lmac_ring = TRUE, 1773 .ring_dir = HAL_SRNG_DST_RING, 1774 /* reg_start is not set because LMAC rings are not accessed 1775 * from host 1776 */ 1777 .reg_start = {}, 1778 .reg_size = {}, 1779 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1780 }, 1781 { /* RXDMA_MONITOR_DESC */ 1782 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_DESC, 1783 .max_rings = 1, 1784 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 1785 .lmac_ring = TRUE, 1786 .ring_dir = HAL_SRNG_SRC_RING, 1787 /* reg_start is not set because LMAC rings are not accessed 1788 * from host 1789 */ 1790 .reg_start = {}, 1791 .reg_size = {}, 1792 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1793 }, 1794 { /* DIR_BUF_RX_DMA_SRC */ 1795 .start_ring_id = HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING, 1796 .max_rings = 1, 1797 .entry_size = 2, 1798 .lmac_ring = TRUE, 1799 .ring_dir = HAL_SRNG_SRC_RING, 1800 /* reg_start is not set because LMAC rings are not accessed 1801 * from host 1802 */ 1803 .reg_start = {}, 1804 .reg_size = {}, 1805 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1806 }, 1807 #ifdef WLAN_FEATURE_CIF_CFR 1808 { /* WIFI_POS_SRC */ 1809 .start_ring_id = HAL_SRNG_WIFI_POS_SRC_DMA_RING, 1810 .max_rings = 1, 1811 .entry_size = sizeof(wmi_oem_dma_buf_release_entry) >> 2, 1812 .lmac_ring = TRUE, 1813 .ring_dir = HAL_SRNG_SRC_RING, 1814 /* reg_start is not set because LMAC rings are not accessed 1815 * from host 1816 */ 1817 .reg_start = {}, 1818 .reg_size = {}, 1819 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1820 }, 1821 #endif 1822 { /* REO2PPE */ 0}, 1823 { /* PPE2TCL */ 0}, 1824 { /* PPE_RELEASE */ 0}, 1825 { /* TX_MONITOR_BUF */ 0}, 1826 { /* TX_MONITOR_DST */ 0}, 1827 { /* SW2RXDMA_NEW */ 0}, 1828 }; 1829 1830 /** 1831 * hal_qca8074_attach() - Attach 8074 target specific hal_soc ops, 1832 * offset and srng table 1833 */ 1834 void hal_qca8074_attach(struct hal_soc *hal_soc) 1835 { 1836 hal_soc->hw_srng_table = hw_srng_table_8074; 1837 hal_srng_hw_reg_offset_init_generic(hal_soc); 1838 hal_hw_txrx_default_ops_attach_li(hal_soc); 1839 hal_hw_txrx_ops_attach_qca8074(hal_soc); 1840 } 1841