1 /* 2 * Copyright (c) 2016-2019 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 #include "hal_hw_headers.h" 19 #include "hal_internal.h" 20 #include "hal_api.h" 21 #include "target_type.h" 22 #include "wcss_version.h" 23 #include "qdf_module.h" 24 25 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_OFFSET \ 26 RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_OFFSET 27 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_MASK \ 28 RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_MASK 29 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_LSB \ 30 RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_LSB 31 #define UNIFIED_PHYRX_HT_SIG_0_HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS_OFFSET \ 32 PHYRX_HT_SIG_0_HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS_OFFSET 33 #define UNIFIED_PHYRX_L_SIG_B_0_L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS_OFFSET \ 34 PHYRX_L_SIG_B_0_L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS_OFFSET 35 #define UNIFIED_PHYRX_L_SIG_A_0_L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS_OFFSET \ 36 PHYRX_L_SIG_A_0_L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS_OFFSET 37 #define UNIFIED_PHYRX_VHT_SIG_A_0_VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS_OFFSET \ 38 PHYRX_VHT_SIG_A_0_VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS_OFFSET 39 #define UNIFIED_PHYRX_HE_SIG_A_SU_0_HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS_OFFSET \ 40 PHYRX_HE_SIG_A_SU_0_HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS_OFFSET 41 #define UNIFIED_PHYRX_HE_SIG_A_MU_DL_0_HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_OFFSET \ 42 PHYRX_HE_SIG_A_MU_DL_0_HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_OFFSET 43 #define UNIFIED_PHYRX_HE_SIG_B1_MU_0_HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_OFFSET \ 44 PHYRX_HE_SIG_B1_MU_0_HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_OFFSET 45 #define UNIFIED_PHYRX_HE_SIG_B2_MU_0_HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_OFFSET \ 46 PHYRX_HE_SIG_B2_MU_0_HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_OFFSET 47 #define UNIFIED_PHYRX_HE_SIG_B2_OFDMA_0_HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_OFFSET \ 48 PHYRX_HE_SIG_B2_OFDMA_0_HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_OFFSET 49 #define UNIFIED_PHYRX_RSSI_LEGACY_3_RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS_OFFSET \ 50 PHYRX_RSSI_LEGACY_3_RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS_OFFSET 51 #define UNIFIED_PHYRX_RSSI_LEGACY_19_RECEIVE_RSSI_INFO_PREAMBLE_RSSI_INFO_DETAILS_OFFSET \ 52 PHYRX_RSSI_LEGACY_19_RECEIVE_RSSI_INFO_PREAMBLE_RSSI_INFO_DETAILS_OFFSET 53 #define UNIFIED_RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET \ 54 RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET 55 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 56 RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET 57 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ 58 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET 59 #define UNIFIED_RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 60 RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET 61 #define UNIFIED_REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 62 REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET 63 #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC \ 64 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER 65 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSE \ 66 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET 67 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 68 RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET 69 #define UNIFIED_TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 70 TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET 71 #define UNIFIED_TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 72 TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET 73 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET \ 74 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET 75 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB \ 76 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB 77 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK \ 78 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK 79 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB \ 80 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB 81 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK \ 82 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK 83 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB \ 84 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB 85 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK \ 86 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK 87 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB \ 88 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB 89 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK \ 90 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK 91 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB \ 92 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB 93 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK \ 94 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK 95 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_MASK \ 96 WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_MASK 97 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_OFFSET \ 98 WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_OFFSET 99 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_LSB \ 100 WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_LSB 101 102 #include "hal_8074v1_tx.h" 103 #include "hal_8074v1_rx.h" 104 #include <hal_generic_api.h> 105 #include <hal_wbm.h> 106 107 108 /** 109 * hal_rx_get_rx_fragment_number_8074v1(): Function to retrieve 110 * rx fragment number 111 * 112 * @nbuf: Network buffer 113 * Returns: rx fragment number 114 */ 115 static 116 uint8_t hal_rx_get_rx_fragment_number_8074v1(uint8_t *buf) 117 { 118 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 119 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 120 121 /* Return first 4 bits as fragment number */ 122 return (HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info) & 123 DOT11_SEQ_FRAG_MASK); 124 } 125 126 /** 127 * hal_rx_msdu_end_da_is_mcbc_get_8074v1(): API to check if 128 * pkt is MCBC from rx_msdu_end TLV 129 * 130 * @ buf: pointer to the start of RX PKT TLV headers 131 * Return: da_is_mcbc 132 */ 133 static uint8_t 134 hal_rx_msdu_end_da_is_mcbc_get_8074v1(uint8_t *buf) 135 { 136 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 137 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 138 139 return HAL_RX_MSDU_END_DA_IS_MCBC_GET(msdu_end); 140 } 141 142 /** 143 * hal_rx_msdu_end_sa_is_valid_get_8074v1(): API to get_8074v1 the 144 * sa_is_valid bit from rx_msdu_end TLV 145 * 146 * @ buf: pointer to the start of RX PKT TLV headers 147 * Return: sa_is_valid bit 148 */ 149 static uint8_t 150 hal_rx_msdu_end_sa_is_valid_get_8074v1(uint8_t *buf) 151 { 152 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 153 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 154 uint8_t sa_is_valid; 155 156 sa_is_valid = HAL_RX_MSDU_END_SA_IS_VALID_GET(msdu_end); 157 158 return sa_is_valid; 159 } 160 161 /** 162 * hal_rx_msdu_end_sa_idx_get_8074v1(): API to get_8074v1 the 163 * sa_idx from rx_msdu_end TLV 164 * 165 * @ buf: pointer to the start of RX PKT TLV headers 166 * Return: sa_idx (SA AST index) 167 */ 168 static uint16_t hal_rx_msdu_end_sa_idx_get_8074v1(uint8_t *buf) 169 { 170 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 171 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 172 uint16_t sa_idx; 173 174 sa_idx = HAL_RX_MSDU_END_SA_IDX_GET(msdu_end); 175 176 return sa_idx; 177 } 178 179 /** 180 * hal_rx_desc_is_first_msdu_8074v1() - Check if first msdu 181 * 182 * @hal_soc_hdl: hal_soc handle 183 * @hw_desc_addr: hardware descriptor address 184 * 185 * Return: 0 - success/ non-zero failure 186 */ 187 static uint32_t hal_rx_desc_is_first_msdu_8074v1(void *hw_desc_addr) 188 { 189 struct rx_pkt_tlvs *rx_tlvs = (struct rx_pkt_tlvs *)hw_desc_addr; 190 struct rx_msdu_end *msdu_end = &rx_tlvs->msdu_end_tlv.rx_msdu_end; 191 192 return HAL_RX_GET(msdu_end, RX_MSDU_END_5, FIRST_MSDU); 193 } 194 195 /** 196 * hal_rx_msdu_end_l3_hdr_padding_get_8074v1(): API to get_8074v1 the 197 * l3_header padding from rx_msdu_end TLV 198 * 199 * @ buf: pointer to the start of RX PKT TLV headers 200 * Return: number of l3 header padding bytes 201 */ 202 static uint32_t hal_rx_msdu_end_l3_hdr_padding_get_8074v1(uint8_t *buf) 203 { 204 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 205 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 206 uint32_t l3_header_padding; 207 208 l3_header_padding = HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(msdu_end); 209 210 return l3_header_padding; 211 } 212 213 /* 214 * @ hal_rx_encryption_info_valid_8074v1: Returns encryption type. 215 * 216 * @ buf: rx_tlv_hdr of the received packet 217 * @ Return: encryption type 218 */ 219 static uint32_t hal_rx_encryption_info_valid_8074v1(uint8_t *buf) 220 { 221 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 222 struct rx_mpdu_start *mpdu_start = 223 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 224 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 225 uint32_t encryption_info = HAL_RX_MPDU_ENCRYPTION_INFO_VALID(mpdu_info); 226 227 return encryption_info; 228 } 229 230 /* 231 * @ hal_rx_print_pn_8074v1: Prints the PN of rx packet. 232 * 233 * @ buf: rx_tlv_hdr of the received packet 234 * @ Return: void 235 */ 236 static void hal_rx_print_pn_8074v1(uint8_t *buf) 237 { 238 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 239 struct rx_mpdu_start *mpdu_start = 240 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 241 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 242 243 uint32_t pn_31_0 = HAL_RX_MPDU_PN_31_0_GET(mpdu_info); 244 uint32_t pn_63_32 = HAL_RX_MPDU_PN_63_32_GET(mpdu_info); 245 uint32_t pn_95_64 = HAL_RX_MPDU_PN_95_64_GET(mpdu_info); 246 uint32_t pn_127_96 = HAL_RX_MPDU_PN_127_96_GET(mpdu_info); 247 248 hal_debug("PN number pn_127_96 0x%x pn_95_64 0x%x pn_63_32 0x%x pn_31_0 0x%x ", 249 pn_127_96, pn_95_64, pn_63_32, pn_31_0); 250 } 251 252 /** 253 * hal_rx_msdu_end_first_msdu_get_8074v1: API to get first msdu status 254 * from rx_msdu_end TLV 255 * 256 * @ buf: pointer to the start of RX PKT TLV headers 257 * Return: first_msdu 258 */ 259 static uint8_t 260 hal_rx_msdu_end_first_msdu_get_8074v1(uint8_t *buf) 261 { 262 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 263 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 264 uint8_t first_msdu; 265 266 first_msdu = HAL_RX_MSDU_END_FIRST_MSDU_GET(msdu_end); 267 268 return first_msdu; 269 } 270 271 /** 272 * hal_rx_msdu_end_da_is_valid_get_8074v1: API to check if da is valid 273 * from rx_msdu_end TLV 274 * 275 * @ buf: pointer to the start of RX PKT TLV headers 276 * Return: da_is_valid 277 */ 278 static uint8_t hal_rx_msdu_end_da_is_valid_get_8074v1(uint8_t *buf) 279 { 280 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 281 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 282 uint8_t da_is_valid; 283 284 da_is_valid = HAL_RX_MSDU_END_DA_IS_VALID_GET(msdu_end); 285 286 return da_is_valid; 287 } 288 289 /** 290 * hal_rx_msdu_end_last_msdu_get_8074v1: API to get last msdu status 291 * from rx_msdu_end TLV 292 * 293 * @ buf: pointer to the start of RX PKT TLV headers 294 * Return: last_msdu 295 */ 296 static uint8_t hal_rx_msdu_end_last_msdu_get_8074v1(uint8_t *buf) 297 { 298 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 299 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 300 uint8_t last_msdu; 301 302 last_msdu = HAL_RX_MSDU_END_LAST_MSDU_GET(msdu_end); 303 304 return last_msdu; 305 } 306 307 /* 308 * hal_rx_get_mpdu_mac_ad4_valid_8074v1(): Retrieves if mpdu 4th addr is valid 309 * 310 * @nbuf: Network buffer 311 * Returns: value of mpdu 4th address valid field 312 */ 313 static bool hal_rx_get_mpdu_mac_ad4_valid_8074v1(uint8_t *buf) 314 { 315 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 316 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 317 bool ad4_valid = 0; 318 319 ad4_valid = HAL_RX_MPDU_GET_MAC_AD4_VALID(rx_mpdu_info); 320 321 return ad4_valid; 322 } 323 324 /** 325 * hal_rx_mpdu_start_sw_peer_id_get_8074v1: Retrieve sw peer_id 326 * @buf: network buffer 327 * 328 * Return: sw peer_id 329 */ 330 static uint32_t hal_rx_mpdu_start_sw_peer_id_get_8074v1(uint8_t *buf) 331 { 332 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 333 struct rx_mpdu_start *mpdu_start = 334 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 335 336 return HAL_RX_MPDU_INFO_SW_PEER_ID_GET( 337 &mpdu_start->rx_mpdu_info_details); 338 } 339 340 /* 341 * hal_rx_mpdu_get_to_ds_8074v1(): API to get the tods info 342 * from rx_mpdu_start 343 * 344 * @buf: pointer to the start of RX PKT TLV header 345 * Return: uint32_t(to_ds) 346 */ 347 348 static uint32_t hal_rx_mpdu_get_to_ds_8074v1(uint8_t *buf) 349 { 350 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 351 struct rx_mpdu_start *mpdu_start = 352 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 353 354 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 355 356 return HAL_RX_MPDU_GET_TODS(mpdu_info); 357 } 358 359 /* 360 * hal_rx_mpdu_get_fr_ds_8074v1(): API to get the from ds info 361 * from rx_mpdu_start 362 * 363 * @buf: pointer to the start of RX PKT TLV header 364 * Return: uint32_t(fr_ds) 365 */ 366 static uint32_t hal_rx_mpdu_get_fr_ds_8074v1(uint8_t *buf) 367 { 368 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 369 struct rx_mpdu_start *mpdu_start = 370 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 371 372 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 373 374 return HAL_RX_MPDU_GET_FROMDS(mpdu_info); 375 } 376 377 /* 378 * hal_rx_get_mpdu_frame_control_valid_8074v1(): Retrieves mpdu 379 * frame control valid 380 * 381 * @nbuf: Network buffer 382 * Returns: value of frame control valid field 383 */ 384 static uint8_t hal_rx_get_mpdu_frame_control_valid_8074v1(uint8_t *buf) 385 { 386 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 387 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 388 389 return HAL_RX_MPDU_GET_FRAME_CONTROL_VALID(rx_mpdu_info); 390 } 391 392 /* 393 * hal_rx_mpdu_get_addr1_8074v1(): API to check get address1 of the mpdu 394 * 395 * @buf: pointer to the start of RX PKT TLV headera 396 * @mac_addr: pointer to mac address 397 * Return: success/failure 398 */ 399 static QDF_STATUS hal_rx_mpdu_get_addr1_8074v1(uint8_t *buf, 400 uint8_t *mac_addr) 401 { 402 struct __attribute__((__packed__)) hal_addr1 { 403 uint32_t ad1_31_0; 404 uint16_t ad1_47_32; 405 }; 406 407 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 408 struct rx_mpdu_start *mpdu_start = 409 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 410 411 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 412 struct hal_addr1 *addr = (struct hal_addr1 *)mac_addr; 413 uint32_t mac_addr_ad1_valid; 414 415 mac_addr_ad1_valid = HAL_RX_MPDU_MAC_ADDR_AD1_VALID_GET(mpdu_info); 416 417 if (mac_addr_ad1_valid) { 418 addr->ad1_31_0 = HAL_RX_MPDU_AD1_31_0_GET(mpdu_info); 419 addr->ad1_47_32 = HAL_RX_MPDU_AD1_47_32_GET(mpdu_info); 420 return QDF_STATUS_SUCCESS; 421 } 422 423 return QDF_STATUS_E_FAILURE; 424 } 425 426 /* 427 * hal_rx_mpdu_get_addr2_8074v1(): API to check get address2 of the mpdu 428 * in the packet 429 * 430 * @buf: pointer to the start of RX PKT TLV header 431 * @mac_addr: pointer to mac address 432 * Return: success/failure 433 */ 434 static QDF_STATUS hal_rx_mpdu_get_addr2_8074v1(uint8_t *buf, uint8_t *mac_addr) 435 { 436 struct __attribute__((__packed__)) hal_addr2 { 437 uint16_t ad2_15_0; 438 uint32_t ad2_47_16; 439 }; 440 441 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 442 struct rx_mpdu_start *mpdu_start = 443 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 444 445 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 446 struct hal_addr2 *addr = (struct hal_addr2 *)mac_addr; 447 uint32_t mac_addr_ad2_valid; 448 449 mac_addr_ad2_valid = HAL_RX_MPDU_MAC_ADDR_AD2_VALID_GET(mpdu_info); 450 451 if (mac_addr_ad2_valid) { 452 addr->ad2_15_0 = HAL_RX_MPDU_AD2_15_0_GET(mpdu_info); 453 addr->ad2_47_16 = HAL_RX_MPDU_AD2_47_16_GET(mpdu_info); 454 return QDF_STATUS_SUCCESS; 455 } 456 457 return QDF_STATUS_E_FAILURE; 458 } 459 460 /* 461 * hal_rx_mpdu_get_addr3_8074v1(): API to get address3 of the mpdu 462 * in the packet 463 * 464 * @buf: pointer to the start of RX PKT TLV header 465 * @mac_addr: pointer to mac address 466 * Return: success/failure 467 */ 468 static QDF_STATUS hal_rx_mpdu_get_addr3_8074v1(uint8_t *buf, uint8_t *mac_addr) 469 { 470 struct __attribute__((__packed__)) hal_addr3 { 471 uint32_t ad3_31_0; 472 uint16_t ad3_47_32; 473 }; 474 475 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 476 struct rx_mpdu_start *mpdu_start = 477 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 478 479 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 480 struct hal_addr3 *addr = (struct hal_addr3 *)mac_addr; 481 uint32_t mac_addr_ad3_valid; 482 483 mac_addr_ad3_valid = HAL_RX_MPDU_MAC_ADDR_AD3_VALID_GET(mpdu_info); 484 485 if (mac_addr_ad3_valid) { 486 addr->ad3_31_0 = HAL_RX_MPDU_AD3_31_0_GET(mpdu_info); 487 addr->ad3_47_32 = HAL_RX_MPDU_AD3_47_32_GET(mpdu_info); 488 return QDF_STATUS_SUCCESS; 489 } 490 491 return QDF_STATUS_E_FAILURE; 492 } 493 494 /* 495 * hal_rx_mpdu_get_addr4_8074v1(): API to get address4 of the mpdu 496 * in the packet 497 * 498 * @buf: pointer to the start of RX PKT TLV header 499 * @mac_addr: pointer to mac address 500 * Return: success/failure 501 */ 502 static QDF_STATUS hal_rx_mpdu_get_addr4_8074v1(uint8_t *buf, uint8_t *mac_addr) 503 { 504 struct __attribute__((__packed__)) hal_addr4 { 505 uint32_t ad4_31_0; 506 uint16_t ad4_47_32; 507 }; 508 509 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 510 struct rx_mpdu_start *mpdu_start = 511 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 512 513 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 514 struct hal_addr4 *addr = (struct hal_addr4 *)mac_addr; 515 uint32_t mac_addr_ad4_valid; 516 517 mac_addr_ad4_valid = HAL_RX_MPDU_MAC_ADDR_AD4_VALID_GET(mpdu_info); 518 519 if (mac_addr_ad4_valid) { 520 addr->ad4_31_0 = HAL_RX_MPDU_AD4_31_0_GET(mpdu_info); 521 addr->ad4_47_32 = HAL_RX_MPDU_AD4_47_32_GET(mpdu_info); 522 return QDF_STATUS_SUCCESS; 523 } 524 525 return QDF_STATUS_E_FAILURE; 526 } 527 528 /* 529 * hal_rx_get_mpdu_sequence_control_valid_8074v1(): Get mpdu 530 * sequence control valid 531 * 532 * @nbuf: Network buffer 533 * Returns: value of sequence control valid field 534 */ 535 static uint8_t hal_rx_get_mpdu_sequence_control_valid_8074v1(uint8_t *buf) 536 { 537 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 538 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 539 540 return HAL_RX_MPDU_GET_SEQUENCE_CONTROL_VALID(rx_mpdu_info); 541 } 542 543 /** 544 * hal_rx_is_unicast_8074v1: check packet is unicast frame or not. 545 * 546 * @ buf: pointer to rx pkt TLV. 547 * 548 * Return: true on unicast. 549 */ 550 static bool hal_rx_is_unicast_8074v1(uint8_t *buf) 551 { 552 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 553 struct rx_mpdu_start *mpdu_start = 554 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 555 uint32_t grp_id; 556 uint8_t *rx_mpdu_info = (uint8_t *)&mpdu_start->rx_mpdu_info_details; 557 558 grp_id = (_HAL_MS((*_OFFSET_TO_WORD_PTR((rx_mpdu_info), 559 RX_MPDU_INFO_0_SW_FRAME_GROUP_ID_OFFSET)), 560 RX_MPDU_INFO_0_SW_FRAME_GROUP_ID_MASK, 561 RX_MPDU_INFO_0_SW_FRAME_GROUP_ID_LSB)); 562 563 return (HAL_MPDU_SW_FRAME_GROUP_UNICAST_DATA == grp_id) ? true : false; 564 } 565 566 /** 567 * hal_rx_tid_get_8074v1: get tid based on qos control valid. 568 * 569 * @ buf: pointer to rx pkt TLV. 570 * 571 * Return: tid 572 */ 573 static uint32_t hal_rx_tid_get_8074v1(hal_soc_handle_t hal_soc_hdl, 574 uint8_t *buf) 575 { 576 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 577 struct rx_mpdu_start *mpdu_start = 578 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 579 uint8_t *rx_mpdu_info = (uint8_t *)&mpdu_start->rx_mpdu_info_details; 580 uint8_t qos_control_valid = 581 (_HAL_MS((*_OFFSET_TO_WORD_PTR((rx_mpdu_info), 582 RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_OFFSET)), 583 RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_MASK, 584 RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_LSB)); 585 586 if (qos_control_valid) 587 return hal_rx_mpdu_start_tid_get_8074(buf); 588 589 return HAL_RX_NON_QOS_TID; 590 } 591 592 /** 593 * hal_rx_hw_desc_get_ppduid_get_8074v1(): retrieve ppdu id 594 * @hw_desc_addr: hw addr 595 * 596 * Return: ppdu id 597 */ 598 static uint32_t hal_rx_hw_desc_get_ppduid_get_8074v1(void *hw_desc_addr) 599 { 600 struct rx_mpdu_info *rx_mpdu_info; 601 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr; 602 603 rx_mpdu_info = 604 &rx_desc->mpdu_start_tlv.rx_mpdu_start.rx_mpdu_info_details; 605 606 return HAL_RX_GET(rx_mpdu_info, RX_MPDU_INFO_0, PHY_PPDU_ID); 607 } 608 609 /** 610 * hal_reo_status_get_header_8074v1 - Process reo desc info 611 * @d - Pointer to reo descriptior 612 * @b - tlv type info 613 * @h1 - Pointer to hal_reo_status_header where info to be stored 614 * 615 * Return - none. 616 * 617 */ 618 static void hal_reo_status_get_header_8074v1(uint32_t *d, int b, void *h1) 619 { 620 uint32_t val1 = 0; 621 struct hal_reo_status_header *h = 622 (struct hal_reo_status_header *)h1; 623 624 switch (b) { 625 case HAL_REO_QUEUE_STATS_STATUS_TLV: 626 val1 = d[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_0, 627 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 628 break; 629 case HAL_REO_FLUSH_QUEUE_STATUS_TLV: 630 val1 = d[HAL_OFFSET_DW(REO_FLUSH_QUEUE_STATUS_0, 631 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 632 break; 633 case HAL_REO_FLUSH_CACHE_STATUS_TLV: 634 val1 = d[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_0, 635 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 636 break; 637 case HAL_REO_UNBLK_CACHE_STATUS_TLV: 638 val1 = d[HAL_OFFSET_DW(REO_UNBLOCK_CACHE_STATUS_0, 639 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 640 break; 641 case HAL_REO_TIMOUT_LIST_STATUS_TLV: 642 val1 = d[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_0, 643 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 644 break; 645 case HAL_REO_DESC_THRES_STATUS_TLV: 646 val1 = 647 d[HAL_OFFSET_DW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0, 648 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 649 break; 650 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: 651 val1 = d[HAL_OFFSET_DW(REO_UPDATE_RX_REO_QUEUE_STATUS_0, 652 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 653 break; 654 default: 655 qdf_nofl_err("ERROR: Unknown tlv\n"); 656 break; 657 } 658 h->cmd_num = 659 HAL_GET_FIELD( 660 UNIFORM_REO_STATUS_HEADER_0, REO_STATUS_NUMBER, 661 val1); 662 h->exec_time = 663 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_0, 664 CMD_EXECUTION_TIME, val1); 665 h->status = 666 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_0, 667 REO_CMD_EXECUTION_STATUS, val1); 668 switch (b) { 669 case HAL_REO_QUEUE_STATS_STATUS_TLV: 670 val1 = d[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_1, 671 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 672 break; 673 case HAL_REO_FLUSH_QUEUE_STATUS_TLV: 674 val1 = d[HAL_OFFSET_DW(REO_FLUSH_QUEUE_STATUS_1, 675 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 676 break; 677 case HAL_REO_FLUSH_CACHE_STATUS_TLV: 678 val1 = d[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_1, 679 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 680 break; 681 case HAL_REO_UNBLK_CACHE_STATUS_TLV: 682 val1 = d[HAL_OFFSET_DW(REO_UNBLOCK_CACHE_STATUS_1, 683 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 684 break; 685 case HAL_REO_TIMOUT_LIST_STATUS_TLV: 686 val1 = d[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_1, 687 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 688 break; 689 case HAL_REO_DESC_THRES_STATUS_TLV: 690 val1 = 691 d[HAL_OFFSET_DW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_1, 692 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 693 break; 694 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: 695 val1 = d[HAL_OFFSET_DW(REO_UPDATE_RX_REO_QUEUE_STATUS_1, 696 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 697 break; 698 default: 699 qdf_nofl_err("ERROR: Unknown tlv\n"); 700 break; 701 } 702 h->tstamp = 703 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_1, TIMESTAMP, val1); 704 } 705 706 /** 707 * hal_rx_mpdu_start_mpdu_qos_control_valid_get_8074v1(): 708 * Retrieve qos control valid bit from the tlv. 709 * @buf: pointer to rx pkt TLV. 710 * 711 * Return: qos control value. 712 */ 713 static inline uint32_t 714 hal_rx_mpdu_start_mpdu_qos_control_valid_get_8074v1(uint8_t *buf) 715 { 716 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 717 struct rx_mpdu_start *mpdu_start = 718 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 719 720 return HAL_RX_MPDU_INFO_QOS_CONTROL_VALID_GET( 721 &mpdu_start->rx_mpdu_info_details); 722 } 723 724 /** 725 * hal_rx_msdu_end_sa_sw_peer_id_get_8074v1(): API to get the 726 * sa_sw_peer_id from rx_msdu_end TLV 727 * @buf: pointer to the start of RX PKT TLV headers 728 * 729 * Return: sa_sw_peer_id index 730 */ 731 static inline uint32_t 732 hal_rx_msdu_end_sa_sw_peer_id_get_8074v1(uint8_t *buf) 733 { 734 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 735 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 736 737 return HAL_RX_MSDU_END_SA_SW_PEER_ID_GET(msdu_end); 738 } 739 740 /** 741 * hal_tx_desc_set_mesh_en_8074v1 - Set mesh_enable flag in Tx descriptor 742 * @desc: Handle to Tx Descriptor 743 * @en: For raw WiFi frames, this indicates transmission to a mesh STA, 744 * enabling the interpretation of the 'Mesh Control Present' bit 745 * (bit 8) of QoS Control (otherwise this bit is ignored), 746 * For native WiFi frames, this indicates that a 'Mesh Control' field 747 * is present between the header and the LLC. 748 * 749 * Return: void 750 */ 751 static inline 752 void hal_tx_desc_set_mesh_en_8074v1(void *desc, uint8_t en) 753 { 754 HAL_SET_FLD(desc, TCL_DATA_CMD_4, MESH_ENABLE) |= 755 HAL_TX_SM(TCL_DATA_CMD_4, MESH_ENABLE, en); 756 } 757 758 static 759 void *hal_rx_msdu0_buffer_addr_lsb_8074v1(void *link_desc_va) 760 { 761 return (void *)HAL_RX_MSDU0_BUFFER_ADDR_LSB(link_desc_va); 762 } 763 764 static 765 void *hal_rx_msdu_desc_info_ptr_get_8074v1(void *msdu0) 766 { 767 return (void *)HAL_RX_MSDU_DESC_INFO_PTR_GET(msdu0); 768 } 769 770 static 771 void *hal_ent_mpdu_desc_info_8074v1(void *ent_ring_desc) 772 { 773 return (void *)HAL_ENT_MPDU_DESC_INFO(ent_ring_desc); 774 } 775 776 static 777 void *hal_dst_mpdu_desc_info_8074v1(void *dst_ring_desc) 778 { 779 return (void *)HAL_DST_MPDU_DESC_INFO(dst_ring_desc); 780 } 781 782 static 783 uint8_t hal_rx_get_fc_valid_8074v1(uint8_t *buf) 784 { 785 return HAL_RX_GET_FC_VALID(buf); 786 } 787 788 static uint8_t hal_rx_get_to_ds_flag_8074v1(uint8_t *buf) 789 { 790 return HAL_RX_GET_TO_DS_FLAG(buf); 791 } 792 793 static uint8_t hal_rx_get_mac_addr2_valid_8074v1(uint8_t *buf) 794 { 795 return HAL_RX_GET_MAC_ADDR2_VALID(buf); 796 } 797 798 static uint8_t hal_rx_get_filter_category_8074v1(uint8_t *buf) 799 { 800 return HAL_RX_GET_FILTER_CATEGORY(buf); 801 } 802 803 static uint32_t 804 hal_rx_get_ppdu_id_8074v1(uint8_t *buf) 805 { 806 return HAL_RX_GET_PPDU_ID(buf); 807 } 808 809 /** 810 * hal_reo_config_8074v1(): Set reo config parameters 811 * @soc: hal soc handle 812 * @reg_val: value to be set 813 * @reo_params: reo parameters 814 * 815 * Return: void 816 */ 817 static void 818 hal_reo_config_8074v1(struct hal_soc *soc, 819 uint32_t reg_val, 820 struct hal_reo_params *reo_params) 821 { 822 HAL_REO_R0_CONFIG(soc, reg_val, reo_params); 823 } 824 825 /** 826 * hal_rx_msdu_desc_info_get_ptr_8074v1() - Get msdu desc info ptr 827 * @msdu_details_ptr - Pointer to msdu_details_ptr 828 * 829 * Return - Pointer to rx_msdu_desc_info structure. 830 * 831 */ 832 static void *hal_rx_msdu_desc_info_get_ptr_8074v1(void *msdu_details_ptr) 833 { 834 return HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr); 835 } 836 837 /** 838 * hal_rx_link_desc_msdu0_ptr_8074v1 - Get pointer to rx_msdu details 839 * @link_desc - Pointer to link desc 840 * 841 * Return - Pointer to rx_msdu_details structure 842 * 843 */ 844 static void *hal_rx_link_desc_msdu0_ptr_8074v1(void *link_desc) 845 { 846 return HAL_RX_LINK_DESC_MSDU0_PTR(link_desc); 847 } 848 849 /** 850 * hal_rx_msdu_flow_idx_get_8074v1: API to get flow index 851 * from rx_msdu_end TLV 852 * @buf: pointer to the start of RX PKT TLV headers 853 * 854 * Return: flow index value from MSDU END TLV 855 */ 856 static inline uint32_t hal_rx_msdu_flow_idx_get_8074v1(uint8_t *buf) 857 { 858 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 859 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 860 861 return HAL_RX_MSDU_END_FLOW_IDX_GET(msdu_end); 862 } 863 864 /** 865 * hal_rx_msdu_flow_idx_invalid_8074v1: API to get flow index invalid 866 * from rx_msdu_end TLV 867 * @buf: pointer to the start of RX PKT TLV headers 868 * 869 * Return: flow index invalid value from MSDU END TLV 870 */ 871 static bool hal_rx_msdu_flow_idx_invalid_8074v1(uint8_t *buf) 872 { 873 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 874 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 875 876 return HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(msdu_end); 877 } 878 879 /** 880 * hal_rx_msdu_flow_idx_timeout_8074v1: API to get flow index timeout 881 * from rx_msdu_end TLV 882 * @buf: pointer to the start of RX PKT TLV headers 883 * 884 * Return: flow index timeout value from MSDU END TLV 885 */ 886 static bool hal_rx_msdu_flow_idx_timeout_8074v1(uint8_t *buf) 887 { 888 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 889 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 890 891 return HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(msdu_end); 892 } 893 894 /** 895 * hal_rx_msdu_fse_metadata_get_8074v1: API to get FSE metadata 896 * from rx_msdu_end TLV 897 * @buf: pointer to the start of RX PKT TLV headers 898 * 899 * Return: fse metadata value from MSDU END TLV 900 */ 901 static uint32_t hal_rx_msdu_fse_metadata_get_8074v1(uint8_t *buf) 902 { 903 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 904 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 905 906 return HAL_RX_MSDU_END_FSE_METADATA_GET(msdu_end); 907 } 908 909 /** 910 * hal_rx_msdu_cce_metadata_get_8074v1: API to get CCE metadata 911 * from rx_msdu_end TLV 912 * @buf: pointer to the start of RX PKT TLV headers 913 * 914 * Return: cce_metadata 915 */ 916 static uint16_t 917 hal_rx_msdu_cce_metadata_get_8074v1(uint8_t *buf) 918 { 919 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 920 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 921 922 return HAL_RX_MSDU_END_CCE_METADATA_GET(msdu_end); 923 } 924 925 /** 926 * hal_rx_msdu_get_flow_params_8074v1: API to get flow index, flow index invalid 927 * and flow index timeout from rx_msdu_end TLV 928 * @buf: pointer to the start of RX PKT TLV headers 929 * @flow_invalid: pointer to return value of flow_idx_valid 930 * @flow_timeout: pointer to return value of flow_idx_timeout 931 * @flow_index: pointer to return value of flow_idx 932 * 933 * Return: none 934 */ 935 static inline void 936 hal_rx_msdu_get_flow_params_8074v1(uint8_t *buf, 937 bool *flow_invalid, 938 bool *flow_timeout, 939 uint32_t *flow_index) 940 { 941 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 942 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 943 944 *flow_invalid = HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(msdu_end); 945 *flow_timeout = HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(msdu_end); 946 *flow_index = HAL_RX_MSDU_END_FLOW_IDX_GET(msdu_end); 947 } 948 949 /** 950 * hal_rx_tlv_get_tcp_chksum_8074v1() - API to get tcp checksum 951 * @buf: rx_tlv_hdr 952 * 953 * Return: tcp checksum 954 */ 955 static uint16_t 956 hal_rx_tlv_get_tcp_chksum_8074v1(uint8_t *buf) 957 { 958 return HAL_RX_TLV_GET_TCP_CHKSUM(buf); 959 } 960 961 /** 962 * hal_rx_get_rx_sequence_8074v1(): Function to retrieve rx sequence number 963 * 964 * @nbuf: Network buffer 965 * Returns: rx sequence number 966 */ 967 static 968 uint16_t hal_rx_get_rx_sequence_8074v1(uint8_t *buf) 969 { 970 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 971 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 972 973 return HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info); 974 } 975 976 struct hal_hw_txrx_ops qca8074_hal_hw_txrx_ops = { 977 978 /* init and setup */ 979 hal_srng_dst_hw_init_generic, 980 hal_srng_src_hw_init_generic, 981 hal_get_hw_hptp_generic, 982 hal_reo_setup_generic, 983 hal_setup_link_idle_list_generic, 984 985 /* tx */ 986 hal_tx_desc_set_dscp_tid_table_id_8074, 987 hal_tx_set_dscp_tid_map_8074, 988 hal_tx_update_dscp_tid_8074, 989 hal_tx_desc_set_lmac_id_8074, 990 hal_tx_desc_set_buf_addr_generic, 991 hal_tx_desc_set_search_type_generic, 992 hal_tx_desc_set_search_index_generic, 993 hal_tx_desc_set_cache_set_num_generic, 994 hal_tx_comp_get_status_generic, 995 hal_tx_comp_get_release_reason_generic, 996 hal_tx_desc_set_mesh_en_8074v1, 997 /* rx */ 998 hal_rx_msdu_start_nss_get_8074, 999 hal_rx_mon_hw_desc_get_mpdu_status_8074, 1000 hal_rx_get_tlv_8074, 1001 hal_rx_proc_phyrx_other_receive_info_tlv_8074, 1002 hal_rx_dump_msdu_start_tlv_8074, 1003 hal_rx_dump_msdu_end_tlv_8074, 1004 hal_get_link_desc_size_8074, 1005 hal_rx_mpdu_start_tid_get_8074, 1006 hal_rx_msdu_start_reception_type_get_8074, 1007 hal_rx_msdu_end_da_idx_get_8074, 1008 hal_rx_msdu_desc_info_get_ptr_8074v1, 1009 hal_rx_link_desc_msdu0_ptr_8074v1, 1010 hal_reo_status_get_header_8074v1, 1011 hal_rx_status_get_tlv_info_generic, 1012 hal_rx_wbm_err_info_get_generic, 1013 hal_rx_dump_mpdu_start_tlv_generic, 1014 1015 hal_tx_set_pcp_tid_map_generic, 1016 hal_tx_update_pcp_tid_generic, 1017 hal_tx_update_tidmap_prty_generic, 1018 hal_rx_get_rx_fragment_number_8074v1, 1019 hal_rx_msdu_end_da_is_mcbc_get_8074v1, 1020 hal_rx_msdu_end_sa_is_valid_get_8074v1, 1021 hal_rx_msdu_end_sa_idx_get_8074v1, 1022 hal_rx_desc_is_first_msdu_8074v1, 1023 hal_rx_msdu_end_l3_hdr_padding_get_8074v1, 1024 hal_rx_encryption_info_valid_8074v1, 1025 hal_rx_print_pn_8074v1, 1026 hal_rx_msdu_end_first_msdu_get_8074v1, 1027 hal_rx_msdu_end_da_is_valid_get_8074v1, 1028 hal_rx_msdu_end_last_msdu_get_8074v1, 1029 hal_rx_get_mpdu_mac_ad4_valid_8074v1, 1030 hal_rx_mpdu_start_sw_peer_id_get_8074v1, 1031 hal_rx_mpdu_get_to_ds_8074v1, 1032 hal_rx_mpdu_get_fr_ds_8074v1, 1033 hal_rx_get_mpdu_frame_control_valid_8074v1, 1034 hal_rx_mpdu_get_addr1_8074v1, 1035 hal_rx_mpdu_get_addr2_8074v1, 1036 hal_rx_mpdu_get_addr3_8074v1, 1037 hal_rx_mpdu_get_addr4_8074v1, 1038 hal_rx_get_mpdu_sequence_control_valid_8074v1, 1039 hal_rx_is_unicast_8074v1, 1040 hal_rx_tid_get_8074v1, 1041 hal_rx_hw_desc_get_ppduid_get_8074v1, 1042 hal_rx_mpdu_start_mpdu_qos_control_valid_get_8074v1, 1043 hal_rx_msdu_end_sa_sw_peer_id_get_8074v1, 1044 hal_rx_msdu0_buffer_addr_lsb_8074v1, 1045 hal_rx_msdu_desc_info_ptr_get_8074v1, 1046 hal_ent_mpdu_desc_info_8074v1, 1047 hal_dst_mpdu_desc_info_8074v1, 1048 hal_rx_get_fc_valid_8074v1, 1049 hal_rx_get_to_ds_flag_8074v1, 1050 hal_rx_get_mac_addr2_valid_8074v1, 1051 hal_rx_get_filter_category_8074v1, 1052 hal_rx_get_ppdu_id_8074v1, 1053 hal_reo_config_8074v1, 1054 hal_rx_msdu_flow_idx_get_8074v1, 1055 hal_rx_msdu_flow_idx_invalid_8074v1, 1056 hal_rx_msdu_flow_idx_timeout_8074v1, 1057 hal_rx_msdu_fse_metadata_get_8074v1, 1058 hal_rx_msdu_cce_metadata_get_8074v1, 1059 hal_rx_msdu_get_flow_params_8074v1, 1060 hal_rx_tlv_get_tcp_chksum_8074v1, 1061 hal_rx_get_rx_sequence_8074v1, 1062 }; 1063 1064 struct hal_hw_srng_config hw_srng_table_8074[] = { 1065 /* TODO: max_rings can populated by querying HW capabilities */ 1066 { /* REO_DST */ 1067 .start_ring_id = HAL_SRNG_REO2SW1, 1068 .max_rings = 4, 1069 .entry_size = sizeof(struct reo_destination_ring) >> 2, 1070 .lmac_ring = FALSE, 1071 .ring_dir = HAL_SRNG_DST_RING, 1072 .reg_start = { 1073 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR( 1074 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1075 HWIO_REO_R2_REO2SW1_RING_HP_ADDR( 1076 SEQ_WCSS_UMAC_REO_REG_OFFSET) 1077 }, 1078 .reg_size = { 1079 HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(0) - 1080 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(0), 1081 HWIO_REO_R2_REO2SW2_RING_HP_ADDR(0) - 1082 HWIO_REO_R2_REO2SW1_RING_HP_ADDR(0), 1083 }, 1084 .max_size = 1085 HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_BMSK >> 1086 HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_SHFT, 1087 }, 1088 { /* REO_EXCEPTION */ 1089 /* Designating REO2TCL ring as exception ring. This ring is 1090 * similar to other REO2SW rings though it is named as REO2TCL. 1091 * Any of theREO2SW rings can be used as exception ring. 1092 */ 1093 .start_ring_id = HAL_SRNG_REO2TCL, 1094 .max_rings = 1, 1095 .entry_size = sizeof(struct reo_destination_ring) >> 2, 1096 .lmac_ring = FALSE, 1097 .ring_dir = HAL_SRNG_DST_RING, 1098 .reg_start = { 1099 HWIO_REO_R0_REO2TCL_RING_BASE_LSB_ADDR( 1100 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1101 HWIO_REO_R2_REO2TCL_RING_HP_ADDR( 1102 SEQ_WCSS_UMAC_REO_REG_OFFSET) 1103 }, 1104 /* Single ring - provide ring size if multiple rings of this 1105 * type are supported 1106 */ 1107 .reg_size = {}, 1108 .max_size = 1109 HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_BMSK >> 1110 HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_SHFT, 1111 }, 1112 { /* REO_REINJECT */ 1113 .start_ring_id = HAL_SRNG_SW2REO, 1114 .max_rings = 1, 1115 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 1116 .lmac_ring = FALSE, 1117 .ring_dir = HAL_SRNG_SRC_RING, 1118 .reg_start = { 1119 HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR( 1120 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1121 HWIO_REO_R2_SW2REO_RING_HP_ADDR( 1122 SEQ_WCSS_UMAC_REO_REG_OFFSET) 1123 }, 1124 /* Single ring - provide ring size if multiple rings of this 1125 * type are supported 1126 */ 1127 .reg_size = {}, 1128 .max_size = HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_BMSK >> 1129 HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_SHFT, 1130 }, 1131 { /* REO_CMD */ 1132 .start_ring_id = HAL_SRNG_REO_CMD, 1133 .max_rings = 1, 1134 .entry_size = (sizeof(struct tlv_32_hdr) + 1135 sizeof(struct reo_get_queue_stats)) >> 2, 1136 .lmac_ring = FALSE, 1137 .ring_dir = HAL_SRNG_SRC_RING, 1138 .reg_start = { 1139 HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR( 1140 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1141 HWIO_REO_R2_REO_CMD_RING_HP_ADDR( 1142 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1143 }, 1144 /* Single ring - provide ring size if multiple rings of this 1145 * type are supported 1146 */ 1147 .reg_size = {}, 1148 .max_size = HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_BMSK >> 1149 HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_SHFT, 1150 }, 1151 { /* REO_STATUS */ 1152 .start_ring_id = HAL_SRNG_REO_STATUS, 1153 .max_rings = 1, 1154 .entry_size = (sizeof(struct tlv_32_hdr) + 1155 sizeof(struct reo_get_queue_stats_status)) >> 2, 1156 .lmac_ring = FALSE, 1157 .ring_dir = HAL_SRNG_DST_RING, 1158 .reg_start = { 1159 HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR( 1160 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1161 HWIO_REO_R2_REO_STATUS_RING_HP_ADDR( 1162 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1163 }, 1164 /* Single ring - provide ring size if multiple rings of this 1165 * type are supported 1166 */ 1167 .reg_size = {}, 1168 .max_size = 1169 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> 1170 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, 1171 }, 1172 { /* TCL_DATA */ 1173 .start_ring_id = HAL_SRNG_SW2TCL1, 1174 .max_rings = 3, 1175 .entry_size = (sizeof(struct tlv_32_hdr) + 1176 sizeof(struct tcl_data_cmd)) >> 2, 1177 .lmac_ring = FALSE, 1178 .ring_dir = HAL_SRNG_SRC_RING, 1179 .reg_start = { 1180 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR( 1181 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1182 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR( 1183 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1184 }, 1185 .reg_size = { 1186 HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(0) - 1187 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(0), 1188 HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(0) - 1189 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(0), 1190 }, 1191 .max_size = 1192 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK >> 1193 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT, 1194 }, 1195 { /* TCL_CMD */ 1196 .start_ring_id = HAL_SRNG_SW2TCL_CMD, 1197 .max_rings = 1, 1198 .entry_size = (sizeof(struct tlv_32_hdr) + 1199 sizeof(struct tcl_gse_cmd)) >> 2, 1200 .lmac_ring = FALSE, 1201 .ring_dir = HAL_SRNG_SRC_RING, 1202 .reg_start = { 1203 HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_ADDR( 1204 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1205 HWIO_TCL_R2_SW2TCL_CMD_RING_HP_ADDR( 1206 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1207 }, 1208 /* Single ring - provide ring size if multiple rings of this 1209 * type are supported 1210 */ 1211 .reg_size = {}, 1212 .max_size = 1213 HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RING_SIZE_BMSK >> 1214 HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RING_SIZE_SHFT, 1215 }, 1216 { /* TCL_STATUS */ 1217 .start_ring_id = HAL_SRNG_TCL_STATUS, 1218 .max_rings = 1, 1219 .entry_size = (sizeof(struct tlv_32_hdr) + 1220 sizeof(struct tcl_status_ring)) >> 2, 1221 .lmac_ring = FALSE, 1222 .ring_dir = HAL_SRNG_DST_RING, 1223 .reg_start = { 1224 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR( 1225 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1226 HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR( 1227 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1228 }, 1229 /* Single ring - provide ring size if multiple rings of this 1230 * type are supported 1231 */ 1232 .reg_size = {}, 1233 .max_size = 1234 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_BMSK >> 1235 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_SHFT, 1236 }, 1237 { /* CE_SRC */ 1238 .start_ring_id = HAL_SRNG_CE_0_SRC, 1239 .max_rings = 12, 1240 .entry_size = sizeof(struct ce_src_desc) >> 2, 1241 .lmac_ring = FALSE, 1242 .ring_dir = HAL_SRNG_SRC_RING, 1243 .reg_start = { 1244 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR( 1245 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET), 1246 HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR( 1247 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET), 1248 }, 1249 .reg_size = { 1250 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET - 1251 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET, 1252 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET - 1253 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET, 1254 }, 1255 .max_size = 1256 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >> 1257 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT, 1258 }, 1259 { /* CE_DST */ 1260 .start_ring_id = HAL_SRNG_CE_0_DST, 1261 .max_rings = 12, 1262 .entry_size = 8 >> 2, 1263 /*TODO: entry_size above should actually be 1264 * sizeof(struct ce_dst_desc) >> 2, but couldn't find definition 1265 * of struct ce_dst_desc in HW header files 1266 */ 1267 .lmac_ring = FALSE, 1268 .ring_dir = HAL_SRNG_SRC_RING, 1269 .reg_start = { 1270 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR( 1271 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 1272 HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR( 1273 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 1274 }, 1275 .reg_size = { 1276 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 1277 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 1278 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 1279 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 1280 }, 1281 .max_size = 1282 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >> 1283 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT, 1284 }, 1285 { /* CE_DST_STATUS */ 1286 .start_ring_id = HAL_SRNG_CE_0_DST_STATUS, 1287 .max_rings = 12, 1288 .entry_size = sizeof(struct ce_stat_desc) >> 2, 1289 .lmac_ring = FALSE, 1290 .ring_dir = HAL_SRNG_DST_RING, 1291 .reg_start = { 1292 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR( 1293 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 1294 HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR( 1295 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 1296 }, 1297 /* TODO: check destination status ring registers */ 1298 .reg_size = { 1299 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 1300 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 1301 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 1302 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 1303 }, 1304 .max_size = 1305 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> 1306 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, 1307 }, 1308 { /* WBM_IDLE_LINK */ 1309 .start_ring_id = HAL_SRNG_WBM_IDLE_LINK, 1310 .max_rings = 1, 1311 .entry_size = sizeof(struct wbm_link_descriptor_ring) >> 2, 1312 .lmac_ring = FALSE, 1313 .ring_dir = HAL_SRNG_SRC_RING, 1314 .reg_start = { 1315 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1316 HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1317 }, 1318 /* Single ring - provide ring size if multiple rings of this 1319 * type are supported 1320 */ 1321 .reg_size = {}, 1322 .max_size = 1323 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_BMSK >> 1324 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_SHFT, 1325 }, 1326 { /* SW2WBM_RELEASE */ 1327 .start_ring_id = HAL_SRNG_WBM_SW_RELEASE, 1328 .max_rings = 1, 1329 .entry_size = sizeof(struct wbm_release_ring) >> 2, 1330 .lmac_ring = FALSE, 1331 .ring_dir = HAL_SRNG_SRC_RING, 1332 .reg_start = { 1333 HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1334 HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1335 }, 1336 /* Single ring - provide ring size if multiple rings of this 1337 * type are supported 1338 */ 1339 .reg_size = {}, 1340 .max_size = 1341 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> 1342 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, 1343 }, 1344 { /* WBM2SW_RELEASE */ 1345 .start_ring_id = HAL_SRNG_WBM2SW0_RELEASE, 1346 .max_rings = 4, 1347 .entry_size = sizeof(struct wbm_release_ring) >> 2, 1348 .lmac_ring = FALSE, 1349 .ring_dir = HAL_SRNG_DST_RING, 1350 .reg_start = { 1351 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1352 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1353 }, 1354 .reg_size = { 1355 HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) - 1356 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1357 HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) - 1358 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1359 }, 1360 .max_size = 1361 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> 1362 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, 1363 }, 1364 { /* RXDMA_BUF */ 1365 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA0_BUF0, 1366 #ifdef IPA_OFFLOAD 1367 .max_rings = 3, 1368 #else 1369 .max_rings = 2, 1370 #endif 1371 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 1372 .lmac_ring = TRUE, 1373 .ring_dir = HAL_SRNG_SRC_RING, 1374 /* reg_start is not set because LMAC rings are not accessed 1375 * from host 1376 */ 1377 .reg_start = {}, 1378 .reg_size = {}, 1379 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1380 }, 1381 { /* RXDMA_DST */ 1382 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW0, 1383 .max_rings = 1, 1384 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 1385 .lmac_ring = TRUE, 1386 .ring_dir = HAL_SRNG_DST_RING, 1387 /* reg_start is not set because LMAC rings are not accessed 1388 * from host 1389 */ 1390 .reg_start = {}, 1391 .reg_size = {}, 1392 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1393 }, 1394 { /* RXDMA_MONITOR_BUF */ 1395 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA2_BUF, 1396 .max_rings = 1, 1397 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 1398 .lmac_ring = TRUE, 1399 .ring_dir = HAL_SRNG_SRC_RING, 1400 /* reg_start is not set because LMAC rings are not accessed 1401 * from host 1402 */ 1403 .reg_start = {}, 1404 .reg_size = {}, 1405 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1406 }, 1407 { /* RXDMA_MONITOR_STATUS */ 1408 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_STATBUF, 1409 .max_rings = 1, 1410 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 1411 .lmac_ring = TRUE, 1412 .ring_dir = HAL_SRNG_SRC_RING, 1413 /* reg_start is not set because LMAC rings are not accessed 1414 * from host 1415 */ 1416 .reg_start = {}, 1417 .reg_size = {}, 1418 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1419 }, 1420 { /* RXDMA_MONITOR_DST */ 1421 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW1, 1422 .max_rings = 1, 1423 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 1424 .lmac_ring = TRUE, 1425 .ring_dir = HAL_SRNG_DST_RING, 1426 /* reg_start is not set because LMAC rings are not accessed 1427 * from host 1428 */ 1429 .reg_start = {}, 1430 .reg_size = {}, 1431 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1432 }, 1433 { /* RXDMA_MONITOR_DESC */ 1434 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_DESC, 1435 .max_rings = 1, 1436 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 1437 .lmac_ring = TRUE, 1438 .ring_dir = HAL_SRNG_SRC_RING, 1439 /* reg_start is not set because LMAC rings are not accessed 1440 * from host 1441 */ 1442 .reg_start = {}, 1443 .reg_size = {}, 1444 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1445 }, 1446 { /* DIR_BUF_RX_DMA_SRC */ 1447 .start_ring_id = HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING, 1448 .max_rings = 1, 1449 .entry_size = 2, 1450 .lmac_ring = TRUE, 1451 .ring_dir = HAL_SRNG_SRC_RING, 1452 /* reg_start is not set because LMAC rings are not accessed 1453 * from host 1454 */ 1455 .reg_start = {}, 1456 .reg_size = {}, 1457 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1458 }, 1459 #ifdef WLAN_FEATURE_CIF_CFR 1460 { /* WIFI_POS_SRC */ 1461 .start_ring_id = HAL_SRNG_WIFI_POS_SRC_DMA_RING, 1462 .max_rings = 1, 1463 .entry_size = sizeof(wmi_oem_dma_buf_release_entry) >> 2, 1464 .lmac_ring = TRUE, 1465 .ring_dir = HAL_SRNG_SRC_RING, 1466 /* reg_start is not set because LMAC rings are not accessed 1467 * from host 1468 */ 1469 .reg_start = {}, 1470 .reg_size = {}, 1471 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1472 }, 1473 #endif 1474 }; 1475 1476 int32_t hal_hw_reg_offset_qca8074[] = { 1477 /* dst */ 1478 REG_OFFSET(DST, HP), 1479 REG_OFFSET(DST, TP), 1480 REG_OFFSET(DST, ID), 1481 REG_OFFSET(DST, MISC), 1482 REG_OFFSET(DST, HP_ADDR_LSB), 1483 REG_OFFSET(DST, HP_ADDR_MSB), 1484 REG_OFFSET(DST, MSI1_BASE_LSB), 1485 REG_OFFSET(DST, MSI1_BASE_MSB), 1486 REG_OFFSET(DST, MSI1_DATA), 1487 REG_OFFSET(DST, BASE_LSB), 1488 REG_OFFSET(DST, BASE_MSB), 1489 REG_OFFSET(DST, PRODUCER_INT_SETUP), 1490 /* src */ 1491 REG_OFFSET(SRC, HP), 1492 REG_OFFSET(SRC, TP), 1493 REG_OFFSET(SRC, ID), 1494 REG_OFFSET(SRC, MISC), 1495 REG_OFFSET(SRC, TP_ADDR_LSB), 1496 REG_OFFSET(SRC, TP_ADDR_MSB), 1497 REG_OFFSET(SRC, MSI1_BASE_LSB), 1498 REG_OFFSET(SRC, MSI1_BASE_MSB), 1499 REG_OFFSET(SRC, MSI1_DATA), 1500 REG_OFFSET(SRC, BASE_LSB), 1501 REG_OFFSET(SRC, BASE_MSB), 1502 REG_OFFSET(SRC, CONSUMER_INT_SETUP_IX0), 1503 REG_OFFSET(SRC, CONSUMER_INT_SETUP_IX1), 1504 }; 1505 1506 /** 1507 * hal_qca8074_attach() - Attach 8074 target specific hal_soc ops, 1508 * offset and srng table 1509 */ 1510 void hal_qca8074_attach(struct hal_soc *hal_soc) 1511 { 1512 hal_soc->hw_srng_table = hw_srng_table_8074; 1513 hal_soc->hal_hw_reg_offset = hal_hw_reg_offset_qca8074; 1514 hal_soc->ops = &qca8074_hal_hw_txrx_ops; 1515 } 1516