1 /* 2 * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved. 3 * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #ifndef _HAL_6750_RX_H_ 21 #define _HAL_6750_RX_H_ 22 #include "qdf_util.h" 23 #include "qdf_types.h" 24 #include "qdf_lock.h" 25 #include "qdf_mem.h" 26 #include "qdf_nbuf.h" 27 #include "tcl_data_cmd.h" 28 #include "mac_tcl_reg_seq_hwioreg.h" 29 #include "phyrx_rssi_legacy.h" 30 #include "rx_msdu_start.h" 31 #include "tlv_tag_def.h" 32 #include "hal_hw_headers.h" 33 #include "hal_internal.h" 34 #include "cdp_txrx_mon_struct.h" 35 #include "qdf_trace.h" 36 #include "hal_rx.h" 37 #include "hal_tx.h" 38 #include "dp_types.h" 39 #include "hal_api_mon.h" 40 #include "phyrx_other_receive_info_ru_details.h" 41 42 #define HAL_RX_MSDU_START_MIMO_SS_BITMAP(_rx_msdu_start)\ 43 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start),\ 44 RX_MSDU_START_5_MIMO_SS_BITMAP_OFFSET)), \ 45 RX_MSDU_START_5_MIMO_SS_BITMAP_MASK, \ 46 RX_MSDU_START_5_MIMO_SS_BITMAP_LSB)) 47 48 #define HAL_RX_MPDU_GET_SEQUENCE_NUMBER(_rx_mpdu_info) \ 49 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 50 RX_MPDU_INFO_11_MPDU_SEQUENCE_NUMBER_OFFSET)), \ 51 RX_MPDU_INFO_11_MPDU_SEQUENCE_NUMBER_MASK, \ 52 RX_MPDU_INFO_11_MPDU_SEQUENCE_NUMBER_LSB)) 53 54 #define HAL_RX_MSDU_END_DA_IS_MCBC_GET(_rx_msdu_end) \ 55 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 56 RX_MSDU_END_10_DA_IS_MCBC_OFFSET)), \ 57 RX_MSDU_END_10_DA_IS_MCBC_MASK, \ 58 RX_MSDU_END_10_DA_IS_MCBC_LSB)) 59 60 #define HAL_RX_MSDU_END_SA_IS_VALID_GET(_rx_msdu_end) \ 61 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 62 RX_MSDU_END_10_SA_IS_VALID_OFFSET)), \ 63 RX_MSDU_END_10_SA_IS_VALID_MASK, \ 64 RX_MSDU_END_10_SA_IS_VALID_LSB)) 65 66 #define HAL_RX_MSDU_END_SA_IDX_GET(_rx_msdu_end) \ 67 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 68 RX_MSDU_END_11_SA_IDX_OFFSET)), \ 69 RX_MSDU_END_11_SA_IDX_MASK, \ 70 RX_MSDU_END_11_SA_IDX_LSB)) 71 72 #define HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(_rx_msdu_end) \ 73 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 74 RX_MSDU_END_10_L3_HEADER_PADDING_OFFSET)), \ 75 RX_MSDU_END_10_L3_HEADER_PADDING_MASK, \ 76 RX_MSDU_END_10_L3_HEADER_PADDING_LSB)) 77 78 #define HAL_RX_MPDU_ENCRYPTION_INFO_VALID(_rx_mpdu_info) \ 79 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 80 RX_MPDU_INFO_11_FRAME_ENCRYPTION_INFO_VALID_OFFSET)), \ 81 RX_MPDU_INFO_11_FRAME_ENCRYPTION_INFO_VALID_MASK, \ 82 RX_MPDU_INFO_11_FRAME_ENCRYPTION_INFO_VALID_LSB)) 83 84 #define HAL_RX_MPDU_PN_31_0_GET(_rx_mpdu_info) \ 85 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 86 RX_MPDU_INFO_3_PN_31_0_OFFSET)), \ 87 RX_MPDU_INFO_3_PN_31_0_MASK, \ 88 RX_MPDU_INFO_3_PN_31_0_LSB)) 89 90 #define HAL_RX_MPDU_PN_63_32_GET(_rx_mpdu_info) \ 91 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 92 RX_MPDU_INFO_4_PN_63_32_OFFSET)), \ 93 RX_MPDU_INFO_4_PN_63_32_MASK, \ 94 RX_MPDU_INFO_4_PN_63_32_LSB)) 95 96 #define HAL_RX_MPDU_PN_95_64_GET(_rx_mpdu_info) \ 97 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 98 RX_MPDU_INFO_5_PN_95_64_OFFSET)), \ 99 RX_MPDU_INFO_5_PN_95_64_MASK, \ 100 RX_MPDU_INFO_5_PN_95_64_LSB)) 101 102 #define HAL_RX_MPDU_PN_127_96_GET(_rx_mpdu_info) \ 103 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 104 RX_MPDU_INFO_6_PN_127_96_OFFSET)), \ 105 RX_MPDU_INFO_6_PN_127_96_MASK, \ 106 RX_MPDU_INFO_6_PN_127_96_LSB)) 107 108 #define HAL_RX_MSDU_END_FIRST_MSDU_GET(_rx_msdu_end) \ 109 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 110 RX_MSDU_END_10_FIRST_MSDU_OFFSET)), \ 111 RX_MSDU_END_10_FIRST_MSDU_MASK, \ 112 RX_MSDU_END_10_FIRST_MSDU_LSB)) 113 114 #define HAL_RX_MSDU_END_DA_IS_VALID_GET(_rx_msdu_end) \ 115 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 116 RX_MSDU_END_10_DA_IS_VALID_OFFSET)), \ 117 RX_MSDU_END_10_DA_IS_VALID_MASK, \ 118 RX_MSDU_END_10_DA_IS_VALID_LSB)) 119 120 #define HAL_RX_MSDU_END_LAST_MSDU_GET(_rx_msdu_end) \ 121 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 122 RX_MSDU_END_10_LAST_MSDU_OFFSET)), \ 123 RX_MSDU_END_10_LAST_MSDU_MASK, \ 124 RX_MSDU_END_10_LAST_MSDU_LSB)) 125 126 #define HAL_RX_MPDU_GET_MAC_AD4_VALID(_rx_mpdu_info) \ 127 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 128 RX_MPDU_INFO_11_MAC_ADDR_AD4_VALID_OFFSET)), \ 129 RX_MPDU_INFO_11_MAC_ADDR_AD4_VALID_MASK, \ 130 RX_MPDU_INFO_11_MAC_ADDR_AD4_VALID_LSB)) 131 132 #define HAL_RX_MPDU_INFO_SW_PEER_ID_GET(_rx_mpdu_info) \ 133 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_info), \ 134 RX_MPDU_INFO_10_SW_PEER_ID_OFFSET)), \ 135 RX_MPDU_INFO_10_SW_PEER_ID_MASK, \ 136 RX_MPDU_INFO_10_SW_PEER_ID_LSB)) 137 138 #define HAL_RX_MPDU_GET_TODS(_rx_mpdu_info) \ 139 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 140 RX_MPDU_INFO_11_TO_DS_OFFSET)), \ 141 RX_MPDU_INFO_11_TO_DS_MASK, \ 142 RX_MPDU_INFO_11_TO_DS_LSB)) 143 144 #define HAL_RX_MPDU_GET_FROMDS(_rx_mpdu_info) \ 145 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 146 RX_MPDU_INFO_11_FR_DS_OFFSET)), \ 147 RX_MPDU_INFO_11_FR_DS_MASK, \ 148 RX_MPDU_INFO_11_FR_DS_LSB)) 149 150 #define HAL_RX_MPDU_GET_FRAME_CONTROL_VALID(_rx_mpdu_info) \ 151 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 152 RX_MPDU_INFO_11_MPDU_FRAME_CONTROL_VALID_OFFSET)), \ 153 RX_MPDU_INFO_11_MPDU_FRAME_CONTROL_VALID_MASK, \ 154 RX_MPDU_INFO_11_MPDU_FRAME_CONTROL_VALID_LSB)) 155 156 #define HAL_RX_MPDU_MAC_ADDR_AD1_VALID_GET(_rx_mpdu_info) \ 157 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 158 RX_MPDU_INFO_11_MAC_ADDR_AD1_VALID_OFFSET)), \ 159 RX_MPDU_INFO_11_MAC_ADDR_AD1_VALID_MASK, \ 160 RX_MPDU_INFO_11_MAC_ADDR_AD1_VALID_LSB)) 161 162 #define HAL_RX_MPDU_AD1_31_0_GET(_rx_mpdu_info) \ 163 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 164 RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_OFFSET)), \ 165 RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_MASK, \ 166 RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_LSB)) 167 168 #define HAL_RX_MPDU_AD1_47_32_GET(_rx_mpdu_info) \ 169 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 170 RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_OFFSET)), \ 171 RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_MASK, \ 172 RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_LSB)) 173 174 #define HAL_RX_MPDU_MAC_ADDR_AD2_VALID_GET(_rx_mpdu_info) \ 175 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 176 RX_MPDU_INFO_11_MAC_ADDR_AD2_VALID_OFFSET)), \ 177 RX_MPDU_INFO_11_MAC_ADDR_AD2_VALID_MASK, \ 178 RX_MPDU_INFO_11_MAC_ADDR_AD2_VALID_LSB)) 179 180 #define HAL_RX_MPDU_AD2_15_0_GET(_rx_mpdu_info) \ 181 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 182 RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_OFFSET)), \ 183 RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_MASK, \ 184 RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_LSB)) 185 186 #define HAL_RX_MPDU_AD2_47_16_GET(_rx_mpdu_info) \ 187 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 188 RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_OFFSET)), \ 189 RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_MASK, \ 190 RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_LSB)) 191 192 #define HAL_RX_MPDU_MAC_ADDR_AD3_VALID_GET(_rx_mpdu_info) \ 193 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 194 RX_MPDU_INFO_11_MAC_ADDR_AD3_VALID_OFFSET)), \ 195 RX_MPDU_INFO_11_MAC_ADDR_AD3_VALID_MASK, \ 196 RX_MPDU_INFO_11_MAC_ADDR_AD3_VALID_LSB)) 197 198 #define HAL_RX_MPDU_AD3_31_0_GET(_rx_mpdu_info) \ 199 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 200 RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_OFFSET)), \ 201 RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_MASK, \ 202 RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_LSB)) 203 204 #define HAL_RX_MPDU_AD3_47_32_GET(_rx_mpdu_info) \ 205 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 206 RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_OFFSET)), \ 207 RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_MASK, \ 208 RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_LSB)) 209 210 #define HAL_RX_MPDU_MAC_ADDR_AD4_VALID_GET(_rx_mpdu_info) \ 211 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 212 RX_MPDU_INFO_11_MAC_ADDR_AD4_VALID_OFFSET)), \ 213 RX_MPDU_INFO_11_MAC_ADDR_AD4_VALID_MASK, \ 214 RX_MPDU_INFO_11_MAC_ADDR_AD4_VALID_LSB)) 215 216 #define HAL_RX_MPDU_AD4_31_0_GET(_rx_mpdu_info) \ 217 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 218 RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_OFFSET)), \ 219 RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_MASK, \ 220 RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_LSB)) 221 222 #define HAL_RX_MPDU_AD4_47_32_GET(_rx_mpdu_info) \ 223 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 224 RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_OFFSET)), \ 225 RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_MASK, \ 226 RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_LSB)) 227 228 #define HAL_RX_MPDU_GET_SEQUENCE_CONTROL_VALID(_rx_mpdu_info) \ 229 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 230 RX_MPDU_INFO_11_MPDU_SEQUENCE_CONTROL_VALID_OFFSET)), \ 231 RX_MPDU_INFO_11_MPDU_SEQUENCE_CONTROL_VALID_MASK, \ 232 RX_MPDU_INFO_11_MPDU_SEQUENCE_CONTROL_VALID_LSB)) 233 234 #define HAL_RX_MPDU_INFO_QOS_CONTROL_VALID_GET(_rx_mpdu_info) \ 235 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_info), \ 236 RX_MPDU_INFO_11_MPDU_QOS_CONTROL_VALID_OFFSET)),\ 237 RX_MPDU_INFO_11_MPDU_QOS_CONTROL_VALID_MASK, \ 238 RX_MPDU_INFO_11_MPDU_QOS_CONTROL_VALID_LSB)) 239 240 #define HAL_RX_MSDU_END_SA_SW_PEER_ID_GET(_rx_msdu_end) \ 241 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 242 RX_MSDU_END_14_SA_SW_PEER_ID_OFFSET)), \ 243 RX_MSDU_END_14_SA_SW_PEER_ID_MASK, \ 244 RX_MSDU_END_14_SA_SW_PEER_ID_LSB)) 245 246 #define HAL_RX_MSDU0_BUFFER_ADDR_LSB(link_desc_va) \ 247 (uint8_t *)(link_desc_va) + \ 248 RX_MSDU_LINK_8_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 249 250 #define HAL_RX_MSDU_DESC_INFO_PTR_GET(msdu0) \ 251 (uint8_t *)(msdu0) + \ 252 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 253 254 #define HAL_ENT_MPDU_DESC_INFO(ent_ring_desc) \ 255 (uint8_t *)(ent_ring_desc) + \ 256 RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_OFFSET 257 258 #define HAL_DST_MPDU_DESC_INFO(dst_ring_desc) \ 259 (uint8_t *)(dst_ring_desc) + \ 260 REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 261 262 #define HAL_RX_GET_FC_VALID(rx_mpdu_start) \ 263 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_11, MPDU_FRAME_CONTROL_VALID) 264 265 #define HAL_RX_GET_TO_DS_FLAG(rx_mpdu_start) \ 266 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_11, TO_DS) 267 268 #define HAL_RX_GET_MAC_ADDR1_VALID(rx_mpdu_start) \ 269 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_11, MAC_ADDR_AD1_VALID) 270 271 #define HAL_RX_GET_MAC_ADDR2_VALID(rx_mpdu_start) \ 272 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_11, MAC_ADDR_AD2_VALID) 273 274 #define HAL_RX_GET_FILTER_CATEGORY(rx_mpdu_start) \ 275 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_9, RXPCU_MPDU_FILTER_IN_CATEGORY) 276 277 #define HAL_RX_GET_PPDU_ID(rx_mpdu_start) \ 278 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_9, PHY_PPDU_ID) 279 280 #define HAL_RX_GET_SW_FRAME_GROUP_ID(rx_mpdu_start) \ 281 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_9, SW_FRAME_GROUP_ID) 282 283 #define HAL_RX_GET_SW_PEER_ID(rx_mpdu_start) \ 284 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_10, SW_PEER_ID) 285 286 #define HAL_REO_R0_CONFIG(soc, reg_val, reo_params) \ 287 do { \ 288 reg_val &= \ 289 ~(HWIO_REO_R0_GENERAL_ENABLE_AGING_LIST_ENABLE_BMSK |\ 290 HWIO_REO_R0_GENERAL_ENABLE_AGING_FLUSH_ENABLE_BMSK); \ 291 reg_val |= \ 292 HAL_SM(HWIO_REO_R0_GENERAL_ENABLE, \ 293 AGING_LIST_ENABLE, 1) |\ 294 HAL_SM(HWIO_REO_R0_GENERAL_ENABLE, \ 295 AGING_FLUSH_ENABLE, 1);\ 296 HAL_REG_WRITE((soc), \ 297 HWIO_REO_R0_GENERAL_ENABLE_ADDR( \ 298 SEQ_WCSS_UMAC_REO_REG_OFFSET), \ 299 (reg_val)); \ 300 reg_val = \ 301 HAL_REG_READ((soc), \ 302 HWIO_REO_R0_MISC_CTL_ADDR( \ 303 SEQ_WCSS_UMAC_REO_REG_OFFSET)); \ 304 reg_val &= \ 305 ~(HWIO_REO_R0_MISC_CTL_FRAGMENT_DEST_RING_BMSK); \ 306 reg_val |= \ 307 HAL_SM(HWIO_REO_R0_MISC_CTL, \ 308 FRAGMENT_DEST_RING, \ 309 (reo_params)->frag_dst_ring); \ 310 HAL_REG_WRITE((soc), \ 311 HWIO_REO_R0_MISC_CTL_ADDR( \ 312 SEQ_WCSS_UMAC_REO_REG_OFFSET), \ 313 (reg_val)); \ 314 reg_val = \ 315 HAL_REG_READ((soc), \ 316 HWIO_REO_R0_GENERAL_ENABLE_ADDR( \ 317 SEQ_WCSS_UMAC_REO_REG_OFFSET)); \ 318 reg_val &= \ 319 (~HWIO_REO_R0_GENERAL_ENABLE_BAR_DEST_RING_BMSK |\ 320 (REO_REMAP_TCL << HWIO_REO_R0_GENERAL_ENABLE_BAR_DEST_RING_SHFT)); \ 321 HAL_REG_WRITE((soc), \ 322 HWIO_REO_R0_GENERAL_ENABLE_ADDR( \ 323 SEQ_WCSS_UMAC_REO_REG_OFFSET), \ 324 (reg_val)); \ 325 } while (0) 326 327 #define HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr) \ 328 ((struct rx_msdu_desc_info *) \ 329 _OFFSET_TO_BYTE_PTR(msdu_details_ptr, \ 330 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_OFFSET)) 331 332 #define HAL_RX_LINK_DESC_MSDU0_PTR(link_desc) \ 333 ((struct rx_msdu_details *) \ 334 _OFFSET_TO_BYTE_PTR((link_desc),\ 335 RX_MSDU_LINK_8_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET)) 336 337 #define HAL_RX_MSDU_END_FLOW_IDX_GET(_rx_msdu_end) \ 338 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 339 RX_MSDU_END_12_FLOW_IDX_OFFSET)), \ 340 RX_MSDU_END_12_FLOW_IDX_MASK, \ 341 RX_MSDU_END_12_FLOW_IDX_LSB)) 342 343 #define HAL_RX_MSDU_END_REO_DEST_IND_GET(_rx_msdu_end) \ 344 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 345 RX_MSDU_END_12_REO_DESTINATION_INDICATION_OFFSET)), \ 346 RX_MSDU_END_12_REO_DESTINATION_INDICATION_MASK, \ 347 RX_MSDU_END_12_REO_DESTINATION_INDICATION_LSB)) 348 349 #define HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(_rx_msdu_end) \ 350 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 351 RX_MSDU_END_10_FLOW_IDX_INVALID_OFFSET)), \ 352 RX_MSDU_END_10_FLOW_IDX_INVALID_MASK, \ 353 RX_MSDU_END_10_FLOW_IDX_INVALID_LSB)) 354 355 #define HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(_rx_msdu_end) \ 356 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 357 RX_MSDU_END_10_FLOW_IDX_TIMEOUT_OFFSET)), \ 358 RX_MSDU_END_10_FLOW_IDX_TIMEOUT_MASK, \ 359 RX_MSDU_END_10_FLOW_IDX_TIMEOUT_LSB)) 360 361 #define HAL_RX_MSDU_END_FSE_METADATA_GET(_rx_msdu_end) \ 362 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 363 RX_MSDU_END_13_FSE_METADATA_OFFSET)), \ 364 RX_MSDU_END_13_FSE_METADATA_MASK, \ 365 RX_MSDU_END_13_FSE_METADATA_LSB)) 366 367 #define HAL_RX_MSDU_END_CCE_METADATA_GET(_rx_msdu_end) \ 368 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 369 RX_MSDU_END_14_CCE_METADATA_OFFSET)), \ 370 RX_MSDU_END_14_CCE_METADATA_MASK, \ 371 RX_MSDU_END_14_CCE_METADATA_LSB)) 372 373 #define HAL_RX_TLV_GET_TCP_CHKSUM(buf) \ 374 (_HAL_MS( \ 375 (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ 376 msdu_end_tlv.rx_msdu_end), \ 377 RX_MSDU_END_10_TCP_UDP_CHKSUM_OFFSET)), \ 378 RX_MSDU_END_10_TCP_UDP_CHKSUM_MASK, \ 379 RX_MSDU_END_10_TCP_UDP_CHKSUM_LSB)) 380 381 #define HAL_RX_MSDU_END_DA_IDX_GET(_rx_msdu_end) \ 382 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 383 RX_MSDU_END_11_DA_IDX_OR_SW_PEER_ID_OFFSET)), \ 384 RX_MSDU_END_11_DA_IDX_OR_SW_PEER_ID_MASK, \ 385 RX_MSDU_END_11_DA_IDX_OR_SW_PEER_ID_LSB)) 386 387 #define HAL_RX_TLV_GET_FLOW_AGGR_CONT(buf) \ 388 (_HAL_MS( \ 389 (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ 390 msdu_end_tlv.rx_msdu_end), \ 391 RX_MSDU_END_15_FLOW_AGGREGATION_CONTINUATION_OFFSET)), \ 392 RX_MSDU_END_15_FLOW_AGGREGATION_CONTINUATION_MASK, \ 393 RX_MSDU_END_15_FLOW_AGGREGATION_CONTINUATION_LSB)) 394 395 #define HAL_RX_TLV_GET_FLOW_AGGR_COUNT(buf) \ 396 (_HAL_MS( \ 397 (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ 398 msdu_end_tlv.rx_msdu_end), \ 399 RX_MSDU_END_15_AGGREGATION_COUNT_OFFSET)), \ 400 RX_MSDU_END_15_AGGREGATION_COUNT_MASK, \ 401 RX_MSDU_END_15_AGGREGATION_COUNT_LSB)) 402 403 #define HAL_RX_TLV_GET_FISA_TIMEOUT(buf) \ 404 (_HAL_MS( \ 405 (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ 406 msdu_end_tlv.rx_msdu_end), \ 407 RX_MSDU_END_15_FISA_TIMEOUT_OFFSET)), \ 408 RX_MSDU_END_15_FISA_TIMEOUT_MASK, \ 409 RX_MSDU_END_15_FISA_TIMEOUT_LSB)) 410 411 #define HAL_RX_TLV_GET_FISA_CUMULATIVE_L4_CHECKSUM(buf) \ 412 (_HAL_MS( \ 413 (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ 414 msdu_end_tlv.rx_msdu_end), \ 415 RX_MSDU_END_16_CUMULATIVE_L4_CHECKSUM_OFFSET)), \ 416 RX_MSDU_END_16_CUMULATIVE_L4_CHECKSUM_MASK, \ 417 RX_MSDU_END_16_CUMULATIVE_L4_CHECKSUM_LSB)) 418 419 #define HAL_RX_TLV_GET_FISA_CUMULATIVE_IP_LENGTH(buf) \ 420 (_HAL_MS( \ 421 (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ 422 msdu_end_tlv.rx_msdu_end), \ 423 RX_MSDU_END_16_CUMULATIVE_IP_LENGTH_OFFSET)), \ 424 RX_MSDU_END_16_CUMULATIVE_IP_LENGTH_MASK, \ 425 RX_MSDU_END_16_CUMULATIVE_IP_LENGTH_LSB)) 426 427 #if defined(QCA_WIFI_QCA6750) && defined(WLAN_CFR_ENABLE) && \ 428 defined(WLAN_ENH_CFR_ENABLE) 429 static inline 430 void hal_rx_get_bb_info_6750(void *rx_tlv, 431 void *ppdu_info_hdl) 432 { 433 struct hal_rx_ppdu_info *ppdu_info = ppdu_info_hdl; 434 435 ppdu_info->cfr_info.bb_captured_channel = 436 HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_3, BB_CAPTURED_CHANNEL); 437 438 ppdu_info->cfr_info.bb_captured_timeout = 439 HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_3, BB_CAPTURED_TIMEOUT); 440 441 ppdu_info->cfr_info.bb_captured_reason = 442 HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_3, BB_CAPTURED_REASON); 443 } 444 445 static inline 446 void hal_rx_get_rtt_info_6750(void *rx_tlv, 447 void *ppdu_info_hdl) 448 { 449 struct hal_rx_ppdu_info *ppdu_info = ppdu_info_hdl; 450 451 ppdu_info->cfr_info.rx_location_info_valid = 452 HAL_RX_GET(rx_tlv, PHYRX_PKT_END_13_RX_PKT_END_DETAILS, 453 RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID); 454 455 ppdu_info->cfr_info.rtt_che_buffer_pointer_low32 = 456 HAL_RX_GET(rx_tlv, 457 PHYRX_PKT_END_12_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS, 458 RTT_CHE_BUFFER_POINTER_LOW32); 459 460 ppdu_info->cfr_info.rtt_che_buffer_pointer_high8 = 461 HAL_RX_GET(rx_tlv, 462 PHYRX_PKT_END_11_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS, 463 RTT_CHE_BUFFER_POINTER_HIGH8); 464 465 ppdu_info->cfr_info.chan_capture_status = 466 HAL_RX_GET(rx_tlv, 467 PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS, 468 RESERVED_8); 469 ppdu_info->cfr_info.rx_start_ts = 470 HAL_RX_GET(rx_tlv, 471 PHYRX_PKT_END_9_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS, 472 RX_START_TS); 473 474 ppdu_info->cfr_info.rtt_cfo_measurement = (int16_t) 475 HAL_RX_GET(rx_tlv, 476 PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS, 477 RTT_CFO_MEASUREMENT); 478 479 ppdu_info->cfr_info.agc_gain_info0 = 480 HAL_RX_GET(rx_tlv, 481 PHYRX_PKT_END_1_RX_PKT_END_DETAILS, 482 PHY_TIMESTAMP_1_LOWER_32); 483 484 ppdu_info->cfr_info.agc_gain_info1 = 485 HAL_RX_GET(rx_tlv, 486 PHYRX_PKT_END_2_RX_PKT_END_DETAILS, 487 PHY_TIMESTAMP_1_UPPER_32); 488 489 ppdu_info->cfr_info.agc_gain_info2 = 490 HAL_RX_GET(rx_tlv, 491 PHYRX_PKT_END_3_RX_PKT_END_DETAILS, 492 PHY_TIMESTAMP_2_LOWER_32); 493 494 ppdu_info->cfr_info.agc_gain_info3 = 495 HAL_RX_GET(rx_tlv, 496 PHYRX_PKT_END_4_RX_PKT_END_DETAILS, 497 PHY_TIMESTAMP_2_UPPER_32); 498 499 ppdu_info->cfr_info.mcs_rate = 500 HAL_RX_GET(rx_tlv, 501 PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS, 502 RTT_MCS_RATE); 503 504 ppdu_info->cfr_info.gi_type = 505 HAL_RX_GET(rx_tlv, 506 PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS, 507 RTT_GI_TYPE); 508 } 509 #endif 510 #endif 511