1 /* 2 * Copyright (c) 2020 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #include "qdf_types.h" 20 #include "qdf_util.h" 21 #include "qdf_types.h" 22 #include "qdf_lock.h" 23 #include "qdf_mem.h" 24 #include "qdf_nbuf.h" 25 #include "hal_hw_headers.h" 26 #include "hal_internal.h" 27 #include "hal_api.h" 28 #include "target_type.h" 29 #include "wcss_version.h" 30 #include "qdf_module.h" 31 32 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_OFFSET \ 33 RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_OFFSET 34 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_MASK \ 35 RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_MASK 36 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_LSB \ 37 RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_LSB 38 #define UNIFIED_PHYRX_HT_SIG_0_HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS_OFFSET \ 39 PHYRX_L_SIG_B_0_PHYRX_L_SIG_B_INFO_DETAILS_RATE_OFFSET 40 #define UNIFIED_PHYRX_L_SIG_B_0_L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS_OFFSET \ 41 PHYRX_L_SIG_B_0_PHYRX_L_SIG_B_INFO_DETAILS_RATE_OFFSET 42 #define UNIFIED_PHYRX_L_SIG_A_0_L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS_OFFSET \ 43 PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_RATE_OFFSET 44 #define UNIFIED_PHYRX_VHT_SIG_A_0_VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS_OFFSET \ 45 PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_OFFSET 46 #define UNIFIED_PHYRX_HE_SIG_A_SU_0_HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS_OFFSET \ 47 PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_OFFSET 48 #define UNIFIED_PHYRX_HE_SIG_A_MU_DL_0_HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_OFFSET \ 49 PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_OFFSET 50 #define UNIFIED_PHYRX_HE_SIG_B1_MU_0_HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_OFFSET \ 51 PHYRX_HE_SIG_B1_MU_0_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_OFFSET 52 #define UNIFIED_PHYRX_HE_SIG_B2_MU_0_HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_OFFSET \ 53 PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_OFFSET 54 #define UNIFIED_PHYRX_HE_SIG_B2_OFDMA_0_HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_OFFSET \ 55 PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_OFFSET 56 57 #define UNIFIED_PHYRX_RSSI_LEGACY_3_RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS_OFFSET \ 58 PHYRX_RSSI_LEGACY_3_RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS_OFFSET 59 #define UNIFIED_PHYRX_RSSI_LEGACY_19_RECEIVE_RSSI_INFO_PREAMBLE_RSSI_INFO_DETAILS_OFFSET \ 60 PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 61 #define UNIFIED_RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET \ 62 RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 63 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 64 RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET 65 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ 66 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET 67 #define UNIFIED_RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 68 RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET 69 #define UNIFIED_REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 70 REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET 71 #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC \ 72 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER 73 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ 74 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET 75 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 76 RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET 77 #define UNIFIED_TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 78 TCL_DATA_CMD_0_BUF_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 79 #define UNIFIED_TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 80 TCL_DATA_CMD_1_BUF_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 81 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET \ 82 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET 83 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB \ 84 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB 85 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK \ 86 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK 87 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB \ 88 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB 89 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK \ 90 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK 91 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB \ 92 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB 93 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK \ 94 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK 95 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB \ 96 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB 97 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK \ 98 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK 99 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB \ 100 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB 101 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK \ 102 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK 103 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_MASK \ 104 WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MASK 105 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_OFFSET \ 106 WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_OFFSET 107 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_LSB \ 108 WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_LSB 109 110 #include "hal_6750_tx.h" 111 #include "hal_6750_rx.h" 112 #include <hal_generic_api.h> 113 #include <hal_wbm.h> 114 115 /* 116 * hal_rx_msdu_start_nss_get_6750(): API to get the NSS 117 * Interval from rx_msdu_start 118 * 119 * @buf: pointer to the start of RX PKT TLV header 120 * Return: uint32_t(nss) 121 */ 122 static uint32_t 123 hal_rx_msdu_start_nss_get_6750(uint8_t *buf) 124 { 125 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 126 struct rx_msdu_start *msdu_start = 127 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 128 uint8_t mimo_ss_bitmap; 129 130 mimo_ss_bitmap = HAL_RX_MSDU_START_MIMO_SS_BITMAP(msdu_start); 131 132 return qdf_get_hweight8(mimo_ss_bitmap); 133 } 134 135 /** 136 * hal_rx_mon_hw_desc_get_mpdu_status_6750(): Retrieve MPDU status 137 * 138 * @ hw_desc_addr: Start address of Rx HW TLVs 139 * @ rs: Status for monitor mode 140 * 141 * Return: void 142 */ 143 static void hal_rx_mon_hw_desc_get_mpdu_status_6750(void *hw_desc_addr, 144 struct mon_rx_status *rs) 145 { 146 struct rx_msdu_start *rx_msdu_start; 147 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr; 148 uint32_t reg_value; 149 const uint32_t sgi_hw_to_cdp[] = { 150 CDP_SGI_0_8_US, 151 CDP_SGI_0_4_US, 152 CDP_SGI_1_6_US, 153 CDP_SGI_3_2_US, 154 }; 155 156 rx_msdu_start = &rx_desc->msdu_start_tlv.rx_msdu_start; 157 158 HAL_RX_GET_MSDU_AGGREGATION(rx_desc, rs); 159 160 rs->ant_signal_db = HAL_RX_GET(rx_msdu_start, 161 RX_MSDU_START_5, USER_RSSI); 162 rs->is_stbc = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, STBC); 163 164 reg_value = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, SGI); 165 rs->sgi = sgi_hw_to_cdp[reg_value]; 166 167 reg_value = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, RECEPTION_TYPE); 168 rs->beamformed = (reg_value == HAL_RX_RECEPTION_TYPE_MU_MIMO) ? 1 : 0; 169 /* TODO: rs->beamformed should be set for SU beamforming also */ 170 } 171 172 #define LINK_DESC_SIZE (NUM_OF_DWORDS_RX_MSDU_LINK << 2) 173 174 static uint32_t hal_get_link_desc_size_6750(void) 175 { 176 return LINK_DESC_SIZE; 177 } 178 179 /* 180 * hal_rx_get_tlv_6750(): API to get the tlv 181 * 182 * @rx_tlv: TLV data extracted from the rx packet 183 * Return: uint8_t 184 */ 185 static uint8_t hal_rx_get_tlv_6750(void *rx_tlv) 186 { 187 return HAL_RX_GET(rx_tlv, PHYRX_RSSI_LEGACY_0, RECEIVE_BANDWIDTH); 188 } 189 190 /** 191 * hal_rx_proc_phyrx_other_receive_info_tlv_6750() 192 * - process other receive info TLV 193 * @rx_tlv_hdr: pointer to TLV header 194 * @ppdu_info: pointer to ppdu_info 195 * 196 * Return: None 197 */ 198 static 199 void hal_rx_proc_phyrx_other_receive_info_tlv_6750(void *rx_tlv_hdr, 200 void *ppdu_info_handle) 201 { 202 uint32_t tlv_tag, tlv_len; 203 uint32_t temp_len, other_tlv_len, other_tlv_tag; 204 void *rx_tlv = (uint8_t *)rx_tlv_hdr + HAL_RX_TLV32_HDR_SIZE; 205 void *other_tlv_hdr = NULL; 206 void *other_tlv = NULL; 207 208 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv_hdr); 209 tlv_len = HAL_RX_GET_USER_TLV32_LEN(rx_tlv_hdr); 210 temp_len = 0; 211 212 other_tlv_hdr = rx_tlv + HAL_RX_TLV32_HDR_SIZE; 213 214 other_tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(other_tlv_hdr); 215 other_tlv_len = HAL_RX_GET_USER_TLV32_LEN(other_tlv_hdr); 216 temp_len += other_tlv_len; 217 other_tlv = other_tlv_hdr + HAL_RX_TLV32_HDR_SIZE; 218 219 switch (other_tlv_tag) { 220 default: 221 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR, 222 "%s unhandled TLV type: %d, TLV len:%d", 223 __func__, other_tlv_tag, other_tlv_len); 224 break; 225 } 226 } 227 228 /** 229 * hal_rx_dump_msdu_start_tlv_6750() : dump RX msdu_start TLV in structured 230 * human readable format. 231 * @ msdu_start: pointer the msdu_start TLV in pkt. 232 * @ dbg_level: log level. 233 * 234 * Return: void 235 */ 236 static void hal_rx_dump_msdu_start_tlv_6750(void *msdustart, uint8_t dbg_level) 237 { 238 struct rx_msdu_start *msdu_start = (struct rx_msdu_start *)msdustart; 239 240 hal_verbose_debug( 241 "rx_msdu_start tlv (1/2) - " 242 "rxpcu_mpdu_filter_in_category: %x " 243 "sw_frame_group_id: %x " 244 "phy_ppdu_id: %x " 245 "msdu_length: %x " 246 "ipsec_esp: %x " 247 "l3_offset: %x " 248 "ipsec_ah: %x " 249 "l4_offset: %x " 250 "msdu_number: %x " 251 "decap_format: %x " 252 "ipv4_proto: %x " 253 "ipv6_proto: %x " 254 "tcp_proto: %x " 255 "udp_proto: %x " 256 "ip_frag: %x " 257 "tcp_only_ack: %x " 258 "da_is_bcast_mcast: %x " 259 "ip4_protocol_ip6_next_header: %x " 260 "toeplitz_hash_2_or_4: %x " 261 "flow_id_toeplitz: %x " 262 "user_rssi: %x " 263 "pkt_type: %x " 264 "stbc: %x " 265 "sgi: %x " 266 "rate_mcs: %x " 267 "receive_bandwidth: %x " 268 "reception_type: %x " 269 "ppdu_start_timestamp: %u ", 270 msdu_start->rxpcu_mpdu_filter_in_category, 271 msdu_start->sw_frame_group_id, 272 msdu_start->phy_ppdu_id, 273 msdu_start->msdu_length, 274 msdu_start->ipsec_esp, 275 msdu_start->l3_offset, 276 msdu_start->ipsec_ah, 277 msdu_start->l4_offset, 278 msdu_start->msdu_number, 279 msdu_start->decap_format, 280 msdu_start->ipv4_proto, 281 msdu_start->ipv6_proto, 282 msdu_start->tcp_proto, 283 msdu_start->udp_proto, 284 msdu_start->ip_frag, 285 msdu_start->tcp_only_ack, 286 msdu_start->da_is_bcast_mcast, 287 msdu_start->ip4_protocol_ip6_next_header, 288 msdu_start->toeplitz_hash_2_or_4, 289 msdu_start->flow_id_toeplitz, 290 msdu_start->user_rssi, 291 msdu_start->pkt_type, 292 msdu_start->stbc, 293 msdu_start->sgi, 294 msdu_start->rate_mcs, 295 msdu_start->receive_bandwidth, 296 msdu_start->reception_type, 297 msdu_start->ppdu_start_timestamp); 298 299 hal_verbose_debug( 300 "rx_msdu_start tlv (2/2) - " 301 "sw_phy_meta_data: %x ", 302 msdu_start->sw_phy_meta_data); 303 } 304 305 /** 306 * hal_rx_dump_msdu_end_tlv_6750: dump RX msdu_end TLV in structured 307 * human readable format. 308 * @ msdu_end: pointer the msdu_end TLV in pkt. 309 * @ dbg_level: log level. 310 * 311 * Return: void 312 */ 313 static void hal_rx_dump_msdu_end_tlv_6750(void *msduend, 314 uint8_t dbg_level) 315 { 316 struct rx_msdu_end *msdu_end = (struct rx_msdu_end *)msduend; 317 QDF_TRACE(QDF_MODULE_ID_DP, dbg_level, 318 "rx_msdu_end tlv (1/2) - " 319 "rxpcu_mpdu_filter_in_category: %x " 320 "sw_frame_group_id: %x " 321 "phy_ppdu_id: %x " 322 "ip_hdr_chksum: %x " 323 "tcp_udp_chksum: %x " 324 "key_id_octet: %x " 325 "cce_super_rule: %x " 326 "cce_classify_not_done_truncat: %x " 327 "cce_classify_not_done_cce_dis: %x " 328 "reported_mpdu_length: %x " 329 "first_msdu: %x " 330 "last_msdu: %x " 331 "sa_idx_timeout: %x " 332 "da_idx_timeout: %x " 333 "msdu_limit_error: %x " 334 "flow_idx_timeout: %x " 335 "flow_idx_invalid: %x " 336 "wifi_parser_error: %x " 337 "amsdu_parser_error: %x", 338 msdu_end->rxpcu_mpdu_filter_in_category, 339 msdu_end->sw_frame_group_id, 340 msdu_end->phy_ppdu_id, 341 msdu_end->ip_hdr_chksum, 342 msdu_end->tcp_udp_chksum, 343 msdu_end->key_id_octet, 344 msdu_end->cce_super_rule, 345 msdu_end->cce_classify_not_done_truncate, 346 msdu_end->cce_classify_not_done_cce_dis, 347 msdu_end->reported_mpdu_length, 348 msdu_end->first_msdu, 349 msdu_end->last_msdu, 350 msdu_end->sa_idx_timeout, 351 msdu_end->da_idx_timeout, 352 msdu_end->msdu_limit_error, 353 msdu_end->flow_idx_timeout, 354 msdu_end->flow_idx_invalid, 355 msdu_end->wifi_parser_error, 356 msdu_end->amsdu_parser_error); 357 QDF_TRACE(QDF_MODULE_ID_DP, dbg_level, 358 "rx_msdu_end tlv (2/2)- " 359 "sa_is_valid: %x " 360 "da_is_valid: %x " 361 "da_is_mcbc: %x " 362 "l3_header_padding: %x " 363 "ipv6_options_crc: %x " 364 "tcp_seq_number: %x " 365 "tcp_ack_number: %x " 366 "tcp_flag: %x " 367 "lro_eligible: %x " 368 "window_size: %x " 369 "da_offset: %x " 370 "sa_offset: %x " 371 "da_offset_valid: %x " 372 "sa_offset_valid: %x " 373 "rule_indication_31_0: %x " 374 "rule_indication_63_32: %x " 375 "sa_idx: %x " 376 "da_idx: %x " 377 "msdu_drop: %x " 378 "reo_destination_indication: %x " 379 "flow_idx: %x " 380 "fse_metadata: %x " 381 "cce_metadata: %x " 382 "sa_sw_peer_id: %x ", 383 msdu_end->sa_is_valid, 384 msdu_end->da_is_valid, 385 msdu_end->da_is_mcbc, 386 msdu_end->l3_header_padding, 387 msdu_end->ipv6_options_crc, 388 msdu_end->tcp_seq_number, 389 msdu_end->tcp_ack_number, 390 msdu_end->tcp_flag, 391 msdu_end->lro_eligible, 392 msdu_end->window_size, 393 msdu_end->da_offset, 394 msdu_end->sa_offset, 395 msdu_end->da_offset_valid, 396 msdu_end->sa_offset_valid, 397 msdu_end->rule_indication_31_0, 398 msdu_end->rule_indication_63_32, 399 msdu_end->sa_idx, 400 msdu_end->da_idx_or_sw_peer_id, 401 msdu_end->msdu_drop, 402 msdu_end->reo_destination_indication, 403 msdu_end->flow_idx, 404 msdu_end->fse_metadata, 405 msdu_end->cce_metadata, 406 msdu_end->sa_sw_peer_id); 407 } 408 409 /* 410 * Get tid from RX_MPDU_START 411 */ 412 #define HAL_RX_MPDU_INFO_TID_GET(_rx_mpdu_info) \ 413 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_info), \ 414 RX_MPDU_INFO_7_TID_OFFSET)), \ 415 RX_MPDU_INFO_7_TID_MASK, \ 416 RX_MPDU_INFO_7_TID_LSB)) 417 418 static uint32_t hal_rx_mpdu_start_tid_get_6750(uint8_t *buf) 419 { 420 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 421 struct rx_mpdu_start *mpdu_start = 422 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 423 uint32_t tid; 424 425 tid = HAL_RX_MPDU_INFO_TID_GET(&mpdu_start->rx_mpdu_info_details); 426 427 return tid; 428 } 429 430 #define HAL_RX_MSDU_START_RECEPTION_TYPE_GET(_rx_msdu_start) \ 431 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start), \ 432 RX_MSDU_START_5_RECEPTION_TYPE_OFFSET)), \ 433 RX_MSDU_START_5_RECEPTION_TYPE_MASK, \ 434 RX_MSDU_START_5_RECEPTION_TYPE_LSB)) 435 436 /* 437 * hal_rx_msdu_start_reception_type_get(): API to get the reception type 438 * Interval from rx_msdu_start 439 * 440 * @buf: pointer to the start of RX PKT TLV header 441 * Return: uint32_t(reception_type) 442 */ 443 static 444 uint32_t hal_rx_msdu_start_reception_type_get_6750(uint8_t *buf) 445 { 446 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 447 struct rx_msdu_start *msdu_start = 448 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 449 uint32_t reception_type; 450 451 reception_type = HAL_RX_MSDU_START_RECEPTION_TYPE_GET(msdu_start); 452 453 return reception_type; 454 } 455 456 /** 457 * hal_rx_msdu_end_da_idx_get_6750: API to get da_idx 458 * from rx_msdu_end TLV 459 * 460 * @ buf: pointer to the start of RX PKT TLV headers 461 * Return: da index 462 */ 463 static uint16_t hal_rx_msdu_end_da_idx_get_6750(uint8_t *buf) 464 { 465 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 466 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 467 uint16_t da_idx; 468 469 da_idx = HAL_RX_MSDU_END_DA_IDX_GET(msdu_end); 470 471 return da_idx; 472 } 473 474 /** 475 * hal_rx_get_rx_fragment_number_6750(): Function to retrieve rx fragment number 476 * 477 * @nbuf: Network buffer 478 * Returns: rx fragment number 479 */ 480 static 481 uint8_t hal_rx_get_rx_fragment_number_6750(uint8_t *buf) 482 { 483 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 484 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 485 486 /* Return first 4 bits as fragment number */ 487 return (HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info) & 488 DOT11_SEQ_FRAG_MASK); 489 } 490 491 /** 492 * hal_rx_msdu_end_da_is_mcbc_get_6750(): API to check if pkt is MCBC 493 * from rx_msdu_end TLV 494 * 495 * @ buf: pointer to the start of RX PKT TLV headers 496 * Return: da_is_mcbc 497 */ 498 static uint8_t 499 hal_rx_msdu_end_da_is_mcbc_get_6750(uint8_t *buf) 500 { 501 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 502 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 503 504 return HAL_RX_MSDU_END_DA_IS_MCBC_GET(msdu_end); 505 } 506 507 /** 508 * hal_rx_msdu_end_sa_is_valid_get_6750(): API to get_6750 the 509 * sa_is_valid bit from rx_msdu_end TLV 510 * 511 * @ buf: pointer to the start of RX PKT TLV headers 512 * Return: sa_is_valid bit 513 */ 514 static uint8_t 515 hal_rx_msdu_end_sa_is_valid_get_6750(uint8_t *buf) 516 { 517 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 518 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 519 uint8_t sa_is_valid; 520 521 sa_is_valid = HAL_RX_MSDU_END_SA_IS_VALID_GET(msdu_end); 522 523 return sa_is_valid; 524 } 525 526 /** 527 * hal_rx_msdu_end_sa_idx_get_6750(): API to get_6750 the 528 * sa_idx from rx_msdu_end TLV 529 * 530 * @ buf: pointer to the start of RX PKT TLV headers 531 * Return: sa_idx (SA AST index) 532 */ 533 static 534 uint16_t hal_rx_msdu_end_sa_idx_get_6750(uint8_t *buf) 535 { 536 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 537 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 538 uint16_t sa_idx; 539 540 sa_idx = HAL_RX_MSDU_END_SA_IDX_GET(msdu_end); 541 542 return sa_idx; 543 } 544 545 /** 546 * hal_rx_desc_is_first_msdu_6750() - Check if first msdu 547 * 548 * @hal_soc_hdl: hal_soc handle 549 * @hw_desc_addr: hardware descriptor address 550 * 551 * Return: 0 - success/ non-zero failure 552 */ 553 static uint32_t hal_rx_desc_is_first_msdu_6750(void *hw_desc_addr) 554 { 555 struct rx_pkt_tlvs *rx_tlvs = (struct rx_pkt_tlvs *)hw_desc_addr; 556 struct rx_msdu_end *msdu_end = &rx_tlvs->msdu_end_tlv.rx_msdu_end; 557 558 return HAL_RX_GET(msdu_end, RX_MSDU_END_10, FIRST_MSDU); 559 } 560 561 /** 562 * hal_rx_msdu_end_l3_hdr_padding_get_6750(): API to get_6750 the 563 * l3_header padding from rx_msdu_end TLV 564 * 565 * @ buf: pointer to the start of RX PKT TLV headers 566 * Return: number of l3 header padding bytes 567 */ 568 static uint32_t hal_rx_msdu_end_l3_hdr_padding_get_6750(uint8_t *buf) 569 { 570 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 571 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 572 uint32_t l3_header_padding; 573 574 l3_header_padding = HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(msdu_end); 575 576 return l3_header_padding; 577 } 578 579 /* 580 * @ hal_rx_encryption_info_valid_6750: Returns encryption type. 581 * 582 * @ buf: rx_tlv_hdr of the received packet 583 * @ Return: encryption type 584 */ 585 static uint32_t hal_rx_encryption_info_valid_6750(uint8_t *buf) 586 { 587 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 588 struct rx_mpdu_start *mpdu_start = 589 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 590 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 591 uint32_t encryption_info = HAL_RX_MPDU_ENCRYPTION_INFO_VALID(mpdu_info); 592 593 return encryption_info; 594 } 595 596 /* 597 * @ hal_rx_print_pn_6750: Prints the PN of rx packet. 598 * 599 * @ buf: rx_tlv_hdr of the received packet 600 * @ Return: void 601 */ 602 static void hal_rx_print_pn_6750(uint8_t *buf) 603 { 604 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 605 struct rx_mpdu_start *mpdu_start = 606 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 607 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 608 609 uint32_t pn_31_0 = HAL_RX_MPDU_PN_31_0_GET(mpdu_info); 610 uint32_t pn_63_32 = HAL_RX_MPDU_PN_63_32_GET(mpdu_info); 611 uint32_t pn_95_64 = HAL_RX_MPDU_PN_95_64_GET(mpdu_info); 612 uint32_t pn_127_96 = HAL_RX_MPDU_PN_127_96_GET(mpdu_info); 613 614 hal_debug("PN number pn_127_96 0x%x pn_95_64 0x%x pn_63_32 0x%x pn_31_0 0x%x ", 615 pn_127_96, pn_95_64, pn_63_32, pn_31_0); 616 } 617 618 /** 619 * hal_rx_msdu_end_first_msdu_get_6750: API to get first msdu status 620 * from rx_msdu_end TLV 621 * 622 * @ buf: pointer to the start of RX PKT TLV headers 623 * Return: first_msdu 624 */ 625 static uint8_t hal_rx_msdu_end_first_msdu_get_6750(uint8_t *buf) 626 { 627 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 628 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 629 uint8_t first_msdu; 630 631 first_msdu = HAL_RX_MSDU_END_FIRST_MSDU_GET(msdu_end); 632 633 return first_msdu; 634 } 635 636 /** 637 * hal_rx_msdu_end_da_is_valid_get_6750: API to check if da is valid 638 * from rx_msdu_end TLV 639 * 640 * @ buf: pointer to the start of RX PKT TLV headers 641 * Return: da_is_valid 642 */ 643 static uint8_t hal_rx_msdu_end_da_is_valid_get_6750(uint8_t *buf) 644 { 645 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 646 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 647 uint8_t da_is_valid; 648 649 da_is_valid = HAL_RX_MSDU_END_DA_IS_VALID_GET(msdu_end); 650 651 return da_is_valid; 652 } 653 654 /** 655 * hal_rx_msdu_end_last_msdu_get_6750: API to get last msdu status 656 * from rx_msdu_end TLV 657 * 658 * @ buf: pointer to the start of RX PKT TLV headers 659 * Return: last_msdu 660 */ 661 static uint8_t hal_rx_msdu_end_last_msdu_get_6750(uint8_t *buf) 662 { 663 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 664 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 665 uint8_t last_msdu; 666 667 last_msdu = HAL_RX_MSDU_END_LAST_MSDU_GET(msdu_end); 668 669 return last_msdu; 670 } 671 672 /* 673 * hal_rx_get_mpdu_mac_ad4_valid_6750(): Retrieves if mpdu 4th addr is valid 674 * 675 * @nbuf: Network buffer 676 * Returns: value of mpdu 4th address valid field 677 */ 678 static bool hal_rx_get_mpdu_mac_ad4_valid_6750(uint8_t *buf) 679 { 680 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 681 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 682 bool ad4_valid = 0; 683 684 ad4_valid = HAL_RX_MPDU_GET_MAC_AD4_VALID(rx_mpdu_info); 685 686 return ad4_valid; 687 } 688 689 /** 690 * hal_rx_mpdu_start_sw_peer_id_get_6750: Retrieve sw peer_id 691 * @buf: network buffer 692 * 693 * Return: sw peer_id 694 */ 695 static uint32_t hal_rx_mpdu_start_sw_peer_id_get_6750(uint8_t *buf) 696 { 697 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 698 struct rx_mpdu_start *mpdu_start = 699 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 700 701 return HAL_RX_MPDU_INFO_SW_PEER_ID_GET( 702 &mpdu_start->rx_mpdu_info_details); 703 } 704 705 /** 706 * hal_rx_mpdu_get_to_ds_6750(): API to get the tods info 707 * from rx_mpdu_start 708 * 709 * @buf: pointer to the start of RX PKT TLV header 710 * Return: uint32_t(to_ds) 711 */ 712 static uint32_t hal_rx_mpdu_get_to_ds_6750(uint8_t *buf) 713 { 714 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 715 struct rx_mpdu_start *mpdu_start = 716 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 717 718 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 719 720 return HAL_RX_MPDU_GET_TODS(mpdu_info); 721 } 722 723 /* 724 * hal_rx_mpdu_get_fr_ds_6750(): API to get the from ds info 725 * from rx_mpdu_start 726 * 727 * @buf: pointer to the start of RX PKT TLV header 728 * Return: uint32_t(fr_ds) 729 */ 730 static uint32_t hal_rx_mpdu_get_fr_ds_6750(uint8_t *buf) 731 { 732 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 733 struct rx_mpdu_start *mpdu_start = 734 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 735 736 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 737 738 return HAL_RX_MPDU_GET_FROMDS(mpdu_info); 739 } 740 741 /* 742 * hal_rx_get_mpdu_frame_control_valid_6750(): Retrieves mpdu 743 * frame control valid 744 * 745 * @nbuf: Network buffer 746 * Returns: value of frame control valid field 747 */ 748 static uint8_t hal_rx_get_mpdu_frame_control_valid_6750(uint8_t *buf) 749 { 750 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 751 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 752 753 return HAL_RX_MPDU_GET_FRAME_CONTROL_VALID(rx_mpdu_info); 754 } 755 756 /* 757 * hal_rx_mpdu_get_addr1_6750(): API to check get address1 of the mpdu 758 * 759 * @buf: pointer to the start of RX PKT TLV headera 760 * @mac_addr: pointer to mac address 761 * Return: success/failure 762 */ 763 static QDF_STATUS hal_rx_mpdu_get_addr1_6750(uint8_t *buf, uint8_t *mac_addr) 764 { 765 struct __attribute__((__packed__)) hal_addr1 { 766 uint32_t ad1_31_0; 767 uint16_t ad1_47_32; 768 }; 769 770 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 771 struct rx_mpdu_start *mpdu_start = 772 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 773 774 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 775 struct hal_addr1 *addr = (struct hal_addr1 *)mac_addr; 776 uint32_t mac_addr_ad1_valid; 777 778 mac_addr_ad1_valid = HAL_RX_MPDU_MAC_ADDR_AD1_VALID_GET(mpdu_info); 779 780 if (mac_addr_ad1_valid) { 781 addr->ad1_31_0 = HAL_RX_MPDU_AD1_31_0_GET(mpdu_info); 782 addr->ad1_47_32 = HAL_RX_MPDU_AD1_47_32_GET(mpdu_info); 783 return QDF_STATUS_SUCCESS; 784 } 785 786 return QDF_STATUS_E_FAILURE; 787 } 788 789 /* 790 * hal_rx_mpdu_get_addr2_6750(): API to check get address2 of the mpdu 791 * in the packet 792 * 793 * @buf: pointer to the start of RX PKT TLV header 794 * @mac_addr: pointer to mac address 795 * Return: success/failure 796 */ 797 static QDF_STATUS hal_rx_mpdu_get_addr2_6750(uint8_t *buf, 798 uint8_t *mac_addr) 799 { 800 struct __attribute__((__packed__)) hal_addr2 { 801 uint16_t ad2_15_0; 802 uint32_t ad2_47_16; 803 }; 804 805 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 806 struct rx_mpdu_start *mpdu_start = 807 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 808 809 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 810 struct hal_addr2 *addr = (struct hal_addr2 *)mac_addr; 811 uint32_t mac_addr_ad2_valid; 812 813 mac_addr_ad2_valid = HAL_RX_MPDU_MAC_ADDR_AD2_VALID_GET(mpdu_info); 814 815 if (mac_addr_ad2_valid) { 816 addr->ad2_15_0 = HAL_RX_MPDU_AD2_15_0_GET(mpdu_info); 817 addr->ad2_47_16 = HAL_RX_MPDU_AD2_47_16_GET(mpdu_info); 818 return QDF_STATUS_SUCCESS; 819 } 820 821 return QDF_STATUS_E_FAILURE; 822 } 823 824 /* 825 * hal_rx_mpdu_get_addr3_6750(): API to get address3 of the mpdu 826 * in the packet 827 * 828 * @buf: pointer to the start of RX PKT TLV header 829 * @mac_addr: pointer to mac address 830 * Return: success/failure 831 */ 832 static QDF_STATUS hal_rx_mpdu_get_addr3_6750(uint8_t *buf, uint8_t *mac_addr) 833 { 834 struct __attribute__((__packed__)) hal_addr3 { 835 uint32_t ad3_31_0; 836 uint16_t ad3_47_32; 837 }; 838 839 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 840 struct rx_mpdu_start *mpdu_start = 841 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 842 843 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 844 struct hal_addr3 *addr = (struct hal_addr3 *)mac_addr; 845 uint32_t mac_addr_ad3_valid; 846 847 mac_addr_ad3_valid = HAL_RX_MPDU_MAC_ADDR_AD3_VALID_GET(mpdu_info); 848 849 if (mac_addr_ad3_valid) { 850 addr->ad3_31_0 = HAL_RX_MPDU_AD3_31_0_GET(mpdu_info); 851 addr->ad3_47_32 = HAL_RX_MPDU_AD3_47_32_GET(mpdu_info); 852 return QDF_STATUS_SUCCESS; 853 } 854 855 return QDF_STATUS_E_FAILURE; 856 } 857 858 /* 859 * hal_rx_mpdu_get_addr4_6750(): API to get address4 of the mpdu 860 * in the packet 861 * 862 * @buf: pointer to the start of RX PKT TLV header 863 * @mac_addr: pointer to mac address 864 * Return: success/failure 865 */ 866 static QDF_STATUS hal_rx_mpdu_get_addr4_6750(uint8_t *buf, uint8_t *mac_addr) 867 { 868 struct __attribute__((__packed__)) hal_addr4 { 869 uint32_t ad4_31_0; 870 uint16_t ad4_47_32; 871 }; 872 873 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 874 struct rx_mpdu_start *mpdu_start = 875 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 876 877 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 878 struct hal_addr4 *addr = (struct hal_addr4 *)mac_addr; 879 uint32_t mac_addr_ad4_valid; 880 881 mac_addr_ad4_valid = HAL_RX_MPDU_MAC_ADDR_AD4_VALID_GET(mpdu_info); 882 883 if (mac_addr_ad4_valid) { 884 addr->ad4_31_0 = HAL_RX_MPDU_AD4_31_0_GET(mpdu_info); 885 addr->ad4_47_32 = HAL_RX_MPDU_AD4_47_32_GET(mpdu_info); 886 return QDF_STATUS_SUCCESS; 887 } 888 889 return QDF_STATUS_E_FAILURE; 890 } 891 892 /* 893 * hal_rx_get_mpdu_sequence_control_valid_6750(): Get mpdu 894 * sequence control valid 895 * 896 * @nbuf: Network buffer 897 * Returns: value of sequence control valid field 898 */ 899 static uint8_t hal_rx_get_mpdu_sequence_control_valid_6750(uint8_t *buf) 900 { 901 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 902 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 903 904 return HAL_RX_MPDU_GET_SEQUENCE_CONTROL_VALID(rx_mpdu_info); 905 } 906 907 /** 908 * hal_rx_is_unicast_6750: check packet is unicast frame or not. 909 * 910 * @ buf: pointer to rx pkt TLV. 911 * 912 * Return: true on unicast. 913 */ 914 static bool hal_rx_is_unicast_6750(uint8_t *buf) 915 { 916 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 917 struct rx_mpdu_start *mpdu_start = 918 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 919 uint32_t grp_id; 920 uint8_t *rx_mpdu_info = (uint8_t *)&mpdu_start->rx_mpdu_info_details; 921 922 grp_id = (_HAL_MS((*_OFFSET_TO_WORD_PTR((rx_mpdu_info), 923 RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_OFFSET)), 924 RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_MASK, 925 RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_LSB)); 926 927 return (HAL_MPDU_SW_FRAME_GROUP_UNICAST_DATA == grp_id) ? true : false; 928 } 929 930 /** 931 * hal_rx_tid_get_6750: get tid based on qos control valid. 932 * @hal_soc_hdl: hal_soc handle 933 * @ buf: pointer to rx pkt TLV. 934 * 935 * Return: tid 936 */ 937 static uint32_t hal_rx_tid_get_6750(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 938 { 939 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 940 struct rx_mpdu_start *mpdu_start = 941 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 942 uint8_t *rx_mpdu_info = (uint8_t *)&mpdu_start->rx_mpdu_info_details; 943 uint8_t qos_control_valid = 944 (_HAL_MS((*_OFFSET_TO_WORD_PTR((rx_mpdu_info), 945 RX_MPDU_INFO_11_MPDU_QOS_CONTROL_VALID_OFFSET)), 946 RX_MPDU_INFO_11_MPDU_QOS_CONTROL_VALID_MASK, 947 RX_MPDU_INFO_11_MPDU_QOS_CONTROL_VALID_LSB)); 948 949 if (qos_control_valid) 950 return hal_rx_mpdu_start_tid_get_6750(buf); 951 952 return HAL_RX_NON_QOS_TID; 953 } 954 955 /** 956 * hal_rx_hw_desc_get_ppduid_get_6750(): retrieve ppdu id 957 * @hw_desc_addr: hw addr 958 * 959 * Return: ppdu id 960 */ 961 static uint32_t hal_rx_hw_desc_get_ppduid_get_6750(void *hw_desc_addr) 962 { 963 struct rx_mpdu_info *rx_mpdu_info; 964 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr; 965 966 rx_mpdu_info = 967 &rx_desc->mpdu_start_tlv.rx_mpdu_start.rx_mpdu_info_details; 968 969 return HAL_RX_GET(rx_mpdu_info, RX_MPDU_INFO_9, PHY_PPDU_ID); 970 } 971 972 /** 973 * hal_reo_status_get_header_6750 - Process reo desc info 974 * @d - Pointer to reo descriptior 975 * @b - tlv type info 976 * @h1 - Pointer to hal_reo_status_header where info to be stored 977 * 978 * Return - none. 979 * 980 */ 981 static void hal_reo_status_get_header_6750(uint32_t *d, int b, void *h1) 982 { 983 uint32_t val1 = 0; 984 struct hal_reo_status_header *h = 985 (struct hal_reo_status_header *)h1; 986 987 switch (b) { 988 case HAL_REO_QUEUE_STATS_STATUS_TLV: 989 val1 = d[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_0, 990 STATUS_HEADER_REO_STATUS_NUMBER)]; 991 break; 992 case HAL_REO_FLUSH_QUEUE_STATUS_TLV: 993 val1 = d[HAL_OFFSET_DW(REO_FLUSH_QUEUE_STATUS_0, 994 STATUS_HEADER_REO_STATUS_NUMBER)]; 995 break; 996 case HAL_REO_FLUSH_CACHE_STATUS_TLV: 997 val1 = d[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_0, 998 STATUS_HEADER_REO_STATUS_NUMBER)]; 999 break; 1000 case HAL_REO_UNBLK_CACHE_STATUS_TLV: 1001 val1 = d[HAL_OFFSET_DW(REO_UNBLOCK_CACHE_STATUS_0, 1002 STATUS_HEADER_REO_STATUS_NUMBER)]; 1003 break; 1004 case HAL_REO_TIMOUT_LIST_STATUS_TLV: 1005 val1 = d[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_0, 1006 STATUS_HEADER_REO_STATUS_NUMBER)]; 1007 break; 1008 case HAL_REO_DESC_THRES_STATUS_TLV: 1009 val1 = 1010 d[HAL_OFFSET_DW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0, 1011 STATUS_HEADER_REO_STATUS_NUMBER)]; 1012 break; 1013 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: 1014 val1 = d[HAL_OFFSET_DW(REO_UPDATE_RX_REO_QUEUE_STATUS_0, 1015 STATUS_HEADER_REO_STATUS_NUMBER)]; 1016 break; 1017 default: 1018 qdf_nofl_err("ERROR: Unknown tlv\n"); 1019 break; 1020 } 1021 h->cmd_num = 1022 HAL_GET_FIELD( 1023 UNIFORM_REO_STATUS_HEADER_0, REO_STATUS_NUMBER, 1024 val1); 1025 h->exec_time = 1026 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_0, 1027 CMD_EXECUTION_TIME, val1); 1028 h->status = 1029 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_0, 1030 REO_CMD_EXECUTION_STATUS, val1); 1031 switch (b) { 1032 case HAL_REO_QUEUE_STATS_STATUS_TLV: 1033 val1 = d[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_1, 1034 STATUS_HEADER_TIMESTAMP)]; 1035 break; 1036 case HAL_REO_FLUSH_QUEUE_STATUS_TLV: 1037 val1 = d[HAL_OFFSET_DW(REO_FLUSH_QUEUE_STATUS_1, 1038 STATUS_HEADER_TIMESTAMP)]; 1039 break; 1040 case HAL_REO_FLUSH_CACHE_STATUS_TLV: 1041 val1 = d[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_1, 1042 STATUS_HEADER_TIMESTAMP)]; 1043 break; 1044 case HAL_REO_UNBLK_CACHE_STATUS_TLV: 1045 val1 = d[HAL_OFFSET_DW(REO_UNBLOCK_CACHE_STATUS_1, 1046 STATUS_HEADER_TIMESTAMP)]; 1047 break; 1048 case HAL_REO_TIMOUT_LIST_STATUS_TLV: 1049 val1 = d[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_1, 1050 STATUS_HEADER_TIMESTAMP)]; 1051 break; 1052 case HAL_REO_DESC_THRES_STATUS_TLV: 1053 val1 = 1054 d[HAL_OFFSET_DW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_1, 1055 STATUS_HEADER_TIMESTAMP)]; 1056 break; 1057 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: 1058 val1 = d[HAL_OFFSET_DW(REO_UPDATE_RX_REO_QUEUE_STATUS_1, 1059 STATUS_HEADER_TIMESTAMP)]; 1060 break; 1061 default: 1062 qdf_nofl_err("ERROR: Unknown tlv\n"); 1063 break; 1064 } 1065 h->tstamp = 1066 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_1, TIMESTAMP, val1); 1067 } 1068 1069 /** 1070 * hal_tx_desc_set_mesh_en_6750 - Set mesh_enable flag in Tx descriptor 1071 * @desc: Handle to Tx Descriptor 1072 * @en: For raw WiFi frames, this indicates transmission to a mesh STA, 1073 * enabling the interpretation of the 'Mesh Control Present' bit 1074 * (bit 8) of QoS Control (otherwise this bit is ignored), 1075 * For native WiFi frames, this indicates that a 'Mesh Control' field 1076 * is present between the header and the LLC. 1077 * 1078 * Return: void 1079 */ 1080 static inline 1081 void hal_tx_desc_set_mesh_en_6750(void *desc, uint8_t en) 1082 { 1083 HAL_SET_FLD(desc, TCL_DATA_CMD_5, MESH_ENABLE) |= 1084 HAL_TX_SM(TCL_DATA_CMD_5, MESH_ENABLE, en); 1085 } 1086 1087 static 1088 void *hal_rx_msdu0_buffer_addr_lsb_6750(void *link_desc_va) 1089 { 1090 return (void *)HAL_RX_MSDU0_BUFFER_ADDR_LSB(link_desc_va); 1091 } 1092 1093 static 1094 void *hal_rx_msdu_desc_info_ptr_get_6750(void *msdu0) 1095 { 1096 return (void *)HAL_RX_MSDU_DESC_INFO_PTR_GET(msdu0); 1097 } 1098 1099 static 1100 void *hal_ent_mpdu_desc_info_6750(void *ent_ring_desc) 1101 { 1102 return (void *)HAL_ENT_MPDU_DESC_INFO(ent_ring_desc); 1103 } 1104 1105 static 1106 void *hal_dst_mpdu_desc_info_6750(void *dst_ring_desc) 1107 { 1108 return (void *)HAL_DST_MPDU_DESC_INFO(dst_ring_desc); 1109 } 1110 1111 static 1112 uint8_t hal_rx_get_fc_valid_6750(uint8_t *buf) 1113 { 1114 return HAL_RX_GET_FC_VALID(buf); 1115 } 1116 1117 static uint8_t hal_rx_get_to_ds_flag_6750(uint8_t *buf) 1118 { 1119 return HAL_RX_GET_TO_DS_FLAG(buf); 1120 } 1121 1122 static uint8_t hal_rx_get_mac_addr2_valid_6750(uint8_t *buf) 1123 { 1124 return HAL_RX_GET_MAC_ADDR2_VALID(buf); 1125 } 1126 1127 static uint8_t hal_rx_get_filter_category_6750(uint8_t *buf) 1128 { 1129 return HAL_RX_GET_FILTER_CATEGORY(buf); 1130 } 1131 1132 static uint32_t 1133 hal_rx_get_ppdu_id_6750(uint8_t *buf) 1134 { 1135 return HAL_RX_GET_PPDU_ID(buf); 1136 } 1137 1138 /** 1139 * hal_reo_config_6750(): Set reo config parameters 1140 * @soc: hal soc handle 1141 * @reg_val: value to be set 1142 * @reo_params: reo parameters 1143 * 1144 * Return: void 1145 */ 1146 static 1147 void hal_reo_config_6750(struct hal_soc *soc, 1148 uint32_t reg_val, 1149 struct hal_reo_params *reo_params) 1150 { 1151 HAL_REO_R0_CONFIG(soc, reg_val, reo_params); 1152 } 1153 1154 /** 1155 * hal_rx_msdu_desc_info_get_ptr_6750() - Get msdu desc info ptr 1156 * @msdu_details_ptr - Pointer to msdu_details_ptr 1157 * 1158 * Return - Pointer to rx_msdu_desc_info structure. 1159 * 1160 */ 1161 static void *hal_rx_msdu_desc_info_get_ptr_6750(void *msdu_details_ptr) 1162 { 1163 return HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr); 1164 } 1165 1166 /** 1167 * hal_rx_link_desc_msdu0_ptr_6750 - Get pointer to rx_msdu details 1168 * @link_desc - Pointer to link desc 1169 * 1170 * Return - Pointer to rx_msdu_details structure 1171 * 1172 */ 1173 static void *hal_rx_link_desc_msdu0_ptr_6750(void *link_desc) 1174 { 1175 return HAL_RX_LINK_DESC_MSDU0_PTR(link_desc); 1176 } 1177 1178 /** 1179 * hal_rx_msdu_flow_idx_get_6750: API to get flow index 1180 * from rx_msdu_end TLV 1181 * @buf: pointer to the start of RX PKT TLV headers 1182 * 1183 * Return: flow index value from MSDU END TLV 1184 */ 1185 static inline uint32_t hal_rx_msdu_flow_idx_get_6750(uint8_t *buf) 1186 { 1187 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1188 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1189 1190 return HAL_RX_MSDU_END_FLOW_IDX_GET(msdu_end); 1191 } 1192 1193 /** 1194 * hal_rx_msdu_flow_idx_invalid_6750: API to get flow index invalid 1195 * from rx_msdu_end TLV 1196 * @buf: pointer to the start of RX PKT TLV headers 1197 * 1198 * Return: flow index invalid value from MSDU END TLV 1199 */ 1200 static bool hal_rx_msdu_flow_idx_invalid_6750(uint8_t *buf) 1201 { 1202 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1203 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1204 1205 return HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(msdu_end); 1206 } 1207 1208 /** 1209 * hal_rx_msdu_flow_idx_timeout_6750: API to get flow index timeout 1210 * from rx_msdu_end TLV 1211 * @buf: pointer to the start of RX PKT TLV headers 1212 * 1213 * Return: flow index timeout value from MSDU END TLV 1214 */ 1215 static bool hal_rx_msdu_flow_idx_timeout_6750(uint8_t *buf) 1216 { 1217 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1218 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1219 1220 return HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(msdu_end); 1221 } 1222 1223 /** 1224 * hal_rx_msdu_fse_metadata_get_6750: API to get FSE metadata 1225 * from rx_msdu_end TLV 1226 * @buf: pointer to the start of RX PKT TLV headers 1227 * 1228 * Return: fse metadata value from MSDU END TLV 1229 */ 1230 static uint32_t hal_rx_msdu_fse_metadata_get_6750(uint8_t *buf) 1231 { 1232 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1233 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1234 1235 return HAL_RX_MSDU_END_FSE_METADATA_GET(msdu_end); 1236 } 1237 1238 /** 1239 * hal_rx_msdu_cce_metadata_get_6750: API to get CCE metadata 1240 * from rx_msdu_end TLV 1241 * @buf: pointer to the start of RX PKT TLV headers 1242 * 1243 * Return: cce_metadata 1244 */ 1245 static uint16_t 1246 hal_rx_msdu_cce_metadata_get_6750(uint8_t *buf) 1247 { 1248 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1249 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1250 1251 return HAL_RX_MSDU_END_CCE_METADATA_GET(msdu_end); 1252 } 1253 1254 /** 1255 * hal_rx_tlv_get_tcp_chksum_6750() - API to get tcp checksum 1256 * @buf: rx_tlv_hdr 1257 * 1258 * Return: tcp checksum 1259 */ 1260 static uint16_t 1261 hal_rx_tlv_get_tcp_chksum_6750(uint8_t *buf) 1262 { 1263 return HAL_RX_TLV_GET_TCP_CHKSUM(buf); 1264 } 1265 1266 /** 1267 * hal_rx_get_rx_sequence_6750(): Function to retrieve rx sequence number 1268 * 1269 * @nbuf: Network buffer 1270 * Returns: rx sequence number 1271 */ 1272 static 1273 uint16_t hal_rx_get_rx_sequence_6750(uint8_t *buf) 1274 { 1275 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 1276 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 1277 1278 return HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info); 1279 } 1280 1281 /** 1282 * hal_get_window_address_6750(): Function to get hp/tp address 1283 * @hal_soc: Pointer to hal_soc 1284 * @addr: address offset of register 1285 * 1286 * Return: modified address offset of register 1287 */ 1288 static inline qdf_iomem_t hal_get_window_address_6750(struct hal_soc *hal_soc, 1289 qdf_iomem_t addr) 1290 { 1291 return addr; 1292 } 1293 1294 struct hal_hw_txrx_ops qca6750_hal_hw_txrx_ops = { 1295 /* init and setup */ 1296 hal_srng_dst_hw_init_generic, 1297 hal_srng_src_hw_init_generic, 1298 hal_get_hw_hptp_generic, 1299 hal_reo_setup_generic, 1300 hal_setup_link_idle_list_generic, 1301 hal_get_window_address_6750, 1302 1303 /* tx */ 1304 hal_tx_desc_set_dscp_tid_table_id_6750, 1305 hal_tx_set_dscp_tid_map_6750, 1306 hal_tx_update_dscp_tid_6750, 1307 hal_tx_desc_set_lmac_id_6750, 1308 hal_tx_desc_set_buf_addr_generic, 1309 hal_tx_desc_set_search_type_generic, 1310 hal_tx_desc_set_search_index_generic, 1311 hal_tx_desc_set_cache_set_num_generic, 1312 hal_tx_comp_get_status_generic, 1313 hal_tx_comp_get_release_reason_generic, 1314 hal_get_wbm_internal_error_generic, 1315 hal_tx_desc_set_mesh_en_6750, 1316 1317 /* rx */ 1318 hal_rx_msdu_start_nss_get_6750, 1319 hal_rx_mon_hw_desc_get_mpdu_status_6750, 1320 hal_rx_get_tlv_6750, 1321 hal_rx_proc_phyrx_other_receive_info_tlv_6750, 1322 hal_rx_dump_msdu_start_tlv_6750, 1323 hal_rx_dump_msdu_end_tlv_6750, 1324 hal_get_link_desc_size_6750, 1325 hal_rx_mpdu_start_tid_get_6750, 1326 hal_rx_msdu_start_reception_type_get_6750, 1327 hal_rx_msdu_end_da_idx_get_6750, 1328 hal_rx_msdu_desc_info_get_ptr_6750, 1329 hal_rx_link_desc_msdu0_ptr_6750, 1330 hal_reo_status_get_header_6750, 1331 hal_rx_status_get_tlv_info_generic, 1332 hal_rx_wbm_err_info_get_generic, 1333 hal_rx_dump_mpdu_start_tlv_generic, 1334 1335 hal_tx_set_pcp_tid_map_generic, 1336 hal_tx_update_pcp_tid_generic, 1337 hal_tx_update_tidmap_prty_generic, 1338 hal_rx_get_rx_fragment_number_6750, 1339 hal_rx_msdu_end_da_is_mcbc_get_6750, 1340 hal_rx_msdu_end_sa_is_valid_get_6750, 1341 hal_rx_msdu_end_sa_idx_get_6750, 1342 hal_rx_desc_is_first_msdu_6750, 1343 hal_rx_msdu_end_l3_hdr_padding_get_6750, 1344 hal_rx_encryption_info_valid_6750, 1345 hal_rx_print_pn_6750, 1346 hal_rx_msdu_end_first_msdu_get_6750, 1347 hal_rx_msdu_end_da_is_valid_get_6750, 1348 hal_rx_msdu_end_last_msdu_get_6750, 1349 hal_rx_get_mpdu_mac_ad4_valid_6750, 1350 hal_rx_mpdu_start_sw_peer_id_get_6750, 1351 hal_rx_mpdu_get_to_ds_6750, 1352 hal_rx_mpdu_get_fr_ds_6750, 1353 hal_rx_get_mpdu_frame_control_valid_6750, 1354 hal_rx_mpdu_get_addr1_6750, 1355 hal_rx_mpdu_get_addr2_6750, 1356 hal_rx_mpdu_get_addr3_6750, 1357 hal_rx_mpdu_get_addr4_6750, 1358 hal_rx_get_mpdu_sequence_control_valid_6750, 1359 hal_rx_is_unicast_6750, 1360 hal_rx_tid_get_6750, 1361 hal_rx_hw_desc_get_ppduid_get_6750, 1362 NULL, 1363 NULL, 1364 hal_rx_msdu0_buffer_addr_lsb_6750, 1365 hal_rx_msdu_desc_info_ptr_get_6750, 1366 hal_ent_mpdu_desc_info_6750, 1367 hal_dst_mpdu_desc_info_6750, 1368 hal_rx_get_fc_valid_6750, 1369 hal_rx_get_to_ds_flag_6750, 1370 hal_rx_get_mac_addr2_valid_6750, 1371 hal_rx_get_filter_category_6750, 1372 hal_rx_get_ppdu_id_6750, 1373 hal_reo_config_6750, 1374 hal_rx_msdu_flow_idx_get_6750, 1375 hal_rx_msdu_flow_idx_invalid_6750, 1376 hal_rx_msdu_flow_idx_timeout_6750, 1377 hal_rx_msdu_fse_metadata_get_6750, 1378 hal_rx_msdu_cce_metadata_get_6750, 1379 NULL, 1380 hal_rx_tlv_get_tcp_chksum_6750, 1381 hal_rx_get_rx_sequence_6750, 1382 NULL, 1383 NULL, 1384 /* rx - msdu end fast path info fields */ 1385 hal_rx_msdu_packet_metadata_get_generic, 1386 }; 1387 1388 struct hal_hw_srng_config hw_srng_table_6750[] = { 1389 /* TODO: max_rings can populated by querying HW capabilities */ 1390 { /* REO_DST */ 1391 .start_ring_id = HAL_SRNG_REO2SW1, 1392 .max_rings = 4, 1393 .entry_size = sizeof(struct reo_destination_ring) >> 2, 1394 .lmac_ring = FALSE, 1395 .ring_dir = HAL_SRNG_DST_RING, 1396 .reg_start = { 1397 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR( 1398 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1399 HWIO_REO_R2_REO2SW1_RING_HP_ADDR( 1400 SEQ_WCSS_UMAC_REO_REG_OFFSET) 1401 }, 1402 .reg_size = { 1403 HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(0) - 1404 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(0), 1405 HWIO_REO_R2_REO2SW2_RING_HP_ADDR(0) - 1406 HWIO_REO_R2_REO2SW1_RING_HP_ADDR(0), 1407 }, 1408 .max_size = 1409 HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_BMSK >> 1410 HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_SHFT, 1411 }, 1412 { /* REO_EXCEPTION */ 1413 /* Designating REO2TCL ring as exception ring. This ring is 1414 * similar to other REO2SW rings though it is named as REO2TCL. 1415 * Any of theREO2SW rings can be used as exception ring. 1416 */ 1417 .start_ring_id = HAL_SRNG_REO2TCL, 1418 .max_rings = 1, 1419 .entry_size = sizeof(struct reo_destination_ring) >> 2, 1420 .lmac_ring = FALSE, 1421 .ring_dir = HAL_SRNG_DST_RING, 1422 .reg_start = { 1423 HWIO_REO_R0_REO2TCL_RING_BASE_LSB_ADDR( 1424 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1425 HWIO_REO_R2_REO2TCL_RING_HP_ADDR( 1426 SEQ_WCSS_UMAC_REO_REG_OFFSET) 1427 }, 1428 /* Single ring - provide ring size if multiple rings of this 1429 * type are supported 1430 */ 1431 .reg_size = {}, 1432 .max_size = 1433 HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_BMSK >> 1434 HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_SHFT, 1435 }, 1436 { /* REO_REINJECT */ 1437 .start_ring_id = HAL_SRNG_SW2REO, 1438 .max_rings = 1, 1439 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 1440 .lmac_ring = FALSE, 1441 .ring_dir = HAL_SRNG_SRC_RING, 1442 .reg_start = { 1443 HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR( 1444 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1445 HWIO_REO_R2_SW2REO_RING_HP_ADDR( 1446 SEQ_WCSS_UMAC_REO_REG_OFFSET) 1447 }, 1448 /* Single ring - provide ring size if multiple rings of this 1449 * type are supported 1450 */ 1451 .reg_size = {}, 1452 .max_size = HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_BMSK >> 1453 HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_SHFT, 1454 }, 1455 { /* REO_CMD */ 1456 .start_ring_id = HAL_SRNG_REO_CMD, 1457 .max_rings = 1, 1458 .entry_size = (sizeof(struct tlv_32_hdr) + 1459 sizeof(struct reo_get_queue_stats)) >> 2, 1460 .lmac_ring = FALSE, 1461 .ring_dir = HAL_SRNG_SRC_RING, 1462 .reg_start = { 1463 HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR( 1464 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1465 HWIO_REO_R2_REO_CMD_RING_HP_ADDR( 1466 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1467 }, 1468 /* Single ring - provide ring size if multiple rings of this 1469 * type are supported 1470 */ 1471 .reg_size = {}, 1472 .max_size = 1473 HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_BMSK >> 1474 HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_SHFT, 1475 }, 1476 { /* REO_STATUS */ 1477 .start_ring_id = HAL_SRNG_REO_STATUS, 1478 .max_rings = 1, 1479 .entry_size = (sizeof(struct tlv_32_hdr) + 1480 sizeof(struct reo_get_queue_stats_status)) >> 2, 1481 .lmac_ring = FALSE, 1482 .ring_dir = HAL_SRNG_DST_RING, 1483 .reg_start = { 1484 HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR( 1485 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1486 HWIO_REO_R2_REO_STATUS_RING_HP_ADDR( 1487 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1488 }, 1489 /* Single ring - provide ring size if multiple rings of this 1490 * type are supported 1491 */ 1492 .reg_size = {}, 1493 .max_size = 1494 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> 1495 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, 1496 }, 1497 { /* TCL_DATA */ 1498 .start_ring_id = HAL_SRNG_SW2TCL1, 1499 .max_rings = 3, 1500 .entry_size = (sizeof(struct tlv_32_hdr) + 1501 sizeof(struct tcl_data_cmd)) >> 2, 1502 .lmac_ring = FALSE, 1503 .ring_dir = HAL_SRNG_SRC_RING, 1504 .reg_start = { 1505 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR( 1506 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1507 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR( 1508 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1509 }, 1510 .reg_size = { 1511 HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(0) - 1512 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(0), 1513 HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(0) - 1514 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(0), 1515 }, 1516 .max_size = 1517 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK >> 1518 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT, 1519 }, 1520 { /* TCL_CMD */ 1521 .start_ring_id = HAL_SRNG_SW2TCL_CMD, 1522 .max_rings = 1, 1523 .entry_size = (sizeof(struct tlv_32_hdr) + 1524 sizeof(struct tcl_gse_cmd)) >> 2, 1525 .lmac_ring = FALSE, 1526 .ring_dir = HAL_SRNG_SRC_RING, 1527 .reg_start = { 1528 HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_ADDR( 1529 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1530 HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_ADDR( 1531 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1532 }, 1533 /* Single ring - provide ring size if multiple rings of this 1534 * type are supported 1535 */ 1536 .reg_size = {}, 1537 .max_size = 1538 HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_SIZE_BMSK >> 1539 HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_SIZE_SHFT, 1540 }, 1541 { /* TCL_STATUS */ 1542 .start_ring_id = HAL_SRNG_TCL_STATUS, 1543 .max_rings = 1, 1544 .entry_size = (sizeof(struct tlv_32_hdr) + 1545 sizeof(struct tcl_status_ring)) >> 2, 1546 .lmac_ring = FALSE, 1547 .ring_dir = HAL_SRNG_DST_RING, 1548 .reg_start = { 1549 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR( 1550 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1551 HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR( 1552 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1553 }, 1554 /* Single ring - provide ring size if multiple rings of this 1555 * type are supported 1556 */ 1557 .reg_size = {}, 1558 .max_size = 1559 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_BMSK >> 1560 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_SHFT, 1561 }, 1562 { /* CE_SRC */ 1563 .start_ring_id = HAL_SRNG_CE_0_SRC, 1564 .max_rings = 12, 1565 .entry_size = sizeof(struct ce_src_desc) >> 2, 1566 .lmac_ring = FALSE, 1567 .ring_dir = HAL_SRNG_SRC_RING, 1568 .reg_start = { 1569 HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR, 1570 HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR, 1571 }, 1572 .reg_size = { 1573 HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR - 1574 HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR, 1575 HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR - 1576 HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR, 1577 }, 1578 .max_size = 1579 HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >> 1580 HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT 1581 }, 1582 { /* CE_DST */ 1583 .start_ring_id = HAL_SRNG_CE_0_DST, 1584 .max_rings = 12, 1585 .entry_size = 8 >> 2, 1586 /*TODO: entry_size above should actually be 1587 * sizeof(struct ce_dst_desc) >> 2, but couldn't find definition 1588 * of struct ce_dst_desc in HW header files 1589 */ 1590 .lmac_ring = FALSE, 1591 .ring_dir = HAL_SRNG_SRC_RING, 1592 .reg_start = { 1593 HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, 1594 HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR, 1595 }, 1596 .reg_size = { 1597 HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR - 1598 HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, 1599 HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR - 1600 HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR 1601 }, 1602 .max_size = 1603 HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >> 1604 HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT 1605 }, 1606 { /* CE_DST_STATUS */ 1607 .start_ring_id = HAL_SRNG_CE_0_DST_STATUS, 1608 .max_rings = 12, 1609 .entry_size = sizeof(struct ce_stat_desc) >> 2, 1610 .lmac_ring = FALSE, 1611 .ring_dir = HAL_SRNG_DST_RING, 1612 .reg_start = { 1613 HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR, 1614 HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR, 1615 }, 1616 /* TODO: check destination status ring registers */ 1617 .reg_size = { 1618 HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR - 1619 HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, 1620 HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR - 1621 HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR 1622 }, 1623 .max_size = 1624 HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> 1625 HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, 1626 }, 1627 { /* WBM_IDLE_LINK */ 1628 .start_ring_id = HAL_SRNG_WBM_IDLE_LINK, 1629 .max_rings = 1, 1630 .entry_size = sizeof(struct wbm_link_descriptor_ring) >> 2, 1631 .lmac_ring = FALSE, 1632 .ring_dir = HAL_SRNG_SRC_RING, 1633 .reg_start = { 1634 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1635 HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1636 }, 1637 /* Single ring - provide ring size if multiple rings of this 1638 * type are supported 1639 */ 1640 .reg_size = {}, 1641 .max_size = 1642 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_BMSK >> 1643 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_SHFT, 1644 }, 1645 { /* SW2WBM_RELEASE */ 1646 .start_ring_id = HAL_SRNG_WBM_SW_RELEASE, 1647 .max_rings = 1, 1648 .entry_size = sizeof(struct wbm_release_ring) >> 2, 1649 .lmac_ring = FALSE, 1650 .ring_dir = HAL_SRNG_SRC_RING, 1651 .reg_start = { 1652 HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1653 HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1654 }, 1655 /* Single ring - provide ring size if multiple rings of this 1656 * type are supported 1657 */ 1658 .reg_size = {}, 1659 .max_size = 1660 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> 1661 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, 1662 }, 1663 { /* WBM2SW_RELEASE */ 1664 .start_ring_id = HAL_SRNG_WBM2SW0_RELEASE, 1665 .max_rings = 4, 1666 .entry_size = sizeof(struct wbm_release_ring) >> 2, 1667 .lmac_ring = FALSE, 1668 .ring_dir = HAL_SRNG_DST_RING, 1669 .reg_start = { 1670 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1671 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1672 }, 1673 .reg_size = { 1674 HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) - 1675 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1676 HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) - 1677 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1678 }, 1679 .max_size = 1680 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> 1681 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, 1682 }, 1683 { /* RXDMA_BUF */ 1684 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA0_BUF0, 1685 #ifdef IPA_OFFLOAD 1686 .max_rings = 3, 1687 #else 1688 .max_rings = 2, 1689 #endif 1690 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 1691 .lmac_ring = TRUE, 1692 .ring_dir = HAL_SRNG_SRC_RING, 1693 /* reg_start is not set because LMAC rings are not accessed 1694 * from host 1695 */ 1696 .reg_start = {}, 1697 .reg_size = {}, 1698 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1699 }, 1700 { /* RXDMA_DST */ 1701 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW0, 1702 .max_rings = 1, 1703 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 1704 .lmac_ring = TRUE, 1705 .ring_dir = HAL_SRNG_DST_RING, 1706 /* reg_start is not set because LMAC rings are not accessed 1707 * from host 1708 */ 1709 .reg_start = {}, 1710 .reg_size = {}, 1711 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1712 }, 1713 { /* RXDMA_MONITOR_BUF */ 1714 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA2_BUF, 1715 .max_rings = 1, 1716 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 1717 .lmac_ring = TRUE, 1718 .ring_dir = HAL_SRNG_SRC_RING, 1719 /* reg_start is not set because LMAC rings are not accessed 1720 * from host 1721 */ 1722 .reg_start = {}, 1723 .reg_size = {}, 1724 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1725 }, 1726 { /* RXDMA_MONITOR_STATUS */ 1727 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_STATBUF, 1728 .max_rings = 1, 1729 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 1730 .lmac_ring = TRUE, 1731 .ring_dir = HAL_SRNG_SRC_RING, 1732 /* reg_start is not set because LMAC rings are not accessed 1733 * from host 1734 */ 1735 .reg_start = {}, 1736 .reg_size = {}, 1737 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1738 }, 1739 { /* RXDMA_MONITOR_DST */ 1740 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW1, 1741 .max_rings = 1, 1742 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 1743 .lmac_ring = TRUE, 1744 .ring_dir = HAL_SRNG_DST_RING, 1745 /* reg_start is not set because LMAC rings are not accessed 1746 * from host 1747 */ 1748 .reg_start = {}, 1749 .reg_size = {}, 1750 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1751 }, 1752 { /* RXDMA_MONITOR_DESC */ 1753 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_DESC, 1754 .max_rings = 1, 1755 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 1756 .lmac_ring = TRUE, 1757 .ring_dir = HAL_SRNG_SRC_RING, 1758 /* reg_start is not set because LMAC rings are not accessed 1759 * from host 1760 */ 1761 .reg_start = {}, 1762 .reg_size = {}, 1763 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1764 }, 1765 { /* DIR_BUF_RX_DMA_SRC */ 1766 .start_ring_id = HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING, 1767 .max_rings = 1, 1768 .entry_size = 2, 1769 .lmac_ring = TRUE, 1770 .ring_dir = HAL_SRNG_SRC_RING, 1771 /* reg_start is not set because LMAC rings are not accessed 1772 * from host 1773 */ 1774 .reg_start = {}, 1775 .reg_size = {}, 1776 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1777 }, 1778 #ifdef WLAN_FEATURE_CIF_CFR 1779 { /* WIFI_POS_SRC */ 1780 .start_ring_id = HAL_SRNG_WIFI_POS_SRC_DMA_RING, 1781 .max_rings = 1, 1782 .entry_size = sizeof(wmi_oem_dma_buf_release_entry) >> 2, 1783 .lmac_ring = TRUE, 1784 .ring_dir = HAL_SRNG_SRC_RING, 1785 /* reg_start is not set because LMAC rings are not accessed 1786 * from host 1787 */ 1788 .reg_start = {}, 1789 .reg_size = {}, 1790 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1791 }, 1792 #endif 1793 }; 1794 1795 int32_t hal_hw_reg_offset_qca6750[] = { 1796 /* dst */ 1797 REG_OFFSET(DST, HP), 1798 REG_OFFSET(DST, TP), 1799 REG_OFFSET(DST, ID), 1800 REG_OFFSET(DST, MISC), 1801 REG_OFFSET(DST, HP_ADDR_LSB), 1802 REG_OFFSET(DST, HP_ADDR_MSB), 1803 REG_OFFSET(DST, MSI1_BASE_LSB), 1804 REG_OFFSET(DST, MSI1_BASE_MSB), 1805 REG_OFFSET(DST, MSI1_DATA), 1806 REG_OFFSET(DST, BASE_LSB), 1807 REG_OFFSET(DST, BASE_MSB), 1808 REG_OFFSET(DST, PRODUCER_INT_SETUP), 1809 /* src */ 1810 REG_OFFSET(SRC, HP), 1811 REG_OFFSET(SRC, TP), 1812 REG_OFFSET(SRC, ID), 1813 REG_OFFSET(SRC, MISC), 1814 REG_OFFSET(SRC, TP_ADDR_LSB), 1815 REG_OFFSET(SRC, TP_ADDR_MSB), 1816 REG_OFFSET(SRC, MSI1_BASE_LSB), 1817 REG_OFFSET(SRC, MSI1_BASE_MSB), 1818 REG_OFFSET(SRC, MSI1_DATA), 1819 REG_OFFSET(SRC, BASE_LSB), 1820 REG_OFFSET(SRC, BASE_MSB), 1821 REG_OFFSET(SRC, CONSUMER_INT_SETUP_IX0), 1822 REG_OFFSET(SRC, CONSUMER_INT_SETUP_IX1), 1823 }; 1824 1825 /** 1826 * hal_qca6750_attach() - Attach 6750 target specific hal_soc ops, 1827 * offset and srng table 1828 */ 1829 void hal_qca6750_attach(struct hal_soc *hal_soc) 1830 { 1831 hal_soc->hw_srng_table = hw_srng_table_6750; 1832 hal_soc->hal_hw_reg_offset = hal_hw_reg_offset_qca6750; 1833 hal_soc->ops = &qca6750_hal_hw_txrx_ops; 1834 } 1835