1 /* 2 * Copyright (c) 2020 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #include "qdf_types.h" 20 #include "qdf_util.h" 21 #include "qdf_types.h" 22 #include "qdf_lock.h" 23 #include "qdf_mem.h" 24 #include "qdf_nbuf.h" 25 #include "hal_hw_headers.h" 26 #include "hal_internal.h" 27 #include "hal_api.h" 28 #include "target_type.h" 29 #include "wcss_version.h" 30 #include "qdf_module.h" 31 #include "hal_flow.h" 32 #include "rx_flow_search_entry.h" 33 #include "hal_rx_flow_info.h" 34 35 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_OFFSET \ 36 RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_OFFSET 37 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_MASK \ 38 RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_MASK 39 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_LSB \ 40 RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_LSB 41 #define UNIFIED_PHYRX_HT_SIG_0_HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS_OFFSET \ 42 PHYRX_L_SIG_B_0_PHYRX_L_SIG_B_INFO_DETAILS_RATE_OFFSET 43 #define UNIFIED_PHYRX_L_SIG_B_0_L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS_OFFSET \ 44 PHYRX_L_SIG_B_0_PHYRX_L_SIG_B_INFO_DETAILS_RATE_OFFSET 45 #define UNIFIED_PHYRX_L_SIG_A_0_L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS_OFFSET \ 46 PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_RATE_OFFSET 47 #define UNIFIED_PHYRX_VHT_SIG_A_0_VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS_OFFSET \ 48 PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_OFFSET 49 #define UNIFIED_PHYRX_HE_SIG_A_SU_0_HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS_OFFSET \ 50 PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_OFFSET 51 #define UNIFIED_PHYRX_HE_SIG_A_MU_DL_0_HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_OFFSET \ 52 PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_OFFSET 53 #define UNIFIED_PHYRX_HE_SIG_B1_MU_0_HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_OFFSET \ 54 PHYRX_HE_SIG_B1_MU_0_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_OFFSET 55 #define UNIFIED_PHYRX_HE_SIG_B2_MU_0_HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_OFFSET \ 56 PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_OFFSET 57 #define UNIFIED_PHYRX_HE_SIG_B2_OFDMA_0_HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_OFFSET \ 58 PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_OFFSET 59 60 #define UNIFIED_PHYRX_RSSI_LEGACY_3_RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS_OFFSET \ 61 PHYRX_RSSI_LEGACY_3_RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS_OFFSET 62 #define UNIFIED_PHYRX_RSSI_LEGACY_19_RECEIVE_RSSI_INFO_PREAMBLE_RSSI_INFO_DETAILS_OFFSET \ 63 PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 64 #define UNIFIED_RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET \ 65 RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 66 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 67 RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET 68 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ 69 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET 70 #define UNIFIED_RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 71 RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET 72 #define UNIFIED_REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 73 REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET 74 #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC \ 75 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER 76 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ 77 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET 78 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 79 RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET 80 #define UNIFIED_TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 81 TCL_DATA_CMD_0_BUF_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 82 #define UNIFIED_TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 83 TCL_DATA_CMD_1_BUF_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 84 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET \ 85 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET 86 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB \ 87 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB 88 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK \ 89 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK 90 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB \ 91 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB 92 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK \ 93 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK 94 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB \ 95 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB 96 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK \ 97 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK 98 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB \ 99 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB 100 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK \ 101 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK 102 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB \ 103 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB 104 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK \ 105 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK 106 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_MASK \ 107 WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MASK 108 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_OFFSET \ 109 WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_OFFSET 110 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_LSB \ 111 WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_LSB 112 113 #include "hal_6750_tx.h" 114 #include "hal_6750_rx.h" 115 #include <hal_generic_api.h> 116 #include <hal_wbm.h> 117 118 /* 119 * hal_rx_msdu_start_nss_get_6750(): API to get the NSS 120 * Interval from rx_msdu_start 121 * 122 * @buf: pointer to the start of RX PKT TLV header 123 * Return: uint32_t(nss) 124 */ 125 static uint32_t 126 hal_rx_msdu_start_nss_get_6750(uint8_t *buf) 127 { 128 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 129 struct rx_msdu_start *msdu_start = 130 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 131 uint8_t mimo_ss_bitmap; 132 133 mimo_ss_bitmap = HAL_RX_MSDU_START_MIMO_SS_BITMAP(msdu_start); 134 135 return qdf_get_hweight8(mimo_ss_bitmap); 136 } 137 138 /** 139 * hal_rx_mon_hw_desc_get_mpdu_status_6750(): Retrieve MPDU status 140 * 141 * @ hw_desc_addr: Start address of Rx HW TLVs 142 * @ rs: Status for monitor mode 143 * 144 * Return: void 145 */ 146 static void hal_rx_mon_hw_desc_get_mpdu_status_6750(void *hw_desc_addr, 147 struct mon_rx_status *rs) 148 { 149 struct rx_msdu_start *rx_msdu_start; 150 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr; 151 uint32_t reg_value; 152 const uint32_t sgi_hw_to_cdp[] = { 153 CDP_SGI_0_8_US, 154 CDP_SGI_0_4_US, 155 CDP_SGI_1_6_US, 156 CDP_SGI_3_2_US, 157 }; 158 159 rx_msdu_start = &rx_desc->msdu_start_tlv.rx_msdu_start; 160 161 HAL_RX_GET_MSDU_AGGREGATION(rx_desc, rs); 162 163 rs->ant_signal_db = HAL_RX_GET(rx_msdu_start, 164 RX_MSDU_START_5, USER_RSSI); 165 rs->is_stbc = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, STBC); 166 167 reg_value = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, SGI); 168 rs->sgi = sgi_hw_to_cdp[reg_value]; 169 170 reg_value = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, RECEPTION_TYPE); 171 rs->beamformed = (reg_value == HAL_RX_RECEPTION_TYPE_MU_MIMO) ? 1 : 0; 172 /* TODO: rs->beamformed should be set for SU beamforming also */ 173 } 174 175 #define LINK_DESC_SIZE (NUM_OF_DWORDS_RX_MSDU_LINK << 2) 176 177 static uint32_t hal_get_link_desc_size_6750(void) 178 { 179 return LINK_DESC_SIZE; 180 } 181 182 /* 183 * hal_rx_get_tlv_6750(): API to get the tlv 184 * 185 * @rx_tlv: TLV data extracted from the rx packet 186 * Return: uint8_t 187 */ 188 static uint8_t hal_rx_get_tlv_6750(void *rx_tlv) 189 { 190 return HAL_RX_GET(rx_tlv, PHYRX_RSSI_LEGACY_0, RECEIVE_BANDWIDTH); 191 } 192 193 /** 194 * hal_rx_proc_phyrx_other_receive_info_tlv_6750() 195 * - process other receive info TLV 196 * @rx_tlv_hdr: pointer to TLV header 197 * @ppdu_info: pointer to ppdu_info 198 * 199 * Return: None 200 */ 201 static 202 void hal_rx_proc_phyrx_other_receive_info_tlv_6750(void *rx_tlv_hdr, 203 void *ppdu_info_handle) 204 { 205 uint32_t tlv_tag, tlv_len; 206 uint32_t temp_len, other_tlv_len, other_tlv_tag; 207 void *rx_tlv = (uint8_t *)rx_tlv_hdr + HAL_RX_TLV32_HDR_SIZE; 208 void *other_tlv_hdr = NULL; 209 void *other_tlv = NULL; 210 211 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv_hdr); 212 tlv_len = HAL_RX_GET_USER_TLV32_LEN(rx_tlv_hdr); 213 temp_len = 0; 214 215 other_tlv_hdr = rx_tlv + HAL_RX_TLV32_HDR_SIZE; 216 217 other_tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(other_tlv_hdr); 218 other_tlv_len = HAL_RX_GET_USER_TLV32_LEN(other_tlv_hdr); 219 temp_len += other_tlv_len; 220 other_tlv = other_tlv_hdr + HAL_RX_TLV32_HDR_SIZE; 221 222 switch (other_tlv_tag) { 223 default: 224 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR, 225 "%s unhandled TLV type: %d, TLV len:%d", 226 __func__, other_tlv_tag, other_tlv_len); 227 break; 228 } 229 } 230 231 /** 232 * hal_rx_dump_msdu_start_tlv_6750() : dump RX msdu_start TLV in structured 233 * human readable format. 234 * @ msdu_start: pointer the msdu_start TLV in pkt. 235 * @ dbg_level: log level. 236 * 237 * Return: void 238 */ 239 static void hal_rx_dump_msdu_start_tlv_6750(void *msdustart, uint8_t dbg_level) 240 { 241 struct rx_msdu_start *msdu_start = (struct rx_msdu_start *)msdustart; 242 243 hal_verbose_debug( 244 "rx_msdu_start tlv (1/2) - " 245 "rxpcu_mpdu_filter_in_category: %x " 246 "sw_frame_group_id: %x " 247 "phy_ppdu_id: %x " 248 "msdu_length: %x " 249 "ipsec_esp: %x " 250 "l3_offset: %x " 251 "ipsec_ah: %x " 252 "l4_offset: %x " 253 "msdu_number: %x " 254 "decap_format: %x " 255 "ipv4_proto: %x " 256 "ipv6_proto: %x " 257 "tcp_proto: %x " 258 "udp_proto: %x " 259 "ip_frag: %x " 260 "tcp_only_ack: %x " 261 "da_is_bcast_mcast: %x " 262 "ip4_protocol_ip6_next_header: %x " 263 "toeplitz_hash_2_or_4: %x " 264 "flow_id_toeplitz: %x " 265 "user_rssi: %x " 266 "pkt_type: %x " 267 "stbc: %x " 268 "sgi: %x " 269 "rate_mcs: %x " 270 "receive_bandwidth: %x " 271 "reception_type: %x " 272 "ppdu_start_timestamp: %u ", 273 msdu_start->rxpcu_mpdu_filter_in_category, 274 msdu_start->sw_frame_group_id, 275 msdu_start->phy_ppdu_id, 276 msdu_start->msdu_length, 277 msdu_start->ipsec_esp, 278 msdu_start->l3_offset, 279 msdu_start->ipsec_ah, 280 msdu_start->l4_offset, 281 msdu_start->msdu_number, 282 msdu_start->decap_format, 283 msdu_start->ipv4_proto, 284 msdu_start->ipv6_proto, 285 msdu_start->tcp_proto, 286 msdu_start->udp_proto, 287 msdu_start->ip_frag, 288 msdu_start->tcp_only_ack, 289 msdu_start->da_is_bcast_mcast, 290 msdu_start->ip4_protocol_ip6_next_header, 291 msdu_start->toeplitz_hash_2_or_4, 292 msdu_start->flow_id_toeplitz, 293 msdu_start->user_rssi, 294 msdu_start->pkt_type, 295 msdu_start->stbc, 296 msdu_start->sgi, 297 msdu_start->rate_mcs, 298 msdu_start->receive_bandwidth, 299 msdu_start->reception_type, 300 msdu_start->ppdu_start_timestamp); 301 302 hal_verbose_debug( 303 "rx_msdu_start tlv (2/2) - " 304 "sw_phy_meta_data: %x ", 305 msdu_start->sw_phy_meta_data); 306 } 307 308 /** 309 * hal_rx_dump_msdu_end_tlv_6750: dump RX msdu_end TLV in structured 310 * human readable format. 311 * @ msdu_end: pointer the msdu_end TLV in pkt. 312 * @ dbg_level: log level. 313 * 314 * Return: void 315 */ 316 static void hal_rx_dump_msdu_end_tlv_6750(void *msduend, 317 uint8_t dbg_level) 318 { 319 struct rx_msdu_end *msdu_end = (struct rx_msdu_end *)msduend; 320 321 __QDF_TRACE_RL(dbg_level, QDF_MODULE_ID_DP, 322 "rx_msdu_end tlv (1/3) - " 323 "rxpcu_mpdu_filter_in_category: %x " 324 "sw_frame_group_id: %x " 325 "phy_ppdu_id: %x " 326 "ip_hdr_chksum: %x " 327 "tcp_udp_chksum: %x " 328 "key_id_octet: %x " 329 "cce_super_rule: %x " 330 "cce_classify_not_done_truncat: %x " 331 "cce_classify_not_done_cce_dis: %x " 332 "reported_mpdu_length: %x " 333 "first_msdu: %x " 334 "last_msdu: %x " 335 "sa_idx_timeout: %x " 336 "da_idx_timeout: %x " 337 "msdu_limit_error: %x " 338 "flow_idx_timeout: %x " 339 "flow_idx_invalid: %x " 340 "wifi_parser_error: %x " 341 "amsdu_parser_error: %x", 342 msdu_end->rxpcu_mpdu_filter_in_category, 343 msdu_end->sw_frame_group_id, 344 msdu_end->phy_ppdu_id, 345 msdu_end->ip_hdr_chksum, 346 msdu_end->tcp_udp_chksum, 347 msdu_end->key_id_octet, 348 msdu_end->cce_super_rule, 349 msdu_end->cce_classify_not_done_truncate, 350 msdu_end->cce_classify_not_done_cce_dis, 351 msdu_end->reported_mpdu_length, 352 msdu_end->first_msdu, 353 msdu_end->last_msdu, 354 msdu_end->sa_idx_timeout, 355 msdu_end->da_idx_timeout, 356 msdu_end->msdu_limit_error, 357 msdu_end->flow_idx_timeout, 358 msdu_end->flow_idx_invalid, 359 msdu_end->wifi_parser_error, 360 msdu_end->amsdu_parser_error); 361 362 __QDF_TRACE_RL(dbg_level, QDF_MODULE_ID_DP, 363 "rx_msdu_end tlv (2/3)- " 364 "sa_is_valid: %x " 365 "da_is_valid: %x " 366 "da_is_mcbc: %x " 367 "l3_header_padding: %x " 368 "ipv6_options_crc: %x " 369 "tcp_seq_number: %x " 370 "tcp_ack_number: %x " 371 "tcp_flag: %x " 372 "lro_eligible: %x " 373 "window_size: %x " 374 "da_offset: %x " 375 "sa_offset: %x " 376 "da_offset_valid: %x " 377 "sa_offset_valid: %x " 378 "rule_indication_31_0: %x " 379 "rule_indication_63_32: %x " 380 "sa_idx: %x " 381 "da_idx: %x " 382 "msdu_drop: %x " 383 "reo_destination_indication: %x " 384 "flow_idx: %x " 385 "fse_metadata: %x " 386 "cce_metadata: %x " 387 "sa_sw_peer_id: %x ", 388 msdu_end->sa_is_valid, 389 msdu_end->da_is_valid, 390 msdu_end->da_is_mcbc, 391 msdu_end->l3_header_padding, 392 msdu_end->ipv6_options_crc, 393 msdu_end->tcp_seq_number, 394 msdu_end->tcp_ack_number, 395 msdu_end->tcp_flag, 396 msdu_end->lro_eligible, 397 msdu_end->window_size, 398 msdu_end->da_offset, 399 msdu_end->sa_offset, 400 msdu_end->da_offset_valid, 401 msdu_end->sa_offset_valid, 402 msdu_end->rule_indication_31_0, 403 msdu_end->rule_indication_63_32, 404 msdu_end->sa_idx, 405 msdu_end->da_idx_or_sw_peer_id, 406 msdu_end->msdu_drop, 407 msdu_end->reo_destination_indication, 408 msdu_end->flow_idx, 409 msdu_end->fse_metadata, 410 msdu_end->cce_metadata, 411 msdu_end->sa_sw_peer_id); 412 __QDF_TRACE_RL(dbg_level, QDF_MODULE_ID_DP, 413 "rx_msdu_end tlv (3/3)" 414 "aggregation_count %x " 415 "flow_aggregation_continuation %x " 416 "fisa_timeout %x " 417 "cumulative_l4_checksum %x " 418 "cumulative_ip_length %x", 419 msdu_end->aggregation_count, 420 msdu_end->flow_aggregation_continuation, 421 msdu_end->fisa_timeout, 422 msdu_end->cumulative_l4_checksum, 423 msdu_end->cumulative_ip_length); 424 } 425 426 /* 427 * Get tid from RX_MPDU_START 428 */ 429 #define HAL_RX_MPDU_INFO_TID_GET(_rx_mpdu_info) \ 430 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_info), \ 431 RX_MPDU_INFO_7_TID_OFFSET)), \ 432 RX_MPDU_INFO_7_TID_MASK, \ 433 RX_MPDU_INFO_7_TID_LSB)) 434 435 static uint32_t hal_rx_mpdu_start_tid_get_6750(uint8_t *buf) 436 { 437 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 438 struct rx_mpdu_start *mpdu_start = 439 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 440 uint32_t tid; 441 442 tid = HAL_RX_MPDU_INFO_TID_GET(&mpdu_start->rx_mpdu_info_details); 443 444 return tid; 445 } 446 447 #define HAL_RX_MSDU_START_RECEPTION_TYPE_GET(_rx_msdu_start) \ 448 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start), \ 449 RX_MSDU_START_5_RECEPTION_TYPE_OFFSET)), \ 450 RX_MSDU_START_5_RECEPTION_TYPE_MASK, \ 451 RX_MSDU_START_5_RECEPTION_TYPE_LSB)) 452 453 /* 454 * hal_rx_msdu_start_reception_type_get(): API to get the reception type 455 * Interval from rx_msdu_start 456 * 457 * @buf: pointer to the start of RX PKT TLV header 458 * Return: uint32_t(reception_type) 459 */ 460 static 461 uint32_t hal_rx_msdu_start_reception_type_get_6750(uint8_t *buf) 462 { 463 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 464 struct rx_msdu_start *msdu_start = 465 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 466 uint32_t reception_type; 467 468 reception_type = HAL_RX_MSDU_START_RECEPTION_TYPE_GET(msdu_start); 469 470 return reception_type; 471 } 472 473 /** 474 * hal_rx_msdu_end_da_idx_get_6750: API to get da_idx 475 * from rx_msdu_end TLV 476 * 477 * @ buf: pointer to the start of RX PKT TLV headers 478 * Return: da index 479 */ 480 static uint16_t hal_rx_msdu_end_da_idx_get_6750(uint8_t *buf) 481 { 482 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 483 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 484 uint16_t da_idx; 485 486 da_idx = HAL_RX_MSDU_END_DA_IDX_GET(msdu_end); 487 488 return da_idx; 489 } 490 491 /** 492 * hal_rx_get_rx_fragment_number_6750(): Function to retrieve rx fragment number 493 * 494 * @nbuf: Network buffer 495 * Returns: rx fragment number 496 */ 497 static 498 uint8_t hal_rx_get_rx_fragment_number_6750(uint8_t *buf) 499 { 500 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 501 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 502 503 /* Return first 4 bits as fragment number */ 504 return (HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info) & 505 DOT11_SEQ_FRAG_MASK); 506 } 507 508 /** 509 * hal_rx_msdu_end_da_is_mcbc_get_6750(): API to check if pkt is MCBC 510 * from rx_msdu_end TLV 511 * 512 * @ buf: pointer to the start of RX PKT TLV headers 513 * Return: da_is_mcbc 514 */ 515 static uint8_t 516 hal_rx_msdu_end_da_is_mcbc_get_6750(uint8_t *buf) 517 { 518 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 519 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 520 521 return HAL_RX_MSDU_END_DA_IS_MCBC_GET(msdu_end); 522 } 523 524 /** 525 * hal_rx_msdu_end_sa_is_valid_get_6750(): API to get_6750 the 526 * sa_is_valid bit from rx_msdu_end TLV 527 * 528 * @ buf: pointer to the start of RX PKT TLV headers 529 * Return: sa_is_valid bit 530 */ 531 static uint8_t 532 hal_rx_msdu_end_sa_is_valid_get_6750(uint8_t *buf) 533 { 534 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 535 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 536 uint8_t sa_is_valid; 537 538 sa_is_valid = HAL_RX_MSDU_END_SA_IS_VALID_GET(msdu_end); 539 540 return sa_is_valid; 541 } 542 543 /** 544 * hal_rx_msdu_end_sa_idx_get_6750(): API to get_6750 the 545 * sa_idx from rx_msdu_end TLV 546 * 547 * @ buf: pointer to the start of RX PKT TLV headers 548 * Return: sa_idx (SA AST index) 549 */ 550 static 551 uint16_t hal_rx_msdu_end_sa_idx_get_6750(uint8_t *buf) 552 { 553 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 554 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 555 uint16_t sa_idx; 556 557 sa_idx = HAL_RX_MSDU_END_SA_IDX_GET(msdu_end); 558 559 return sa_idx; 560 } 561 562 /** 563 * hal_rx_desc_is_first_msdu_6750() - Check if first msdu 564 * 565 * @hal_soc_hdl: hal_soc handle 566 * @hw_desc_addr: hardware descriptor address 567 * 568 * Return: 0 - success/ non-zero failure 569 */ 570 static uint32_t hal_rx_desc_is_first_msdu_6750(void *hw_desc_addr) 571 { 572 struct rx_pkt_tlvs *rx_tlvs = (struct rx_pkt_tlvs *)hw_desc_addr; 573 struct rx_msdu_end *msdu_end = &rx_tlvs->msdu_end_tlv.rx_msdu_end; 574 575 return HAL_RX_GET(msdu_end, RX_MSDU_END_10, FIRST_MSDU); 576 } 577 578 /** 579 * hal_rx_msdu_end_l3_hdr_padding_get_6750(): API to get_6750 the 580 * l3_header padding from rx_msdu_end TLV 581 * 582 * @ buf: pointer to the start of RX PKT TLV headers 583 * Return: number of l3 header padding bytes 584 */ 585 static uint32_t hal_rx_msdu_end_l3_hdr_padding_get_6750(uint8_t *buf) 586 { 587 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 588 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 589 uint32_t l3_header_padding; 590 591 l3_header_padding = HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(msdu_end); 592 593 return l3_header_padding; 594 } 595 596 /* 597 * @ hal_rx_encryption_info_valid_6750: Returns encryption type. 598 * 599 * @ buf: rx_tlv_hdr of the received packet 600 * @ Return: encryption type 601 */ 602 static uint32_t hal_rx_encryption_info_valid_6750(uint8_t *buf) 603 { 604 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 605 struct rx_mpdu_start *mpdu_start = 606 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 607 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 608 uint32_t encryption_info = HAL_RX_MPDU_ENCRYPTION_INFO_VALID(mpdu_info); 609 610 return encryption_info; 611 } 612 613 /* 614 * @ hal_rx_print_pn_6750: Prints the PN of rx packet. 615 * 616 * @ buf: rx_tlv_hdr of the received packet 617 * @ Return: void 618 */ 619 static void hal_rx_print_pn_6750(uint8_t *buf) 620 { 621 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 622 struct rx_mpdu_start *mpdu_start = 623 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 624 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 625 626 uint32_t pn_31_0 = HAL_RX_MPDU_PN_31_0_GET(mpdu_info); 627 uint32_t pn_63_32 = HAL_RX_MPDU_PN_63_32_GET(mpdu_info); 628 uint32_t pn_95_64 = HAL_RX_MPDU_PN_95_64_GET(mpdu_info); 629 uint32_t pn_127_96 = HAL_RX_MPDU_PN_127_96_GET(mpdu_info); 630 631 hal_debug("PN number pn_127_96 0x%x pn_95_64 0x%x pn_63_32 0x%x pn_31_0 0x%x ", 632 pn_127_96, pn_95_64, pn_63_32, pn_31_0); 633 } 634 635 /** 636 * hal_rx_msdu_end_first_msdu_get_6750: API to get first msdu status 637 * from rx_msdu_end TLV 638 * 639 * @ buf: pointer to the start of RX PKT TLV headers 640 * Return: first_msdu 641 */ 642 static uint8_t hal_rx_msdu_end_first_msdu_get_6750(uint8_t *buf) 643 { 644 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 645 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 646 uint8_t first_msdu; 647 648 first_msdu = HAL_RX_MSDU_END_FIRST_MSDU_GET(msdu_end); 649 650 return first_msdu; 651 } 652 653 /** 654 * hal_rx_msdu_end_da_is_valid_get_6750: API to check if da is valid 655 * from rx_msdu_end TLV 656 * 657 * @ buf: pointer to the start of RX PKT TLV headers 658 * Return: da_is_valid 659 */ 660 static uint8_t hal_rx_msdu_end_da_is_valid_get_6750(uint8_t *buf) 661 { 662 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 663 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 664 uint8_t da_is_valid; 665 666 da_is_valid = HAL_RX_MSDU_END_DA_IS_VALID_GET(msdu_end); 667 668 return da_is_valid; 669 } 670 671 /** 672 * hal_rx_msdu_end_last_msdu_get_6750: API to get last msdu status 673 * from rx_msdu_end TLV 674 * 675 * @ buf: pointer to the start of RX PKT TLV headers 676 * Return: last_msdu 677 */ 678 static uint8_t hal_rx_msdu_end_last_msdu_get_6750(uint8_t *buf) 679 { 680 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 681 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 682 uint8_t last_msdu; 683 684 last_msdu = HAL_RX_MSDU_END_LAST_MSDU_GET(msdu_end); 685 686 return last_msdu; 687 } 688 689 /* 690 * hal_rx_get_mpdu_mac_ad4_valid_6750(): Retrieves if mpdu 4th addr is valid 691 * 692 * @nbuf: Network buffer 693 * Returns: value of mpdu 4th address valid field 694 */ 695 static bool hal_rx_get_mpdu_mac_ad4_valid_6750(uint8_t *buf) 696 { 697 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 698 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 699 bool ad4_valid = 0; 700 701 ad4_valid = HAL_RX_MPDU_GET_MAC_AD4_VALID(rx_mpdu_info); 702 703 return ad4_valid; 704 } 705 706 /** 707 * hal_rx_mpdu_start_sw_peer_id_get_6750: Retrieve sw peer_id 708 * @buf: network buffer 709 * 710 * Return: sw peer_id 711 */ 712 static uint32_t hal_rx_mpdu_start_sw_peer_id_get_6750(uint8_t *buf) 713 { 714 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 715 struct rx_mpdu_start *mpdu_start = 716 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 717 718 return HAL_RX_MPDU_INFO_SW_PEER_ID_GET( 719 &mpdu_start->rx_mpdu_info_details); 720 } 721 722 /** 723 * hal_rx_mpdu_get_to_ds_6750(): API to get the tods info 724 * from rx_mpdu_start 725 * 726 * @buf: pointer to the start of RX PKT TLV header 727 * Return: uint32_t(to_ds) 728 */ 729 static uint32_t hal_rx_mpdu_get_to_ds_6750(uint8_t *buf) 730 { 731 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 732 struct rx_mpdu_start *mpdu_start = 733 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 734 735 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 736 737 return HAL_RX_MPDU_GET_TODS(mpdu_info); 738 } 739 740 /* 741 * hal_rx_mpdu_get_fr_ds_6750(): API to get the from ds info 742 * from rx_mpdu_start 743 * 744 * @buf: pointer to the start of RX PKT TLV header 745 * Return: uint32_t(fr_ds) 746 */ 747 static uint32_t hal_rx_mpdu_get_fr_ds_6750(uint8_t *buf) 748 { 749 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 750 struct rx_mpdu_start *mpdu_start = 751 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 752 753 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 754 755 return HAL_RX_MPDU_GET_FROMDS(mpdu_info); 756 } 757 758 /* 759 * hal_rx_get_mpdu_frame_control_valid_6750(): Retrieves mpdu 760 * frame control valid 761 * 762 * @nbuf: Network buffer 763 * Returns: value of frame control valid field 764 */ 765 static uint8_t hal_rx_get_mpdu_frame_control_valid_6750(uint8_t *buf) 766 { 767 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 768 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 769 770 return HAL_RX_MPDU_GET_FRAME_CONTROL_VALID(rx_mpdu_info); 771 } 772 773 /* 774 * hal_rx_mpdu_get_addr1_6750(): API to check get address1 of the mpdu 775 * 776 * @buf: pointer to the start of RX PKT TLV headera 777 * @mac_addr: pointer to mac address 778 * Return: success/failure 779 */ 780 static QDF_STATUS hal_rx_mpdu_get_addr1_6750(uint8_t *buf, uint8_t *mac_addr) 781 { 782 struct __attribute__((__packed__)) hal_addr1 { 783 uint32_t ad1_31_0; 784 uint16_t ad1_47_32; 785 }; 786 787 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 788 struct rx_mpdu_start *mpdu_start = 789 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 790 791 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 792 struct hal_addr1 *addr = (struct hal_addr1 *)mac_addr; 793 uint32_t mac_addr_ad1_valid; 794 795 mac_addr_ad1_valid = HAL_RX_MPDU_MAC_ADDR_AD1_VALID_GET(mpdu_info); 796 797 if (mac_addr_ad1_valid) { 798 addr->ad1_31_0 = HAL_RX_MPDU_AD1_31_0_GET(mpdu_info); 799 addr->ad1_47_32 = HAL_RX_MPDU_AD1_47_32_GET(mpdu_info); 800 return QDF_STATUS_SUCCESS; 801 } 802 803 return QDF_STATUS_E_FAILURE; 804 } 805 806 /* 807 * hal_rx_mpdu_get_addr2_6750(): API to check get address2 of the mpdu 808 * in the packet 809 * 810 * @buf: pointer to the start of RX PKT TLV header 811 * @mac_addr: pointer to mac address 812 * Return: success/failure 813 */ 814 static QDF_STATUS hal_rx_mpdu_get_addr2_6750(uint8_t *buf, 815 uint8_t *mac_addr) 816 { 817 struct __attribute__((__packed__)) hal_addr2 { 818 uint16_t ad2_15_0; 819 uint32_t ad2_47_16; 820 }; 821 822 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 823 struct rx_mpdu_start *mpdu_start = 824 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 825 826 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 827 struct hal_addr2 *addr = (struct hal_addr2 *)mac_addr; 828 uint32_t mac_addr_ad2_valid; 829 830 mac_addr_ad2_valid = HAL_RX_MPDU_MAC_ADDR_AD2_VALID_GET(mpdu_info); 831 832 if (mac_addr_ad2_valid) { 833 addr->ad2_15_0 = HAL_RX_MPDU_AD2_15_0_GET(mpdu_info); 834 addr->ad2_47_16 = HAL_RX_MPDU_AD2_47_16_GET(mpdu_info); 835 return QDF_STATUS_SUCCESS; 836 } 837 838 return QDF_STATUS_E_FAILURE; 839 } 840 841 /* 842 * hal_rx_mpdu_get_addr3_6750(): API to get address3 of the mpdu 843 * in the packet 844 * 845 * @buf: pointer to the start of RX PKT TLV header 846 * @mac_addr: pointer to mac address 847 * Return: success/failure 848 */ 849 static QDF_STATUS hal_rx_mpdu_get_addr3_6750(uint8_t *buf, uint8_t *mac_addr) 850 { 851 struct __attribute__((__packed__)) hal_addr3 { 852 uint32_t ad3_31_0; 853 uint16_t ad3_47_32; 854 }; 855 856 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 857 struct rx_mpdu_start *mpdu_start = 858 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 859 860 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 861 struct hal_addr3 *addr = (struct hal_addr3 *)mac_addr; 862 uint32_t mac_addr_ad3_valid; 863 864 mac_addr_ad3_valid = HAL_RX_MPDU_MAC_ADDR_AD3_VALID_GET(mpdu_info); 865 866 if (mac_addr_ad3_valid) { 867 addr->ad3_31_0 = HAL_RX_MPDU_AD3_31_0_GET(mpdu_info); 868 addr->ad3_47_32 = HAL_RX_MPDU_AD3_47_32_GET(mpdu_info); 869 return QDF_STATUS_SUCCESS; 870 } 871 872 return QDF_STATUS_E_FAILURE; 873 } 874 875 /* 876 * hal_rx_mpdu_get_addr4_6750(): API to get address4 of the mpdu 877 * in the packet 878 * 879 * @buf: pointer to the start of RX PKT TLV header 880 * @mac_addr: pointer to mac address 881 * Return: success/failure 882 */ 883 static QDF_STATUS hal_rx_mpdu_get_addr4_6750(uint8_t *buf, uint8_t *mac_addr) 884 { 885 struct __attribute__((__packed__)) hal_addr4 { 886 uint32_t ad4_31_0; 887 uint16_t ad4_47_32; 888 }; 889 890 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 891 struct rx_mpdu_start *mpdu_start = 892 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 893 894 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 895 struct hal_addr4 *addr = (struct hal_addr4 *)mac_addr; 896 uint32_t mac_addr_ad4_valid; 897 898 mac_addr_ad4_valid = HAL_RX_MPDU_MAC_ADDR_AD4_VALID_GET(mpdu_info); 899 900 if (mac_addr_ad4_valid) { 901 addr->ad4_31_0 = HAL_RX_MPDU_AD4_31_0_GET(mpdu_info); 902 addr->ad4_47_32 = HAL_RX_MPDU_AD4_47_32_GET(mpdu_info); 903 return QDF_STATUS_SUCCESS; 904 } 905 906 return QDF_STATUS_E_FAILURE; 907 } 908 909 /* 910 * hal_rx_get_mpdu_sequence_control_valid_6750(): Get mpdu 911 * sequence control valid 912 * 913 * @nbuf: Network buffer 914 * Returns: value of sequence control valid field 915 */ 916 static uint8_t hal_rx_get_mpdu_sequence_control_valid_6750(uint8_t *buf) 917 { 918 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 919 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 920 921 return HAL_RX_MPDU_GET_SEQUENCE_CONTROL_VALID(rx_mpdu_info); 922 } 923 924 /** 925 * hal_rx_is_unicast_6750: check packet is unicast frame or not. 926 * 927 * @ buf: pointer to rx pkt TLV. 928 * 929 * Return: true on unicast. 930 */ 931 static bool hal_rx_is_unicast_6750(uint8_t *buf) 932 { 933 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 934 struct rx_mpdu_start *mpdu_start = 935 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 936 uint32_t grp_id; 937 uint8_t *rx_mpdu_info = (uint8_t *)&mpdu_start->rx_mpdu_info_details; 938 939 grp_id = (_HAL_MS((*_OFFSET_TO_WORD_PTR((rx_mpdu_info), 940 RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_OFFSET)), 941 RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_MASK, 942 RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_LSB)); 943 944 return (HAL_MPDU_SW_FRAME_GROUP_UNICAST_DATA == grp_id) ? true : false; 945 } 946 947 /** 948 * hal_rx_tid_get_6750: get tid based on qos control valid. 949 * @hal_soc_hdl: hal_soc handle 950 * @ buf: pointer to rx pkt TLV. 951 * 952 * Return: tid 953 */ 954 static uint32_t hal_rx_tid_get_6750(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 955 { 956 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 957 struct rx_mpdu_start *mpdu_start = 958 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 959 uint8_t *rx_mpdu_info = (uint8_t *)&mpdu_start->rx_mpdu_info_details; 960 uint8_t qos_control_valid = 961 (_HAL_MS((*_OFFSET_TO_WORD_PTR((rx_mpdu_info), 962 RX_MPDU_INFO_11_MPDU_QOS_CONTROL_VALID_OFFSET)), 963 RX_MPDU_INFO_11_MPDU_QOS_CONTROL_VALID_MASK, 964 RX_MPDU_INFO_11_MPDU_QOS_CONTROL_VALID_LSB)); 965 966 if (qos_control_valid) 967 return hal_rx_mpdu_start_tid_get_6750(buf); 968 969 return HAL_RX_NON_QOS_TID; 970 } 971 972 /** 973 * hal_rx_hw_desc_get_ppduid_get_6750(): retrieve ppdu id 974 * @rx_tlv_hdr: rx tlv header 975 * @rxdma_dst_ring_desc: rxdma HW descriptor 976 * 977 * Return: ppdu id 978 */ 979 static uint32_t hal_rx_hw_desc_get_ppduid_get_6750(void *rx_tlv_hdr, 980 void *rxdma_dst_ring_desc) 981 { 982 struct rx_mpdu_info *rx_mpdu_info; 983 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)rx_tlv_hdr; 984 985 rx_mpdu_info = 986 &rx_desc->mpdu_start_tlv.rx_mpdu_start.rx_mpdu_info_details; 987 988 return HAL_RX_GET(rx_mpdu_info, RX_MPDU_INFO_9, PHY_PPDU_ID); 989 } 990 991 /** 992 * hal_reo_status_get_header_6750 - Process reo desc info 993 * @d - Pointer to reo descriptior 994 * @b - tlv type info 995 * @h1 - Pointer to hal_reo_status_header where info to be stored 996 * 997 * Return - none. 998 * 999 */ 1000 static void hal_reo_status_get_header_6750(uint32_t *d, int b, void *h1) 1001 { 1002 uint32_t val1 = 0; 1003 struct hal_reo_status_header *h = 1004 (struct hal_reo_status_header *)h1; 1005 1006 switch (b) { 1007 case HAL_REO_QUEUE_STATS_STATUS_TLV: 1008 val1 = d[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_0, 1009 STATUS_HEADER_REO_STATUS_NUMBER)]; 1010 break; 1011 case HAL_REO_FLUSH_QUEUE_STATUS_TLV: 1012 val1 = d[HAL_OFFSET_DW(REO_FLUSH_QUEUE_STATUS_0, 1013 STATUS_HEADER_REO_STATUS_NUMBER)]; 1014 break; 1015 case HAL_REO_FLUSH_CACHE_STATUS_TLV: 1016 val1 = d[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_0, 1017 STATUS_HEADER_REO_STATUS_NUMBER)]; 1018 break; 1019 case HAL_REO_UNBLK_CACHE_STATUS_TLV: 1020 val1 = d[HAL_OFFSET_DW(REO_UNBLOCK_CACHE_STATUS_0, 1021 STATUS_HEADER_REO_STATUS_NUMBER)]; 1022 break; 1023 case HAL_REO_TIMOUT_LIST_STATUS_TLV: 1024 val1 = d[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_0, 1025 STATUS_HEADER_REO_STATUS_NUMBER)]; 1026 break; 1027 case HAL_REO_DESC_THRES_STATUS_TLV: 1028 val1 = 1029 d[HAL_OFFSET_DW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0, 1030 STATUS_HEADER_REO_STATUS_NUMBER)]; 1031 break; 1032 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: 1033 val1 = d[HAL_OFFSET_DW(REO_UPDATE_RX_REO_QUEUE_STATUS_0, 1034 STATUS_HEADER_REO_STATUS_NUMBER)]; 1035 break; 1036 default: 1037 qdf_nofl_err("ERROR: Unknown tlv\n"); 1038 break; 1039 } 1040 h->cmd_num = 1041 HAL_GET_FIELD( 1042 UNIFORM_REO_STATUS_HEADER_0, REO_STATUS_NUMBER, 1043 val1); 1044 h->exec_time = 1045 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_0, 1046 CMD_EXECUTION_TIME, val1); 1047 h->status = 1048 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_0, 1049 REO_CMD_EXECUTION_STATUS, val1); 1050 switch (b) { 1051 case HAL_REO_QUEUE_STATS_STATUS_TLV: 1052 val1 = d[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_1, 1053 STATUS_HEADER_TIMESTAMP)]; 1054 break; 1055 case HAL_REO_FLUSH_QUEUE_STATUS_TLV: 1056 val1 = d[HAL_OFFSET_DW(REO_FLUSH_QUEUE_STATUS_1, 1057 STATUS_HEADER_TIMESTAMP)]; 1058 break; 1059 case HAL_REO_FLUSH_CACHE_STATUS_TLV: 1060 val1 = d[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_1, 1061 STATUS_HEADER_TIMESTAMP)]; 1062 break; 1063 case HAL_REO_UNBLK_CACHE_STATUS_TLV: 1064 val1 = d[HAL_OFFSET_DW(REO_UNBLOCK_CACHE_STATUS_1, 1065 STATUS_HEADER_TIMESTAMP)]; 1066 break; 1067 case HAL_REO_TIMOUT_LIST_STATUS_TLV: 1068 val1 = d[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_1, 1069 STATUS_HEADER_TIMESTAMP)]; 1070 break; 1071 case HAL_REO_DESC_THRES_STATUS_TLV: 1072 val1 = 1073 d[HAL_OFFSET_DW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_1, 1074 STATUS_HEADER_TIMESTAMP)]; 1075 break; 1076 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: 1077 val1 = d[HAL_OFFSET_DW(REO_UPDATE_RX_REO_QUEUE_STATUS_1, 1078 STATUS_HEADER_TIMESTAMP)]; 1079 break; 1080 default: 1081 qdf_nofl_err("ERROR: Unknown tlv\n"); 1082 break; 1083 } 1084 h->tstamp = 1085 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_1, TIMESTAMP, val1); 1086 } 1087 1088 /** 1089 * hal_tx_desc_set_mesh_en_6750 - Set mesh_enable flag in Tx descriptor 1090 * @desc: Handle to Tx Descriptor 1091 * @en: For raw WiFi frames, this indicates transmission to a mesh STA, 1092 * enabling the interpretation of the 'Mesh Control Present' bit 1093 * (bit 8) of QoS Control (otherwise this bit is ignored), 1094 * For native WiFi frames, this indicates that a 'Mesh Control' field 1095 * is present between the header and the LLC. 1096 * 1097 * Return: void 1098 */ 1099 static inline 1100 void hal_tx_desc_set_mesh_en_6750(void *desc, uint8_t en) 1101 { 1102 HAL_SET_FLD(desc, TCL_DATA_CMD_5, MESH_ENABLE) |= 1103 HAL_TX_SM(TCL_DATA_CMD_5, MESH_ENABLE, en); 1104 } 1105 1106 static 1107 void *hal_rx_msdu0_buffer_addr_lsb_6750(void *link_desc_va) 1108 { 1109 return (void *)HAL_RX_MSDU0_BUFFER_ADDR_LSB(link_desc_va); 1110 } 1111 1112 static 1113 void *hal_rx_msdu_desc_info_ptr_get_6750(void *msdu0) 1114 { 1115 return (void *)HAL_RX_MSDU_DESC_INFO_PTR_GET(msdu0); 1116 } 1117 1118 static 1119 void *hal_ent_mpdu_desc_info_6750(void *ent_ring_desc) 1120 { 1121 return (void *)HAL_ENT_MPDU_DESC_INFO(ent_ring_desc); 1122 } 1123 1124 static 1125 void *hal_dst_mpdu_desc_info_6750(void *dst_ring_desc) 1126 { 1127 return (void *)HAL_DST_MPDU_DESC_INFO(dst_ring_desc); 1128 } 1129 1130 static 1131 uint8_t hal_rx_get_fc_valid_6750(uint8_t *buf) 1132 { 1133 return HAL_RX_GET_FC_VALID(buf); 1134 } 1135 1136 static uint8_t hal_rx_get_to_ds_flag_6750(uint8_t *buf) 1137 { 1138 return HAL_RX_GET_TO_DS_FLAG(buf); 1139 } 1140 1141 static uint8_t hal_rx_get_mac_addr2_valid_6750(uint8_t *buf) 1142 { 1143 return HAL_RX_GET_MAC_ADDR2_VALID(buf); 1144 } 1145 1146 static uint8_t hal_rx_get_filter_category_6750(uint8_t *buf) 1147 { 1148 return HAL_RX_GET_FILTER_CATEGORY(buf); 1149 } 1150 1151 static uint32_t 1152 hal_rx_get_ppdu_id_6750(uint8_t *buf) 1153 { 1154 return HAL_RX_GET_PPDU_ID(buf); 1155 } 1156 1157 /** 1158 * hal_reo_config_6750(): Set reo config parameters 1159 * @soc: hal soc handle 1160 * @reg_val: value to be set 1161 * @reo_params: reo parameters 1162 * 1163 * Return: void 1164 */ 1165 static 1166 void hal_reo_config_6750(struct hal_soc *soc, 1167 uint32_t reg_val, 1168 struct hal_reo_params *reo_params) 1169 { 1170 HAL_REO_R0_CONFIG(soc, reg_val, reo_params); 1171 } 1172 1173 /** 1174 * hal_rx_msdu_desc_info_get_ptr_6750() - Get msdu desc info ptr 1175 * @msdu_details_ptr - Pointer to msdu_details_ptr 1176 * 1177 * Return - Pointer to rx_msdu_desc_info structure. 1178 * 1179 */ 1180 static void *hal_rx_msdu_desc_info_get_ptr_6750(void *msdu_details_ptr) 1181 { 1182 return HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr); 1183 } 1184 1185 /** 1186 * hal_rx_link_desc_msdu0_ptr_6750 - Get pointer to rx_msdu details 1187 * @link_desc - Pointer to link desc 1188 * 1189 * Return - Pointer to rx_msdu_details structure 1190 * 1191 */ 1192 static void *hal_rx_link_desc_msdu0_ptr_6750(void *link_desc) 1193 { 1194 return HAL_RX_LINK_DESC_MSDU0_PTR(link_desc); 1195 } 1196 1197 /** 1198 * hal_rx_msdu_flow_idx_get_6750: API to get flow index 1199 * from rx_msdu_end TLV 1200 * @buf: pointer to the start of RX PKT TLV headers 1201 * 1202 * Return: flow index value from MSDU END TLV 1203 */ 1204 static inline uint32_t hal_rx_msdu_flow_idx_get_6750(uint8_t *buf) 1205 { 1206 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1207 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1208 1209 return HAL_RX_MSDU_END_FLOW_IDX_GET(msdu_end); 1210 } 1211 1212 /** 1213 * hal_rx_msdu_flow_idx_invalid_6750: API to get flow index invalid 1214 * from rx_msdu_end TLV 1215 * @buf: pointer to the start of RX PKT TLV headers 1216 * 1217 * Return: flow index invalid value from MSDU END TLV 1218 */ 1219 static bool hal_rx_msdu_flow_idx_invalid_6750(uint8_t *buf) 1220 { 1221 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1222 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1223 1224 return HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(msdu_end); 1225 } 1226 1227 /** 1228 * hal_rx_msdu_flow_idx_timeout_6750: API to get flow index timeout 1229 * from rx_msdu_end TLV 1230 * @buf: pointer to the start of RX PKT TLV headers 1231 * 1232 * Return: flow index timeout value from MSDU END TLV 1233 */ 1234 static bool hal_rx_msdu_flow_idx_timeout_6750(uint8_t *buf) 1235 { 1236 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1237 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1238 1239 return HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(msdu_end); 1240 } 1241 1242 /** 1243 * hal_rx_msdu_fse_metadata_get_6750: API to get FSE metadata 1244 * from rx_msdu_end TLV 1245 * @buf: pointer to the start of RX PKT TLV headers 1246 * 1247 * Return: fse metadata value from MSDU END TLV 1248 */ 1249 static uint32_t hal_rx_msdu_fse_metadata_get_6750(uint8_t *buf) 1250 { 1251 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1252 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1253 1254 return HAL_RX_MSDU_END_FSE_METADATA_GET(msdu_end); 1255 } 1256 1257 /** 1258 * hal_rx_msdu_cce_metadata_get_6750: API to get CCE metadata 1259 * from rx_msdu_end TLV 1260 * @buf: pointer to the start of RX PKT TLV headers 1261 * 1262 * Return: cce_metadata 1263 */ 1264 static uint16_t 1265 hal_rx_msdu_cce_metadata_get_6750(uint8_t *buf) 1266 { 1267 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1268 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1269 1270 return HAL_RX_MSDU_END_CCE_METADATA_GET(msdu_end); 1271 } 1272 1273 /** 1274 * hal_rx_msdu_get_flow_params_6750: API to get flow index, flow index invalid 1275 * and flow index timeout from rx_msdu_end TLV 1276 * @buf: pointer to the start of RX PKT TLV headers 1277 * @flow_invalid: pointer to return value of flow_idx_valid 1278 * @flow_timeout: pointer to return value of flow_idx_timeout 1279 * @flow_index: pointer to return value of flow_idx 1280 * 1281 * Return: none 1282 */ 1283 static inline void 1284 hal_rx_msdu_get_flow_params_6750(uint8_t *buf, 1285 bool *flow_invalid, 1286 bool *flow_timeout, 1287 uint32_t *flow_index) 1288 { 1289 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1290 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1291 1292 *flow_invalid = HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(msdu_end); 1293 *flow_timeout = HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(msdu_end); 1294 *flow_index = HAL_RX_MSDU_END_FLOW_IDX_GET(msdu_end); 1295 } 1296 1297 /** 1298 * hal_rx_tlv_get_tcp_chksum_6750() - API to get tcp checksum 1299 * @buf: rx_tlv_hdr 1300 * 1301 * Return: tcp checksum 1302 */ 1303 static uint16_t 1304 hal_rx_tlv_get_tcp_chksum_6750(uint8_t *buf) 1305 { 1306 return HAL_RX_TLV_GET_TCP_CHKSUM(buf); 1307 } 1308 1309 /** 1310 * hal_rx_get_rx_sequence_6750(): Function to retrieve rx sequence number 1311 * 1312 * @nbuf: Network buffer 1313 * Returns: rx sequence number 1314 */ 1315 static 1316 uint16_t hal_rx_get_rx_sequence_6750(uint8_t *buf) 1317 { 1318 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 1319 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 1320 1321 return HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info); 1322 } 1323 1324 #define UMAC_WINDOW_REMAP_RANGE 0x14 1325 #define CE_WINDOW_REMAP_RANGE 0x37 1326 #define CMEM_WINDOW_REMAP_RANGE 0x2 1327 1328 /** 1329 * hal_get_window_address_6750(): Function to get hp/tp address 1330 * @hal_soc: Pointer to hal_soc 1331 * @addr: address offset of register 1332 * 1333 * Return: modified address offset of register 1334 */ 1335 static inline qdf_iomem_t hal_get_window_address_6750(struct hal_soc *hal_soc, 1336 qdf_iomem_t addr) 1337 { 1338 uint32_t offset; 1339 uint32_t window; 1340 uint8_t scale; 1341 1342 offset = addr - hal_soc->dev_base_addr; 1343 window = (offset >> WINDOW_SHIFT) & WINDOW_VALUE_MASK; 1344 1345 /* UMAC: 2nd window, CE: 3rd window, CMEM: 4th window */ 1346 switch (window) { 1347 case UMAC_WINDOW_REMAP_RANGE: 1348 scale = 1; 1349 break; 1350 case CE_WINDOW_REMAP_RANGE: 1351 scale = 2; 1352 break; 1353 case CMEM_WINDOW_REMAP_RANGE: 1354 scale = 3; 1355 break; 1356 default: 1357 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR, 1358 "%s: ERROR: Accessing Wrong register\n", __func__); 1359 qdf_assert_always(0); 1360 return 0; 1361 } 1362 1363 return hal_soc->dev_base_addr + (scale * WINDOW_START) + 1364 (offset & WINDOW_RANGE_MASK); 1365 } 1366 1367 /** 1368 * hal_rx_get_fisa_cumulative_l4_checksum_6750() - Retrieve cumulative 1369 * checksum 1370 * @buf: buffer pointer 1371 * 1372 * Return: cumulative checksum 1373 */ 1374 static inline 1375 uint16_t hal_rx_get_fisa_cumulative_l4_checksum_6750(uint8_t *buf) 1376 { 1377 return HAL_RX_TLV_GET_FISA_CUMULATIVE_L4_CHECKSUM(buf); 1378 } 1379 1380 /** 1381 * hal_rx_get_fisa_cumulative_ip_length_6750() - Retrieve cumulative 1382 * ip length 1383 * @buf: buffer pointer 1384 * 1385 * Return: cumulative length 1386 */ 1387 static inline 1388 uint16_t hal_rx_get_fisa_cumulative_ip_length_6750(uint8_t *buf) 1389 { 1390 return HAL_RX_TLV_GET_FISA_CUMULATIVE_IP_LENGTH(buf); 1391 } 1392 1393 /** 1394 * hal_rx_get_udp_proto_6750() - Retrieve udp proto value 1395 * @buf: buffer 1396 * 1397 * Return: udp proto bit 1398 */ 1399 static inline 1400 bool hal_rx_get_udp_proto_6750(uint8_t *buf) 1401 { 1402 return HAL_RX_TLV_GET_UDP_PROTO(buf); 1403 } 1404 1405 /** 1406 * hal_rx_get_flow_agg_continuation_6750() - retrieve flow agg 1407 * continuation 1408 * @buf: buffer 1409 * 1410 * Return: flow agg 1411 */ 1412 static inline 1413 bool hal_rx_get_flow_agg_continuation_6750(uint8_t *buf) 1414 { 1415 return HAL_RX_TLV_GET_FLOW_AGGR_CONT(buf); 1416 } 1417 1418 /** 1419 * hal_rx_get_flow_agg_count_6750()- Retrieve flow agg count 1420 * @buf: buffer 1421 * 1422 * Return: flow agg count 1423 */ 1424 static inline 1425 uint8_t hal_rx_get_flow_agg_count_6750(uint8_t *buf) 1426 { 1427 return HAL_RX_TLV_GET_FLOW_AGGR_COUNT(buf); 1428 } 1429 1430 /** 1431 * hal_rx_get_fisa_timeout_6750() - Retrieve fisa timeout 1432 * @buf: buffer 1433 * 1434 * Return: fisa timeout 1435 */ 1436 static inline 1437 bool hal_rx_get_fisa_timeout_6750(uint8_t *buf) 1438 { 1439 return HAL_RX_TLV_GET_FISA_TIMEOUT(buf); 1440 } 1441 1442 /** 1443 * hal_rx_mpdu_start_tlv_tag_valid_6750 () - API to check if RX_MPDU_START 1444 * tlv tag is valid 1445 * 1446 *@rx_tlv_hdr: start address of rx_pkt_tlvs 1447 * 1448 * Return: true if RX_MPDU_START is valied, else false. 1449 */ 1450 static uint8_t hal_rx_mpdu_start_tlv_tag_valid_6750(void *rx_tlv_hdr) 1451 { 1452 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)rx_tlv_hdr; 1453 uint32_t tlv_tag; 1454 1455 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(&rx_desc->mpdu_start_tlv); 1456 1457 return tlv_tag == WIFIRX_MPDU_START_E ? true : false; 1458 } 1459 1460 /** 1461 * hal_reo_set_err_dst_remap_6750(): Function to set REO error destination 1462 * ring remap register 1463 * @hal_soc: Pointer to hal_soc 1464 * 1465 * Return: none. 1466 */ 1467 static void 1468 hal_reo_set_err_dst_remap_6750(void *hal_soc) 1469 { 1470 /* 1471 * Set REO error 2k jump (error code 5) / OOR (error code 7) 1472 * frame routed to REO2TCL ring. 1473 */ 1474 uint32_t dst_remap_ix0 = 1475 HAL_REO_ERR_REMAP_IX0(REO_REMAP_RELEASE, 0) | 1476 HAL_REO_ERR_REMAP_IX0(REO_REMAP_RELEASE, 1) | 1477 HAL_REO_ERR_REMAP_IX0(REO_REMAP_RELEASE, 2) | 1478 HAL_REO_ERR_REMAP_IX0(REO_REMAP_RELEASE, 3) | 1479 HAL_REO_ERR_REMAP_IX0(REO_REMAP_RELEASE, 4) | 1480 HAL_REO_ERR_REMAP_IX0(REO_REMAP_TCL, 5) | 1481 HAL_REO_ERR_REMAP_IX0(REO_REMAP_RELEASE, 6) | 1482 HAL_REO_ERR_REMAP_IX0(REO_REMAP_TCL, 7); 1483 1484 HAL_REG_WRITE(hal_soc, 1485 HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ADDR( 1486 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1487 dst_remap_ix0); 1488 1489 hal_info("HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0 0x%x", 1490 HAL_REG_READ( 1491 hal_soc, 1492 HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ADDR( 1493 SEQ_WCSS_UMAC_REO_REG_OFFSET))); 1494 } 1495 1496 /* 1497 * hal_rx_flow_setup_fse_6750() - Setup a flow search entry in HW FST 1498 * @fst: Pointer to the Rx Flow Search Table 1499 * @table_offset: offset into the table where the flow is to be setup 1500 * @flow: Flow Parameters 1501 * 1502 * Flow table entry fields are updated in host byte order, little endian order. 1503 * 1504 * Return: Success/Failure 1505 */ 1506 static void * 1507 hal_rx_flow_setup_fse_6750(uint8_t *rx_fst, uint32_t table_offset, 1508 uint8_t *rx_flow) 1509 { 1510 struct hal_rx_fst *fst = (struct hal_rx_fst *)rx_fst; 1511 struct hal_rx_flow *flow = (struct hal_rx_flow *)rx_flow; 1512 uint8_t *fse; 1513 bool fse_valid; 1514 1515 if (table_offset >= fst->max_entries) { 1516 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR, 1517 "HAL FSE table offset %u exceeds max entries %u", 1518 table_offset, fst->max_entries); 1519 return NULL; 1520 } 1521 1522 fse = (uint8_t *)fst->base_vaddr + 1523 (table_offset * HAL_RX_FST_ENTRY_SIZE); 1524 1525 fse_valid = HAL_GET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, VALID); 1526 1527 if (fse_valid) { 1528 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_DEBUG, 1529 "HAL FSE %pK already valid", fse); 1530 return NULL; 1531 } 1532 1533 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_0, SRC_IP_127_96) = 1534 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_0, SRC_IP_127_96, 1535 (flow->tuple_info.src_ip_127_96)); 1536 1537 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_1, SRC_IP_95_64) = 1538 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_1, SRC_IP_95_64, 1539 (flow->tuple_info.src_ip_95_64)); 1540 1541 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_2, SRC_IP_63_32) = 1542 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_2, SRC_IP_63_32, 1543 (flow->tuple_info.src_ip_63_32)); 1544 1545 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_3, SRC_IP_31_0) = 1546 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_3, SRC_IP_31_0, 1547 (flow->tuple_info.src_ip_31_0)); 1548 1549 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_4, DEST_IP_127_96) = 1550 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_4, DEST_IP_127_96, 1551 (flow->tuple_info.dest_ip_127_96)); 1552 1553 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_5, DEST_IP_95_64) = 1554 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_5, DEST_IP_95_64, 1555 (flow->tuple_info.dest_ip_95_64)); 1556 1557 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_6, DEST_IP_63_32) = 1558 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_6, DEST_IP_63_32, 1559 (flow->tuple_info.dest_ip_63_32)); 1560 1561 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_7, DEST_IP_31_0) = 1562 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_7, DEST_IP_31_0, 1563 (flow->tuple_info.dest_ip_31_0)); 1564 1565 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, DEST_PORT); 1566 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, DEST_PORT) |= 1567 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_8, DEST_PORT, 1568 (flow->tuple_info.dest_port)); 1569 1570 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, SRC_PORT); 1571 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, SRC_PORT) |= 1572 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_8, SRC_PORT, 1573 (flow->tuple_info.src_port)); 1574 1575 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, L4_PROTOCOL); 1576 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, L4_PROTOCOL) |= 1577 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, L4_PROTOCOL, 1578 flow->tuple_info.l4_protocol); 1579 1580 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_HANDLER); 1581 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_HANDLER) |= 1582 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_HANDLER, 1583 flow->reo_destination_handler); 1584 1585 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, VALID); 1586 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, VALID) |= 1587 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, VALID, 1); 1588 1589 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_10, METADATA); 1590 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_10, METADATA) = 1591 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_10, METADATA, 1592 (flow->fse_metadata)); 1593 1594 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_INDICATION); 1595 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_INDICATION) |= 1596 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, 1597 REO_DESTINATION_INDICATION, 1598 flow->reo_destination_indication); 1599 1600 /* Reset all the other fields in FSE */ 1601 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, RESERVED_9); 1602 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, MSDU_DROP); 1603 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_11, MSDU_COUNT); 1604 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_12, MSDU_BYTE_COUNT); 1605 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_13, TIMESTAMP); 1606 1607 return fse; 1608 } 1609 1610 /* 1611 * hal_rx_flow_setup_cmem_fse_6750() - Setup a flow search entry in HW CMEM FST 1612 * @hal_soc: hal_soc reference 1613 * @cmem_ba: CMEM base address 1614 * @table_offset: offset into the table where the flow is to be setup 1615 * @flow: Flow Parameters 1616 * 1617 * Return: Success/Failure 1618 */ 1619 static uint32_t 1620 hal_rx_flow_setup_cmem_fse_6750(struct hal_soc *hal_soc, uint32_t cmem_ba, 1621 uint32_t table_offset, uint8_t *rx_flow) 1622 { 1623 struct hal_rx_flow *flow = (struct hal_rx_flow *)rx_flow; 1624 uint32_t fse_offset; 1625 uint32_t value; 1626 1627 fse_offset = cmem_ba + (table_offset * HAL_RX_FST_ENTRY_SIZE); 1628 1629 /* Reset the Valid bit */ 1630 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY_9, 1631 VALID), 0); 1632 1633 value = HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_0, SRC_IP_127_96, 1634 (flow->tuple_info.src_ip_127_96)); 1635 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY_0, 1636 SRC_IP_127_96), value); 1637 1638 value = HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_1, SRC_IP_95_64, 1639 (flow->tuple_info.src_ip_95_64)); 1640 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY_1, 1641 SRC_IP_95_64), value); 1642 1643 value = HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_2, SRC_IP_63_32, 1644 (flow->tuple_info.src_ip_63_32)); 1645 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY_2, 1646 SRC_IP_63_32), value); 1647 1648 value = HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_3, SRC_IP_31_0, 1649 (flow->tuple_info.src_ip_31_0)); 1650 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY_3, 1651 SRC_IP_31_0), value); 1652 1653 value = HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_4, DEST_IP_127_96, 1654 (flow->tuple_info.dest_ip_127_96)); 1655 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY_4, 1656 DEST_IP_127_96), value); 1657 1658 value = HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_5, DEST_IP_95_64, 1659 (flow->tuple_info.dest_ip_95_64)); 1660 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY_5, 1661 DEST_IP_95_64), value); 1662 1663 value = HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_6, DEST_IP_63_32, 1664 (flow->tuple_info.dest_ip_63_32)); 1665 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY_6, 1666 DEST_IP_63_32), value); 1667 1668 value = HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_7, DEST_IP_31_0, 1669 (flow->tuple_info.dest_ip_31_0)); 1670 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY_7, 1671 DEST_IP_31_0), value); 1672 1673 value = 0 | HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_8, DEST_PORT, 1674 (flow->tuple_info.dest_port)); 1675 value |= HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_8, SRC_PORT, 1676 (flow->tuple_info.src_port)); 1677 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY_8, 1678 SRC_PORT), value); 1679 1680 value = HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_10, METADATA, 1681 (flow->fse_metadata)); 1682 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY_10, 1683 METADATA), value); 1684 1685 /* Reset all the other fields in FSE */ 1686 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY_11, 1687 MSDU_COUNT), 0); 1688 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY_12, 1689 MSDU_BYTE_COUNT), 0); 1690 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY_13, 1691 TIMESTAMP), 0); 1692 1693 value = 0 | HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, L4_PROTOCOL, 1694 flow->tuple_info.l4_protocol); 1695 value |= HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_HANDLER, 1696 flow->reo_destination_handler); 1697 value |= HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, 1698 REO_DESTINATION_INDICATION, 1699 flow->reo_destination_indication); 1700 value |= HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, VALID, 1); 1701 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY_9, 1702 L4_PROTOCOL), value); 1703 1704 return fse_offset; 1705 } 1706 1707 /** 1708 * hal_rx_flow_get_cmem_fse_ts_6750() - Get timestamp field from CMEM FSE 1709 * @hal_soc: hal_soc reference 1710 * @fse_offset: CMEM FSE offset 1711 * 1712 * Return: Timestamp 1713 */ 1714 static uint32_t hal_rx_flow_get_cmem_fse_ts_6750(struct hal_soc *hal_soc, 1715 uint32_t fse_offset) 1716 { 1717 return HAL_CMEM_READ(hal_soc, fse_offset + 1718 HAL_OFFSET(RX_FLOW_SEARCH_ENTRY_13, TIMESTAMP)); 1719 } 1720 1721 /** 1722 * hal_rx_flow_get_cmem_fse_6750() - Get FSE from CMEM 1723 * @hal_soc: hal_soc reference 1724 * @fse_offset: CMEM FSE offset 1725 * @fse: referece where FSE will be copied 1726 * @len: length of FSE 1727 * 1728 * Return: If read is succesfull or not 1729 */ 1730 static void 1731 hal_rx_flow_get_cmem_fse_6750(struct hal_soc *hal_soc, uint32_t fse_offset, 1732 uint32_t *fse, qdf_size_t len) 1733 { 1734 int i; 1735 1736 if (len != HAL_RX_FST_ENTRY_SIZE) 1737 return; 1738 1739 for (i = 0; i < NUM_OF_DWORDS_RX_FLOW_SEARCH_ENTRY; i++) 1740 fse[i] = HAL_CMEM_READ(hal_soc, fse_offset + i * 4); 1741 } 1742 1743 /** 1744 * hal_rx_msdu_get_reo_destination_indication_6750: API to get 1745 * reo_destination_indication from rx_msdu_end TLV 1746 * @buf: pointer to the start of RX PKT TLV headers 1747 * @reo_destination_indication: pointer to return value of reo_destination_indication 1748 * 1749 * Return: none 1750 */ 1751 static void 1752 hal_rx_msdu_get_reo_destination_indication_6750(uint8_t *buf, 1753 uint32_t *reo_destination_indication) 1754 { 1755 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1756 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1757 1758 *reo_destination_indication = HAL_RX_MSDU_END_REO_DEST_IND_GET(msdu_end); 1759 } 1760 1761 static 1762 void hal_compute_reo_remap_ix2_ix3_6750(uint32_t *ring, uint32_t num_rings, 1763 uint32_t *remap1, uint32_t *remap2) 1764 { 1765 switch (num_rings) { 1766 case 3: 1767 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 1768 HAL_REO_REMAP_IX2(ring[1], 17) | 1769 HAL_REO_REMAP_IX2(ring[2], 18) | 1770 HAL_REO_REMAP_IX2(ring[0], 19) | 1771 HAL_REO_REMAP_IX2(ring[1], 20) | 1772 HAL_REO_REMAP_IX2(ring[2], 21) | 1773 HAL_REO_REMAP_IX2(ring[0], 22) | 1774 HAL_REO_REMAP_IX2(ring[1], 23); 1775 1776 *remap2 = HAL_REO_REMAP_IX3(ring[2], 24) | 1777 HAL_REO_REMAP_IX3(ring[0], 25) | 1778 HAL_REO_REMAP_IX3(ring[1], 26) | 1779 HAL_REO_REMAP_IX3(ring[2], 27) | 1780 HAL_REO_REMAP_IX3(ring[0], 28) | 1781 HAL_REO_REMAP_IX3(ring[1], 29) | 1782 HAL_REO_REMAP_IX3(ring[2], 30) | 1783 HAL_REO_REMAP_IX3(ring[0], 31); 1784 break; 1785 case 4: 1786 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 1787 HAL_REO_REMAP_IX2(ring[1], 17) | 1788 HAL_REO_REMAP_IX2(ring[2], 18) | 1789 HAL_REO_REMAP_IX2(ring[3], 19) | 1790 HAL_REO_REMAP_IX2(ring[0], 20) | 1791 HAL_REO_REMAP_IX2(ring[1], 21) | 1792 HAL_REO_REMAP_IX2(ring[2], 22) | 1793 HAL_REO_REMAP_IX2(ring[3], 23); 1794 1795 *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) | 1796 HAL_REO_REMAP_IX3(ring[1], 25) | 1797 HAL_REO_REMAP_IX3(ring[2], 26) | 1798 HAL_REO_REMAP_IX3(ring[3], 27) | 1799 HAL_REO_REMAP_IX3(ring[0], 28) | 1800 HAL_REO_REMAP_IX3(ring[1], 29) | 1801 HAL_REO_REMAP_IX3(ring[2], 30) | 1802 HAL_REO_REMAP_IX3(ring[3], 31); 1803 break; 1804 } 1805 } 1806 1807 struct hal_hw_txrx_ops qca6750_hal_hw_txrx_ops = { 1808 /* init and setup */ 1809 hal_srng_dst_hw_init_generic, 1810 hal_srng_src_hw_init_generic, 1811 hal_get_hw_hptp_generic, 1812 hal_reo_setup_generic, 1813 hal_setup_link_idle_list_generic, 1814 hal_get_window_address_6750, 1815 hal_reo_set_err_dst_remap_6750, 1816 1817 /* tx */ 1818 hal_tx_desc_set_dscp_tid_table_id_6750, 1819 hal_tx_set_dscp_tid_map_6750, 1820 hal_tx_update_dscp_tid_6750, 1821 hal_tx_desc_set_lmac_id_6750, 1822 hal_tx_desc_set_buf_addr_generic, 1823 hal_tx_desc_set_search_type_generic, 1824 hal_tx_desc_set_search_index_generic, 1825 hal_tx_desc_set_cache_set_num_generic, 1826 hal_tx_comp_get_status_generic, 1827 hal_tx_comp_get_release_reason_generic, 1828 hal_get_wbm_internal_error_generic, 1829 hal_tx_desc_set_mesh_en_6750, 1830 hal_tx_init_cmd_credit_ring_6750, 1831 1832 /* rx */ 1833 hal_rx_msdu_start_nss_get_6750, 1834 hal_rx_mon_hw_desc_get_mpdu_status_6750, 1835 hal_rx_get_tlv_6750, 1836 hal_rx_proc_phyrx_other_receive_info_tlv_6750, 1837 hal_rx_dump_msdu_start_tlv_6750, 1838 hal_rx_dump_msdu_end_tlv_6750, 1839 hal_get_link_desc_size_6750, 1840 hal_rx_mpdu_start_tid_get_6750, 1841 hal_rx_msdu_start_reception_type_get_6750, 1842 hal_rx_msdu_end_da_idx_get_6750, 1843 hal_rx_msdu_desc_info_get_ptr_6750, 1844 hal_rx_link_desc_msdu0_ptr_6750, 1845 hal_reo_status_get_header_6750, 1846 hal_rx_status_get_tlv_info_generic, 1847 hal_rx_wbm_err_info_get_generic, 1848 hal_rx_dump_mpdu_start_tlv_generic, 1849 1850 hal_tx_set_pcp_tid_map_generic, 1851 hal_tx_update_pcp_tid_generic, 1852 hal_tx_update_tidmap_prty_generic, 1853 hal_rx_get_rx_fragment_number_6750, 1854 hal_rx_msdu_end_da_is_mcbc_get_6750, 1855 hal_rx_msdu_end_sa_is_valid_get_6750, 1856 hal_rx_msdu_end_sa_idx_get_6750, 1857 hal_rx_desc_is_first_msdu_6750, 1858 hal_rx_msdu_end_l3_hdr_padding_get_6750, 1859 hal_rx_encryption_info_valid_6750, 1860 hal_rx_print_pn_6750, 1861 hal_rx_msdu_end_first_msdu_get_6750, 1862 hal_rx_msdu_end_da_is_valid_get_6750, 1863 hal_rx_msdu_end_last_msdu_get_6750, 1864 hal_rx_get_mpdu_mac_ad4_valid_6750, 1865 hal_rx_mpdu_start_sw_peer_id_get_6750, 1866 hal_rx_mpdu_get_to_ds_6750, 1867 hal_rx_mpdu_get_fr_ds_6750, 1868 hal_rx_get_mpdu_frame_control_valid_6750, 1869 hal_rx_mpdu_get_addr1_6750, 1870 hal_rx_mpdu_get_addr2_6750, 1871 hal_rx_mpdu_get_addr3_6750, 1872 hal_rx_mpdu_get_addr4_6750, 1873 hal_rx_get_mpdu_sequence_control_valid_6750, 1874 hal_rx_is_unicast_6750, 1875 hal_rx_tid_get_6750, 1876 hal_rx_hw_desc_get_ppduid_get_6750, 1877 NULL, 1878 NULL, 1879 hal_rx_msdu0_buffer_addr_lsb_6750, 1880 hal_rx_msdu_desc_info_ptr_get_6750, 1881 hal_ent_mpdu_desc_info_6750, 1882 hal_dst_mpdu_desc_info_6750, 1883 hal_rx_get_fc_valid_6750, 1884 hal_rx_get_to_ds_flag_6750, 1885 hal_rx_get_mac_addr2_valid_6750, 1886 hal_rx_get_filter_category_6750, 1887 hal_rx_get_ppdu_id_6750, 1888 hal_reo_config_6750, 1889 hal_rx_msdu_flow_idx_get_6750, 1890 hal_rx_msdu_flow_idx_invalid_6750, 1891 hal_rx_msdu_flow_idx_timeout_6750, 1892 hal_rx_msdu_fse_metadata_get_6750, 1893 hal_rx_msdu_cce_metadata_get_6750, 1894 hal_rx_msdu_get_flow_params_6750, 1895 hal_rx_tlv_get_tcp_chksum_6750, 1896 hal_rx_get_rx_sequence_6750, 1897 #if defined(QCA_WIFI_QCA6750) && defined(WLAN_CFR_ENABLE) && \ 1898 defined(WLAN_ENH_CFR_ENABLE) 1899 hal_rx_get_bb_info_6750, 1900 hal_rx_get_rtt_info_6750, 1901 #else 1902 NULL, 1903 NULL, 1904 #endif 1905 /* rx - msdu end fast path info fields */ 1906 hal_rx_msdu_packet_metadata_get_generic, 1907 hal_rx_get_fisa_cumulative_l4_checksum_6750, 1908 hal_rx_get_fisa_cumulative_ip_length_6750, 1909 hal_rx_get_udp_proto_6750, 1910 hal_rx_get_flow_agg_continuation_6750, 1911 hal_rx_get_flow_agg_count_6750, 1912 hal_rx_get_fisa_timeout_6750, 1913 hal_rx_mpdu_start_tlv_tag_valid_6750, 1914 NULL, 1915 NULL, 1916 1917 /* rx - TLV struct offsets */ 1918 hal_rx_msdu_end_offset_get_generic, 1919 hal_rx_attn_offset_get_generic, 1920 hal_rx_msdu_start_offset_get_generic, 1921 hal_rx_mpdu_start_offset_get_generic, 1922 hal_rx_mpdu_end_offset_get_generic, 1923 hal_rx_flow_setup_fse_6750, 1924 hal_compute_reo_remap_ix2_ix3_6750, 1925 1926 /* CMEM FSE */ 1927 hal_rx_flow_setup_cmem_fse_6750, 1928 hal_rx_flow_get_cmem_fse_ts_6750, 1929 hal_rx_flow_get_cmem_fse_6750, 1930 hal_rx_msdu_get_reo_destination_indication_6750 1931 }; 1932 1933 struct hal_hw_srng_config hw_srng_table_6750[] = { 1934 /* TODO: max_rings can populated by querying HW capabilities */ 1935 { /* REO_DST */ 1936 .start_ring_id = HAL_SRNG_REO2SW1, 1937 .max_rings = 4, 1938 .entry_size = sizeof(struct reo_destination_ring) >> 2, 1939 .lmac_ring = FALSE, 1940 .ring_dir = HAL_SRNG_DST_RING, 1941 .reg_start = { 1942 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR( 1943 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1944 HWIO_REO_R2_REO2SW1_RING_HP_ADDR( 1945 SEQ_WCSS_UMAC_REO_REG_OFFSET) 1946 }, 1947 .reg_size = { 1948 HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(0) - 1949 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(0), 1950 HWIO_REO_R2_REO2SW2_RING_HP_ADDR(0) - 1951 HWIO_REO_R2_REO2SW1_RING_HP_ADDR(0), 1952 }, 1953 .max_size = 1954 HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_BMSK >> 1955 HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_SHFT, 1956 }, 1957 { /* REO_EXCEPTION */ 1958 /* Designating REO2TCL ring as exception ring. This ring is 1959 * similar to other REO2SW rings though it is named as REO2TCL. 1960 * Any of theREO2SW rings can be used as exception ring. 1961 */ 1962 .start_ring_id = HAL_SRNG_REO2TCL, 1963 .max_rings = 1, 1964 .entry_size = sizeof(struct reo_destination_ring) >> 2, 1965 .lmac_ring = FALSE, 1966 .ring_dir = HAL_SRNG_DST_RING, 1967 .reg_start = { 1968 HWIO_REO_R0_REO2TCL_RING_BASE_LSB_ADDR( 1969 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1970 HWIO_REO_R2_REO2TCL_RING_HP_ADDR( 1971 SEQ_WCSS_UMAC_REO_REG_OFFSET) 1972 }, 1973 /* Single ring - provide ring size if multiple rings of this 1974 * type are supported 1975 */ 1976 .reg_size = {}, 1977 .max_size = 1978 HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_BMSK >> 1979 HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_SHFT, 1980 }, 1981 { /* REO_REINJECT */ 1982 .start_ring_id = HAL_SRNG_SW2REO, 1983 .max_rings = 1, 1984 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 1985 .lmac_ring = FALSE, 1986 .ring_dir = HAL_SRNG_SRC_RING, 1987 .reg_start = { 1988 HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR( 1989 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1990 HWIO_REO_R2_SW2REO_RING_HP_ADDR( 1991 SEQ_WCSS_UMAC_REO_REG_OFFSET) 1992 }, 1993 /* Single ring - provide ring size if multiple rings of this 1994 * type are supported 1995 */ 1996 .reg_size = {}, 1997 .max_size = HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_BMSK >> 1998 HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_SHFT, 1999 }, 2000 { /* REO_CMD */ 2001 .start_ring_id = HAL_SRNG_REO_CMD, 2002 .max_rings = 1, 2003 .entry_size = (sizeof(struct tlv_32_hdr) + 2004 sizeof(struct reo_get_queue_stats)) >> 2, 2005 .lmac_ring = FALSE, 2006 .ring_dir = HAL_SRNG_SRC_RING, 2007 .reg_start = { 2008 HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR( 2009 SEQ_WCSS_UMAC_REO_REG_OFFSET), 2010 HWIO_REO_R2_REO_CMD_RING_HP_ADDR( 2011 SEQ_WCSS_UMAC_REO_REG_OFFSET), 2012 }, 2013 /* Single ring - provide ring size if multiple rings of this 2014 * type are supported 2015 */ 2016 .reg_size = {}, 2017 .max_size = 2018 HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_BMSK >> 2019 HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_SHFT, 2020 }, 2021 { /* REO_STATUS */ 2022 .start_ring_id = HAL_SRNG_REO_STATUS, 2023 .max_rings = 1, 2024 .entry_size = (sizeof(struct tlv_32_hdr) + 2025 sizeof(struct reo_get_queue_stats_status)) >> 2, 2026 .lmac_ring = FALSE, 2027 .ring_dir = HAL_SRNG_DST_RING, 2028 .reg_start = { 2029 HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR( 2030 SEQ_WCSS_UMAC_REO_REG_OFFSET), 2031 HWIO_REO_R2_REO_STATUS_RING_HP_ADDR( 2032 SEQ_WCSS_UMAC_REO_REG_OFFSET), 2033 }, 2034 /* Single ring - provide ring size if multiple rings of this 2035 * type are supported 2036 */ 2037 .reg_size = {}, 2038 .max_size = 2039 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> 2040 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, 2041 }, 2042 { /* TCL_DATA */ 2043 .start_ring_id = HAL_SRNG_SW2TCL1, 2044 .max_rings = 3, 2045 .entry_size = (sizeof(struct tlv_32_hdr) + 2046 sizeof(struct tcl_data_cmd)) >> 2, 2047 .lmac_ring = FALSE, 2048 .ring_dir = HAL_SRNG_SRC_RING, 2049 .reg_start = { 2050 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR( 2051 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 2052 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR( 2053 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 2054 }, 2055 .reg_size = { 2056 HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(0) - 2057 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(0), 2058 HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(0) - 2059 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(0), 2060 }, 2061 .max_size = 2062 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK >> 2063 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT, 2064 }, 2065 { /* TCL_CMD */ 2066 .start_ring_id = HAL_SRNG_SW2TCL_CMD, 2067 .max_rings = 1, 2068 .entry_size = (sizeof(struct tlv_32_hdr) + 2069 sizeof(struct tcl_gse_cmd)) >> 2, 2070 .lmac_ring = FALSE, 2071 .ring_dir = HAL_SRNG_SRC_RING, 2072 .reg_start = { 2073 HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_ADDR( 2074 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 2075 HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_ADDR( 2076 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 2077 }, 2078 /* Single ring - provide ring size if multiple rings of this 2079 * type are supported 2080 */ 2081 .reg_size = {}, 2082 .max_size = 2083 HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_SIZE_BMSK >> 2084 HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_SIZE_SHFT, 2085 }, 2086 { /* TCL_STATUS */ 2087 .start_ring_id = HAL_SRNG_TCL_STATUS, 2088 .max_rings = 1, 2089 .entry_size = (sizeof(struct tlv_32_hdr) + 2090 sizeof(struct tcl_status_ring)) >> 2, 2091 .lmac_ring = FALSE, 2092 .ring_dir = HAL_SRNG_DST_RING, 2093 .reg_start = { 2094 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR( 2095 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 2096 HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR( 2097 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 2098 }, 2099 /* Single ring - provide ring size if multiple rings of this 2100 * type are supported 2101 */ 2102 .reg_size = {}, 2103 .max_size = 2104 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_BMSK >> 2105 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_SHFT, 2106 }, 2107 { /* CE_SRC */ 2108 .start_ring_id = HAL_SRNG_CE_0_SRC, 2109 .max_rings = 12, 2110 .entry_size = sizeof(struct ce_src_desc) >> 2, 2111 .lmac_ring = FALSE, 2112 .ring_dir = HAL_SRNG_SRC_RING, 2113 .reg_start = { 2114 HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR, 2115 HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR, 2116 }, 2117 .reg_size = { 2118 HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR - 2119 HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR, 2120 HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR - 2121 HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR, 2122 }, 2123 .max_size = 2124 HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >> 2125 HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT 2126 }, 2127 { /* CE_DST */ 2128 .start_ring_id = HAL_SRNG_CE_0_DST, 2129 .max_rings = 12, 2130 .entry_size = 8 >> 2, 2131 /*TODO: entry_size above should actually be 2132 * sizeof(struct ce_dst_desc) >> 2, but couldn't find definition 2133 * of struct ce_dst_desc in HW header files 2134 */ 2135 .lmac_ring = FALSE, 2136 .ring_dir = HAL_SRNG_SRC_RING, 2137 .reg_start = { 2138 HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, 2139 HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR, 2140 }, 2141 .reg_size = { 2142 HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR - 2143 HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, 2144 HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR - 2145 HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR 2146 }, 2147 .max_size = 2148 HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >> 2149 HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT 2150 }, 2151 { /* CE_DST_STATUS */ 2152 .start_ring_id = HAL_SRNG_CE_0_DST_STATUS, 2153 .max_rings = 12, 2154 .entry_size = sizeof(struct ce_stat_desc) >> 2, 2155 .lmac_ring = FALSE, 2156 .ring_dir = HAL_SRNG_DST_RING, 2157 .reg_start = { 2158 HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR, 2159 HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR, 2160 }, 2161 /* TODO: check destination status ring registers */ 2162 .reg_size = { 2163 HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR - 2164 HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, 2165 HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR - 2166 HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR 2167 }, 2168 .max_size = 2169 HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> 2170 HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, 2171 }, 2172 { /* WBM_IDLE_LINK */ 2173 .start_ring_id = HAL_SRNG_WBM_IDLE_LINK, 2174 .max_rings = 1, 2175 .entry_size = sizeof(struct wbm_link_descriptor_ring) >> 2, 2176 .lmac_ring = FALSE, 2177 .ring_dir = HAL_SRNG_SRC_RING, 2178 .reg_start = { 2179 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2180 HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2181 }, 2182 /* Single ring - provide ring size if multiple rings of this 2183 * type are supported 2184 */ 2185 .reg_size = {}, 2186 .max_size = 2187 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_BMSK >> 2188 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_SHFT, 2189 }, 2190 { /* SW2WBM_RELEASE */ 2191 .start_ring_id = HAL_SRNG_WBM_SW_RELEASE, 2192 .max_rings = 1, 2193 .entry_size = sizeof(struct wbm_release_ring) >> 2, 2194 .lmac_ring = FALSE, 2195 .ring_dir = HAL_SRNG_SRC_RING, 2196 .reg_start = { 2197 HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2198 HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2199 }, 2200 /* Single ring - provide ring size if multiple rings of this 2201 * type are supported 2202 */ 2203 .reg_size = {}, 2204 .max_size = 2205 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> 2206 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, 2207 }, 2208 { /* WBM2SW_RELEASE */ 2209 .start_ring_id = HAL_SRNG_WBM2SW0_RELEASE, 2210 .max_rings = 4, 2211 .entry_size = sizeof(struct wbm_release_ring) >> 2, 2212 .lmac_ring = FALSE, 2213 .ring_dir = HAL_SRNG_DST_RING, 2214 .reg_start = { 2215 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2216 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2217 }, 2218 .reg_size = { 2219 HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) - 2220 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2221 HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) - 2222 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2223 }, 2224 .max_size = 2225 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> 2226 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, 2227 }, 2228 { /* RXDMA_BUF */ 2229 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA0_BUF0, 2230 #ifdef IPA_OFFLOAD 2231 .max_rings = 3, 2232 #else 2233 .max_rings = 2, 2234 #endif 2235 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 2236 .lmac_ring = TRUE, 2237 .ring_dir = HAL_SRNG_SRC_RING, 2238 /* reg_start is not set because LMAC rings are not accessed 2239 * from host 2240 */ 2241 .reg_start = {}, 2242 .reg_size = {}, 2243 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2244 }, 2245 { /* RXDMA_DST */ 2246 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW0, 2247 .max_rings = 1, 2248 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 2249 .lmac_ring = TRUE, 2250 .ring_dir = HAL_SRNG_DST_RING, 2251 /* reg_start is not set because LMAC rings are not accessed 2252 * from host 2253 */ 2254 .reg_start = {}, 2255 .reg_size = {}, 2256 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2257 }, 2258 { /* RXDMA_MONITOR_BUF */ 2259 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA2_BUF, 2260 .max_rings = 1, 2261 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 2262 .lmac_ring = TRUE, 2263 .ring_dir = HAL_SRNG_SRC_RING, 2264 /* reg_start is not set because LMAC rings are not accessed 2265 * from host 2266 */ 2267 .reg_start = {}, 2268 .reg_size = {}, 2269 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2270 }, 2271 { /* RXDMA_MONITOR_STATUS */ 2272 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_STATBUF, 2273 .max_rings = 1, 2274 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 2275 .lmac_ring = TRUE, 2276 .ring_dir = HAL_SRNG_SRC_RING, 2277 /* reg_start is not set because LMAC rings are not accessed 2278 * from host 2279 */ 2280 .reg_start = {}, 2281 .reg_size = {}, 2282 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2283 }, 2284 { /* RXDMA_MONITOR_DST */ 2285 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW1, 2286 .max_rings = 1, 2287 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 2288 .lmac_ring = TRUE, 2289 .ring_dir = HAL_SRNG_DST_RING, 2290 /* reg_start is not set because LMAC rings are not accessed 2291 * from host 2292 */ 2293 .reg_start = {}, 2294 .reg_size = {}, 2295 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2296 }, 2297 { /* RXDMA_MONITOR_DESC */ 2298 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_DESC, 2299 .max_rings = 1, 2300 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 2301 .lmac_ring = TRUE, 2302 .ring_dir = HAL_SRNG_SRC_RING, 2303 /* reg_start is not set because LMAC rings are not accessed 2304 * from host 2305 */ 2306 .reg_start = {}, 2307 .reg_size = {}, 2308 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2309 }, 2310 { /* DIR_BUF_RX_DMA_SRC */ 2311 .start_ring_id = HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING, 2312 /* 2313 * one ring is for spectral scan 2314 * the other is for cfr 2315 */ 2316 .max_rings = 2, 2317 .entry_size = 2, 2318 .lmac_ring = TRUE, 2319 .ring_dir = HAL_SRNG_SRC_RING, 2320 /* reg_start is not set because LMAC rings are not accessed 2321 * from host 2322 */ 2323 .reg_start = {}, 2324 .reg_size = {}, 2325 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2326 }, 2327 #ifdef WLAN_FEATURE_CIF_CFR 2328 { /* WIFI_POS_SRC */ 2329 .start_ring_id = HAL_SRNG_WIFI_POS_SRC_DMA_RING, 2330 .max_rings = 1, 2331 .entry_size = sizeof(wmi_oem_dma_buf_release_entry) >> 2, 2332 .lmac_ring = TRUE, 2333 .ring_dir = HAL_SRNG_SRC_RING, 2334 /* reg_start is not set because LMAC rings are not accessed 2335 * from host 2336 */ 2337 .reg_start = {}, 2338 .reg_size = {}, 2339 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2340 }, 2341 #endif 2342 }; 2343 2344 int32_t hal_hw_reg_offset_qca6750[] = { 2345 /* dst */ 2346 REG_OFFSET(DST, HP), 2347 REG_OFFSET(DST, TP), 2348 REG_OFFSET(DST, ID), 2349 REG_OFFSET(DST, MISC), 2350 REG_OFFSET(DST, HP_ADDR_LSB), 2351 REG_OFFSET(DST, HP_ADDR_MSB), 2352 REG_OFFSET(DST, MSI1_BASE_LSB), 2353 REG_OFFSET(DST, MSI1_BASE_MSB), 2354 REG_OFFSET(DST, MSI1_DATA), 2355 REG_OFFSET(DST, BASE_LSB), 2356 REG_OFFSET(DST, BASE_MSB), 2357 REG_OFFSET(DST, PRODUCER_INT_SETUP), 2358 /* src */ 2359 REG_OFFSET(SRC, HP), 2360 REG_OFFSET(SRC, TP), 2361 REG_OFFSET(SRC, ID), 2362 REG_OFFSET(SRC, MISC), 2363 REG_OFFSET(SRC, TP_ADDR_LSB), 2364 REG_OFFSET(SRC, TP_ADDR_MSB), 2365 REG_OFFSET(SRC, MSI1_BASE_LSB), 2366 REG_OFFSET(SRC, MSI1_BASE_MSB), 2367 REG_OFFSET(SRC, MSI1_DATA), 2368 REG_OFFSET(SRC, BASE_LSB), 2369 REG_OFFSET(SRC, BASE_MSB), 2370 REG_OFFSET(SRC, CONSUMER_INT_SETUP_IX0), 2371 REG_OFFSET(SRC, CONSUMER_INT_SETUP_IX1), 2372 }; 2373 2374 /** 2375 * hal_qca6750_attach() - Attach 6750 target specific hal_soc ops, 2376 * offset and srng table 2377 */ 2378 void hal_qca6750_attach(struct hal_soc *hal_soc) 2379 { 2380 hal_soc->hw_srng_table = hw_srng_table_6750; 2381 hal_soc->hal_hw_reg_offset = hal_hw_reg_offset_qca6750; 2382 hal_soc->ops = &qca6750_hal_hw_txrx_ops; 2383 } 2384