1 /* 2 * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved. 3 * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #include "qdf_types.h" 21 #include "qdf_util.h" 22 #include "qdf_types.h" 23 #include "qdf_lock.h" 24 #include "qdf_mem.h" 25 #include "qdf_nbuf.h" 26 #include "hal_li_hw_headers.h" 27 #include "hal_internal.h" 28 #include "hal_api.h" 29 #include "target_type.h" 30 #include "wcss_version.h" 31 #include "qdf_module.h" 32 #include "hal_flow.h" 33 #include "rx_flow_search_entry.h" 34 #include "hal_rx_flow_info.h" 35 36 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_OFFSET \ 37 RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_OFFSET 38 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_MASK \ 39 RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_MASK 40 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_LSB \ 41 RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_LSB 42 #define UNIFIED_PHYRX_HT_SIG_0_HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS_OFFSET \ 43 PHYRX_L_SIG_B_0_PHYRX_L_SIG_B_INFO_DETAILS_RATE_OFFSET 44 #define UNIFIED_PHYRX_L_SIG_B_0_L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS_OFFSET \ 45 PHYRX_L_SIG_B_0_PHYRX_L_SIG_B_INFO_DETAILS_RATE_OFFSET 46 #define UNIFIED_PHYRX_L_SIG_A_0_L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS_OFFSET \ 47 PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_RATE_OFFSET 48 #define UNIFIED_PHYRX_VHT_SIG_A_0_VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS_OFFSET \ 49 PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_OFFSET 50 #define UNIFIED_PHYRX_HE_SIG_A_SU_0_HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS_OFFSET \ 51 PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_OFFSET 52 #define UNIFIED_PHYRX_HE_SIG_A_MU_DL_0_HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_OFFSET \ 53 PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_OFFSET 54 #define UNIFIED_PHYRX_HE_SIG_B1_MU_0_HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_OFFSET \ 55 PHYRX_HE_SIG_B1_MU_0_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_OFFSET 56 #define UNIFIED_PHYRX_HE_SIG_B2_MU_0_HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_OFFSET \ 57 PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_OFFSET 58 #define UNIFIED_PHYRX_HE_SIG_B2_OFDMA_0_HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_OFFSET \ 59 PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_OFFSET 60 61 #define UNIFIED_PHYRX_RSSI_LEGACY_3_RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS_OFFSET \ 62 PHYRX_RSSI_LEGACY_3_RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS_OFFSET 63 #define UNIFIED_PHYRX_RSSI_LEGACY_19_RECEIVE_RSSI_INFO_PREAMBLE_RSSI_INFO_DETAILS_OFFSET \ 64 PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 65 #define UNIFIED_RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET \ 66 RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 67 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 68 RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET 69 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ 70 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET 71 #define UNIFIED_RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 72 RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET 73 #define UNIFIED_REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 74 REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET 75 #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC \ 76 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER 77 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ 78 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET 79 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 80 RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET 81 #define UNIFIED_TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 82 TCL_DATA_CMD_0_BUF_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 83 #define UNIFIED_TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 84 TCL_DATA_CMD_1_BUF_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 85 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET \ 86 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET 87 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB \ 88 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB 89 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK \ 90 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK 91 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB \ 92 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB 93 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK \ 94 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK 95 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB \ 96 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB 97 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK \ 98 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK 99 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB \ 100 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB 101 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK \ 102 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK 103 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB \ 104 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB 105 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK \ 106 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK 107 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_MASK \ 108 WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MASK 109 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_OFFSET \ 110 WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_OFFSET 111 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_LSB \ 112 WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_LSB 113 114 #include "hal_6750_tx.h" 115 #include "hal_6750_rx.h" 116 #include <hal_generic_api.h> 117 #include "hal_li_rx.h" 118 #include "hal_li_api.h" 119 #include "hal_li_generic_api.h" 120 121 /* 122 * hal_rx_msdu_start_nss_get_6750(): API to get the NSS 123 * Interval from rx_msdu_start 124 * 125 * @buf: pointer to the start of RX PKT TLV header 126 * Return: uint32_t(nss) 127 */ 128 static uint32_t 129 hal_rx_msdu_start_nss_get_6750(uint8_t *buf) 130 { 131 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 132 struct rx_msdu_start *msdu_start = 133 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 134 uint8_t mimo_ss_bitmap; 135 136 mimo_ss_bitmap = HAL_RX_MSDU_START_MIMO_SS_BITMAP(msdu_start); 137 138 return qdf_get_hweight8(mimo_ss_bitmap); 139 } 140 141 /** 142 * hal_rx_msdu_start_get_len_6750(): API to get the MSDU length 143 * from rx_msdu_start TLV 144 * 145 * @ buf: pointer to the start of RX PKT TLV headers 146 * Return: (uint32_t)msdu length 147 */ 148 static uint32_t hal_rx_msdu_start_get_len_6750(uint8_t *buf) 149 { 150 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 151 struct rx_msdu_start *msdu_start = 152 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 153 uint32_t msdu_len; 154 155 msdu_len = HAL_RX_MSDU_START_MSDU_LEN_GET(msdu_start); 156 157 return msdu_len; 158 } 159 160 /** 161 * hal_rx_mon_hw_desc_get_mpdu_status_6750(): Retrieve MPDU status 162 * 163 * @ hw_desc_addr: Start address of Rx HW TLVs 164 * @ rs: Status for monitor mode 165 * 166 * Return: void 167 */ 168 static void hal_rx_mon_hw_desc_get_mpdu_status_6750(void *hw_desc_addr, 169 struct mon_rx_status *rs) 170 { 171 struct rx_msdu_start *rx_msdu_start; 172 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr; 173 uint32_t reg_value; 174 const uint32_t sgi_hw_to_cdp[] = { 175 CDP_SGI_0_8_US, 176 CDP_SGI_0_4_US, 177 CDP_SGI_1_6_US, 178 CDP_SGI_3_2_US, 179 }; 180 181 rx_msdu_start = &rx_desc->msdu_start_tlv.rx_msdu_start; 182 183 HAL_RX_GET_MSDU_AGGREGATION(rx_desc, rs); 184 185 rs->ant_signal_db = HAL_RX_GET(rx_msdu_start, 186 RX_MSDU_START_5, USER_RSSI); 187 rs->is_stbc = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, STBC); 188 189 reg_value = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, SGI); 190 rs->sgi = sgi_hw_to_cdp[reg_value]; 191 192 reg_value = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, RECEPTION_TYPE); 193 rs->beamformed = (reg_value == HAL_RX_RECEPTION_TYPE_MU_MIMO) ? 1 : 0; 194 /* TODO: rs->beamformed should be set for SU beamforming also */ 195 } 196 197 #define LINK_DESC_SIZE (NUM_OF_DWORDS_RX_MSDU_LINK << 2) 198 199 static uint32_t hal_get_link_desc_size_6750(void) 200 { 201 return LINK_DESC_SIZE; 202 } 203 204 /* 205 * hal_rx_get_tlv_6750(): API to get the tlv 206 * 207 * @rx_tlv: TLV data extracted from the rx packet 208 * Return: uint8_t 209 */ 210 static uint8_t hal_rx_get_tlv_6750(void *rx_tlv) 211 { 212 return HAL_RX_GET(rx_tlv, PHYRX_RSSI_LEGACY_0, RECEIVE_BANDWIDTH); 213 } 214 215 /** 216 * hal_rx_proc_phyrx_other_receive_info_tlv_6750() 217 * - process other receive info TLV 218 * @rx_tlv_hdr: pointer to TLV header 219 * @ppdu_info: pointer to ppdu_info 220 * 221 * Return: None 222 */ 223 static 224 void hal_rx_proc_phyrx_other_receive_info_tlv_6750(void *rx_tlv_hdr, 225 void *ppdu_info_handle) 226 { 227 uint32_t tlv_tag, tlv_len; 228 uint32_t temp_len, other_tlv_len, other_tlv_tag; 229 void *rx_tlv = (uint8_t *)rx_tlv_hdr + HAL_RX_TLV32_HDR_SIZE; 230 void *other_tlv_hdr = NULL; 231 void *other_tlv = NULL; 232 233 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv_hdr); 234 tlv_len = HAL_RX_GET_USER_TLV32_LEN(rx_tlv_hdr); 235 temp_len = 0; 236 237 other_tlv_hdr = rx_tlv + HAL_RX_TLV32_HDR_SIZE; 238 239 other_tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(other_tlv_hdr); 240 other_tlv_len = HAL_RX_GET_USER_TLV32_LEN(other_tlv_hdr); 241 temp_len += other_tlv_len; 242 other_tlv = other_tlv_hdr + HAL_RX_TLV32_HDR_SIZE; 243 244 switch (other_tlv_tag) { 245 default: 246 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR, 247 "%s unhandled TLV type: %d, TLV len:%d", 248 __func__, other_tlv_tag, other_tlv_len); 249 break; 250 } 251 } 252 253 /** 254 * hal_rx_dump_msdu_start_tlv_6750() : dump RX msdu_start TLV in structured 255 * human readable format. 256 * @ msdu_start: pointer the msdu_start TLV in pkt. 257 * @ dbg_level: log level. 258 * 259 * Return: void 260 */ 261 static void hal_rx_dump_msdu_start_tlv_6750(void *msdustart, uint8_t dbg_level) 262 { 263 struct rx_msdu_start *msdu_start = (struct rx_msdu_start *)msdustart; 264 265 hal_verbose_debug( 266 "rx_msdu_start tlv (1/2) - " 267 "rxpcu_mpdu_filter_in_category: %x " 268 "sw_frame_group_id: %x " 269 "phy_ppdu_id: %x " 270 "msdu_length: %x " 271 "ipsec_esp: %x " 272 "l3_offset: %x " 273 "ipsec_ah: %x " 274 "l4_offset: %x " 275 "msdu_number: %x " 276 "decap_format: %x " 277 "ipv4_proto: %x " 278 "ipv6_proto: %x " 279 "tcp_proto: %x " 280 "udp_proto: %x " 281 "ip_frag: %x " 282 "tcp_only_ack: %x " 283 "da_is_bcast_mcast: %x " 284 "ip4_protocol_ip6_next_header: %x " 285 "toeplitz_hash_2_or_4: %x " 286 "flow_id_toeplitz: %x " 287 "user_rssi: %x " 288 "pkt_type: %x " 289 "stbc: %x " 290 "sgi: %x " 291 "rate_mcs: %x " 292 "receive_bandwidth: %x " 293 "reception_type: %x " 294 "ppdu_start_timestamp: %u ", 295 msdu_start->rxpcu_mpdu_filter_in_category, 296 msdu_start->sw_frame_group_id, 297 msdu_start->phy_ppdu_id, 298 msdu_start->msdu_length, 299 msdu_start->ipsec_esp, 300 msdu_start->l3_offset, 301 msdu_start->ipsec_ah, 302 msdu_start->l4_offset, 303 msdu_start->msdu_number, 304 msdu_start->decap_format, 305 msdu_start->ipv4_proto, 306 msdu_start->ipv6_proto, 307 msdu_start->tcp_proto, 308 msdu_start->udp_proto, 309 msdu_start->ip_frag, 310 msdu_start->tcp_only_ack, 311 msdu_start->da_is_bcast_mcast, 312 msdu_start->ip4_protocol_ip6_next_header, 313 msdu_start->toeplitz_hash_2_or_4, 314 msdu_start->flow_id_toeplitz, 315 msdu_start->user_rssi, 316 msdu_start->pkt_type, 317 msdu_start->stbc, 318 msdu_start->sgi, 319 msdu_start->rate_mcs, 320 msdu_start->receive_bandwidth, 321 msdu_start->reception_type, 322 msdu_start->ppdu_start_timestamp); 323 324 hal_verbose_debug( 325 "rx_msdu_start tlv (2/2) - " 326 "sw_phy_meta_data: %x ", 327 msdu_start->sw_phy_meta_data); 328 } 329 330 /** 331 * hal_rx_dump_msdu_end_tlv_6750: dump RX msdu_end TLV in structured 332 * human readable format. 333 * @ msdu_end: pointer the msdu_end TLV in pkt. 334 * @ dbg_level: log level. 335 * 336 * Return: void 337 */ 338 static void hal_rx_dump_msdu_end_tlv_6750(void *msduend, 339 uint8_t dbg_level) 340 { 341 struct rx_msdu_end *msdu_end = (struct rx_msdu_end *)msduend; 342 343 __QDF_TRACE_RL(dbg_level, QDF_MODULE_ID_DP, 344 "rx_msdu_end tlv (1/3) - " 345 "rxpcu_mpdu_filter_in_category: %x " 346 "sw_frame_group_id: %x " 347 "phy_ppdu_id: %x " 348 "ip_hdr_chksum: %x " 349 "tcp_udp_chksum: %x " 350 "key_id_octet: %x " 351 "cce_super_rule: %x " 352 "cce_classify_not_done_truncat: %x " 353 "cce_classify_not_done_cce_dis: %x " 354 "reported_mpdu_length: %x " 355 "first_msdu: %x " 356 "last_msdu: %x " 357 "sa_idx_timeout: %x " 358 "da_idx_timeout: %x " 359 "msdu_limit_error: %x " 360 "flow_idx_timeout: %x " 361 "flow_idx_invalid: %x " 362 "wifi_parser_error: %x " 363 "amsdu_parser_error: %x", 364 msdu_end->rxpcu_mpdu_filter_in_category, 365 msdu_end->sw_frame_group_id, 366 msdu_end->phy_ppdu_id, 367 msdu_end->ip_hdr_chksum, 368 msdu_end->tcp_udp_chksum, 369 msdu_end->key_id_octet, 370 msdu_end->cce_super_rule, 371 msdu_end->cce_classify_not_done_truncate, 372 msdu_end->cce_classify_not_done_cce_dis, 373 msdu_end->reported_mpdu_length, 374 msdu_end->first_msdu, 375 msdu_end->last_msdu, 376 msdu_end->sa_idx_timeout, 377 msdu_end->da_idx_timeout, 378 msdu_end->msdu_limit_error, 379 msdu_end->flow_idx_timeout, 380 msdu_end->flow_idx_invalid, 381 msdu_end->wifi_parser_error, 382 msdu_end->amsdu_parser_error); 383 384 __QDF_TRACE_RL(dbg_level, QDF_MODULE_ID_DP, 385 "rx_msdu_end tlv (2/3)- " 386 "sa_is_valid: %x " 387 "da_is_valid: %x " 388 "da_is_mcbc: %x " 389 "l3_header_padding: %x " 390 "ipv6_options_crc: %x " 391 "tcp_seq_number: %x " 392 "tcp_ack_number: %x " 393 "tcp_flag: %x " 394 "lro_eligible: %x " 395 "window_size: %x " 396 "da_offset: %x " 397 "sa_offset: %x " 398 "da_offset_valid: %x " 399 "sa_offset_valid: %x " 400 "rule_indication_31_0: %x " 401 "rule_indication_63_32: %x " 402 "sa_idx: %x " 403 "da_idx: %x " 404 "msdu_drop: %x " 405 "reo_destination_indication: %x " 406 "flow_idx: %x " 407 "fse_metadata: %x " 408 "cce_metadata: %x " 409 "sa_sw_peer_id: %x ", 410 msdu_end->sa_is_valid, 411 msdu_end->da_is_valid, 412 msdu_end->da_is_mcbc, 413 msdu_end->l3_header_padding, 414 msdu_end->ipv6_options_crc, 415 msdu_end->tcp_seq_number, 416 msdu_end->tcp_ack_number, 417 msdu_end->tcp_flag, 418 msdu_end->lro_eligible, 419 msdu_end->window_size, 420 msdu_end->da_offset, 421 msdu_end->sa_offset, 422 msdu_end->da_offset_valid, 423 msdu_end->sa_offset_valid, 424 msdu_end->rule_indication_31_0, 425 msdu_end->rule_indication_63_32, 426 msdu_end->sa_idx, 427 msdu_end->da_idx_or_sw_peer_id, 428 msdu_end->msdu_drop, 429 msdu_end->reo_destination_indication, 430 msdu_end->flow_idx, 431 msdu_end->fse_metadata, 432 msdu_end->cce_metadata, 433 msdu_end->sa_sw_peer_id); 434 __QDF_TRACE_RL(dbg_level, QDF_MODULE_ID_DP, 435 "rx_msdu_end tlv (3/3)" 436 "aggregation_count %x " 437 "flow_aggregation_continuation %x " 438 "fisa_timeout %x " 439 "cumulative_l4_checksum %x " 440 "cumulative_ip_length %x", 441 msdu_end->aggregation_count, 442 msdu_end->flow_aggregation_continuation, 443 msdu_end->fisa_timeout, 444 msdu_end->cumulative_l4_checksum, 445 msdu_end->cumulative_ip_length); 446 } 447 448 /* 449 * Get tid from RX_MPDU_START 450 */ 451 #define HAL_RX_MPDU_INFO_TID_GET(_rx_mpdu_info) \ 452 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_info), \ 453 RX_MPDU_INFO_7_TID_OFFSET)), \ 454 RX_MPDU_INFO_7_TID_MASK, \ 455 RX_MPDU_INFO_7_TID_LSB)) 456 457 static uint32_t hal_rx_mpdu_start_tid_get_6750(uint8_t *buf) 458 { 459 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 460 struct rx_mpdu_start *mpdu_start = 461 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 462 uint32_t tid; 463 464 tid = HAL_RX_MPDU_INFO_TID_GET(&mpdu_start->rx_mpdu_info_details); 465 466 return tid; 467 } 468 469 #define HAL_RX_MSDU_START_RECEPTION_TYPE_GET(_rx_msdu_start) \ 470 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start), \ 471 RX_MSDU_START_5_RECEPTION_TYPE_OFFSET)), \ 472 RX_MSDU_START_5_RECEPTION_TYPE_MASK, \ 473 RX_MSDU_START_5_RECEPTION_TYPE_LSB)) 474 475 /* 476 * hal_rx_msdu_start_reception_type_get(): API to get the reception type 477 * Interval from rx_msdu_start 478 * 479 * @buf: pointer to the start of RX PKT TLV header 480 * Return: uint32_t(reception_type) 481 */ 482 static 483 uint32_t hal_rx_msdu_start_reception_type_get_6750(uint8_t *buf) 484 { 485 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 486 struct rx_msdu_start *msdu_start = 487 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 488 uint32_t reception_type; 489 490 reception_type = HAL_RX_MSDU_START_RECEPTION_TYPE_GET(msdu_start); 491 492 return reception_type; 493 } 494 495 /** 496 * hal_rx_msdu_end_da_idx_get_6750: API to get da_idx 497 * from rx_msdu_end TLV 498 * 499 * @ buf: pointer to the start of RX PKT TLV headers 500 * Return: da index 501 */ 502 static uint16_t hal_rx_msdu_end_da_idx_get_6750(uint8_t *buf) 503 { 504 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 505 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 506 uint16_t da_idx; 507 508 da_idx = HAL_RX_MSDU_END_DA_IDX_GET(msdu_end); 509 510 return da_idx; 511 } 512 513 /** 514 * hal_rx_get_rx_fragment_number_6750(): Function to retrieve rx fragment number 515 * 516 * @nbuf: Network buffer 517 * Returns: rx fragment number 518 */ 519 static 520 uint8_t hal_rx_get_rx_fragment_number_6750(uint8_t *buf) 521 { 522 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 523 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 524 525 /* Return first 4 bits as fragment number */ 526 return (HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info) & 527 DOT11_SEQ_FRAG_MASK); 528 } 529 530 /** 531 * hal_rx_msdu_end_da_is_mcbc_get_6750(): API to check if pkt is MCBC 532 * from rx_msdu_end TLV 533 * 534 * @ buf: pointer to the start of RX PKT TLV headers 535 * Return: da_is_mcbc 536 */ 537 static uint8_t 538 hal_rx_msdu_end_da_is_mcbc_get_6750(uint8_t *buf) 539 { 540 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 541 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 542 543 return HAL_RX_MSDU_END_DA_IS_MCBC_GET(msdu_end); 544 } 545 546 /** 547 * hal_rx_msdu_end_sa_is_valid_get_6750(): API to get_6750 the 548 * sa_is_valid bit from rx_msdu_end TLV 549 * 550 * @ buf: pointer to the start of RX PKT TLV headers 551 * Return: sa_is_valid bit 552 */ 553 static uint8_t 554 hal_rx_msdu_end_sa_is_valid_get_6750(uint8_t *buf) 555 { 556 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 557 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 558 uint8_t sa_is_valid; 559 560 sa_is_valid = HAL_RX_MSDU_END_SA_IS_VALID_GET(msdu_end); 561 562 return sa_is_valid; 563 } 564 565 /** 566 * hal_rx_msdu_end_sa_idx_get_6750(): API to get_6750 the 567 * sa_idx from rx_msdu_end TLV 568 * 569 * @ buf: pointer to the start of RX PKT TLV headers 570 * Return: sa_idx (SA AST index) 571 */ 572 static 573 uint16_t hal_rx_msdu_end_sa_idx_get_6750(uint8_t *buf) 574 { 575 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 576 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 577 uint16_t sa_idx; 578 579 sa_idx = HAL_RX_MSDU_END_SA_IDX_GET(msdu_end); 580 581 return sa_idx; 582 } 583 584 /** 585 * hal_rx_desc_is_first_msdu_6750() - Check if first msdu 586 * 587 * @hal_soc_hdl: hal_soc handle 588 * @hw_desc_addr: hardware descriptor address 589 * 590 * Return: 0 - success/ non-zero failure 591 */ 592 static uint32_t hal_rx_desc_is_first_msdu_6750(void *hw_desc_addr) 593 { 594 struct rx_pkt_tlvs *rx_tlvs = (struct rx_pkt_tlvs *)hw_desc_addr; 595 struct rx_msdu_end *msdu_end = &rx_tlvs->msdu_end_tlv.rx_msdu_end; 596 597 return HAL_RX_GET(msdu_end, RX_MSDU_END_10, FIRST_MSDU); 598 } 599 600 /** 601 * hal_rx_msdu_end_l3_hdr_padding_get_6750(): API to get_6750 the 602 * l3_header padding from rx_msdu_end TLV 603 * 604 * @ buf: pointer to the start of RX PKT TLV headers 605 * Return: number of l3 header padding bytes 606 */ 607 static uint32_t hal_rx_msdu_end_l3_hdr_padding_get_6750(uint8_t *buf) 608 { 609 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 610 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 611 uint32_t l3_header_padding; 612 613 l3_header_padding = HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(msdu_end); 614 615 return l3_header_padding; 616 } 617 618 /* 619 * @ hal_rx_encryption_info_valid_6750: Returns encryption type. 620 * 621 * @ buf: rx_tlv_hdr of the received packet 622 * @ Return: encryption type 623 */ 624 static uint32_t hal_rx_encryption_info_valid_6750(uint8_t *buf) 625 { 626 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 627 struct rx_mpdu_start *mpdu_start = 628 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 629 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 630 uint32_t encryption_info = HAL_RX_MPDU_ENCRYPTION_INFO_VALID(mpdu_info); 631 632 return encryption_info; 633 } 634 635 /* 636 * @ hal_rx_print_pn_6750: Prints the PN of rx packet. 637 * 638 * @ buf: rx_tlv_hdr of the received packet 639 * @ Return: void 640 */ 641 static void hal_rx_print_pn_6750(uint8_t *buf) 642 { 643 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 644 struct rx_mpdu_start *mpdu_start = 645 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 646 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 647 648 uint32_t pn_31_0 = HAL_RX_MPDU_PN_31_0_GET(mpdu_info); 649 uint32_t pn_63_32 = HAL_RX_MPDU_PN_63_32_GET(mpdu_info); 650 uint32_t pn_95_64 = HAL_RX_MPDU_PN_95_64_GET(mpdu_info); 651 uint32_t pn_127_96 = HAL_RX_MPDU_PN_127_96_GET(mpdu_info); 652 653 hal_debug("PN number pn_127_96 0x%x pn_95_64 0x%x pn_63_32 0x%x pn_31_0 0x%x ", 654 pn_127_96, pn_95_64, pn_63_32, pn_31_0); 655 } 656 657 /** 658 * hal_rx_msdu_end_first_msdu_get_6750: API to get first msdu status 659 * from rx_msdu_end TLV 660 * 661 * @ buf: pointer to the start of RX PKT TLV headers 662 * Return: first_msdu 663 */ 664 static uint8_t hal_rx_msdu_end_first_msdu_get_6750(uint8_t *buf) 665 { 666 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 667 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 668 uint8_t first_msdu; 669 670 first_msdu = HAL_RX_MSDU_END_FIRST_MSDU_GET(msdu_end); 671 672 return first_msdu; 673 } 674 675 /** 676 * hal_rx_msdu_end_da_is_valid_get_6750: API to check if da is valid 677 * from rx_msdu_end TLV 678 * 679 * @ buf: pointer to the start of RX PKT TLV headers 680 * Return: da_is_valid 681 */ 682 static uint8_t hal_rx_msdu_end_da_is_valid_get_6750(uint8_t *buf) 683 { 684 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 685 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 686 uint8_t da_is_valid; 687 688 da_is_valid = HAL_RX_MSDU_END_DA_IS_VALID_GET(msdu_end); 689 690 return da_is_valid; 691 } 692 693 /** 694 * hal_rx_msdu_end_last_msdu_get_6750: API to get last msdu status 695 * from rx_msdu_end TLV 696 * 697 * @ buf: pointer to the start of RX PKT TLV headers 698 * Return: last_msdu 699 */ 700 static uint8_t hal_rx_msdu_end_last_msdu_get_6750(uint8_t *buf) 701 { 702 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 703 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 704 uint8_t last_msdu; 705 706 last_msdu = HAL_RX_MSDU_END_LAST_MSDU_GET(msdu_end); 707 708 return last_msdu; 709 } 710 711 /* 712 * hal_rx_get_mpdu_mac_ad4_valid_6750(): Retrieves if mpdu 4th addr is valid 713 * 714 * @nbuf: Network buffer 715 * Returns: value of mpdu 4th address valid field 716 */ 717 static bool hal_rx_get_mpdu_mac_ad4_valid_6750(uint8_t *buf) 718 { 719 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 720 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 721 bool ad4_valid = 0; 722 723 ad4_valid = HAL_RX_MPDU_GET_MAC_AD4_VALID(rx_mpdu_info); 724 725 return ad4_valid; 726 } 727 728 /** 729 * hal_rx_mpdu_start_sw_peer_id_get_6750: Retrieve sw peer_id 730 * @buf: network buffer 731 * 732 * Return: sw peer_id 733 */ 734 static uint32_t hal_rx_mpdu_start_sw_peer_id_get_6750(uint8_t *buf) 735 { 736 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 737 struct rx_mpdu_start *mpdu_start = 738 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 739 740 return HAL_RX_MPDU_INFO_SW_PEER_ID_GET( 741 &mpdu_start->rx_mpdu_info_details); 742 } 743 744 /** 745 * hal_rx_mpdu_get_to_ds_6750(): API to get the tods info 746 * from rx_mpdu_start 747 * 748 * @buf: pointer to the start of RX PKT TLV header 749 * Return: uint32_t(to_ds) 750 */ 751 static uint32_t hal_rx_mpdu_get_to_ds_6750(uint8_t *buf) 752 { 753 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 754 struct rx_mpdu_start *mpdu_start = 755 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 756 757 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 758 759 return HAL_RX_MPDU_GET_TODS(mpdu_info); 760 } 761 762 /* 763 * hal_rx_mpdu_get_fr_ds_6750(): API to get the from ds info 764 * from rx_mpdu_start 765 * 766 * @buf: pointer to the start of RX PKT TLV header 767 * Return: uint32_t(fr_ds) 768 */ 769 static uint32_t hal_rx_mpdu_get_fr_ds_6750(uint8_t *buf) 770 { 771 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 772 struct rx_mpdu_start *mpdu_start = 773 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 774 775 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 776 777 return HAL_RX_MPDU_GET_FROMDS(mpdu_info); 778 } 779 780 /* 781 * hal_rx_get_mpdu_frame_control_valid_6750(): Retrieves mpdu 782 * frame control valid 783 * 784 * @nbuf: Network buffer 785 * Returns: value of frame control valid field 786 */ 787 static uint8_t hal_rx_get_mpdu_frame_control_valid_6750(uint8_t *buf) 788 { 789 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 790 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 791 792 return HAL_RX_MPDU_GET_FRAME_CONTROL_VALID(rx_mpdu_info); 793 } 794 795 /* 796 * hal_rx_mpdu_get_addr1_6750(): API to check get address1 of the mpdu 797 * 798 * @buf: pointer to the start of RX PKT TLV headera 799 * @mac_addr: pointer to mac address 800 * Return: success/failure 801 */ 802 static QDF_STATUS hal_rx_mpdu_get_addr1_6750(uint8_t *buf, uint8_t *mac_addr) 803 { 804 struct __attribute__((__packed__)) hal_addr1 { 805 uint32_t ad1_31_0; 806 uint16_t ad1_47_32; 807 }; 808 809 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 810 struct rx_mpdu_start *mpdu_start = 811 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 812 813 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 814 struct hal_addr1 *addr = (struct hal_addr1 *)mac_addr; 815 uint32_t mac_addr_ad1_valid; 816 817 mac_addr_ad1_valid = HAL_RX_MPDU_MAC_ADDR_AD1_VALID_GET(mpdu_info); 818 819 if (mac_addr_ad1_valid) { 820 addr->ad1_31_0 = HAL_RX_MPDU_AD1_31_0_GET(mpdu_info); 821 addr->ad1_47_32 = HAL_RX_MPDU_AD1_47_32_GET(mpdu_info); 822 return QDF_STATUS_SUCCESS; 823 } 824 825 return QDF_STATUS_E_FAILURE; 826 } 827 828 /* 829 * hal_rx_mpdu_get_addr2_6750(): API to check get address2 of the mpdu 830 * in the packet 831 * 832 * @buf: pointer to the start of RX PKT TLV header 833 * @mac_addr: pointer to mac address 834 * Return: success/failure 835 */ 836 static QDF_STATUS hal_rx_mpdu_get_addr2_6750(uint8_t *buf, 837 uint8_t *mac_addr) 838 { 839 struct __attribute__((__packed__)) hal_addr2 { 840 uint16_t ad2_15_0; 841 uint32_t ad2_47_16; 842 }; 843 844 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 845 struct rx_mpdu_start *mpdu_start = 846 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 847 848 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 849 struct hal_addr2 *addr = (struct hal_addr2 *)mac_addr; 850 uint32_t mac_addr_ad2_valid; 851 852 mac_addr_ad2_valid = HAL_RX_MPDU_MAC_ADDR_AD2_VALID_GET(mpdu_info); 853 854 if (mac_addr_ad2_valid) { 855 addr->ad2_15_0 = HAL_RX_MPDU_AD2_15_0_GET(mpdu_info); 856 addr->ad2_47_16 = HAL_RX_MPDU_AD2_47_16_GET(mpdu_info); 857 return QDF_STATUS_SUCCESS; 858 } 859 860 return QDF_STATUS_E_FAILURE; 861 } 862 863 /* 864 * hal_rx_mpdu_get_addr3_6750(): API to get address3 of the mpdu 865 * in the packet 866 * 867 * @buf: pointer to the start of RX PKT TLV header 868 * @mac_addr: pointer to mac address 869 * Return: success/failure 870 */ 871 static QDF_STATUS hal_rx_mpdu_get_addr3_6750(uint8_t *buf, uint8_t *mac_addr) 872 { 873 struct __attribute__((__packed__)) hal_addr3 { 874 uint32_t ad3_31_0; 875 uint16_t ad3_47_32; 876 }; 877 878 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 879 struct rx_mpdu_start *mpdu_start = 880 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 881 882 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 883 struct hal_addr3 *addr = (struct hal_addr3 *)mac_addr; 884 uint32_t mac_addr_ad3_valid; 885 886 mac_addr_ad3_valid = HAL_RX_MPDU_MAC_ADDR_AD3_VALID_GET(mpdu_info); 887 888 if (mac_addr_ad3_valid) { 889 addr->ad3_31_0 = HAL_RX_MPDU_AD3_31_0_GET(mpdu_info); 890 addr->ad3_47_32 = HAL_RX_MPDU_AD3_47_32_GET(mpdu_info); 891 return QDF_STATUS_SUCCESS; 892 } 893 894 return QDF_STATUS_E_FAILURE; 895 } 896 897 /* 898 * hal_rx_mpdu_get_addr4_6750(): API to get address4 of the mpdu 899 * in the packet 900 * 901 * @buf: pointer to the start of RX PKT TLV header 902 * @mac_addr: pointer to mac address 903 * Return: success/failure 904 */ 905 static QDF_STATUS hal_rx_mpdu_get_addr4_6750(uint8_t *buf, uint8_t *mac_addr) 906 { 907 struct __attribute__((__packed__)) hal_addr4 { 908 uint32_t ad4_31_0; 909 uint16_t ad4_47_32; 910 }; 911 912 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 913 struct rx_mpdu_start *mpdu_start = 914 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 915 916 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 917 struct hal_addr4 *addr = (struct hal_addr4 *)mac_addr; 918 uint32_t mac_addr_ad4_valid; 919 920 mac_addr_ad4_valid = HAL_RX_MPDU_MAC_ADDR_AD4_VALID_GET(mpdu_info); 921 922 if (mac_addr_ad4_valid) { 923 addr->ad4_31_0 = HAL_RX_MPDU_AD4_31_0_GET(mpdu_info); 924 addr->ad4_47_32 = HAL_RX_MPDU_AD4_47_32_GET(mpdu_info); 925 return QDF_STATUS_SUCCESS; 926 } 927 928 return QDF_STATUS_E_FAILURE; 929 } 930 931 /* 932 * hal_rx_get_mpdu_sequence_control_valid_6750(): Get mpdu 933 * sequence control valid 934 * 935 * @nbuf: Network buffer 936 * Returns: value of sequence control valid field 937 */ 938 static uint8_t hal_rx_get_mpdu_sequence_control_valid_6750(uint8_t *buf) 939 { 940 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 941 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 942 943 return HAL_RX_MPDU_GET_SEQUENCE_CONTROL_VALID(rx_mpdu_info); 944 } 945 946 /** 947 * hal_rx_is_unicast_6750: check packet is unicast frame or not. 948 * 949 * @ buf: pointer to rx pkt TLV. 950 * 951 * Return: true on unicast. 952 */ 953 static bool hal_rx_is_unicast_6750(uint8_t *buf) 954 { 955 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 956 struct rx_mpdu_start *mpdu_start = 957 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 958 uint32_t grp_id; 959 uint8_t *rx_mpdu_info = (uint8_t *)&mpdu_start->rx_mpdu_info_details; 960 961 grp_id = (_HAL_MS((*_OFFSET_TO_WORD_PTR((rx_mpdu_info), 962 RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_OFFSET)), 963 RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_MASK, 964 RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_LSB)); 965 966 return (HAL_MPDU_SW_FRAME_GROUP_UNICAST_DATA == grp_id) ? true : false; 967 } 968 969 /** 970 * hal_rx_tid_get_6750: get tid based on qos control valid. 971 * @hal_soc_hdl: hal_soc handle 972 * @ buf: pointer to rx pkt TLV. 973 * 974 * Return: tid 975 */ 976 static uint32_t hal_rx_tid_get_6750(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 977 { 978 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 979 struct rx_mpdu_start *mpdu_start = 980 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 981 uint8_t *rx_mpdu_info = (uint8_t *)&mpdu_start->rx_mpdu_info_details; 982 uint8_t qos_control_valid = 983 (_HAL_MS((*_OFFSET_TO_WORD_PTR((rx_mpdu_info), 984 RX_MPDU_INFO_11_MPDU_QOS_CONTROL_VALID_OFFSET)), 985 RX_MPDU_INFO_11_MPDU_QOS_CONTROL_VALID_MASK, 986 RX_MPDU_INFO_11_MPDU_QOS_CONTROL_VALID_LSB)); 987 988 if (qos_control_valid) 989 return hal_rx_mpdu_start_tid_get_6750(buf); 990 991 return HAL_RX_NON_QOS_TID; 992 } 993 994 /** 995 * hal_rx_hw_desc_get_ppduid_get_6750(): retrieve ppdu id 996 * @rx_tlv_hdr: rx tlv header 997 * @rxdma_dst_ring_desc: rxdma HW descriptor 998 * 999 * Return: ppdu id 1000 */ 1001 static uint32_t hal_rx_hw_desc_get_ppduid_get_6750(void *rx_tlv_hdr, 1002 void *rxdma_dst_ring_desc) 1003 { 1004 struct rx_mpdu_info *rx_mpdu_info; 1005 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)rx_tlv_hdr; 1006 1007 rx_mpdu_info = 1008 &rx_desc->mpdu_start_tlv.rx_mpdu_start.rx_mpdu_info_details; 1009 1010 return HAL_RX_GET(rx_mpdu_info, RX_MPDU_INFO_9, PHY_PPDU_ID); 1011 } 1012 1013 /** 1014 * hal_reo_status_get_header_6750 - Process reo desc info 1015 * @ring_desc: REO status ring descriptor 1016 * @b - tlv type info 1017 * @h1 - Pointer to hal_reo_status_header where info to be stored 1018 * 1019 * Return - none. 1020 * 1021 */ 1022 static void hal_reo_status_get_header_6750(hal_ring_desc_t ring_desc, int b, 1023 void *h1) 1024 { 1025 uint32_t *d = (uint32_t *)ring_desc; 1026 uint32_t val1 = 0; 1027 struct hal_reo_status_header *h = 1028 (struct hal_reo_status_header *)h1; 1029 1030 /* Offsets of descriptor fields defined in HW headers start 1031 * from the field after TLV header 1032 */ 1033 d += HAL_GET_NUM_DWORDS(sizeof(struct tlv_32_hdr)); 1034 1035 switch (b) { 1036 case HAL_REO_QUEUE_STATS_STATUS_TLV: 1037 val1 = d[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_0, 1038 STATUS_HEADER_REO_STATUS_NUMBER)]; 1039 break; 1040 case HAL_REO_FLUSH_QUEUE_STATUS_TLV: 1041 val1 = d[HAL_OFFSET_DW(REO_FLUSH_QUEUE_STATUS_0, 1042 STATUS_HEADER_REO_STATUS_NUMBER)]; 1043 break; 1044 case HAL_REO_FLUSH_CACHE_STATUS_TLV: 1045 val1 = d[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_0, 1046 STATUS_HEADER_REO_STATUS_NUMBER)]; 1047 break; 1048 case HAL_REO_UNBLK_CACHE_STATUS_TLV: 1049 val1 = d[HAL_OFFSET_DW(REO_UNBLOCK_CACHE_STATUS_0, 1050 STATUS_HEADER_REO_STATUS_NUMBER)]; 1051 break; 1052 case HAL_REO_TIMOUT_LIST_STATUS_TLV: 1053 val1 = d[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_0, 1054 STATUS_HEADER_REO_STATUS_NUMBER)]; 1055 break; 1056 case HAL_REO_DESC_THRES_STATUS_TLV: 1057 val1 = 1058 d[HAL_OFFSET_DW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0, 1059 STATUS_HEADER_REO_STATUS_NUMBER)]; 1060 break; 1061 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: 1062 val1 = d[HAL_OFFSET_DW(REO_UPDATE_RX_REO_QUEUE_STATUS_0, 1063 STATUS_HEADER_REO_STATUS_NUMBER)]; 1064 break; 1065 default: 1066 qdf_nofl_err("ERROR: Unknown tlv\n"); 1067 break; 1068 } 1069 h->cmd_num = 1070 HAL_GET_FIELD( 1071 UNIFORM_REO_STATUS_HEADER_0, REO_STATUS_NUMBER, 1072 val1); 1073 h->exec_time = 1074 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_0, 1075 CMD_EXECUTION_TIME, val1); 1076 h->status = 1077 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_0, 1078 REO_CMD_EXECUTION_STATUS, val1); 1079 switch (b) { 1080 case HAL_REO_QUEUE_STATS_STATUS_TLV: 1081 val1 = d[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_1, 1082 STATUS_HEADER_TIMESTAMP)]; 1083 break; 1084 case HAL_REO_FLUSH_QUEUE_STATUS_TLV: 1085 val1 = d[HAL_OFFSET_DW(REO_FLUSH_QUEUE_STATUS_1, 1086 STATUS_HEADER_TIMESTAMP)]; 1087 break; 1088 case HAL_REO_FLUSH_CACHE_STATUS_TLV: 1089 val1 = d[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_1, 1090 STATUS_HEADER_TIMESTAMP)]; 1091 break; 1092 case HAL_REO_UNBLK_CACHE_STATUS_TLV: 1093 val1 = d[HAL_OFFSET_DW(REO_UNBLOCK_CACHE_STATUS_1, 1094 STATUS_HEADER_TIMESTAMP)]; 1095 break; 1096 case HAL_REO_TIMOUT_LIST_STATUS_TLV: 1097 val1 = d[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_1, 1098 STATUS_HEADER_TIMESTAMP)]; 1099 break; 1100 case HAL_REO_DESC_THRES_STATUS_TLV: 1101 val1 = 1102 d[HAL_OFFSET_DW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_1, 1103 STATUS_HEADER_TIMESTAMP)]; 1104 break; 1105 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: 1106 val1 = d[HAL_OFFSET_DW(REO_UPDATE_RX_REO_QUEUE_STATUS_1, 1107 STATUS_HEADER_TIMESTAMP)]; 1108 break; 1109 default: 1110 qdf_nofl_err("ERROR: Unknown tlv\n"); 1111 break; 1112 } 1113 h->tstamp = 1114 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_1, TIMESTAMP, val1); 1115 } 1116 1117 /** 1118 * hal_tx_desc_set_mesh_en_6750 - Set mesh_enable flag in Tx descriptor 1119 * @desc: Handle to Tx Descriptor 1120 * @en: For raw WiFi frames, this indicates transmission to a mesh STA, 1121 * enabling the interpretation of the 'Mesh Control Present' bit 1122 * (bit 8) of QoS Control (otherwise this bit is ignored), 1123 * For native WiFi frames, this indicates that a 'Mesh Control' field 1124 * is present between the header and the LLC. 1125 * 1126 * Return: void 1127 */ 1128 static inline 1129 void hal_tx_desc_set_mesh_en_6750(void *desc, uint8_t en) 1130 { 1131 HAL_SET_FLD(desc, TCL_DATA_CMD_5, MESH_ENABLE) |= 1132 HAL_TX_SM(TCL_DATA_CMD_5, MESH_ENABLE, en); 1133 } 1134 1135 static 1136 void *hal_rx_msdu0_buffer_addr_lsb_6750(void *link_desc_va) 1137 { 1138 return (void *)HAL_RX_MSDU0_BUFFER_ADDR_LSB(link_desc_va); 1139 } 1140 1141 static 1142 void *hal_rx_msdu_desc_info_ptr_get_6750(void *msdu0) 1143 { 1144 return (void *)HAL_RX_MSDU_DESC_INFO_PTR_GET(msdu0); 1145 } 1146 1147 static 1148 void *hal_ent_mpdu_desc_info_6750(void *ent_ring_desc) 1149 { 1150 return (void *)HAL_ENT_MPDU_DESC_INFO(ent_ring_desc); 1151 } 1152 1153 static 1154 void *hal_dst_mpdu_desc_info_6750(void *dst_ring_desc) 1155 { 1156 return (void *)HAL_DST_MPDU_DESC_INFO(dst_ring_desc); 1157 } 1158 1159 static 1160 uint8_t hal_rx_get_fc_valid_6750(uint8_t *buf) 1161 { 1162 return HAL_RX_GET_FC_VALID(buf); 1163 } 1164 1165 static uint8_t hal_rx_get_to_ds_flag_6750(uint8_t *buf) 1166 { 1167 return HAL_RX_GET_TO_DS_FLAG(buf); 1168 } 1169 1170 static uint8_t hal_rx_get_mac_addr2_valid_6750(uint8_t *buf) 1171 { 1172 return HAL_RX_GET_MAC_ADDR2_VALID(buf); 1173 } 1174 1175 static uint8_t hal_rx_get_filter_category_6750(uint8_t *buf) 1176 { 1177 return HAL_RX_GET_FILTER_CATEGORY(buf); 1178 } 1179 1180 static uint32_t 1181 hal_rx_get_ppdu_id_6750(uint8_t *buf) 1182 { 1183 return HAL_RX_GET_PPDU_ID(buf); 1184 } 1185 1186 /** 1187 * hal_reo_config_6750(): Set reo config parameters 1188 * @soc: hal soc handle 1189 * @reg_val: value to be set 1190 * @reo_params: reo parameters 1191 * 1192 * Return: void 1193 */ 1194 static 1195 void hal_reo_config_6750(struct hal_soc *soc, 1196 uint32_t reg_val, 1197 struct hal_reo_params *reo_params) 1198 { 1199 HAL_REO_R0_CONFIG(soc, reg_val, reo_params); 1200 } 1201 1202 /** 1203 * hal_rx_msdu_desc_info_get_ptr_6750() - Get msdu desc info ptr 1204 * @msdu_details_ptr - Pointer to msdu_details_ptr 1205 * 1206 * Return - Pointer to rx_msdu_desc_info structure. 1207 * 1208 */ 1209 static void *hal_rx_msdu_desc_info_get_ptr_6750(void *msdu_details_ptr) 1210 { 1211 return HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr); 1212 } 1213 1214 /** 1215 * hal_rx_link_desc_msdu0_ptr_6750 - Get pointer to rx_msdu details 1216 * @link_desc - Pointer to link desc 1217 * 1218 * Return - Pointer to rx_msdu_details structure 1219 * 1220 */ 1221 static void *hal_rx_link_desc_msdu0_ptr_6750(void *link_desc) 1222 { 1223 return HAL_RX_LINK_DESC_MSDU0_PTR(link_desc); 1224 } 1225 1226 /** 1227 * hal_rx_msdu_flow_idx_get_6750: API to get flow index 1228 * from rx_msdu_end TLV 1229 * @buf: pointer to the start of RX PKT TLV headers 1230 * 1231 * Return: flow index value from MSDU END TLV 1232 */ 1233 static inline uint32_t hal_rx_msdu_flow_idx_get_6750(uint8_t *buf) 1234 { 1235 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1236 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1237 1238 return HAL_RX_MSDU_END_FLOW_IDX_GET(msdu_end); 1239 } 1240 1241 /** 1242 * hal_rx_msdu_flow_idx_invalid_6750: API to get flow index invalid 1243 * from rx_msdu_end TLV 1244 * @buf: pointer to the start of RX PKT TLV headers 1245 * 1246 * Return: flow index invalid value from MSDU END TLV 1247 */ 1248 static bool hal_rx_msdu_flow_idx_invalid_6750(uint8_t *buf) 1249 { 1250 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1251 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1252 1253 return HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(msdu_end); 1254 } 1255 1256 /** 1257 * hal_rx_msdu_flow_idx_timeout_6750: API to get flow index timeout 1258 * from rx_msdu_end TLV 1259 * @buf: pointer to the start of RX PKT TLV headers 1260 * 1261 * Return: flow index timeout value from MSDU END TLV 1262 */ 1263 static bool hal_rx_msdu_flow_idx_timeout_6750(uint8_t *buf) 1264 { 1265 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1266 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1267 1268 return HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(msdu_end); 1269 } 1270 1271 /** 1272 * hal_rx_msdu_fse_metadata_get_6750: API to get FSE metadata 1273 * from rx_msdu_end TLV 1274 * @buf: pointer to the start of RX PKT TLV headers 1275 * 1276 * Return: fse metadata value from MSDU END TLV 1277 */ 1278 static uint32_t hal_rx_msdu_fse_metadata_get_6750(uint8_t *buf) 1279 { 1280 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1281 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1282 1283 return HAL_RX_MSDU_END_FSE_METADATA_GET(msdu_end); 1284 } 1285 1286 /** 1287 * hal_rx_msdu_cce_metadata_get_6750: API to get CCE metadata 1288 * from rx_msdu_end TLV 1289 * @buf: pointer to the start of RX PKT TLV headers 1290 * 1291 * Return: cce_metadata 1292 */ 1293 static uint16_t 1294 hal_rx_msdu_cce_metadata_get_6750(uint8_t *buf) 1295 { 1296 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1297 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1298 1299 return HAL_RX_MSDU_END_CCE_METADATA_GET(msdu_end); 1300 } 1301 1302 /** 1303 * hal_rx_msdu_get_flow_params_6750: API to get flow index, flow index invalid 1304 * and flow index timeout from rx_msdu_end TLV 1305 * @buf: pointer to the start of RX PKT TLV headers 1306 * @flow_invalid: pointer to return value of flow_idx_valid 1307 * @flow_timeout: pointer to return value of flow_idx_timeout 1308 * @flow_index: pointer to return value of flow_idx 1309 * 1310 * Return: none 1311 */ 1312 static inline void 1313 hal_rx_msdu_get_flow_params_6750(uint8_t *buf, 1314 bool *flow_invalid, 1315 bool *flow_timeout, 1316 uint32_t *flow_index) 1317 { 1318 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1319 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1320 1321 *flow_invalid = HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(msdu_end); 1322 *flow_timeout = HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(msdu_end); 1323 *flow_index = HAL_RX_MSDU_END_FLOW_IDX_GET(msdu_end); 1324 } 1325 1326 /** 1327 * hal_rx_tlv_get_tcp_chksum_6750() - API to get tcp checksum 1328 * @buf: rx_tlv_hdr 1329 * 1330 * Return: tcp checksum 1331 */ 1332 static uint16_t 1333 hal_rx_tlv_get_tcp_chksum_6750(uint8_t *buf) 1334 { 1335 return HAL_RX_TLV_GET_TCP_CHKSUM(buf); 1336 } 1337 1338 /** 1339 * hal_rx_get_rx_sequence_6750(): Function to retrieve rx sequence number 1340 * 1341 * @nbuf: Network buffer 1342 * Returns: rx sequence number 1343 */ 1344 static 1345 uint16_t hal_rx_get_rx_sequence_6750(uint8_t *buf) 1346 { 1347 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 1348 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 1349 1350 return HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info); 1351 } 1352 1353 #define UMAC_WINDOW_REMAP_RANGE 0x14 1354 #define CE_WINDOW_REMAP_RANGE 0x37 1355 #define CMEM_WINDOW_REMAP_RANGE 0x2 1356 1357 /** 1358 * hal_get_window_address_6750(): Function to get hp/tp address 1359 * @hal_soc: Pointer to hal_soc 1360 * @addr: address offset of register 1361 * 1362 * Return: modified address offset of register 1363 */ 1364 static inline qdf_iomem_t hal_get_window_address_6750(struct hal_soc *hal_soc, 1365 qdf_iomem_t addr) 1366 { 1367 uint32_t offset; 1368 uint32_t window; 1369 uint8_t scale; 1370 1371 offset = addr - hal_soc->dev_base_addr; 1372 window = (offset >> WINDOW_SHIFT) & WINDOW_VALUE_MASK; 1373 1374 /* UMAC: 2nd window, CE: 3rd window, CMEM: 4th window */ 1375 switch (window) { 1376 case UMAC_WINDOW_REMAP_RANGE: 1377 scale = 1; 1378 break; 1379 case CE_WINDOW_REMAP_RANGE: 1380 scale = 2; 1381 break; 1382 case CMEM_WINDOW_REMAP_RANGE: 1383 scale = 3; 1384 break; 1385 default: 1386 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR, 1387 "%s: ERROR: Accessing Wrong register\n", __func__); 1388 qdf_assert_always(0); 1389 return 0; 1390 } 1391 1392 return hal_soc->dev_base_addr + (scale * WINDOW_START) + 1393 (offset & WINDOW_RANGE_MASK); 1394 } 1395 1396 /** 1397 * hal_rx_get_fisa_cumulative_l4_checksum_6750() - Retrieve cumulative 1398 * checksum 1399 * @buf: buffer pointer 1400 * 1401 * Return: cumulative checksum 1402 */ 1403 static inline 1404 uint16_t hal_rx_get_fisa_cumulative_l4_checksum_6750(uint8_t *buf) 1405 { 1406 return HAL_RX_TLV_GET_FISA_CUMULATIVE_L4_CHECKSUM(buf); 1407 } 1408 1409 /** 1410 * hal_rx_get_fisa_cumulative_ip_length_6750() - Retrieve cumulative 1411 * ip length 1412 * @buf: buffer pointer 1413 * 1414 * Return: cumulative length 1415 */ 1416 static inline 1417 uint16_t hal_rx_get_fisa_cumulative_ip_length_6750(uint8_t *buf) 1418 { 1419 return HAL_RX_TLV_GET_FISA_CUMULATIVE_IP_LENGTH(buf); 1420 } 1421 1422 /** 1423 * hal_rx_get_udp_proto_6750() - Retrieve udp proto value 1424 * @buf: buffer 1425 * 1426 * Return: udp proto bit 1427 */ 1428 static inline 1429 bool hal_rx_get_udp_proto_6750(uint8_t *buf) 1430 { 1431 return HAL_RX_TLV_GET_UDP_PROTO(buf); 1432 } 1433 1434 /** 1435 * hal_rx_get_flow_agg_continuation_6750() - retrieve flow agg 1436 * continuation 1437 * @buf: buffer 1438 * 1439 * Return: flow agg 1440 */ 1441 static inline 1442 bool hal_rx_get_flow_agg_continuation_6750(uint8_t *buf) 1443 { 1444 return HAL_RX_TLV_GET_FLOW_AGGR_CONT(buf); 1445 } 1446 1447 /** 1448 * hal_rx_get_flow_agg_count_6750()- Retrieve flow agg count 1449 * @buf: buffer 1450 * 1451 * Return: flow agg count 1452 */ 1453 static inline 1454 uint8_t hal_rx_get_flow_agg_count_6750(uint8_t *buf) 1455 { 1456 return HAL_RX_TLV_GET_FLOW_AGGR_COUNT(buf); 1457 } 1458 1459 /** 1460 * hal_rx_get_fisa_timeout_6750() - Retrieve fisa timeout 1461 * @buf: buffer 1462 * 1463 * Return: fisa timeout 1464 */ 1465 static inline 1466 bool hal_rx_get_fisa_timeout_6750(uint8_t *buf) 1467 { 1468 return HAL_RX_TLV_GET_FISA_TIMEOUT(buf); 1469 } 1470 1471 /** 1472 * hal_rx_mpdu_start_tlv_tag_valid_6750 () - API to check if RX_MPDU_START 1473 * tlv tag is valid 1474 * 1475 *@rx_tlv_hdr: start address of rx_pkt_tlvs 1476 * 1477 * Return: true if RX_MPDU_START is valid, else false. 1478 */ 1479 static uint8_t hal_rx_mpdu_start_tlv_tag_valid_6750(void *rx_tlv_hdr) 1480 { 1481 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)rx_tlv_hdr; 1482 uint32_t tlv_tag; 1483 1484 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(&rx_desc->mpdu_start_tlv); 1485 1486 return tlv_tag == WIFIRX_MPDU_START_E ? true : false; 1487 } 1488 1489 /** 1490 * hal_reo_set_err_dst_remap_6750(): Function to set REO error destination 1491 * ring remap register 1492 * @hal_soc: Pointer to hal_soc 1493 * 1494 * Return: none. 1495 */ 1496 static void 1497 hal_reo_set_err_dst_remap_6750(void *hal_soc) 1498 { 1499 /* 1500 * Set REO error 2k jump (error code 5) / OOR (error code 7) 1501 * frame routed to REO2TCL ring. 1502 */ 1503 uint32_t dst_remap_ix0 = 1504 HAL_REO_ERR_REMAP_IX0(REO_REMAP_RELEASE, 0) | 1505 HAL_REO_ERR_REMAP_IX0(REO_REMAP_RELEASE, 1) | 1506 HAL_REO_ERR_REMAP_IX0(REO_REMAP_RELEASE, 2) | 1507 HAL_REO_ERR_REMAP_IX0(REO_REMAP_RELEASE, 3) | 1508 HAL_REO_ERR_REMAP_IX0(REO_REMAP_RELEASE, 4) | 1509 HAL_REO_ERR_REMAP_IX0(REO_REMAP_TCL, 5) | 1510 HAL_REO_ERR_REMAP_IX0(REO_REMAP_TCL, 6) | 1511 HAL_REO_ERR_REMAP_IX0(REO_REMAP_TCL, 7); 1512 1513 uint32_t dst_remap_ix1 = 1514 HAL_REO_ERR_REMAP_IX1(REO_REMAP_RELEASE, 14) | 1515 HAL_REO_ERR_REMAP_IX1(REO_REMAP_RELEASE, 13) | 1516 HAL_REO_ERR_REMAP_IX1(REO_REMAP_RELEASE, 12) | 1517 HAL_REO_ERR_REMAP_IX1(REO_REMAP_RELEASE, 11) | 1518 HAL_REO_ERR_REMAP_IX1(REO_REMAP_RELEASE, 10) | 1519 HAL_REO_ERR_REMAP_IX1(REO_REMAP_RELEASE, 9) | 1520 HAL_REO_ERR_REMAP_IX1(REO_REMAP_TCL, 8); 1521 1522 HAL_REG_WRITE(hal_soc, 1523 HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ADDR( 1524 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1525 dst_remap_ix0); 1526 1527 hal_info("HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0 0x%x", 1528 HAL_REG_READ( 1529 hal_soc, 1530 HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ADDR( 1531 SEQ_WCSS_UMAC_REO_REG_OFFSET))); 1532 1533 HAL_REG_WRITE(hal_soc, 1534 HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ADDR( 1535 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1536 dst_remap_ix1); 1537 1538 hal_info("HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1 0x%x", 1539 HAL_REG_READ( 1540 hal_soc, 1541 HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ADDR( 1542 SEQ_WCSS_UMAC_REO_REG_OFFSET))); 1543 } 1544 1545 /* 1546 * hal_rx_flow_setup_fse_6750() - Setup a flow search entry in HW FST 1547 * @fst: Pointer to the Rx Flow Search Table 1548 * @table_offset: offset into the table where the flow is to be setup 1549 * @flow: Flow Parameters 1550 * 1551 * Flow table entry fields are updated in host byte order, little endian order. 1552 * 1553 * Return: Success/Failure 1554 */ 1555 static void * 1556 hal_rx_flow_setup_fse_6750(uint8_t *rx_fst, uint32_t table_offset, 1557 uint8_t *rx_flow) 1558 { 1559 struct hal_rx_fst *fst = (struct hal_rx_fst *)rx_fst; 1560 struct hal_rx_flow *flow = (struct hal_rx_flow *)rx_flow; 1561 uint8_t *fse; 1562 bool fse_valid; 1563 1564 if (table_offset >= fst->max_entries) { 1565 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR, 1566 "HAL FSE table offset %u exceeds max entries %u", 1567 table_offset, fst->max_entries); 1568 return NULL; 1569 } 1570 1571 fse = (uint8_t *)fst->base_vaddr + 1572 (table_offset * HAL_RX_FST_ENTRY_SIZE); 1573 1574 fse_valid = HAL_GET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, VALID); 1575 1576 if (fse_valid) { 1577 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_DEBUG, 1578 "HAL FSE %pK already valid", fse); 1579 return NULL; 1580 } 1581 1582 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_0, SRC_IP_127_96) = 1583 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_0, SRC_IP_127_96, 1584 (flow->tuple_info.src_ip_127_96)); 1585 1586 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_1, SRC_IP_95_64) = 1587 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_1, SRC_IP_95_64, 1588 (flow->tuple_info.src_ip_95_64)); 1589 1590 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_2, SRC_IP_63_32) = 1591 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_2, SRC_IP_63_32, 1592 (flow->tuple_info.src_ip_63_32)); 1593 1594 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_3, SRC_IP_31_0) = 1595 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_3, SRC_IP_31_0, 1596 (flow->tuple_info.src_ip_31_0)); 1597 1598 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_4, DEST_IP_127_96) = 1599 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_4, DEST_IP_127_96, 1600 (flow->tuple_info.dest_ip_127_96)); 1601 1602 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_5, DEST_IP_95_64) = 1603 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_5, DEST_IP_95_64, 1604 (flow->tuple_info.dest_ip_95_64)); 1605 1606 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_6, DEST_IP_63_32) = 1607 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_6, DEST_IP_63_32, 1608 (flow->tuple_info.dest_ip_63_32)); 1609 1610 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_7, DEST_IP_31_0) = 1611 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_7, DEST_IP_31_0, 1612 (flow->tuple_info.dest_ip_31_0)); 1613 1614 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, DEST_PORT); 1615 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, DEST_PORT) |= 1616 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_8, DEST_PORT, 1617 (flow->tuple_info.dest_port)); 1618 1619 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, SRC_PORT); 1620 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, SRC_PORT) |= 1621 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_8, SRC_PORT, 1622 (flow->tuple_info.src_port)); 1623 1624 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, L4_PROTOCOL); 1625 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, L4_PROTOCOL) |= 1626 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, L4_PROTOCOL, 1627 flow->tuple_info.l4_protocol); 1628 1629 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_HANDLER); 1630 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_HANDLER) |= 1631 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_HANDLER, 1632 flow->reo_destination_handler); 1633 1634 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, VALID); 1635 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, VALID) |= 1636 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, VALID, 1); 1637 1638 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_10, METADATA); 1639 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_10, METADATA) = 1640 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_10, METADATA, 1641 (flow->fse_metadata)); 1642 1643 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_INDICATION); 1644 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_INDICATION) |= 1645 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, 1646 REO_DESTINATION_INDICATION, 1647 flow->reo_destination_indication); 1648 1649 /* Reset all the other fields in FSE */ 1650 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, RESERVED_9); 1651 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, MSDU_DROP); 1652 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_11, MSDU_COUNT); 1653 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_12, MSDU_BYTE_COUNT); 1654 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_13, TIMESTAMP); 1655 1656 return fse; 1657 } 1658 1659 /* 1660 * hal_rx_flow_setup_cmem_fse_6750() - Setup a flow search entry in HW CMEM FST 1661 * @hal_soc: hal_soc reference 1662 * @cmem_ba: CMEM base address 1663 * @table_offset: offset into the table where the flow is to be setup 1664 * @flow: Flow Parameters 1665 * 1666 * Return: Success/Failure 1667 */ 1668 static uint32_t 1669 hal_rx_flow_setup_cmem_fse_6750(struct hal_soc *hal_soc, uint32_t cmem_ba, 1670 uint32_t table_offset, uint8_t *rx_flow) 1671 { 1672 struct hal_rx_flow *flow = (struct hal_rx_flow *)rx_flow; 1673 uint32_t fse_offset; 1674 uint32_t value; 1675 1676 fse_offset = cmem_ba + (table_offset * HAL_RX_FST_ENTRY_SIZE); 1677 1678 /* Reset the Valid bit */ 1679 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY_9, 1680 VALID), 0); 1681 1682 value = HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_0, SRC_IP_127_96, 1683 (flow->tuple_info.src_ip_127_96)); 1684 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY_0, 1685 SRC_IP_127_96), value); 1686 1687 value = HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_1, SRC_IP_95_64, 1688 (flow->tuple_info.src_ip_95_64)); 1689 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY_1, 1690 SRC_IP_95_64), value); 1691 1692 value = HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_2, SRC_IP_63_32, 1693 (flow->tuple_info.src_ip_63_32)); 1694 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY_2, 1695 SRC_IP_63_32), value); 1696 1697 value = HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_3, SRC_IP_31_0, 1698 (flow->tuple_info.src_ip_31_0)); 1699 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY_3, 1700 SRC_IP_31_0), value); 1701 1702 value = HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_4, DEST_IP_127_96, 1703 (flow->tuple_info.dest_ip_127_96)); 1704 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY_4, 1705 DEST_IP_127_96), value); 1706 1707 value = HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_5, DEST_IP_95_64, 1708 (flow->tuple_info.dest_ip_95_64)); 1709 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY_5, 1710 DEST_IP_95_64), value); 1711 1712 value = HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_6, DEST_IP_63_32, 1713 (flow->tuple_info.dest_ip_63_32)); 1714 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY_6, 1715 DEST_IP_63_32), value); 1716 1717 value = HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_7, DEST_IP_31_0, 1718 (flow->tuple_info.dest_ip_31_0)); 1719 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY_7, 1720 DEST_IP_31_0), value); 1721 1722 value = 0 | HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_8, DEST_PORT, 1723 (flow->tuple_info.dest_port)); 1724 value |= HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_8, SRC_PORT, 1725 (flow->tuple_info.src_port)); 1726 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY_8, 1727 SRC_PORT), value); 1728 1729 value = HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_10, METADATA, 1730 (flow->fse_metadata)); 1731 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY_10, 1732 METADATA), value); 1733 1734 /* Reset all the other fields in FSE */ 1735 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY_11, 1736 MSDU_COUNT), 0); 1737 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY_12, 1738 MSDU_BYTE_COUNT), 0); 1739 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY_13, 1740 TIMESTAMP), 0); 1741 1742 value = 0 | HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, L4_PROTOCOL, 1743 flow->tuple_info.l4_protocol); 1744 value |= HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_HANDLER, 1745 flow->reo_destination_handler); 1746 value |= HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, 1747 REO_DESTINATION_INDICATION, 1748 flow->reo_destination_indication); 1749 value |= HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, VALID, 1); 1750 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY_9, 1751 L4_PROTOCOL), value); 1752 1753 return fse_offset; 1754 } 1755 1756 /** 1757 * hal_rx_flow_get_cmem_fse_ts_6750() - Get timestamp field from CMEM FSE 1758 * @hal_soc: hal_soc reference 1759 * @fse_offset: CMEM FSE offset 1760 * 1761 * Return: Timestamp 1762 */ 1763 static uint32_t hal_rx_flow_get_cmem_fse_ts_6750(struct hal_soc *hal_soc, 1764 uint32_t fse_offset) 1765 { 1766 return HAL_CMEM_READ(hal_soc, fse_offset + 1767 HAL_OFFSET(RX_FLOW_SEARCH_ENTRY_13, TIMESTAMP)); 1768 } 1769 1770 /** 1771 * hal_rx_flow_get_cmem_fse_6750() - Get FSE from CMEM 1772 * @hal_soc: hal_soc reference 1773 * @fse_offset: CMEM FSE offset 1774 * @fse: reference where FSE will be copied 1775 * @len: length of FSE 1776 * 1777 * Return: If read is successful or not 1778 */ 1779 static void 1780 hal_rx_flow_get_cmem_fse_6750(struct hal_soc *hal_soc, uint32_t fse_offset, 1781 uint32_t *fse, qdf_size_t len) 1782 { 1783 int i; 1784 1785 if (len != HAL_RX_FST_ENTRY_SIZE) 1786 return; 1787 1788 for (i = 0; i < NUM_OF_DWORDS_RX_FLOW_SEARCH_ENTRY; i++) 1789 fse[i] = HAL_CMEM_READ(hal_soc, fse_offset + i * 4); 1790 } 1791 1792 /** 1793 * hal_rx_msdu_get_reo_destination_indication_6750: API to get 1794 * reo_destination_indication from rx_msdu_end TLV 1795 * @buf: pointer to the start of RX PKT TLV headers 1796 * @reo_destination_indication: pointer to return value of reo_destination_indication 1797 * 1798 * Return: none 1799 */ 1800 static void 1801 hal_rx_msdu_get_reo_destination_indication_6750(uint8_t *buf, 1802 uint32_t *reo_destination_indication) 1803 { 1804 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1805 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1806 1807 *reo_destination_indication = HAL_RX_MSDU_END_REO_DEST_IND_GET(msdu_end); 1808 } 1809 1810 static 1811 void hal_compute_reo_remap_ix2_ix3_6750(uint32_t *ring, uint32_t num_rings, 1812 uint32_t *remap1, uint32_t *remap2) 1813 { 1814 switch (num_rings) { 1815 case 3: 1816 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 1817 HAL_REO_REMAP_IX2(ring[1], 17) | 1818 HAL_REO_REMAP_IX2(ring[2], 18) | 1819 HAL_REO_REMAP_IX2(ring[0], 19) | 1820 HAL_REO_REMAP_IX2(ring[1], 20) | 1821 HAL_REO_REMAP_IX2(ring[2], 21) | 1822 HAL_REO_REMAP_IX2(ring[0], 22) | 1823 HAL_REO_REMAP_IX2(ring[1], 23); 1824 1825 *remap2 = HAL_REO_REMAP_IX3(ring[2], 24) | 1826 HAL_REO_REMAP_IX3(ring[0], 25) | 1827 HAL_REO_REMAP_IX3(ring[1], 26) | 1828 HAL_REO_REMAP_IX3(ring[2], 27) | 1829 HAL_REO_REMAP_IX3(ring[0], 28) | 1830 HAL_REO_REMAP_IX3(ring[1], 29) | 1831 HAL_REO_REMAP_IX3(ring[2], 30) | 1832 HAL_REO_REMAP_IX3(ring[0], 31); 1833 break; 1834 case 4: 1835 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 1836 HAL_REO_REMAP_IX2(ring[1], 17) | 1837 HAL_REO_REMAP_IX2(ring[2], 18) | 1838 HAL_REO_REMAP_IX2(ring[3], 19) | 1839 HAL_REO_REMAP_IX2(ring[0], 20) | 1840 HAL_REO_REMAP_IX2(ring[1], 21) | 1841 HAL_REO_REMAP_IX2(ring[2], 22) | 1842 HAL_REO_REMAP_IX2(ring[3], 23); 1843 1844 *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) | 1845 HAL_REO_REMAP_IX3(ring[1], 25) | 1846 HAL_REO_REMAP_IX3(ring[2], 26) | 1847 HAL_REO_REMAP_IX3(ring[3], 27) | 1848 HAL_REO_REMAP_IX3(ring[0], 28) | 1849 HAL_REO_REMAP_IX3(ring[1], 29) | 1850 HAL_REO_REMAP_IX3(ring[2], 30) | 1851 HAL_REO_REMAP_IX3(ring[3], 31); 1852 break; 1853 } 1854 } 1855 1856 static 1857 void hal_compute_reo_remap_ix0_6750(uint32_t *remap0) 1858 { 1859 *remap0 = HAL_REO_REMAP_IX0(REO_REMAP_SW1, 0) | 1860 HAL_REO_REMAP_IX0(REO_REMAP_SW1, 1) | 1861 HAL_REO_REMAP_IX0(REO_REMAP_SW2, 2) | 1862 HAL_REO_REMAP_IX0(REO_REMAP_SW3, 3) | 1863 HAL_REO_REMAP_IX0(REO_REMAP_SW2, 4) | 1864 HAL_REO_REMAP_IX0(REO_REMAP_RELEASE, 5) | 1865 HAL_REO_REMAP_IX0(REO_REMAP_FW, 6) | 1866 HAL_REO_REMAP_IX0(REO_REMAP_FW, 7); 1867 } 1868 1869 #ifdef WLAN_FEATURE_MARK_FIRST_WAKEUP_PACKET 1870 /** 1871 * hal_get_first_wow_wakeup_packet_6750(): Function to retrieve 1872 * rx_msdu_end_1_reserved_1a 1873 * 1874 * reserved_1a is used by target to tag the first packet that wakes up host from 1875 * WoW 1876 * 1877 * @buf: Network buffer 1878 * 1879 * Dummy function for QCA6750 1880 * 1881 * Returns: 1 to indicate it is first packet received that wakes up host from 1882 * WoW. Otherwise 0 1883 */ 1884 static inline uint8_t hal_get_first_wow_wakeup_packet_6750(uint8_t *buf) 1885 { 1886 return 0; 1887 } 1888 #endif 1889 1890 static void hal_hw_txrx_ops_attach_qca6750(struct hal_soc *hal_soc) 1891 { 1892 /* init and setup */ 1893 hal_soc->ops->hal_srng_dst_hw_init = hal_srng_dst_hw_init_generic; 1894 hal_soc->ops->hal_srng_src_hw_init = hal_srng_src_hw_init_generic; 1895 hal_soc->ops->hal_get_hw_hptp = hal_get_hw_hptp_generic; 1896 hal_soc->ops->hal_reo_setup = hal_reo_setup_generic_li; 1897 hal_soc->ops->hal_get_window_address = hal_get_window_address_6750; 1898 hal_soc->ops->hal_reo_set_err_dst_remap = hal_reo_set_err_dst_remap_6750; 1899 1900 /* tx */ 1901 hal_soc->ops->hal_tx_desc_set_dscp_tid_table_id = 1902 hal_tx_desc_set_dscp_tid_table_id_6750; 1903 hal_soc->ops->hal_tx_set_dscp_tid_map = hal_tx_set_dscp_tid_map_6750; 1904 hal_soc->ops->hal_tx_update_dscp_tid = hal_tx_update_dscp_tid_6750; 1905 hal_soc->ops->hal_tx_desc_set_lmac_id = hal_tx_desc_set_lmac_id_6750; 1906 hal_soc->ops->hal_tx_desc_set_buf_addr = 1907 hal_tx_desc_set_buf_addr_generic_li; 1908 hal_soc->ops->hal_tx_desc_set_search_type = 1909 hal_tx_desc_set_search_type_generic_li; 1910 hal_soc->ops->hal_tx_desc_set_search_index = 1911 hal_tx_desc_set_search_index_generic_li; 1912 hal_soc->ops->hal_tx_desc_set_cache_set_num = 1913 hal_tx_desc_set_cache_set_num_generic_li; 1914 hal_soc->ops->hal_tx_comp_get_status = 1915 hal_tx_comp_get_status_generic_li; 1916 hal_soc->ops->hal_tx_comp_get_release_reason = 1917 hal_tx_comp_get_release_reason_generic_li; 1918 hal_soc->ops->hal_get_wbm_internal_error = 1919 hal_get_wbm_internal_error_generic_li; 1920 hal_soc->ops->hal_tx_desc_set_mesh_en = hal_tx_desc_set_mesh_en_6750; 1921 hal_soc->ops->hal_tx_init_cmd_credit_ring = 1922 hal_tx_init_cmd_credit_ring_6750; 1923 1924 /* rx */ 1925 hal_soc->ops->hal_rx_msdu_start_nss_get = 1926 hal_rx_msdu_start_nss_get_6750; 1927 hal_soc->ops->hal_rx_mon_hw_desc_get_mpdu_status = 1928 hal_rx_mon_hw_desc_get_mpdu_status_6750; 1929 hal_soc->ops->hal_rx_get_tlv = hal_rx_get_tlv_6750; 1930 hal_soc->ops->hal_rx_proc_phyrx_other_receive_info_tlv = 1931 hal_rx_proc_phyrx_other_receive_info_tlv_6750; 1932 hal_soc->ops->hal_rx_dump_msdu_start_tlv = 1933 hal_rx_dump_msdu_start_tlv_6750; 1934 hal_soc->ops->hal_rx_dump_msdu_end_tlv = hal_rx_dump_msdu_end_tlv_6750; 1935 hal_soc->ops->hal_get_link_desc_size = hal_get_link_desc_size_6750; 1936 hal_soc->ops->hal_rx_mpdu_start_tid_get = 1937 hal_rx_mpdu_start_tid_get_6750; 1938 hal_soc->ops->hal_rx_msdu_start_reception_type_get = 1939 hal_rx_msdu_start_reception_type_get_6750; 1940 hal_soc->ops->hal_rx_msdu_end_da_idx_get = 1941 hal_rx_msdu_end_da_idx_get_6750; 1942 hal_soc->ops->hal_rx_msdu_desc_info_get_ptr = 1943 hal_rx_msdu_desc_info_get_ptr_6750; 1944 hal_soc->ops->hal_rx_link_desc_msdu0_ptr = 1945 hal_rx_link_desc_msdu0_ptr_6750; 1946 hal_soc->ops->hal_reo_status_get_header = 1947 hal_reo_status_get_header_6750; 1948 hal_soc->ops->hal_rx_status_get_tlv_info = 1949 hal_rx_status_get_tlv_info_generic_li; 1950 hal_soc->ops->hal_rx_wbm_err_info_get = 1951 hal_rx_wbm_err_info_get_generic_li; 1952 hal_soc->ops->hal_rx_dump_mpdu_start_tlv = 1953 hal_rx_dump_mpdu_start_tlv_generic_li; 1954 1955 hal_soc->ops->hal_tx_set_pcp_tid_map = 1956 hal_tx_set_pcp_tid_map_generic_li; 1957 hal_soc->ops->hal_tx_update_pcp_tid_map = 1958 hal_tx_update_pcp_tid_generic_li; 1959 hal_soc->ops->hal_tx_set_tidmap_prty = 1960 hal_tx_update_tidmap_prty_generic_li; 1961 hal_soc->ops->hal_rx_get_rx_fragment_number = 1962 hal_rx_get_rx_fragment_number_6750; 1963 hal_soc->ops->hal_rx_msdu_end_da_is_mcbc_get = 1964 hal_rx_msdu_end_da_is_mcbc_get_6750; 1965 hal_soc->ops->hal_rx_msdu_end_sa_is_valid_get = 1966 hal_rx_msdu_end_sa_is_valid_get_6750; 1967 hal_soc->ops->hal_rx_msdu_end_sa_idx_get = 1968 hal_rx_msdu_end_sa_idx_get_6750; 1969 hal_soc->ops->hal_rx_desc_is_first_msdu = 1970 hal_rx_desc_is_first_msdu_6750; 1971 hal_soc->ops->hal_rx_msdu_end_l3_hdr_padding_get = 1972 hal_rx_msdu_end_l3_hdr_padding_get_6750; 1973 hal_soc->ops->hal_rx_encryption_info_valid = 1974 hal_rx_encryption_info_valid_6750; 1975 hal_soc->ops->hal_rx_print_pn = hal_rx_print_pn_6750; 1976 hal_soc->ops->hal_rx_msdu_end_first_msdu_get = 1977 hal_rx_msdu_end_first_msdu_get_6750; 1978 hal_soc->ops->hal_rx_msdu_end_da_is_valid_get = 1979 hal_rx_msdu_end_da_is_valid_get_6750; 1980 hal_soc->ops->hal_rx_msdu_end_last_msdu_get = 1981 hal_rx_msdu_end_last_msdu_get_6750; 1982 hal_soc->ops->hal_rx_get_mpdu_mac_ad4_valid = 1983 hal_rx_get_mpdu_mac_ad4_valid_6750; 1984 hal_soc->ops->hal_rx_mpdu_start_sw_peer_id_get = 1985 hal_rx_mpdu_start_sw_peer_id_get_6750; 1986 hal_soc->ops->hal_rx_tlv_peer_meta_data_get = 1987 hal_rx_mpdu_peer_meta_data_get_li; 1988 hal_soc->ops->hal_rx_mpdu_get_to_ds = hal_rx_mpdu_get_to_ds_6750; 1989 hal_soc->ops->hal_rx_mpdu_get_fr_ds = hal_rx_mpdu_get_fr_ds_6750; 1990 hal_soc->ops->hal_rx_get_mpdu_frame_control_valid = 1991 hal_rx_get_mpdu_frame_control_valid_6750; 1992 hal_soc->ops->hal_rx_get_frame_ctrl_field = 1993 hal_rx_get_frame_ctrl_field_li; 1994 hal_soc->ops->hal_rx_mpdu_get_addr1 = hal_rx_mpdu_get_addr1_6750; 1995 hal_soc->ops->hal_rx_mpdu_get_addr2 = hal_rx_mpdu_get_addr2_6750; 1996 hal_soc->ops->hal_rx_mpdu_get_addr3 = hal_rx_mpdu_get_addr3_6750; 1997 hal_soc->ops->hal_rx_mpdu_get_addr4 = hal_rx_mpdu_get_addr4_6750; 1998 hal_soc->ops->hal_rx_get_mpdu_sequence_control_valid = 1999 hal_rx_get_mpdu_sequence_control_valid_6750; 2000 hal_soc->ops->hal_rx_is_unicast = hal_rx_is_unicast_6750; 2001 hal_soc->ops->hal_rx_tid_get = hal_rx_tid_get_6750; 2002 hal_soc->ops->hal_rx_hw_desc_get_ppduid_get = 2003 hal_rx_hw_desc_get_ppduid_get_6750; 2004 hal_soc->ops->hal_rx_msdu0_buffer_addr_lsb = 2005 hal_rx_msdu0_buffer_addr_lsb_6750; 2006 hal_soc->ops->hal_rx_msdu_desc_info_ptr_get = 2007 hal_rx_msdu_desc_info_ptr_get_6750; 2008 hal_soc->ops->hal_ent_mpdu_desc_info = hal_ent_mpdu_desc_info_6750; 2009 hal_soc->ops->hal_dst_mpdu_desc_info = hal_dst_mpdu_desc_info_6750; 2010 hal_soc->ops->hal_rx_get_fc_valid = hal_rx_get_fc_valid_6750; 2011 hal_soc->ops->hal_rx_get_to_ds_flag = hal_rx_get_to_ds_flag_6750; 2012 hal_soc->ops->hal_rx_get_mac_addr2_valid = 2013 hal_rx_get_mac_addr2_valid_6750; 2014 hal_soc->ops->hal_rx_get_filter_category = 2015 hal_rx_get_filter_category_6750; 2016 hal_soc->ops->hal_rx_get_ppdu_id = hal_rx_get_ppdu_id_6750; 2017 hal_soc->ops->hal_reo_config = hal_reo_config_6750; 2018 hal_soc->ops->hal_rx_msdu_flow_idx_get = hal_rx_msdu_flow_idx_get_6750; 2019 hal_soc->ops->hal_rx_msdu_flow_idx_invalid = 2020 hal_rx_msdu_flow_idx_invalid_6750; 2021 hal_soc->ops->hal_rx_msdu_flow_idx_timeout = 2022 hal_rx_msdu_flow_idx_timeout_6750; 2023 hal_soc->ops->hal_rx_msdu_fse_metadata_get = 2024 hal_rx_msdu_fse_metadata_get_6750; 2025 hal_soc->ops->hal_rx_msdu_cce_match_get = 2026 hal_rx_msdu_cce_match_get_li; 2027 hal_soc->ops->hal_rx_msdu_cce_metadata_get = 2028 hal_rx_msdu_cce_metadata_get_6750; 2029 hal_soc->ops->hal_rx_msdu_get_flow_params = 2030 hal_rx_msdu_get_flow_params_6750; 2031 hal_soc->ops->hal_rx_tlv_get_tcp_chksum = 2032 hal_rx_tlv_get_tcp_chksum_6750; 2033 hal_soc->ops->hal_rx_get_rx_sequence = hal_rx_get_rx_sequence_6750; 2034 #if defined(QCA_WIFI_QCA6750) && defined(WLAN_CFR_ENABLE) && \ 2035 defined(WLAN_ENH_CFR_ENABLE) 2036 hal_soc->ops->hal_rx_get_bb_info = hal_rx_get_bb_info_6750; 2037 hal_soc->ops->hal_rx_get_rtt_info = hal_rx_get_rtt_info_6750; 2038 #endif 2039 /* rx - msdu end fast path info fields */ 2040 hal_soc->ops->hal_rx_msdu_packet_metadata_get = 2041 hal_rx_msdu_packet_metadata_get_generic_li; 2042 hal_soc->ops->hal_rx_get_fisa_cumulative_l4_checksum = 2043 hal_rx_get_fisa_cumulative_l4_checksum_6750; 2044 hal_soc->ops->hal_rx_get_fisa_cumulative_ip_length = 2045 hal_rx_get_fisa_cumulative_ip_length_6750; 2046 hal_soc->ops->hal_rx_get_udp_proto = hal_rx_get_udp_proto_6750; 2047 hal_soc->ops->hal_rx_get_fisa_flow_agg_continuation = 2048 hal_rx_get_flow_agg_continuation_6750; 2049 hal_soc->ops->hal_rx_get_fisa_flow_agg_count = 2050 hal_rx_get_flow_agg_count_6750; 2051 hal_soc->ops->hal_rx_get_fisa_timeout = hal_rx_get_fisa_timeout_6750; 2052 hal_soc->ops->hal_rx_mpdu_start_tlv_tag_valid = 2053 hal_rx_mpdu_start_tlv_tag_valid_6750; 2054 2055 /* rx - TLV struct offsets */ 2056 hal_soc->ops->hal_rx_msdu_end_offset_get = 2057 hal_rx_msdu_end_offset_get_generic; 2058 hal_soc->ops->hal_rx_attn_offset_get = hal_rx_attn_offset_get_generic; 2059 hal_soc->ops->hal_rx_msdu_start_offset_get = 2060 hal_rx_msdu_start_offset_get_generic; 2061 hal_soc->ops->hal_rx_mpdu_start_offset_get = 2062 hal_rx_mpdu_start_offset_get_generic; 2063 hal_soc->ops->hal_rx_mpdu_end_offset_get = 2064 hal_rx_mpdu_end_offset_get_generic; 2065 #ifndef NO_RX_PKT_HDR_TLV 2066 hal_soc->ops->hal_rx_pkt_tlv_offset_get = 2067 hal_rx_pkt_tlv_offset_get_generic; 2068 #endif 2069 hal_soc->ops->hal_rx_flow_setup_fse = hal_rx_flow_setup_fse_6750; 2070 hal_soc->ops->hal_rx_flow_get_tuple_info = 2071 hal_rx_flow_get_tuple_info_li; 2072 hal_soc->ops->hal_rx_flow_delete_entry = 2073 hal_rx_flow_delete_entry_li; 2074 hal_soc->ops->hal_rx_fst_get_fse_size = hal_rx_fst_get_fse_size_li; 2075 hal_soc->ops->hal_compute_reo_remap_ix2_ix3 = 2076 hal_compute_reo_remap_ix2_ix3_6750; 2077 2078 /* CMEM FSE */ 2079 hal_soc->ops->hal_rx_flow_setup_cmem_fse = 2080 hal_rx_flow_setup_cmem_fse_6750; 2081 hal_soc->ops->hal_rx_flow_get_cmem_fse_ts = 2082 hal_rx_flow_get_cmem_fse_ts_6750; 2083 hal_soc->ops->hal_rx_flow_get_cmem_fse = hal_rx_flow_get_cmem_fse_6750; 2084 hal_soc->ops->hal_rx_msdu_get_reo_destination_indication = 2085 hal_rx_msdu_get_reo_destination_indication_6750; 2086 hal_soc->ops->hal_setup_link_idle_list = 2087 hal_setup_link_idle_list_generic_li; 2088 #ifdef WLAN_FEATURE_MARK_FIRST_WAKEUP_PACKET 2089 hal_soc->ops->hal_get_first_wow_wakeup_packet = 2090 hal_get_first_wow_wakeup_packet_6750; 2091 #endif 2092 hal_soc->ops->hal_compute_reo_remap_ix0 = 2093 hal_compute_reo_remap_ix0_6750; 2094 hal_soc->ops->hal_rx_tlv_msdu_len_get = 2095 hal_rx_msdu_start_get_len_6750; 2096 }; 2097 2098 struct hal_hw_srng_config hw_srng_table_6750[] = { 2099 /* TODO: max_rings can populated by querying HW capabilities */ 2100 { /* REO_DST */ 2101 .start_ring_id = HAL_SRNG_REO2SW1, 2102 .max_rings = 4, 2103 .entry_size = sizeof(struct reo_destination_ring) >> 2, 2104 .lmac_ring = FALSE, 2105 .ring_dir = HAL_SRNG_DST_RING, 2106 .reg_start = { 2107 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR( 2108 SEQ_WCSS_UMAC_REO_REG_OFFSET), 2109 HWIO_REO_R2_REO2SW1_RING_HP_ADDR( 2110 SEQ_WCSS_UMAC_REO_REG_OFFSET) 2111 }, 2112 .reg_size = { 2113 HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(0) - 2114 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(0), 2115 HWIO_REO_R2_REO2SW2_RING_HP_ADDR(0) - 2116 HWIO_REO_R2_REO2SW1_RING_HP_ADDR(0), 2117 }, 2118 .max_size = 2119 HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_BMSK >> 2120 HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_SHFT, 2121 }, 2122 { /* REO_EXCEPTION */ 2123 /* Designating REO2TCL ring as exception ring. This ring is 2124 * similar to other REO2SW rings though it is named as REO2TCL. 2125 * Any of theREO2SW rings can be used as exception ring. 2126 */ 2127 .start_ring_id = HAL_SRNG_REO2TCL, 2128 .max_rings = 1, 2129 .entry_size = sizeof(struct reo_destination_ring) >> 2, 2130 .lmac_ring = FALSE, 2131 .ring_dir = HAL_SRNG_DST_RING, 2132 .reg_start = { 2133 HWIO_REO_R0_REO2TCL_RING_BASE_LSB_ADDR( 2134 SEQ_WCSS_UMAC_REO_REG_OFFSET), 2135 HWIO_REO_R2_REO2TCL_RING_HP_ADDR( 2136 SEQ_WCSS_UMAC_REO_REG_OFFSET) 2137 }, 2138 /* Single ring - provide ring size if multiple rings of this 2139 * type are supported 2140 */ 2141 .reg_size = {}, 2142 .max_size = 2143 HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_BMSK >> 2144 HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_SHFT, 2145 }, 2146 { /* REO_REINJECT */ 2147 .start_ring_id = HAL_SRNG_SW2REO, 2148 .max_rings = 1, 2149 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 2150 .lmac_ring = FALSE, 2151 .ring_dir = HAL_SRNG_SRC_RING, 2152 .reg_start = { 2153 HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR( 2154 SEQ_WCSS_UMAC_REO_REG_OFFSET), 2155 HWIO_REO_R2_SW2REO_RING_HP_ADDR( 2156 SEQ_WCSS_UMAC_REO_REG_OFFSET) 2157 }, 2158 /* Single ring - provide ring size if multiple rings of this 2159 * type are supported 2160 */ 2161 .reg_size = {}, 2162 .max_size = HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_BMSK >> 2163 HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_SHFT, 2164 }, 2165 { /* REO_CMD */ 2166 .start_ring_id = HAL_SRNG_REO_CMD, 2167 .max_rings = 1, 2168 .entry_size = (sizeof(struct tlv_32_hdr) + 2169 sizeof(struct reo_get_queue_stats)) >> 2, 2170 .lmac_ring = FALSE, 2171 .ring_dir = HAL_SRNG_SRC_RING, 2172 .reg_start = { 2173 HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR( 2174 SEQ_WCSS_UMAC_REO_REG_OFFSET), 2175 HWIO_REO_R2_REO_CMD_RING_HP_ADDR( 2176 SEQ_WCSS_UMAC_REO_REG_OFFSET), 2177 }, 2178 /* Single ring - provide ring size if multiple rings of this 2179 * type are supported 2180 */ 2181 .reg_size = {}, 2182 .max_size = 2183 HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_BMSK >> 2184 HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_SHFT, 2185 }, 2186 { /* REO_STATUS */ 2187 .start_ring_id = HAL_SRNG_REO_STATUS, 2188 .max_rings = 1, 2189 .entry_size = (sizeof(struct tlv_32_hdr) + 2190 sizeof(struct reo_get_queue_stats_status)) >> 2, 2191 .lmac_ring = FALSE, 2192 .ring_dir = HAL_SRNG_DST_RING, 2193 .reg_start = { 2194 HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR( 2195 SEQ_WCSS_UMAC_REO_REG_OFFSET), 2196 HWIO_REO_R2_REO_STATUS_RING_HP_ADDR( 2197 SEQ_WCSS_UMAC_REO_REG_OFFSET), 2198 }, 2199 /* Single ring - provide ring size if multiple rings of this 2200 * type are supported 2201 */ 2202 .reg_size = {}, 2203 .max_size = 2204 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> 2205 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, 2206 }, 2207 { /* TCL_DATA */ 2208 .start_ring_id = HAL_SRNG_SW2TCL1, 2209 .max_rings = 3, 2210 .entry_size = (sizeof(struct tlv_32_hdr) + 2211 sizeof(struct tcl_data_cmd)) >> 2, 2212 .lmac_ring = FALSE, 2213 .ring_dir = HAL_SRNG_SRC_RING, 2214 .reg_start = { 2215 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR( 2216 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 2217 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR( 2218 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 2219 }, 2220 .reg_size = { 2221 HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(0) - 2222 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(0), 2223 HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(0) - 2224 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(0), 2225 }, 2226 .max_size = 2227 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK >> 2228 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT, 2229 }, 2230 { /* TCL_CMD */ 2231 .start_ring_id = HAL_SRNG_SW2TCL_CMD, 2232 .max_rings = 1, 2233 .entry_size = (sizeof(struct tlv_32_hdr) + 2234 sizeof(struct tcl_gse_cmd)) >> 2, 2235 .lmac_ring = FALSE, 2236 .ring_dir = HAL_SRNG_SRC_RING, 2237 .reg_start = { 2238 HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_ADDR( 2239 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 2240 HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_ADDR( 2241 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 2242 }, 2243 /* Single ring - provide ring size if multiple rings of this 2244 * type are supported 2245 */ 2246 .reg_size = {}, 2247 .max_size = 2248 HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_SIZE_BMSK >> 2249 HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_SIZE_SHFT, 2250 }, 2251 { /* TCL_STATUS */ 2252 .start_ring_id = HAL_SRNG_TCL_STATUS, 2253 .max_rings = 1, 2254 .entry_size = (sizeof(struct tlv_32_hdr) + 2255 sizeof(struct tcl_status_ring)) >> 2, 2256 .lmac_ring = FALSE, 2257 .ring_dir = HAL_SRNG_DST_RING, 2258 .reg_start = { 2259 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR( 2260 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 2261 HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR( 2262 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 2263 }, 2264 /* Single ring - provide ring size if multiple rings of this 2265 * type are supported 2266 */ 2267 .reg_size = {}, 2268 .max_size = 2269 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_BMSK >> 2270 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_SHFT, 2271 }, 2272 { /* CE_SRC */ 2273 .start_ring_id = HAL_SRNG_CE_0_SRC, 2274 .max_rings = 12, 2275 .entry_size = sizeof(struct ce_src_desc) >> 2, 2276 .lmac_ring = FALSE, 2277 .ring_dir = HAL_SRNG_SRC_RING, 2278 .reg_start = { 2279 HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR, 2280 HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR, 2281 }, 2282 .reg_size = { 2283 HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR - 2284 HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR, 2285 HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR - 2286 HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR, 2287 }, 2288 .max_size = 2289 HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >> 2290 HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT 2291 }, 2292 { /* CE_DST */ 2293 .start_ring_id = HAL_SRNG_CE_0_DST, 2294 .max_rings = 12, 2295 .entry_size = 8 >> 2, 2296 /*TODO: entry_size above should actually be 2297 * sizeof(struct ce_dst_desc) >> 2, but couldn't find definition 2298 * of struct ce_dst_desc in HW header files 2299 */ 2300 .lmac_ring = FALSE, 2301 .ring_dir = HAL_SRNG_SRC_RING, 2302 .reg_start = { 2303 HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, 2304 HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR, 2305 }, 2306 .reg_size = { 2307 HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR - 2308 HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, 2309 HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR - 2310 HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR 2311 }, 2312 .max_size = 2313 HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >> 2314 HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT 2315 }, 2316 { /* CE_DST_STATUS */ 2317 .start_ring_id = HAL_SRNG_CE_0_DST_STATUS, 2318 .max_rings = 12, 2319 .entry_size = sizeof(struct ce_stat_desc) >> 2, 2320 .lmac_ring = FALSE, 2321 .ring_dir = HAL_SRNG_DST_RING, 2322 .reg_start = { 2323 HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR, 2324 HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR, 2325 }, 2326 /* TODO: check destination status ring registers */ 2327 .reg_size = { 2328 HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR - 2329 HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, 2330 HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR - 2331 HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR 2332 }, 2333 .max_size = 2334 HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> 2335 HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, 2336 }, 2337 { /* WBM_IDLE_LINK */ 2338 .start_ring_id = HAL_SRNG_WBM_IDLE_LINK, 2339 .max_rings = 1, 2340 .entry_size = sizeof(struct wbm_link_descriptor_ring) >> 2, 2341 .lmac_ring = FALSE, 2342 .ring_dir = HAL_SRNG_SRC_RING, 2343 .reg_start = { 2344 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2345 HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2346 }, 2347 /* Single ring - provide ring size if multiple rings of this 2348 * type are supported 2349 */ 2350 .reg_size = {}, 2351 .max_size = 2352 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_BMSK >> 2353 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_SHFT, 2354 }, 2355 { /* SW2WBM_RELEASE */ 2356 .start_ring_id = HAL_SRNG_WBM_SW_RELEASE, 2357 .max_rings = 1, 2358 .entry_size = sizeof(struct wbm_release_ring) >> 2, 2359 .lmac_ring = FALSE, 2360 .ring_dir = HAL_SRNG_SRC_RING, 2361 .reg_start = { 2362 HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2363 HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2364 }, 2365 /* Single ring - provide ring size if multiple rings of this 2366 * type are supported 2367 */ 2368 .reg_size = {}, 2369 .max_size = 2370 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> 2371 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, 2372 }, 2373 { /* WBM2SW_RELEASE */ 2374 .start_ring_id = HAL_SRNG_WBM2SW0_RELEASE, 2375 #if defined(TX_MULTI_TCL) || defined(CONFIG_PLD_IPCIE_FW_SIM) 2376 .max_rings = 5, 2377 #else 2378 .max_rings = 4, 2379 #endif 2380 .entry_size = sizeof(struct wbm_release_ring) >> 2, 2381 .lmac_ring = FALSE, 2382 .ring_dir = HAL_SRNG_DST_RING, 2383 .reg_start = { 2384 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2385 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2386 }, 2387 .reg_size = { 2388 HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) - 2389 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2390 HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) - 2391 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2392 }, 2393 .max_size = 2394 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> 2395 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, 2396 }, 2397 { /* RXDMA_BUF */ 2398 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA0_BUF0, 2399 #ifdef IPA_OFFLOAD 2400 .max_rings = 3, 2401 #else 2402 .max_rings = 2, 2403 #endif 2404 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 2405 .lmac_ring = TRUE, 2406 .ring_dir = HAL_SRNG_SRC_RING, 2407 /* reg_start is not set because LMAC rings are not accessed 2408 * from host 2409 */ 2410 .reg_start = {}, 2411 .reg_size = {}, 2412 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2413 }, 2414 { /* RXDMA_DST */ 2415 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW0, 2416 .max_rings = 1, 2417 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 2418 .lmac_ring = TRUE, 2419 .ring_dir = HAL_SRNG_DST_RING, 2420 /* reg_start is not set because LMAC rings are not accessed 2421 * from host 2422 */ 2423 .reg_start = {}, 2424 .reg_size = {}, 2425 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2426 }, 2427 { /* RXDMA_MONITOR_BUF */ 2428 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA2_BUF, 2429 .max_rings = 1, 2430 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 2431 .lmac_ring = TRUE, 2432 .ring_dir = HAL_SRNG_SRC_RING, 2433 /* reg_start is not set because LMAC rings are not accessed 2434 * from host 2435 */ 2436 .reg_start = {}, 2437 .reg_size = {}, 2438 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2439 }, 2440 { /* RXDMA_MONITOR_STATUS */ 2441 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_STATBUF, 2442 .max_rings = 1, 2443 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 2444 .lmac_ring = TRUE, 2445 .ring_dir = HAL_SRNG_SRC_RING, 2446 /* reg_start is not set because LMAC rings are not accessed 2447 * from host 2448 */ 2449 .reg_start = {}, 2450 .reg_size = {}, 2451 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2452 }, 2453 { /* RXDMA_MONITOR_DST */ 2454 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW1, 2455 .max_rings = 1, 2456 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 2457 .lmac_ring = TRUE, 2458 .ring_dir = HAL_SRNG_DST_RING, 2459 /* reg_start is not set because LMAC rings are not accessed 2460 * from host 2461 */ 2462 .reg_start = {}, 2463 .reg_size = {}, 2464 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2465 }, 2466 { /* RXDMA_MONITOR_DESC */ 2467 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_DESC, 2468 .max_rings = 1, 2469 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 2470 .lmac_ring = TRUE, 2471 .ring_dir = HAL_SRNG_SRC_RING, 2472 /* reg_start is not set because LMAC rings are not accessed 2473 * from host 2474 */ 2475 .reg_start = {}, 2476 .reg_size = {}, 2477 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2478 }, 2479 { /* DIR_BUF_RX_DMA_SRC */ 2480 .start_ring_id = HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING, 2481 /* 2482 * one ring is for spectral scan 2483 * the other is for cfr 2484 */ 2485 .max_rings = 2, 2486 .entry_size = 2, 2487 .lmac_ring = TRUE, 2488 .ring_dir = HAL_SRNG_SRC_RING, 2489 /* reg_start is not set because LMAC rings are not accessed 2490 * from host 2491 */ 2492 .reg_start = {}, 2493 .reg_size = {}, 2494 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2495 }, 2496 #ifdef WLAN_FEATURE_CIF_CFR 2497 { /* WIFI_POS_SRC */ 2498 .start_ring_id = HAL_SRNG_WIFI_POS_SRC_DMA_RING, 2499 .max_rings = 1, 2500 .entry_size = sizeof(wmi_oem_dma_buf_release_entry) >> 2, 2501 .lmac_ring = TRUE, 2502 .ring_dir = HAL_SRNG_SRC_RING, 2503 /* reg_start is not set because LMAC rings are not accessed 2504 * from host 2505 */ 2506 .reg_start = {}, 2507 .reg_size = {}, 2508 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2509 }, 2510 #endif 2511 { /* REO2PPE */ 0}, 2512 { /* PPE2TCL */ 0}, 2513 { /* PPE_RELEASE */ 0}, 2514 { /* TX_MONITOR_BUF */ 0}, 2515 { /* TX_MONITOR_DST */ 0}, 2516 { /* SW2RXDMA_NEW */ 0}, 2517 }; 2518 2519 /** 2520 * hal_qca6750_attach() - Attach 6750 target specific hal_soc ops, 2521 * offset and srng table 2522 */ 2523 void hal_qca6750_attach(struct hal_soc *hal_soc) 2524 { 2525 hal_soc->hw_srng_table = hw_srng_table_6750; 2526 hal_srng_hw_reg_offset_init_generic(hal_soc); 2527 hal_hw_txrx_default_ops_attach_li(hal_soc); 2528 hal_hw_txrx_ops_attach_qca6750(hal_soc); 2529 } 2530