1 /* 2 * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #include "qdf_types.h" 20 #include "qdf_util.h" 21 #include "qdf_types.h" 22 #include "qdf_lock.h" 23 #include "qdf_mem.h" 24 #include "qdf_nbuf.h" 25 #include "hal_li_hw_headers.h" 26 #include "hal_internal.h" 27 #include "hal_api.h" 28 #include "target_type.h" 29 #include "wcss_version.h" 30 #include "qdf_module.h" 31 #include "hal_flow.h" 32 #include "rx_flow_search_entry.h" 33 #include "hal_rx_flow_info.h" 34 35 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_OFFSET \ 36 RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_OFFSET 37 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_MASK \ 38 RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_MASK 39 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_LSB \ 40 RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_LSB 41 #define UNIFIED_PHYRX_HT_SIG_0_HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS_OFFSET \ 42 PHYRX_L_SIG_B_0_PHYRX_L_SIG_B_INFO_DETAILS_RATE_OFFSET 43 #define UNIFIED_PHYRX_L_SIG_B_0_L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS_OFFSET \ 44 PHYRX_L_SIG_B_0_PHYRX_L_SIG_B_INFO_DETAILS_RATE_OFFSET 45 #define UNIFIED_PHYRX_L_SIG_A_0_L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS_OFFSET \ 46 PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_RATE_OFFSET 47 #define UNIFIED_PHYRX_VHT_SIG_A_0_VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS_OFFSET \ 48 PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_OFFSET 49 #define UNIFIED_PHYRX_HE_SIG_A_SU_0_HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS_OFFSET \ 50 PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_OFFSET 51 #define UNIFIED_PHYRX_HE_SIG_A_MU_DL_0_HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_OFFSET \ 52 PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_OFFSET 53 #define UNIFIED_PHYRX_HE_SIG_B1_MU_0_HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_OFFSET \ 54 PHYRX_HE_SIG_B1_MU_0_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_OFFSET 55 #define UNIFIED_PHYRX_HE_SIG_B2_MU_0_HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_OFFSET \ 56 PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_OFFSET 57 #define UNIFIED_PHYRX_HE_SIG_B2_OFDMA_0_HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_OFFSET \ 58 PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_OFFSET 59 60 #define UNIFIED_PHYRX_RSSI_LEGACY_3_RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS_OFFSET \ 61 PHYRX_RSSI_LEGACY_3_RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS_OFFSET 62 #define UNIFIED_PHYRX_RSSI_LEGACY_19_RECEIVE_RSSI_INFO_PREAMBLE_RSSI_INFO_DETAILS_OFFSET \ 63 PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 64 #define UNIFIED_RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET \ 65 RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 66 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 67 RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET 68 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ 69 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET 70 #define UNIFIED_RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 71 RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET 72 #define UNIFIED_REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 73 REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET 74 #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC \ 75 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER 76 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ 77 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET 78 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 79 RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET 80 #define UNIFIED_TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 81 TCL_DATA_CMD_0_BUF_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 82 #define UNIFIED_TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 83 TCL_DATA_CMD_1_BUF_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 84 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET \ 85 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET 86 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB \ 87 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB 88 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK \ 89 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK 90 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB \ 91 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB 92 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK \ 93 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK 94 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB \ 95 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB 96 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK \ 97 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK 98 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB \ 99 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB 100 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK \ 101 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK 102 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB \ 103 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB 104 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK \ 105 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK 106 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_MASK \ 107 WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MASK 108 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_OFFSET \ 109 WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_OFFSET 110 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_LSB \ 111 WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_LSB 112 113 #include "hal_6750_tx.h" 114 #include "hal_6750_rx.h" 115 #include <hal_generic_api.h> 116 #include "hal_li_rx.h" 117 #include "hal_li_api.h" 118 #include "hal_li_generic_api.h" 119 120 /* 121 * hal_rx_msdu_start_nss_get_6750(): API to get the NSS 122 * Interval from rx_msdu_start 123 * 124 * @buf: pointer to the start of RX PKT TLV header 125 * Return: uint32_t(nss) 126 */ 127 static uint32_t 128 hal_rx_msdu_start_nss_get_6750(uint8_t *buf) 129 { 130 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 131 struct rx_msdu_start *msdu_start = 132 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 133 uint8_t mimo_ss_bitmap; 134 135 mimo_ss_bitmap = HAL_RX_MSDU_START_MIMO_SS_BITMAP(msdu_start); 136 137 return qdf_get_hweight8(mimo_ss_bitmap); 138 } 139 140 /** 141 * hal_rx_mon_hw_desc_get_mpdu_status_6750(): Retrieve MPDU status 142 * 143 * @ hw_desc_addr: Start address of Rx HW TLVs 144 * @ rs: Status for monitor mode 145 * 146 * Return: void 147 */ 148 static void hal_rx_mon_hw_desc_get_mpdu_status_6750(void *hw_desc_addr, 149 struct mon_rx_status *rs) 150 { 151 struct rx_msdu_start *rx_msdu_start; 152 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr; 153 uint32_t reg_value; 154 const uint32_t sgi_hw_to_cdp[] = { 155 CDP_SGI_0_8_US, 156 CDP_SGI_0_4_US, 157 CDP_SGI_1_6_US, 158 CDP_SGI_3_2_US, 159 }; 160 161 rx_msdu_start = &rx_desc->msdu_start_tlv.rx_msdu_start; 162 163 HAL_RX_GET_MSDU_AGGREGATION(rx_desc, rs); 164 165 rs->ant_signal_db = HAL_RX_GET(rx_msdu_start, 166 RX_MSDU_START_5, USER_RSSI); 167 rs->is_stbc = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, STBC); 168 169 reg_value = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, SGI); 170 rs->sgi = sgi_hw_to_cdp[reg_value]; 171 172 reg_value = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, RECEPTION_TYPE); 173 rs->beamformed = (reg_value == HAL_RX_RECEPTION_TYPE_MU_MIMO) ? 1 : 0; 174 /* TODO: rs->beamformed should be set for SU beamforming also */ 175 } 176 177 #define LINK_DESC_SIZE (NUM_OF_DWORDS_RX_MSDU_LINK << 2) 178 179 static uint32_t hal_get_link_desc_size_6750(void) 180 { 181 return LINK_DESC_SIZE; 182 } 183 184 /* 185 * hal_rx_get_tlv_6750(): API to get the tlv 186 * 187 * @rx_tlv: TLV data extracted from the rx packet 188 * Return: uint8_t 189 */ 190 static uint8_t hal_rx_get_tlv_6750(void *rx_tlv) 191 { 192 return HAL_RX_GET(rx_tlv, PHYRX_RSSI_LEGACY_0, RECEIVE_BANDWIDTH); 193 } 194 195 /** 196 * hal_rx_proc_phyrx_other_receive_info_tlv_6750() 197 * - process other receive info TLV 198 * @rx_tlv_hdr: pointer to TLV header 199 * @ppdu_info: pointer to ppdu_info 200 * 201 * Return: None 202 */ 203 static 204 void hal_rx_proc_phyrx_other_receive_info_tlv_6750(void *rx_tlv_hdr, 205 void *ppdu_info_handle) 206 { 207 uint32_t tlv_tag, tlv_len; 208 uint32_t temp_len, other_tlv_len, other_tlv_tag; 209 void *rx_tlv = (uint8_t *)rx_tlv_hdr + HAL_RX_TLV32_HDR_SIZE; 210 void *other_tlv_hdr = NULL; 211 void *other_tlv = NULL; 212 213 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv_hdr); 214 tlv_len = HAL_RX_GET_USER_TLV32_LEN(rx_tlv_hdr); 215 temp_len = 0; 216 217 other_tlv_hdr = rx_tlv + HAL_RX_TLV32_HDR_SIZE; 218 219 other_tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(other_tlv_hdr); 220 other_tlv_len = HAL_RX_GET_USER_TLV32_LEN(other_tlv_hdr); 221 temp_len += other_tlv_len; 222 other_tlv = other_tlv_hdr + HAL_RX_TLV32_HDR_SIZE; 223 224 switch (other_tlv_tag) { 225 default: 226 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR, 227 "%s unhandled TLV type: %d, TLV len:%d", 228 __func__, other_tlv_tag, other_tlv_len); 229 break; 230 } 231 } 232 233 /** 234 * hal_rx_dump_msdu_start_tlv_6750() : dump RX msdu_start TLV in structured 235 * human readable format. 236 * @ msdu_start: pointer the msdu_start TLV in pkt. 237 * @ dbg_level: log level. 238 * 239 * Return: void 240 */ 241 static void hal_rx_dump_msdu_start_tlv_6750(void *msdustart, uint8_t dbg_level) 242 { 243 struct rx_msdu_start *msdu_start = (struct rx_msdu_start *)msdustart; 244 245 hal_verbose_debug( 246 "rx_msdu_start tlv (1/2) - " 247 "rxpcu_mpdu_filter_in_category: %x " 248 "sw_frame_group_id: %x " 249 "phy_ppdu_id: %x " 250 "msdu_length: %x " 251 "ipsec_esp: %x " 252 "l3_offset: %x " 253 "ipsec_ah: %x " 254 "l4_offset: %x " 255 "msdu_number: %x " 256 "decap_format: %x " 257 "ipv4_proto: %x " 258 "ipv6_proto: %x " 259 "tcp_proto: %x " 260 "udp_proto: %x " 261 "ip_frag: %x " 262 "tcp_only_ack: %x " 263 "da_is_bcast_mcast: %x " 264 "ip4_protocol_ip6_next_header: %x " 265 "toeplitz_hash_2_or_4: %x " 266 "flow_id_toeplitz: %x " 267 "user_rssi: %x " 268 "pkt_type: %x " 269 "stbc: %x " 270 "sgi: %x " 271 "rate_mcs: %x " 272 "receive_bandwidth: %x " 273 "reception_type: %x " 274 "ppdu_start_timestamp: %u ", 275 msdu_start->rxpcu_mpdu_filter_in_category, 276 msdu_start->sw_frame_group_id, 277 msdu_start->phy_ppdu_id, 278 msdu_start->msdu_length, 279 msdu_start->ipsec_esp, 280 msdu_start->l3_offset, 281 msdu_start->ipsec_ah, 282 msdu_start->l4_offset, 283 msdu_start->msdu_number, 284 msdu_start->decap_format, 285 msdu_start->ipv4_proto, 286 msdu_start->ipv6_proto, 287 msdu_start->tcp_proto, 288 msdu_start->udp_proto, 289 msdu_start->ip_frag, 290 msdu_start->tcp_only_ack, 291 msdu_start->da_is_bcast_mcast, 292 msdu_start->ip4_protocol_ip6_next_header, 293 msdu_start->toeplitz_hash_2_or_4, 294 msdu_start->flow_id_toeplitz, 295 msdu_start->user_rssi, 296 msdu_start->pkt_type, 297 msdu_start->stbc, 298 msdu_start->sgi, 299 msdu_start->rate_mcs, 300 msdu_start->receive_bandwidth, 301 msdu_start->reception_type, 302 msdu_start->ppdu_start_timestamp); 303 304 hal_verbose_debug( 305 "rx_msdu_start tlv (2/2) - " 306 "sw_phy_meta_data: %x ", 307 msdu_start->sw_phy_meta_data); 308 } 309 310 /** 311 * hal_rx_dump_msdu_end_tlv_6750: dump RX msdu_end TLV in structured 312 * human readable format. 313 * @ msdu_end: pointer the msdu_end TLV in pkt. 314 * @ dbg_level: log level. 315 * 316 * Return: void 317 */ 318 static void hal_rx_dump_msdu_end_tlv_6750(void *msduend, 319 uint8_t dbg_level) 320 { 321 struct rx_msdu_end *msdu_end = (struct rx_msdu_end *)msduend; 322 323 __QDF_TRACE_RL(dbg_level, QDF_MODULE_ID_DP, 324 "rx_msdu_end tlv (1/3) - " 325 "rxpcu_mpdu_filter_in_category: %x " 326 "sw_frame_group_id: %x " 327 "phy_ppdu_id: %x " 328 "ip_hdr_chksum: %x " 329 "tcp_udp_chksum: %x " 330 "key_id_octet: %x " 331 "cce_super_rule: %x " 332 "cce_classify_not_done_truncat: %x " 333 "cce_classify_not_done_cce_dis: %x " 334 "reported_mpdu_length: %x " 335 "first_msdu: %x " 336 "last_msdu: %x " 337 "sa_idx_timeout: %x " 338 "da_idx_timeout: %x " 339 "msdu_limit_error: %x " 340 "flow_idx_timeout: %x " 341 "flow_idx_invalid: %x " 342 "wifi_parser_error: %x " 343 "amsdu_parser_error: %x", 344 msdu_end->rxpcu_mpdu_filter_in_category, 345 msdu_end->sw_frame_group_id, 346 msdu_end->phy_ppdu_id, 347 msdu_end->ip_hdr_chksum, 348 msdu_end->tcp_udp_chksum, 349 msdu_end->key_id_octet, 350 msdu_end->cce_super_rule, 351 msdu_end->cce_classify_not_done_truncate, 352 msdu_end->cce_classify_not_done_cce_dis, 353 msdu_end->reported_mpdu_length, 354 msdu_end->first_msdu, 355 msdu_end->last_msdu, 356 msdu_end->sa_idx_timeout, 357 msdu_end->da_idx_timeout, 358 msdu_end->msdu_limit_error, 359 msdu_end->flow_idx_timeout, 360 msdu_end->flow_idx_invalid, 361 msdu_end->wifi_parser_error, 362 msdu_end->amsdu_parser_error); 363 364 __QDF_TRACE_RL(dbg_level, QDF_MODULE_ID_DP, 365 "rx_msdu_end tlv (2/3)- " 366 "sa_is_valid: %x " 367 "da_is_valid: %x " 368 "da_is_mcbc: %x " 369 "l3_header_padding: %x " 370 "ipv6_options_crc: %x " 371 "tcp_seq_number: %x " 372 "tcp_ack_number: %x " 373 "tcp_flag: %x " 374 "lro_eligible: %x " 375 "window_size: %x " 376 "da_offset: %x " 377 "sa_offset: %x " 378 "da_offset_valid: %x " 379 "sa_offset_valid: %x " 380 "rule_indication_31_0: %x " 381 "rule_indication_63_32: %x " 382 "sa_idx: %x " 383 "da_idx: %x " 384 "msdu_drop: %x " 385 "reo_destination_indication: %x " 386 "flow_idx: %x " 387 "fse_metadata: %x " 388 "cce_metadata: %x " 389 "sa_sw_peer_id: %x ", 390 msdu_end->sa_is_valid, 391 msdu_end->da_is_valid, 392 msdu_end->da_is_mcbc, 393 msdu_end->l3_header_padding, 394 msdu_end->ipv6_options_crc, 395 msdu_end->tcp_seq_number, 396 msdu_end->tcp_ack_number, 397 msdu_end->tcp_flag, 398 msdu_end->lro_eligible, 399 msdu_end->window_size, 400 msdu_end->da_offset, 401 msdu_end->sa_offset, 402 msdu_end->da_offset_valid, 403 msdu_end->sa_offset_valid, 404 msdu_end->rule_indication_31_0, 405 msdu_end->rule_indication_63_32, 406 msdu_end->sa_idx, 407 msdu_end->da_idx_or_sw_peer_id, 408 msdu_end->msdu_drop, 409 msdu_end->reo_destination_indication, 410 msdu_end->flow_idx, 411 msdu_end->fse_metadata, 412 msdu_end->cce_metadata, 413 msdu_end->sa_sw_peer_id); 414 __QDF_TRACE_RL(dbg_level, QDF_MODULE_ID_DP, 415 "rx_msdu_end tlv (3/3)" 416 "aggregation_count %x " 417 "flow_aggregation_continuation %x " 418 "fisa_timeout %x " 419 "cumulative_l4_checksum %x " 420 "cumulative_ip_length %x", 421 msdu_end->aggregation_count, 422 msdu_end->flow_aggregation_continuation, 423 msdu_end->fisa_timeout, 424 msdu_end->cumulative_l4_checksum, 425 msdu_end->cumulative_ip_length); 426 } 427 428 /* 429 * Get tid from RX_MPDU_START 430 */ 431 #define HAL_RX_MPDU_INFO_TID_GET(_rx_mpdu_info) \ 432 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_info), \ 433 RX_MPDU_INFO_7_TID_OFFSET)), \ 434 RX_MPDU_INFO_7_TID_MASK, \ 435 RX_MPDU_INFO_7_TID_LSB)) 436 437 static uint32_t hal_rx_mpdu_start_tid_get_6750(uint8_t *buf) 438 { 439 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 440 struct rx_mpdu_start *mpdu_start = 441 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 442 uint32_t tid; 443 444 tid = HAL_RX_MPDU_INFO_TID_GET(&mpdu_start->rx_mpdu_info_details); 445 446 return tid; 447 } 448 449 #define HAL_RX_MSDU_START_RECEPTION_TYPE_GET(_rx_msdu_start) \ 450 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start), \ 451 RX_MSDU_START_5_RECEPTION_TYPE_OFFSET)), \ 452 RX_MSDU_START_5_RECEPTION_TYPE_MASK, \ 453 RX_MSDU_START_5_RECEPTION_TYPE_LSB)) 454 455 /* 456 * hal_rx_msdu_start_reception_type_get(): API to get the reception type 457 * Interval from rx_msdu_start 458 * 459 * @buf: pointer to the start of RX PKT TLV header 460 * Return: uint32_t(reception_type) 461 */ 462 static 463 uint32_t hal_rx_msdu_start_reception_type_get_6750(uint8_t *buf) 464 { 465 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 466 struct rx_msdu_start *msdu_start = 467 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 468 uint32_t reception_type; 469 470 reception_type = HAL_RX_MSDU_START_RECEPTION_TYPE_GET(msdu_start); 471 472 return reception_type; 473 } 474 475 /** 476 * hal_rx_msdu_end_da_idx_get_6750: API to get da_idx 477 * from rx_msdu_end TLV 478 * 479 * @ buf: pointer to the start of RX PKT TLV headers 480 * Return: da index 481 */ 482 static uint16_t hal_rx_msdu_end_da_idx_get_6750(uint8_t *buf) 483 { 484 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 485 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 486 uint16_t da_idx; 487 488 da_idx = HAL_RX_MSDU_END_DA_IDX_GET(msdu_end); 489 490 return da_idx; 491 } 492 493 /** 494 * hal_rx_get_rx_fragment_number_6750(): Function to retrieve rx fragment number 495 * 496 * @nbuf: Network buffer 497 * Returns: rx fragment number 498 */ 499 static 500 uint8_t hal_rx_get_rx_fragment_number_6750(uint8_t *buf) 501 { 502 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 503 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 504 505 /* Return first 4 bits as fragment number */ 506 return (HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info) & 507 DOT11_SEQ_FRAG_MASK); 508 } 509 510 /** 511 * hal_rx_msdu_end_da_is_mcbc_get_6750(): API to check if pkt is MCBC 512 * from rx_msdu_end TLV 513 * 514 * @ buf: pointer to the start of RX PKT TLV headers 515 * Return: da_is_mcbc 516 */ 517 static uint8_t 518 hal_rx_msdu_end_da_is_mcbc_get_6750(uint8_t *buf) 519 { 520 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 521 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 522 523 return HAL_RX_MSDU_END_DA_IS_MCBC_GET(msdu_end); 524 } 525 526 /** 527 * hal_rx_msdu_end_sa_is_valid_get_6750(): API to get_6750 the 528 * sa_is_valid bit from rx_msdu_end TLV 529 * 530 * @ buf: pointer to the start of RX PKT TLV headers 531 * Return: sa_is_valid bit 532 */ 533 static uint8_t 534 hal_rx_msdu_end_sa_is_valid_get_6750(uint8_t *buf) 535 { 536 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 537 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 538 uint8_t sa_is_valid; 539 540 sa_is_valid = HAL_RX_MSDU_END_SA_IS_VALID_GET(msdu_end); 541 542 return sa_is_valid; 543 } 544 545 /** 546 * hal_rx_msdu_end_sa_idx_get_6750(): API to get_6750 the 547 * sa_idx from rx_msdu_end TLV 548 * 549 * @ buf: pointer to the start of RX PKT TLV headers 550 * Return: sa_idx (SA AST index) 551 */ 552 static 553 uint16_t hal_rx_msdu_end_sa_idx_get_6750(uint8_t *buf) 554 { 555 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 556 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 557 uint16_t sa_idx; 558 559 sa_idx = HAL_RX_MSDU_END_SA_IDX_GET(msdu_end); 560 561 return sa_idx; 562 } 563 564 /** 565 * hal_rx_desc_is_first_msdu_6750() - Check if first msdu 566 * 567 * @hal_soc_hdl: hal_soc handle 568 * @hw_desc_addr: hardware descriptor address 569 * 570 * Return: 0 - success/ non-zero failure 571 */ 572 static uint32_t hal_rx_desc_is_first_msdu_6750(void *hw_desc_addr) 573 { 574 struct rx_pkt_tlvs *rx_tlvs = (struct rx_pkt_tlvs *)hw_desc_addr; 575 struct rx_msdu_end *msdu_end = &rx_tlvs->msdu_end_tlv.rx_msdu_end; 576 577 return HAL_RX_GET(msdu_end, RX_MSDU_END_10, FIRST_MSDU); 578 } 579 580 /** 581 * hal_rx_msdu_end_l3_hdr_padding_get_6750(): API to get_6750 the 582 * l3_header padding from rx_msdu_end TLV 583 * 584 * @ buf: pointer to the start of RX PKT TLV headers 585 * Return: number of l3 header padding bytes 586 */ 587 static uint32_t hal_rx_msdu_end_l3_hdr_padding_get_6750(uint8_t *buf) 588 { 589 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 590 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 591 uint32_t l3_header_padding; 592 593 l3_header_padding = HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(msdu_end); 594 595 return l3_header_padding; 596 } 597 598 /* 599 * @ hal_rx_encryption_info_valid_6750: Returns encryption type. 600 * 601 * @ buf: rx_tlv_hdr of the received packet 602 * @ Return: encryption type 603 */ 604 static uint32_t hal_rx_encryption_info_valid_6750(uint8_t *buf) 605 { 606 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 607 struct rx_mpdu_start *mpdu_start = 608 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 609 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 610 uint32_t encryption_info = HAL_RX_MPDU_ENCRYPTION_INFO_VALID(mpdu_info); 611 612 return encryption_info; 613 } 614 615 /* 616 * @ hal_rx_print_pn_6750: Prints the PN of rx packet. 617 * 618 * @ buf: rx_tlv_hdr of the received packet 619 * @ Return: void 620 */ 621 static void hal_rx_print_pn_6750(uint8_t *buf) 622 { 623 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 624 struct rx_mpdu_start *mpdu_start = 625 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 626 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 627 628 uint32_t pn_31_0 = HAL_RX_MPDU_PN_31_0_GET(mpdu_info); 629 uint32_t pn_63_32 = HAL_RX_MPDU_PN_63_32_GET(mpdu_info); 630 uint32_t pn_95_64 = HAL_RX_MPDU_PN_95_64_GET(mpdu_info); 631 uint32_t pn_127_96 = HAL_RX_MPDU_PN_127_96_GET(mpdu_info); 632 633 hal_debug("PN number pn_127_96 0x%x pn_95_64 0x%x pn_63_32 0x%x pn_31_0 0x%x ", 634 pn_127_96, pn_95_64, pn_63_32, pn_31_0); 635 } 636 637 /** 638 * hal_rx_msdu_end_first_msdu_get_6750: API to get first msdu status 639 * from rx_msdu_end TLV 640 * 641 * @ buf: pointer to the start of RX PKT TLV headers 642 * Return: first_msdu 643 */ 644 static uint8_t hal_rx_msdu_end_first_msdu_get_6750(uint8_t *buf) 645 { 646 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 647 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 648 uint8_t first_msdu; 649 650 first_msdu = HAL_RX_MSDU_END_FIRST_MSDU_GET(msdu_end); 651 652 return first_msdu; 653 } 654 655 /** 656 * hal_rx_msdu_end_da_is_valid_get_6750: API to check if da is valid 657 * from rx_msdu_end TLV 658 * 659 * @ buf: pointer to the start of RX PKT TLV headers 660 * Return: da_is_valid 661 */ 662 static uint8_t hal_rx_msdu_end_da_is_valid_get_6750(uint8_t *buf) 663 { 664 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 665 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 666 uint8_t da_is_valid; 667 668 da_is_valid = HAL_RX_MSDU_END_DA_IS_VALID_GET(msdu_end); 669 670 return da_is_valid; 671 } 672 673 /** 674 * hal_rx_msdu_end_last_msdu_get_6750: API to get last msdu status 675 * from rx_msdu_end TLV 676 * 677 * @ buf: pointer to the start of RX PKT TLV headers 678 * Return: last_msdu 679 */ 680 static uint8_t hal_rx_msdu_end_last_msdu_get_6750(uint8_t *buf) 681 { 682 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 683 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 684 uint8_t last_msdu; 685 686 last_msdu = HAL_RX_MSDU_END_LAST_MSDU_GET(msdu_end); 687 688 return last_msdu; 689 } 690 691 /* 692 * hal_rx_get_mpdu_mac_ad4_valid_6750(): Retrieves if mpdu 4th addr is valid 693 * 694 * @nbuf: Network buffer 695 * Returns: value of mpdu 4th address valid field 696 */ 697 static bool hal_rx_get_mpdu_mac_ad4_valid_6750(uint8_t *buf) 698 { 699 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 700 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 701 bool ad4_valid = 0; 702 703 ad4_valid = HAL_RX_MPDU_GET_MAC_AD4_VALID(rx_mpdu_info); 704 705 return ad4_valid; 706 } 707 708 /** 709 * hal_rx_mpdu_start_sw_peer_id_get_6750: Retrieve sw peer_id 710 * @buf: network buffer 711 * 712 * Return: sw peer_id 713 */ 714 static uint32_t hal_rx_mpdu_start_sw_peer_id_get_6750(uint8_t *buf) 715 { 716 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 717 struct rx_mpdu_start *mpdu_start = 718 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 719 720 return HAL_RX_MPDU_INFO_SW_PEER_ID_GET( 721 &mpdu_start->rx_mpdu_info_details); 722 } 723 724 /** 725 * hal_rx_mpdu_get_to_ds_6750(): API to get the tods info 726 * from rx_mpdu_start 727 * 728 * @buf: pointer to the start of RX PKT TLV header 729 * Return: uint32_t(to_ds) 730 */ 731 static uint32_t hal_rx_mpdu_get_to_ds_6750(uint8_t *buf) 732 { 733 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 734 struct rx_mpdu_start *mpdu_start = 735 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 736 737 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 738 739 return HAL_RX_MPDU_GET_TODS(mpdu_info); 740 } 741 742 /* 743 * hal_rx_mpdu_get_fr_ds_6750(): API to get the from ds info 744 * from rx_mpdu_start 745 * 746 * @buf: pointer to the start of RX PKT TLV header 747 * Return: uint32_t(fr_ds) 748 */ 749 static uint32_t hal_rx_mpdu_get_fr_ds_6750(uint8_t *buf) 750 { 751 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 752 struct rx_mpdu_start *mpdu_start = 753 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 754 755 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 756 757 return HAL_RX_MPDU_GET_FROMDS(mpdu_info); 758 } 759 760 /* 761 * hal_rx_get_mpdu_frame_control_valid_6750(): Retrieves mpdu 762 * frame control valid 763 * 764 * @nbuf: Network buffer 765 * Returns: value of frame control valid field 766 */ 767 static uint8_t hal_rx_get_mpdu_frame_control_valid_6750(uint8_t *buf) 768 { 769 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 770 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 771 772 return HAL_RX_MPDU_GET_FRAME_CONTROL_VALID(rx_mpdu_info); 773 } 774 775 /* 776 * hal_rx_mpdu_get_addr1_6750(): API to check get address1 of the mpdu 777 * 778 * @buf: pointer to the start of RX PKT TLV headera 779 * @mac_addr: pointer to mac address 780 * Return: success/failure 781 */ 782 static QDF_STATUS hal_rx_mpdu_get_addr1_6750(uint8_t *buf, uint8_t *mac_addr) 783 { 784 struct __attribute__((__packed__)) hal_addr1 { 785 uint32_t ad1_31_0; 786 uint16_t ad1_47_32; 787 }; 788 789 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 790 struct rx_mpdu_start *mpdu_start = 791 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 792 793 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 794 struct hal_addr1 *addr = (struct hal_addr1 *)mac_addr; 795 uint32_t mac_addr_ad1_valid; 796 797 mac_addr_ad1_valid = HAL_RX_MPDU_MAC_ADDR_AD1_VALID_GET(mpdu_info); 798 799 if (mac_addr_ad1_valid) { 800 addr->ad1_31_0 = HAL_RX_MPDU_AD1_31_0_GET(mpdu_info); 801 addr->ad1_47_32 = HAL_RX_MPDU_AD1_47_32_GET(mpdu_info); 802 return QDF_STATUS_SUCCESS; 803 } 804 805 return QDF_STATUS_E_FAILURE; 806 } 807 808 /* 809 * hal_rx_mpdu_get_addr2_6750(): API to check get address2 of the mpdu 810 * in the packet 811 * 812 * @buf: pointer to the start of RX PKT TLV header 813 * @mac_addr: pointer to mac address 814 * Return: success/failure 815 */ 816 static QDF_STATUS hal_rx_mpdu_get_addr2_6750(uint8_t *buf, 817 uint8_t *mac_addr) 818 { 819 struct __attribute__((__packed__)) hal_addr2 { 820 uint16_t ad2_15_0; 821 uint32_t ad2_47_16; 822 }; 823 824 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 825 struct rx_mpdu_start *mpdu_start = 826 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 827 828 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 829 struct hal_addr2 *addr = (struct hal_addr2 *)mac_addr; 830 uint32_t mac_addr_ad2_valid; 831 832 mac_addr_ad2_valid = HAL_RX_MPDU_MAC_ADDR_AD2_VALID_GET(mpdu_info); 833 834 if (mac_addr_ad2_valid) { 835 addr->ad2_15_0 = HAL_RX_MPDU_AD2_15_0_GET(mpdu_info); 836 addr->ad2_47_16 = HAL_RX_MPDU_AD2_47_16_GET(mpdu_info); 837 return QDF_STATUS_SUCCESS; 838 } 839 840 return QDF_STATUS_E_FAILURE; 841 } 842 843 /* 844 * hal_rx_mpdu_get_addr3_6750(): API to get address3 of the mpdu 845 * in the packet 846 * 847 * @buf: pointer to the start of RX PKT TLV header 848 * @mac_addr: pointer to mac address 849 * Return: success/failure 850 */ 851 static QDF_STATUS hal_rx_mpdu_get_addr3_6750(uint8_t *buf, uint8_t *mac_addr) 852 { 853 struct __attribute__((__packed__)) hal_addr3 { 854 uint32_t ad3_31_0; 855 uint16_t ad3_47_32; 856 }; 857 858 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 859 struct rx_mpdu_start *mpdu_start = 860 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 861 862 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 863 struct hal_addr3 *addr = (struct hal_addr3 *)mac_addr; 864 uint32_t mac_addr_ad3_valid; 865 866 mac_addr_ad3_valid = HAL_RX_MPDU_MAC_ADDR_AD3_VALID_GET(mpdu_info); 867 868 if (mac_addr_ad3_valid) { 869 addr->ad3_31_0 = HAL_RX_MPDU_AD3_31_0_GET(mpdu_info); 870 addr->ad3_47_32 = HAL_RX_MPDU_AD3_47_32_GET(mpdu_info); 871 return QDF_STATUS_SUCCESS; 872 } 873 874 return QDF_STATUS_E_FAILURE; 875 } 876 877 /* 878 * hal_rx_mpdu_get_addr4_6750(): API to get address4 of the mpdu 879 * in the packet 880 * 881 * @buf: pointer to the start of RX PKT TLV header 882 * @mac_addr: pointer to mac address 883 * Return: success/failure 884 */ 885 static QDF_STATUS hal_rx_mpdu_get_addr4_6750(uint8_t *buf, uint8_t *mac_addr) 886 { 887 struct __attribute__((__packed__)) hal_addr4 { 888 uint32_t ad4_31_0; 889 uint16_t ad4_47_32; 890 }; 891 892 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 893 struct rx_mpdu_start *mpdu_start = 894 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 895 896 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 897 struct hal_addr4 *addr = (struct hal_addr4 *)mac_addr; 898 uint32_t mac_addr_ad4_valid; 899 900 mac_addr_ad4_valid = HAL_RX_MPDU_MAC_ADDR_AD4_VALID_GET(mpdu_info); 901 902 if (mac_addr_ad4_valid) { 903 addr->ad4_31_0 = HAL_RX_MPDU_AD4_31_0_GET(mpdu_info); 904 addr->ad4_47_32 = HAL_RX_MPDU_AD4_47_32_GET(mpdu_info); 905 return QDF_STATUS_SUCCESS; 906 } 907 908 return QDF_STATUS_E_FAILURE; 909 } 910 911 /* 912 * hal_rx_get_mpdu_sequence_control_valid_6750(): Get mpdu 913 * sequence control valid 914 * 915 * @nbuf: Network buffer 916 * Returns: value of sequence control valid field 917 */ 918 static uint8_t hal_rx_get_mpdu_sequence_control_valid_6750(uint8_t *buf) 919 { 920 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 921 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 922 923 return HAL_RX_MPDU_GET_SEQUENCE_CONTROL_VALID(rx_mpdu_info); 924 } 925 926 /** 927 * hal_rx_is_unicast_6750: check packet is unicast frame or not. 928 * 929 * @ buf: pointer to rx pkt TLV. 930 * 931 * Return: true on unicast. 932 */ 933 static bool hal_rx_is_unicast_6750(uint8_t *buf) 934 { 935 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 936 struct rx_mpdu_start *mpdu_start = 937 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 938 uint32_t grp_id; 939 uint8_t *rx_mpdu_info = (uint8_t *)&mpdu_start->rx_mpdu_info_details; 940 941 grp_id = (_HAL_MS((*_OFFSET_TO_WORD_PTR((rx_mpdu_info), 942 RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_OFFSET)), 943 RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_MASK, 944 RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_LSB)); 945 946 return (HAL_MPDU_SW_FRAME_GROUP_UNICAST_DATA == grp_id) ? true : false; 947 } 948 949 /** 950 * hal_rx_tid_get_6750: get tid based on qos control valid. 951 * @hal_soc_hdl: hal_soc handle 952 * @ buf: pointer to rx pkt TLV. 953 * 954 * Return: tid 955 */ 956 static uint32_t hal_rx_tid_get_6750(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 957 { 958 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 959 struct rx_mpdu_start *mpdu_start = 960 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 961 uint8_t *rx_mpdu_info = (uint8_t *)&mpdu_start->rx_mpdu_info_details; 962 uint8_t qos_control_valid = 963 (_HAL_MS((*_OFFSET_TO_WORD_PTR((rx_mpdu_info), 964 RX_MPDU_INFO_11_MPDU_QOS_CONTROL_VALID_OFFSET)), 965 RX_MPDU_INFO_11_MPDU_QOS_CONTROL_VALID_MASK, 966 RX_MPDU_INFO_11_MPDU_QOS_CONTROL_VALID_LSB)); 967 968 if (qos_control_valid) 969 return hal_rx_mpdu_start_tid_get_6750(buf); 970 971 return HAL_RX_NON_QOS_TID; 972 } 973 974 /** 975 * hal_rx_hw_desc_get_ppduid_get_6750(): retrieve ppdu id 976 * @rx_tlv_hdr: rx tlv header 977 * @rxdma_dst_ring_desc: rxdma HW descriptor 978 * 979 * Return: ppdu id 980 */ 981 static uint32_t hal_rx_hw_desc_get_ppduid_get_6750(void *rx_tlv_hdr, 982 void *rxdma_dst_ring_desc) 983 { 984 struct rx_mpdu_info *rx_mpdu_info; 985 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)rx_tlv_hdr; 986 987 rx_mpdu_info = 988 &rx_desc->mpdu_start_tlv.rx_mpdu_start.rx_mpdu_info_details; 989 990 return HAL_RX_GET(rx_mpdu_info, RX_MPDU_INFO_9, PHY_PPDU_ID); 991 } 992 993 /** 994 * hal_reo_status_get_header_6750 - Process reo desc info 995 * @ring_desc: REO status ring descriptor 996 * @b - tlv type info 997 * @h1 - Pointer to hal_reo_status_header where info to be stored 998 * 999 * Return - none. 1000 * 1001 */ 1002 static void hal_reo_status_get_header_6750(hal_ring_desc_t ring_desc, int b, 1003 void *h1) 1004 { 1005 uint32_t *d = (uint32_t *)ring_desc; 1006 uint32_t val1 = 0; 1007 struct hal_reo_status_header *h = 1008 (struct hal_reo_status_header *)h1; 1009 1010 /* Offsets of descriptor fields defined in HW headers start 1011 * from the field after TLV header 1012 */ 1013 d += HAL_GET_NUM_DWORDS(sizeof(struct tlv_32_hdr)); 1014 1015 switch (b) { 1016 case HAL_REO_QUEUE_STATS_STATUS_TLV: 1017 val1 = d[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_0, 1018 STATUS_HEADER_REO_STATUS_NUMBER)]; 1019 break; 1020 case HAL_REO_FLUSH_QUEUE_STATUS_TLV: 1021 val1 = d[HAL_OFFSET_DW(REO_FLUSH_QUEUE_STATUS_0, 1022 STATUS_HEADER_REO_STATUS_NUMBER)]; 1023 break; 1024 case HAL_REO_FLUSH_CACHE_STATUS_TLV: 1025 val1 = d[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_0, 1026 STATUS_HEADER_REO_STATUS_NUMBER)]; 1027 break; 1028 case HAL_REO_UNBLK_CACHE_STATUS_TLV: 1029 val1 = d[HAL_OFFSET_DW(REO_UNBLOCK_CACHE_STATUS_0, 1030 STATUS_HEADER_REO_STATUS_NUMBER)]; 1031 break; 1032 case HAL_REO_TIMOUT_LIST_STATUS_TLV: 1033 val1 = d[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_0, 1034 STATUS_HEADER_REO_STATUS_NUMBER)]; 1035 break; 1036 case HAL_REO_DESC_THRES_STATUS_TLV: 1037 val1 = 1038 d[HAL_OFFSET_DW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0, 1039 STATUS_HEADER_REO_STATUS_NUMBER)]; 1040 break; 1041 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: 1042 val1 = d[HAL_OFFSET_DW(REO_UPDATE_RX_REO_QUEUE_STATUS_0, 1043 STATUS_HEADER_REO_STATUS_NUMBER)]; 1044 break; 1045 default: 1046 qdf_nofl_err("ERROR: Unknown tlv\n"); 1047 break; 1048 } 1049 h->cmd_num = 1050 HAL_GET_FIELD( 1051 UNIFORM_REO_STATUS_HEADER_0, REO_STATUS_NUMBER, 1052 val1); 1053 h->exec_time = 1054 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_0, 1055 CMD_EXECUTION_TIME, val1); 1056 h->status = 1057 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_0, 1058 REO_CMD_EXECUTION_STATUS, val1); 1059 switch (b) { 1060 case HAL_REO_QUEUE_STATS_STATUS_TLV: 1061 val1 = d[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_1, 1062 STATUS_HEADER_TIMESTAMP)]; 1063 break; 1064 case HAL_REO_FLUSH_QUEUE_STATUS_TLV: 1065 val1 = d[HAL_OFFSET_DW(REO_FLUSH_QUEUE_STATUS_1, 1066 STATUS_HEADER_TIMESTAMP)]; 1067 break; 1068 case HAL_REO_FLUSH_CACHE_STATUS_TLV: 1069 val1 = d[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_1, 1070 STATUS_HEADER_TIMESTAMP)]; 1071 break; 1072 case HAL_REO_UNBLK_CACHE_STATUS_TLV: 1073 val1 = d[HAL_OFFSET_DW(REO_UNBLOCK_CACHE_STATUS_1, 1074 STATUS_HEADER_TIMESTAMP)]; 1075 break; 1076 case HAL_REO_TIMOUT_LIST_STATUS_TLV: 1077 val1 = d[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_1, 1078 STATUS_HEADER_TIMESTAMP)]; 1079 break; 1080 case HAL_REO_DESC_THRES_STATUS_TLV: 1081 val1 = 1082 d[HAL_OFFSET_DW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_1, 1083 STATUS_HEADER_TIMESTAMP)]; 1084 break; 1085 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: 1086 val1 = d[HAL_OFFSET_DW(REO_UPDATE_RX_REO_QUEUE_STATUS_1, 1087 STATUS_HEADER_TIMESTAMP)]; 1088 break; 1089 default: 1090 qdf_nofl_err("ERROR: Unknown tlv\n"); 1091 break; 1092 } 1093 h->tstamp = 1094 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_1, TIMESTAMP, val1); 1095 } 1096 1097 /** 1098 * hal_tx_desc_set_mesh_en_6750 - Set mesh_enable flag in Tx descriptor 1099 * @desc: Handle to Tx Descriptor 1100 * @en: For raw WiFi frames, this indicates transmission to a mesh STA, 1101 * enabling the interpretation of the 'Mesh Control Present' bit 1102 * (bit 8) of QoS Control (otherwise this bit is ignored), 1103 * For native WiFi frames, this indicates that a 'Mesh Control' field 1104 * is present between the header and the LLC. 1105 * 1106 * Return: void 1107 */ 1108 static inline 1109 void hal_tx_desc_set_mesh_en_6750(void *desc, uint8_t en) 1110 { 1111 HAL_SET_FLD(desc, TCL_DATA_CMD_5, MESH_ENABLE) |= 1112 HAL_TX_SM(TCL_DATA_CMD_5, MESH_ENABLE, en); 1113 } 1114 1115 static 1116 void *hal_rx_msdu0_buffer_addr_lsb_6750(void *link_desc_va) 1117 { 1118 return (void *)HAL_RX_MSDU0_BUFFER_ADDR_LSB(link_desc_va); 1119 } 1120 1121 static 1122 void *hal_rx_msdu_desc_info_ptr_get_6750(void *msdu0) 1123 { 1124 return (void *)HAL_RX_MSDU_DESC_INFO_PTR_GET(msdu0); 1125 } 1126 1127 static 1128 void *hal_ent_mpdu_desc_info_6750(void *ent_ring_desc) 1129 { 1130 return (void *)HAL_ENT_MPDU_DESC_INFO(ent_ring_desc); 1131 } 1132 1133 static 1134 void *hal_dst_mpdu_desc_info_6750(void *dst_ring_desc) 1135 { 1136 return (void *)HAL_DST_MPDU_DESC_INFO(dst_ring_desc); 1137 } 1138 1139 static 1140 uint8_t hal_rx_get_fc_valid_6750(uint8_t *buf) 1141 { 1142 return HAL_RX_GET_FC_VALID(buf); 1143 } 1144 1145 static uint8_t hal_rx_get_to_ds_flag_6750(uint8_t *buf) 1146 { 1147 return HAL_RX_GET_TO_DS_FLAG(buf); 1148 } 1149 1150 static uint8_t hal_rx_get_mac_addr2_valid_6750(uint8_t *buf) 1151 { 1152 return HAL_RX_GET_MAC_ADDR2_VALID(buf); 1153 } 1154 1155 static uint8_t hal_rx_get_filter_category_6750(uint8_t *buf) 1156 { 1157 return HAL_RX_GET_FILTER_CATEGORY(buf); 1158 } 1159 1160 static uint32_t 1161 hal_rx_get_ppdu_id_6750(uint8_t *buf) 1162 { 1163 return HAL_RX_GET_PPDU_ID(buf); 1164 } 1165 1166 /** 1167 * hal_reo_config_6750(): Set reo config parameters 1168 * @soc: hal soc handle 1169 * @reg_val: value to be set 1170 * @reo_params: reo parameters 1171 * 1172 * Return: void 1173 */ 1174 static 1175 void hal_reo_config_6750(struct hal_soc *soc, 1176 uint32_t reg_val, 1177 struct hal_reo_params *reo_params) 1178 { 1179 HAL_REO_R0_CONFIG(soc, reg_val, reo_params); 1180 } 1181 1182 /** 1183 * hal_rx_msdu_desc_info_get_ptr_6750() - Get msdu desc info ptr 1184 * @msdu_details_ptr - Pointer to msdu_details_ptr 1185 * 1186 * Return - Pointer to rx_msdu_desc_info structure. 1187 * 1188 */ 1189 static void *hal_rx_msdu_desc_info_get_ptr_6750(void *msdu_details_ptr) 1190 { 1191 return HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr); 1192 } 1193 1194 /** 1195 * hal_rx_link_desc_msdu0_ptr_6750 - Get pointer to rx_msdu details 1196 * @link_desc - Pointer to link desc 1197 * 1198 * Return - Pointer to rx_msdu_details structure 1199 * 1200 */ 1201 static void *hal_rx_link_desc_msdu0_ptr_6750(void *link_desc) 1202 { 1203 return HAL_RX_LINK_DESC_MSDU0_PTR(link_desc); 1204 } 1205 1206 /** 1207 * hal_rx_msdu_flow_idx_get_6750: API to get flow index 1208 * from rx_msdu_end TLV 1209 * @buf: pointer to the start of RX PKT TLV headers 1210 * 1211 * Return: flow index value from MSDU END TLV 1212 */ 1213 static inline uint32_t hal_rx_msdu_flow_idx_get_6750(uint8_t *buf) 1214 { 1215 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1216 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1217 1218 return HAL_RX_MSDU_END_FLOW_IDX_GET(msdu_end); 1219 } 1220 1221 /** 1222 * hal_rx_msdu_flow_idx_invalid_6750: API to get flow index invalid 1223 * from rx_msdu_end TLV 1224 * @buf: pointer to the start of RX PKT TLV headers 1225 * 1226 * Return: flow index invalid value from MSDU END TLV 1227 */ 1228 static bool hal_rx_msdu_flow_idx_invalid_6750(uint8_t *buf) 1229 { 1230 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1231 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1232 1233 return HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(msdu_end); 1234 } 1235 1236 /** 1237 * hal_rx_msdu_flow_idx_timeout_6750: API to get flow index timeout 1238 * from rx_msdu_end TLV 1239 * @buf: pointer to the start of RX PKT TLV headers 1240 * 1241 * Return: flow index timeout value from MSDU END TLV 1242 */ 1243 static bool hal_rx_msdu_flow_idx_timeout_6750(uint8_t *buf) 1244 { 1245 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1246 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1247 1248 return HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(msdu_end); 1249 } 1250 1251 /** 1252 * hal_rx_msdu_fse_metadata_get_6750: API to get FSE metadata 1253 * from rx_msdu_end TLV 1254 * @buf: pointer to the start of RX PKT TLV headers 1255 * 1256 * Return: fse metadata value from MSDU END TLV 1257 */ 1258 static uint32_t hal_rx_msdu_fse_metadata_get_6750(uint8_t *buf) 1259 { 1260 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1261 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1262 1263 return HAL_RX_MSDU_END_FSE_METADATA_GET(msdu_end); 1264 } 1265 1266 /** 1267 * hal_rx_msdu_cce_metadata_get_6750: API to get CCE metadata 1268 * from rx_msdu_end TLV 1269 * @buf: pointer to the start of RX PKT TLV headers 1270 * 1271 * Return: cce_metadata 1272 */ 1273 static uint16_t 1274 hal_rx_msdu_cce_metadata_get_6750(uint8_t *buf) 1275 { 1276 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1277 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1278 1279 return HAL_RX_MSDU_END_CCE_METADATA_GET(msdu_end); 1280 } 1281 1282 /** 1283 * hal_rx_msdu_get_flow_params_6750: API to get flow index, flow index invalid 1284 * and flow index timeout from rx_msdu_end TLV 1285 * @buf: pointer to the start of RX PKT TLV headers 1286 * @flow_invalid: pointer to return value of flow_idx_valid 1287 * @flow_timeout: pointer to return value of flow_idx_timeout 1288 * @flow_index: pointer to return value of flow_idx 1289 * 1290 * Return: none 1291 */ 1292 static inline void 1293 hal_rx_msdu_get_flow_params_6750(uint8_t *buf, 1294 bool *flow_invalid, 1295 bool *flow_timeout, 1296 uint32_t *flow_index) 1297 { 1298 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1299 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1300 1301 *flow_invalid = HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(msdu_end); 1302 *flow_timeout = HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(msdu_end); 1303 *flow_index = HAL_RX_MSDU_END_FLOW_IDX_GET(msdu_end); 1304 } 1305 1306 /** 1307 * hal_rx_tlv_get_tcp_chksum_6750() - API to get tcp checksum 1308 * @buf: rx_tlv_hdr 1309 * 1310 * Return: tcp checksum 1311 */ 1312 static uint16_t 1313 hal_rx_tlv_get_tcp_chksum_6750(uint8_t *buf) 1314 { 1315 return HAL_RX_TLV_GET_TCP_CHKSUM(buf); 1316 } 1317 1318 /** 1319 * hal_rx_get_rx_sequence_6750(): Function to retrieve rx sequence number 1320 * 1321 * @nbuf: Network buffer 1322 * Returns: rx sequence number 1323 */ 1324 static 1325 uint16_t hal_rx_get_rx_sequence_6750(uint8_t *buf) 1326 { 1327 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 1328 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 1329 1330 return HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info); 1331 } 1332 1333 #define UMAC_WINDOW_REMAP_RANGE 0x14 1334 #define CE_WINDOW_REMAP_RANGE 0x37 1335 #define CMEM_WINDOW_REMAP_RANGE 0x2 1336 1337 /** 1338 * hal_get_window_address_6750(): Function to get hp/tp address 1339 * @hal_soc: Pointer to hal_soc 1340 * @addr: address offset of register 1341 * 1342 * Return: modified address offset of register 1343 */ 1344 static inline qdf_iomem_t hal_get_window_address_6750(struct hal_soc *hal_soc, 1345 qdf_iomem_t addr) 1346 { 1347 uint32_t offset; 1348 uint32_t window; 1349 uint8_t scale; 1350 1351 offset = addr - hal_soc->dev_base_addr; 1352 window = (offset >> WINDOW_SHIFT) & WINDOW_VALUE_MASK; 1353 1354 /* UMAC: 2nd window, CE: 3rd window, CMEM: 4th window */ 1355 switch (window) { 1356 case UMAC_WINDOW_REMAP_RANGE: 1357 scale = 1; 1358 break; 1359 case CE_WINDOW_REMAP_RANGE: 1360 scale = 2; 1361 break; 1362 case CMEM_WINDOW_REMAP_RANGE: 1363 scale = 3; 1364 break; 1365 default: 1366 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR, 1367 "%s: ERROR: Accessing Wrong register\n", __func__); 1368 qdf_assert_always(0); 1369 return 0; 1370 } 1371 1372 return hal_soc->dev_base_addr + (scale * WINDOW_START) + 1373 (offset & WINDOW_RANGE_MASK); 1374 } 1375 1376 /** 1377 * hal_rx_get_fisa_cumulative_l4_checksum_6750() - Retrieve cumulative 1378 * checksum 1379 * @buf: buffer pointer 1380 * 1381 * Return: cumulative checksum 1382 */ 1383 static inline 1384 uint16_t hal_rx_get_fisa_cumulative_l4_checksum_6750(uint8_t *buf) 1385 { 1386 return HAL_RX_TLV_GET_FISA_CUMULATIVE_L4_CHECKSUM(buf); 1387 } 1388 1389 /** 1390 * hal_rx_get_fisa_cumulative_ip_length_6750() - Retrieve cumulative 1391 * ip length 1392 * @buf: buffer pointer 1393 * 1394 * Return: cumulative length 1395 */ 1396 static inline 1397 uint16_t hal_rx_get_fisa_cumulative_ip_length_6750(uint8_t *buf) 1398 { 1399 return HAL_RX_TLV_GET_FISA_CUMULATIVE_IP_LENGTH(buf); 1400 } 1401 1402 /** 1403 * hal_rx_get_udp_proto_6750() - Retrieve udp proto value 1404 * @buf: buffer 1405 * 1406 * Return: udp proto bit 1407 */ 1408 static inline 1409 bool hal_rx_get_udp_proto_6750(uint8_t *buf) 1410 { 1411 return HAL_RX_TLV_GET_UDP_PROTO(buf); 1412 } 1413 1414 /** 1415 * hal_rx_get_flow_agg_continuation_6750() - retrieve flow agg 1416 * continuation 1417 * @buf: buffer 1418 * 1419 * Return: flow agg 1420 */ 1421 static inline 1422 bool hal_rx_get_flow_agg_continuation_6750(uint8_t *buf) 1423 { 1424 return HAL_RX_TLV_GET_FLOW_AGGR_CONT(buf); 1425 } 1426 1427 /** 1428 * hal_rx_get_flow_agg_count_6750()- Retrieve flow agg count 1429 * @buf: buffer 1430 * 1431 * Return: flow agg count 1432 */ 1433 static inline 1434 uint8_t hal_rx_get_flow_agg_count_6750(uint8_t *buf) 1435 { 1436 return HAL_RX_TLV_GET_FLOW_AGGR_COUNT(buf); 1437 } 1438 1439 /** 1440 * hal_rx_get_fisa_timeout_6750() - Retrieve fisa timeout 1441 * @buf: buffer 1442 * 1443 * Return: fisa timeout 1444 */ 1445 static inline 1446 bool hal_rx_get_fisa_timeout_6750(uint8_t *buf) 1447 { 1448 return HAL_RX_TLV_GET_FISA_TIMEOUT(buf); 1449 } 1450 1451 /** 1452 * hal_rx_mpdu_start_tlv_tag_valid_6750 () - API to check if RX_MPDU_START 1453 * tlv tag is valid 1454 * 1455 *@rx_tlv_hdr: start address of rx_pkt_tlvs 1456 * 1457 * Return: true if RX_MPDU_START is valied, else false. 1458 */ 1459 static uint8_t hal_rx_mpdu_start_tlv_tag_valid_6750(void *rx_tlv_hdr) 1460 { 1461 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)rx_tlv_hdr; 1462 uint32_t tlv_tag; 1463 1464 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(&rx_desc->mpdu_start_tlv); 1465 1466 return tlv_tag == WIFIRX_MPDU_START_E ? true : false; 1467 } 1468 1469 /** 1470 * hal_reo_set_err_dst_remap_6750(): Function to set REO error destination 1471 * ring remap register 1472 * @hal_soc: Pointer to hal_soc 1473 * 1474 * Return: none. 1475 */ 1476 static void 1477 hal_reo_set_err_dst_remap_6750(void *hal_soc) 1478 { 1479 /* 1480 * Set REO error 2k jump (error code 5) / OOR (error code 7) 1481 * frame routed to REO2TCL ring. 1482 */ 1483 uint32_t dst_remap_ix0 = 1484 HAL_REO_ERR_REMAP_IX0(REO_REMAP_RELEASE, 0) | 1485 HAL_REO_ERR_REMAP_IX0(REO_REMAP_RELEASE, 1) | 1486 HAL_REO_ERR_REMAP_IX0(REO_REMAP_RELEASE, 2) | 1487 HAL_REO_ERR_REMAP_IX0(REO_REMAP_RELEASE, 3) | 1488 HAL_REO_ERR_REMAP_IX0(REO_REMAP_RELEASE, 4) | 1489 HAL_REO_ERR_REMAP_IX0(REO_REMAP_TCL, 5) | 1490 HAL_REO_ERR_REMAP_IX0(REO_REMAP_TCL, 6) | 1491 HAL_REO_ERR_REMAP_IX0(REO_REMAP_TCL, 7); 1492 1493 uint32_t dst_remap_ix1 = 1494 HAL_REO_ERR_REMAP_IX1(REO_REMAP_RELEASE, 14) | 1495 HAL_REO_ERR_REMAP_IX1(REO_REMAP_RELEASE, 13) | 1496 HAL_REO_ERR_REMAP_IX1(REO_REMAP_RELEASE, 12) | 1497 HAL_REO_ERR_REMAP_IX1(REO_REMAP_RELEASE, 11) | 1498 HAL_REO_ERR_REMAP_IX1(REO_REMAP_RELEASE, 10) | 1499 HAL_REO_ERR_REMAP_IX1(REO_REMAP_RELEASE, 9) | 1500 HAL_REO_ERR_REMAP_IX1(REO_REMAP_TCL, 8); 1501 1502 HAL_REG_WRITE(hal_soc, 1503 HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ADDR( 1504 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1505 dst_remap_ix0); 1506 1507 hal_info("HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0 0x%x", 1508 HAL_REG_READ( 1509 hal_soc, 1510 HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ADDR( 1511 SEQ_WCSS_UMAC_REO_REG_OFFSET))); 1512 1513 HAL_REG_WRITE(hal_soc, 1514 HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ADDR( 1515 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1516 dst_remap_ix1); 1517 1518 hal_info("HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1 0x%x", 1519 HAL_REG_READ( 1520 hal_soc, 1521 HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ADDR( 1522 SEQ_WCSS_UMAC_REO_REG_OFFSET))); 1523 } 1524 1525 /* 1526 * hal_rx_flow_setup_fse_6750() - Setup a flow search entry in HW FST 1527 * @fst: Pointer to the Rx Flow Search Table 1528 * @table_offset: offset into the table where the flow is to be setup 1529 * @flow: Flow Parameters 1530 * 1531 * Flow table entry fields are updated in host byte order, little endian order. 1532 * 1533 * Return: Success/Failure 1534 */ 1535 static void * 1536 hal_rx_flow_setup_fse_6750(uint8_t *rx_fst, uint32_t table_offset, 1537 uint8_t *rx_flow) 1538 { 1539 struct hal_rx_fst *fst = (struct hal_rx_fst *)rx_fst; 1540 struct hal_rx_flow *flow = (struct hal_rx_flow *)rx_flow; 1541 uint8_t *fse; 1542 bool fse_valid; 1543 1544 if (table_offset >= fst->max_entries) { 1545 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR, 1546 "HAL FSE table offset %u exceeds max entries %u", 1547 table_offset, fst->max_entries); 1548 return NULL; 1549 } 1550 1551 fse = (uint8_t *)fst->base_vaddr + 1552 (table_offset * HAL_RX_FST_ENTRY_SIZE); 1553 1554 fse_valid = HAL_GET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, VALID); 1555 1556 if (fse_valid) { 1557 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_DEBUG, 1558 "HAL FSE %pK already valid", fse); 1559 return NULL; 1560 } 1561 1562 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_0, SRC_IP_127_96) = 1563 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_0, SRC_IP_127_96, 1564 (flow->tuple_info.src_ip_127_96)); 1565 1566 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_1, SRC_IP_95_64) = 1567 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_1, SRC_IP_95_64, 1568 (flow->tuple_info.src_ip_95_64)); 1569 1570 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_2, SRC_IP_63_32) = 1571 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_2, SRC_IP_63_32, 1572 (flow->tuple_info.src_ip_63_32)); 1573 1574 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_3, SRC_IP_31_0) = 1575 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_3, SRC_IP_31_0, 1576 (flow->tuple_info.src_ip_31_0)); 1577 1578 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_4, DEST_IP_127_96) = 1579 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_4, DEST_IP_127_96, 1580 (flow->tuple_info.dest_ip_127_96)); 1581 1582 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_5, DEST_IP_95_64) = 1583 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_5, DEST_IP_95_64, 1584 (flow->tuple_info.dest_ip_95_64)); 1585 1586 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_6, DEST_IP_63_32) = 1587 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_6, DEST_IP_63_32, 1588 (flow->tuple_info.dest_ip_63_32)); 1589 1590 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_7, DEST_IP_31_0) = 1591 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_7, DEST_IP_31_0, 1592 (flow->tuple_info.dest_ip_31_0)); 1593 1594 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, DEST_PORT); 1595 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, DEST_PORT) |= 1596 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_8, DEST_PORT, 1597 (flow->tuple_info.dest_port)); 1598 1599 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, SRC_PORT); 1600 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, SRC_PORT) |= 1601 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_8, SRC_PORT, 1602 (flow->tuple_info.src_port)); 1603 1604 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, L4_PROTOCOL); 1605 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, L4_PROTOCOL) |= 1606 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, L4_PROTOCOL, 1607 flow->tuple_info.l4_protocol); 1608 1609 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_HANDLER); 1610 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_HANDLER) |= 1611 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_HANDLER, 1612 flow->reo_destination_handler); 1613 1614 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, VALID); 1615 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, VALID) |= 1616 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, VALID, 1); 1617 1618 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_10, METADATA); 1619 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_10, METADATA) = 1620 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_10, METADATA, 1621 (flow->fse_metadata)); 1622 1623 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_INDICATION); 1624 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_INDICATION) |= 1625 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, 1626 REO_DESTINATION_INDICATION, 1627 flow->reo_destination_indication); 1628 1629 /* Reset all the other fields in FSE */ 1630 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, RESERVED_9); 1631 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, MSDU_DROP); 1632 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_11, MSDU_COUNT); 1633 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_12, MSDU_BYTE_COUNT); 1634 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_13, TIMESTAMP); 1635 1636 return fse; 1637 } 1638 1639 /* 1640 * hal_rx_flow_setup_cmem_fse_6750() - Setup a flow search entry in HW CMEM FST 1641 * @hal_soc: hal_soc reference 1642 * @cmem_ba: CMEM base address 1643 * @table_offset: offset into the table where the flow is to be setup 1644 * @flow: Flow Parameters 1645 * 1646 * Return: Success/Failure 1647 */ 1648 static uint32_t 1649 hal_rx_flow_setup_cmem_fse_6750(struct hal_soc *hal_soc, uint32_t cmem_ba, 1650 uint32_t table_offset, uint8_t *rx_flow) 1651 { 1652 struct hal_rx_flow *flow = (struct hal_rx_flow *)rx_flow; 1653 uint32_t fse_offset; 1654 uint32_t value; 1655 1656 fse_offset = cmem_ba + (table_offset * HAL_RX_FST_ENTRY_SIZE); 1657 1658 /* Reset the Valid bit */ 1659 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY_9, 1660 VALID), 0); 1661 1662 value = HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_0, SRC_IP_127_96, 1663 (flow->tuple_info.src_ip_127_96)); 1664 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY_0, 1665 SRC_IP_127_96), value); 1666 1667 value = HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_1, SRC_IP_95_64, 1668 (flow->tuple_info.src_ip_95_64)); 1669 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY_1, 1670 SRC_IP_95_64), value); 1671 1672 value = HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_2, SRC_IP_63_32, 1673 (flow->tuple_info.src_ip_63_32)); 1674 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY_2, 1675 SRC_IP_63_32), value); 1676 1677 value = HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_3, SRC_IP_31_0, 1678 (flow->tuple_info.src_ip_31_0)); 1679 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY_3, 1680 SRC_IP_31_0), value); 1681 1682 value = HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_4, DEST_IP_127_96, 1683 (flow->tuple_info.dest_ip_127_96)); 1684 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY_4, 1685 DEST_IP_127_96), value); 1686 1687 value = HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_5, DEST_IP_95_64, 1688 (flow->tuple_info.dest_ip_95_64)); 1689 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY_5, 1690 DEST_IP_95_64), value); 1691 1692 value = HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_6, DEST_IP_63_32, 1693 (flow->tuple_info.dest_ip_63_32)); 1694 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY_6, 1695 DEST_IP_63_32), value); 1696 1697 value = HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_7, DEST_IP_31_0, 1698 (flow->tuple_info.dest_ip_31_0)); 1699 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY_7, 1700 DEST_IP_31_0), value); 1701 1702 value = 0 | HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_8, DEST_PORT, 1703 (flow->tuple_info.dest_port)); 1704 value |= HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_8, SRC_PORT, 1705 (flow->tuple_info.src_port)); 1706 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY_8, 1707 SRC_PORT), value); 1708 1709 value = HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_10, METADATA, 1710 (flow->fse_metadata)); 1711 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY_10, 1712 METADATA), value); 1713 1714 /* Reset all the other fields in FSE */ 1715 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY_11, 1716 MSDU_COUNT), 0); 1717 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY_12, 1718 MSDU_BYTE_COUNT), 0); 1719 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY_13, 1720 TIMESTAMP), 0); 1721 1722 value = 0 | HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, L4_PROTOCOL, 1723 flow->tuple_info.l4_protocol); 1724 value |= HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_HANDLER, 1725 flow->reo_destination_handler); 1726 value |= HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, 1727 REO_DESTINATION_INDICATION, 1728 flow->reo_destination_indication); 1729 value |= HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, VALID, 1); 1730 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY_9, 1731 L4_PROTOCOL), value); 1732 1733 return fse_offset; 1734 } 1735 1736 /** 1737 * hal_rx_flow_get_cmem_fse_ts_6750() - Get timestamp field from CMEM FSE 1738 * @hal_soc: hal_soc reference 1739 * @fse_offset: CMEM FSE offset 1740 * 1741 * Return: Timestamp 1742 */ 1743 static uint32_t hal_rx_flow_get_cmem_fse_ts_6750(struct hal_soc *hal_soc, 1744 uint32_t fse_offset) 1745 { 1746 return HAL_CMEM_READ(hal_soc, fse_offset + 1747 HAL_OFFSET(RX_FLOW_SEARCH_ENTRY_13, TIMESTAMP)); 1748 } 1749 1750 /** 1751 * hal_rx_flow_get_cmem_fse_6750() - Get FSE from CMEM 1752 * @hal_soc: hal_soc reference 1753 * @fse_offset: CMEM FSE offset 1754 * @fse: referece where FSE will be copied 1755 * @len: length of FSE 1756 * 1757 * Return: If read is succesfull or not 1758 */ 1759 static void 1760 hal_rx_flow_get_cmem_fse_6750(struct hal_soc *hal_soc, uint32_t fse_offset, 1761 uint32_t *fse, qdf_size_t len) 1762 { 1763 int i; 1764 1765 if (len != HAL_RX_FST_ENTRY_SIZE) 1766 return; 1767 1768 for (i = 0; i < NUM_OF_DWORDS_RX_FLOW_SEARCH_ENTRY; i++) 1769 fse[i] = HAL_CMEM_READ(hal_soc, fse_offset + i * 4); 1770 } 1771 1772 /** 1773 * hal_rx_msdu_get_reo_destination_indication_6750: API to get 1774 * reo_destination_indication from rx_msdu_end TLV 1775 * @buf: pointer to the start of RX PKT TLV headers 1776 * @reo_destination_indication: pointer to return value of reo_destination_indication 1777 * 1778 * Return: none 1779 */ 1780 static void 1781 hal_rx_msdu_get_reo_destination_indication_6750(uint8_t *buf, 1782 uint32_t *reo_destination_indication) 1783 { 1784 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1785 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1786 1787 *reo_destination_indication = HAL_RX_MSDU_END_REO_DEST_IND_GET(msdu_end); 1788 } 1789 1790 static 1791 void hal_compute_reo_remap_ix2_ix3_6750(uint32_t *ring, uint32_t num_rings, 1792 uint32_t *remap1, uint32_t *remap2) 1793 { 1794 switch (num_rings) { 1795 case 3: 1796 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 1797 HAL_REO_REMAP_IX2(ring[1], 17) | 1798 HAL_REO_REMAP_IX2(ring[2], 18) | 1799 HAL_REO_REMAP_IX2(ring[0], 19) | 1800 HAL_REO_REMAP_IX2(ring[1], 20) | 1801 HAL_REO_REMAP_IX2(ring[2], 21) | 1802 HAL_REO_REMAP_IX2(ring[0], 22) | 1803 HAL_REO_REMAP_IX2(ring[1], 23); 1804 1805 *remap2 = HAL_REO_REMAP_IX3(ring[2], 24) | 1806 HAL_REO_REMAP_IX3(ring[0], 25) | 1807 HAL_REO_REMAP_IX3(ring[1], 26) | 1808 HAL_REO_REMAP_IX3(ring[2], 27) | 1809 HAL_REO_REMAP_IX3(ring[0], 28) | 1810 HAL_REO_REMAP_IX3(ring[1], 29) | 1811 HAL_REO_REMAP_IX3(ring[2], 30) | 1812 HAL_REO_REMAP_IX3(ring[0], 31); 1813 break; 1814 case 4: 1815 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 1816 HAL_REO_REMAP_IX2(ring[1], 17) | 1817 HAL_REO_REMAP_IX2(ring[2], 18) | 1818 HAL_REO_REMAP_IX2(ring[3], 19) | 1819 HAL_REO_REMAP_IX2(ring[0], 20) | 1820 HAL_REO_REMAP_IX2(ring[1], 21) | 1821 HAL_REO_REMAP_IX2(ring[2], 22) | 1822 HAL_REO_REMAP_IX2(ring[3], 23); 1823 1824 *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) | 1825 HAL_REO_REMAP_IX3(ring[1], 25) | 1826 HAL_REO_REMAP_IX3(ring[2], 26) | 1827 HAL_REO_REMAP_IX3(ring[3], 27) | 1828 HAL_REO_REMAP_IX3(ring[0], 28) | 1829 HAL_REO_REMAP_IX3(ring[1], 29) | 1830 HAL_REO_REMAP_IX3(ring[2], 30) | 1831 HAL_REO_REMAP_IX3(ring[3], 31); 1832 break; 1833 } 1834 } 1835 1836 static void hal_hw_txrx_ops_attach_qca6750(struct hal_soc *hal_soc) 1837 { 1838 /* init and setup */ 1839 hal_soc->ops->hal_srng_dst_hw_init = hal_srng_dst_hw_init_generic; 1840 hal_soc->ops->hal_srng_src_hw_init = hal_srng_src_hw_init_generic; 1841 hal_soc->ops->hal_get_hw_hptp = hal_get_hw_hptp_generic; 1842 hal_soc->ops->hal_reo_setup = hal_reo_setup_generic_li; 1843 hal_soc->ops->hal_get_window_address = hal_get_window_address_6750; 1844 hal_soc->ops->hal_reo_set_err_dst_remap = hal_reo_set_err_dst_remap_6750; 1845 1846 /* tx */ 1847 hal_soc->ops->hal_tx_desc_set_dscp_tid_table_id = 1848 hal_tx_desc_set_dscp_tid_table_id_6750; 1849 hal_soc->ops->hal_tx_set_dscp_tid_map = hal_tx_set_dscp_tid_map_6750; 1850 hal_soc->ops->hal_tx_update_dscp_tid = hal_tx_update_dscp_tid_6750; 1851 hal_soc->ops->hal_tx_desc_set_lmac_id = hal_tx_desc_set_lmac_id_6750; 1852 hal_soc->ops->hal_tx_desc_set_buf_addr = 1853 hal_tx_desc_set_buf_addr_generic_li; 1854 hal_soc->ops->hal_tx_desc_set_search_type = 1855 hal_tx_desc_set_search_type_generic_li; 1856 hal_soc->ops->hal_tx_desc_set_search_index = 1857 hal_tx_desc_set_search_index_generic_li; 1858 hal_soc->ops->hal_tx_desc_set_cache_set_num = 1859 hal_tx_desc_set_cache_set_num_generic_li; 1860 hal_soc->ops->hal_tx_comp_get_status = 1861 hal_tx_comp_get_status_generic_li; 1862 hal_soc->ops->hal_tx_comp_get_release_reason = 1863 hal_tx_comp_get_release_reason_generic_li; 1864 hal_soc->ops->hal_get_wbm_internal_error = 1865 hal_get_wbm_internal_error_generic_li; 1866 hal_soc->ops->hal_tx_desc_set_mesh_en = hal_tx_desc_set_mesh_en_6750; 1867 hal_soc->ops->hal_tx_init_cmd_credit_ring = 1868 hal_tx_init_cmd_credit_ring_6750; 1869 1870 /* rx */ 1871 hal_soc->ops->hal_rx_msdu_start_nss_get = 1872 hal_rx_msdu_start_nss_get_6750; 1873 hal_soc->ops->hal_rx_mon_hw_desc_get_mpdu_status = 1874 hal_rx_mon_hw_desc_get_mpdu_status_6750; 1875 hal_soc->ops->hal_rx_get_tlv = hal_rx_get_tlv_6750; 1876 hal_soc->ops->hal_rx_proc_phyrx_other_receive_info_tlv = 1877 hal_rx_proc_phyrx_other_receive_info_tlv_6750; 1878 hal_soc->ops->hal_rx_dump_msdu_start_tlv = 1879 hal_rx_dump_msdu_start_tlv_6750; 1880 hal_soc->ops->hal_rx_dump_msdu_end_tlv = hal_rx_dump_msdu_end_tlv_6750; 1881 hal_soc->ops->hal_get_link_desc_size = hal_get_link_desc_size_6750; 1882 hal_soc->ops->hal_rx_mpdu_start_tid_get = 1883 hal_rx_mpdu_start_tid_get_6750; 1884 hal_soc->ops->hal_rx_msdu_start_reception_type_get = 1885 hal_rx_msdu_start_reception_type_get_6750; 1886 hal_soc->ops->hal_rx_msdu_end_da_idx_get = 1887 hal_rx_msdu_end_da_idx_get_6750; 1888 hal_soc->ops->hal_rx_msdu_desc_info_get_ptr = 1889 hal_rx_msdu_desc_info_get_ptr_6750; 1890 hal_soc->ops->hal_rx_link_desc_msdu0_ptr = 1891 hal_rx_link_desc_msdu0_ptr_6750; 1892 hal_soc->ops->hal_reo_status_get_header = 1893 hal_reo_status_get_header_6750; 1894 hal_soc->ops->hal_rx_status_get_tlv_info = 1895 hal_rx_status_get_tlv_info_generic_li; 1896 hal_soc->ops->hal_rx_wbm_err_info_get = 1897 hal_rx_wbm_err_info_get_generic_li; 1898 hal_soc->ops->hal_rx_dump_mpdu_start_tlv = 1899 hal_rx_dump_mpdu_start_tlv_generic_li; 1900 1901 hal_soc->ops->hal_tx_set_pcp_tid_map = 1902 hal_tx_set_pcp_tid_map_generic_li; 1903 hal_soc->ops->hal_tx_update_pcp_tid_map = 1904 hal_tx_update_pcp_tid_generic_li; 1905 hal_soc->ops->hal_tx_set_tidmap_prty = 1906 hal_tx_update_tidmap_prty_generic_li; 1907 hal_soc->ops->hal_rx_get_rx_fragment_number = 1908 hal_rx_get_rx_fragment_number_6750; 1909 hal_soc->ops->hal_rx_msdu_end_da_is_mcbc_get = 1910 hal_rx_msdu_end_da_is_mcbc_get_6750; 1911 hal_soc->ops->hal_rx_msdu_end_sa_is_valid_get = 1912 hal_rx_msdu_end_sa_is_valid_get_6750; 1913 hal_soc->ops->hal_rx_msdu_end_sa_idx_get = 1914 hal_rx_msdu_end_sa_idx_get_6750; 1915 hal_soc->ops->hal_rx_desc_is_first_msdu = 1916 hal_rx_desc_is_first_msdu_6750; 1917 hal_soc->ops->hal_rx_msdu_end_l3_hdr_padding_get = 1918 hal_rx_msdu_end_l3_hdr_padding_get_6750; 1919 hal_soc->ops->hal_rx_encryption_info_valid = 1920 hal_rx_encryption_info_valid_6750; 1921 hal_soc->ops->hal_rx_print_pn = hal_rx_print_pn_6750; 1922 hal_soc->ops->hal_rx_msdu_end_first_msdu_get = 1923 hal_rx_msdu_end_first_msdu_get_6750; 1924 hal_soc->ops->hal_rx_msdu_end_da_is_valid_get = 1925 hal_rx_msdu_end_da_is_valid_get_6750; 1926 hal_soc->ops->hal_rx_msdu_end_last_msdu_get = 1927 hal_rx_msdu_end_last_msdu_get_6750; 1928 hal_soc->ops->hal_rx_get_mpdu_mac_ad4_valid = 1929 hal_rx_get_mpdu_mac_ad4_valid_6750; 1930 hal_soc->ops->hal_rx_mpdu_start_sw_peer_id_get = 1931 hal_rx_mpdu_start_sw_peer_id_get_6750; 1932 hal_soc->ops->hal_rx_mpdu_get_to_ds = hal_rx_mpdu_get_to_ds_6750; 1933 hal_soc->ops->hal_rx_mpdu_get_fr_ds = hal_rx_mpdu_get_fr_ds_6750; 1934 hal_soc->ops->hal_rx_get_mpdu_frame_control_valid = 1935 hal_rx_get_mpdu_frame_control_valid_6750; 1936 hal_soc->ops->hal_rx_mpdu_get_addr1 = hal_rx_mpdu_get_addr1_6750; 1937 hal_soc->ops->hal_rx_mpdu_get_addr2 = hal_rx_mpdu_get_addr2_6750; 1938 hal_soc->ops->hal_rx_mpdu_get_addr3 = hal_rx_mpdu_get_addr3_6750; 1939 hal_soc->ops->hal_rx_mpdu_get_addr4 = hal_rx_mpdu_get_addr4_6750; 1940 hal_soc->ops->hal_rx_get_mpdu_sequence_control_valid = 1941 hal_rx_get_mpdu_sequence_control_valid_6750; 1942 hal_soc->ops->hal_rx_is_unicast = hal_rx_is_unicast_6750; 1943 hal_soc->ops->hal_rx_tid_get = hal_rx_tid_get_6750; 1944 hal_soc->ops->hal_rx_hw_desc_get_ppduid_get = 1945 hal_rx_hw_desc_get_ppduid_get_6750; 1946 hal_soc->ops->hal_rx_msdu0_buffer_addr_lsb = 1947 hal_rx_msdu0_buffer_addr_lsb_6750; 1948 hal_soc->ops->hal_rx_msdu_desc_info_ptr_get = 1949 hal_rx_msdu_desc_info_ptr_get_6750; 1950 hal_soc->ops->hal_ent_mpdu_desc_info = hal_ent_mpdu_desc_info_6750; 1951 hal_soc->ops->hal_dst_mpdu_desc_info = hal_dst_mpdu_desc_info_6750; 1952 hal_soc->ops->hal_rx_get_fc_valid = hal_rx_get_fc_valid_6750; 1953 hal_soc->ops->hal_rx_get_to_ds_flag = hal_rx_get_to_ds_flag_6750; 1954 hal_soc->ops->hal_rx_get_mac_addr2_valid = 1955 hal_rx_get_mac_addr2_valid_6750; 1956 hal_soc->ops->hal_rx_get_filter_category = 1957 hal_rx_get_filter_category_6750; 1958 hal_soc->ops->hal_rx_get_ppdu_id = hal_rx_get_ppdu_id_6750; 1959 hal_soc->ops->hal_reo_config = hal_reo_config_6750; 1960 hal_soc->ops->hal_rx_msdu_flow_idx_get = hal_rx_msdu_flow_idx_get_6750; 1961 hal_soc->ops->hal_rx_msdu_flow_idx_invalid = 1962 hal_rx_msdu_flow_idx_invalid_6750; 1963 hal_soc->ops->hal_rx_msdu_flow_idx_timeout = 1964 hal_rx_msdu_flow_idx_timeout_6750; 1965 hal_soc->ops->hal_rx_msdu_fse_metadata_get = 1966 hal_rx_msdu_fse_metadata_get_6750; 1967 hal_soc->ops->hal_rx_msdu_cce_metadata_get = 1968 hal_rx_msdu_cce_metadata_get_6750; 1969 hal_soc->ops->hal_rx_msdu_get_flow_params = 1970 hal_rx_msdu_get_flow_params_6750; 1971 hal_soc->ops->hal_rx_tlv_get_tcp_chksum = 1972 hal_rx_tlv_get_tcp_chksum_6750; 1973 hal_soc->ops->hal_rx_get_rx_sequence = hal_rx_get_rx_sequence_6750; 1974 #if defined(QCA_WIFI_QCA6750) && defined(WLAN_CFR_ENABLE) && \ 1975 defined(WLAN_ENH_CFR_ENABLE) 1976 hal_soc->ops->hal_rx_get_bb_info = hal_rx_get_bb_info_6750; 1977 hal_soc->ops->hal_rx_get_rtt_info = hal_rx_get_rtt_info_6750; 1978 #endif 1979 /* rx - msdu end fast path info fields */ 1980 hal_soc->ops->hal_rx_msdu_packet_metadata_get = 1981 hal_rx_msdu_packet_metadata_get_generic_li; 1982 hal_soc->ops->hal_rx_get_fisa_cumulative_l4_checksum = 1983 hal_rx_get_fisa_cumulative_l4_checksum_6750; 1984 hal_soc->ops->hal_rx_get_fisa_cumulative_ip_length = 1985 hal_rx_get_fisa_cumulative_ip_length_6750; 1986 hal_soc->ops->hal_rx_get_udp_proto = hal_rx_get_udp_proto_6750; 1987 hal_soc->ops->hal_rx_get_fisa_flow_agg_continuation = 1988 hal_rx_get_flow_agg_continuation_6750; 1989 hal_soc->ops->hal_rx_get_fisa_flow_agg_count = 1990 hal_rx_get_flow_agg_count_6750; 1991 hal_soc->ops->hal_rx_get_fisa_timeout = hal_rx_get_fisa_timeout_6750; 1992 hal_soc->ops->hal_rx_mpdu_start_tlv_tag_valid = 1993 hal_rx_mpdu_start_tlv_tag_valid_6750; 1994 1995 /* rx - TLV struct offsets */ 1996 hal_soc->ops->hal_rx_msdu_end_offset_get = 1997 hal_rx_msdu_end_offset_get_generic; 1998 hal_soc->ops->hal_rx_attn_offset_get = hal_rx_attn_offset_get_generic; 1999 hal_soc->ops->hal_rx_msdu_start_offset_get = 2000 hal_rx_msdu_start_offset_get_generic; 2001 hal_soc->ops->hal_rx_mpdu_start_offset_get = 2002 hal_rx_mpdu_start_offset_get_generic; 2003 hal_soc->ops->hal_rx_mpdu_end_offset_get = 2004 hal_rx_mpdu_end_offset_get_generic; 2005 #ifndef NO_RX_PKT_HDR_TLV 2006 hal_soc->ops->hal_rx_pkt_tlv_offset_get = 2007 hal_rx_pkt_tlv_offset_get_generic; 2008 #endif 2009 hal_soc->ops->hal_rx_flow_setup_fse = hal_rx_flow_setup_fse_6750; 2010 hal_soc->ops->hal_compute_reo_remap_ix2_ix3 = 2011 hal_compute_reo_remap_ix2_ix3_6750; 2012 2013 /* CMEM FSE */ 2014 hal_soc->ops->hal_rx_flow_setup_cmem_fse = 2015 hal_rx_flow_setup_cmem_fse_6750; 2016 hal_soc->ops->hal_rx_flow_get_cmem_fse_ts = 2017 hal_rx_flow_get_cmem_fse_ts_6750; 2018 hal_soc->ops->hal_rx_flow_get_cmem_fse = hal_rx_flow_get_cmem_fse_6750; 2019 hal_soc->ops->hal_rx_msdu_get_reo_destination_indication = 2020 hal_rx_msdu_get_reo_destination_indication_6750; 2021 hal_soc->ops->hal_setup_link_idle_list = 2022 hal_setup_link_idle_list_generic_li; 2023 }; 2024 2025 struct hal_hw_srng_config hw_srng_table_6750[] = { 2026 /* TODO: max_rings can populated by querying HW capabilities */ 2027 { /* REO_DST */ 2028 .start_ring_id = HAL_SRNG_REO2SW1, 2029 .max_rings = 4, 2030 .entry_size = sizeof(struct reo_destination_ring) >> 2, 2031 .lmac_ring = FALSE, 2032 .ring_dir = HAL_SRNG_DST_RING, 2033 .reg_start = { 2034 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR( 2035 SEQ_WCSS_UMAC_REO_REG_OFFSET), 2036 HWIO_REO_R2_REO2SW1_RING_HP_ADDR( 2037 SEQ_WCSS_UMAC_REO_REG_OFFSET) 2038 }, 2039 .reg_size = { 2040 HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(0) - 2041 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(0), 2042 HWIO_REO_R2_REO2SW2_RING_HP_ADDR(0) - 2043 HWIO_REO_R2_REO2SW1_RING_HP_ADDR(0), 2044 }, 2045 .max_size = 2046 HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_BMSK >> 2047 HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_SHFT, 2048 }, 2049 { /* REO_EXCEPTION */ 2050 /* Designating REO2TCL ring as exception ring. This ring is 2051 * similar to other REO2SW rings though it is named as REO2TCL. 2052 * Any of theREO2SW rings can be used as exception ring. 2053 */ 2054 .start_ring_id = HAL_SRNG_REO2TCL, 2055 .max_rings = 1, 2056 .entry_size = sizeof(struct reo_destination_ring) >> 2, 2057 .lmac_ring = FALSE, 2058 .ring_dir = HAL_SRNG_DST_RING, 2059 .reg_start = { 2060 HWIO_REO_R0_REO2TCL_RING_BASE_LSB_ADDR( 2061 SEQ_WCSS_UMAC_REO_REG_OFFSET), 2062 HWIO_REO_R2_REO2TCL_RING_HP_ADDR( 2063 SEQ_WCSS_UMAC_REO_REG_OFFSET) 2064 }, 2065 /* Single ring - provide ring size if multiple rings of this 2066 * type are supported 2067 */ 2068 .reg_size = {}, 2069 .max_size = 2070 HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_BMSK >> 2071 HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_SHFT, 2072 }, 2073 { /* REO_REINJECT */ 2074 .start_ring_id = HAL_SRNG_SW2REO, 2075 .max_rings = 1, 2076 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 2077 .lmac_ring = FALSE, 2078 .ring_dir = HAL_SRNG_SRC_RING, 2079 .reg_start = { 2080 HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR( 2081 SEQ_WCSS_UMAC_REO_REG_OFFSET), 2082 HWIO_REO_R2_SW2REO_RING_HP_ADDR( 2083 SEQ_WCSS_UMAC_REO_REG_OFFSET) 2084 }, 2085 /* Single ring - provide ring size if multiple rings of this 2086 * type are supported 2087 */ 2088 .reg_size = {}, 2089 .max_size = HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_BMSK >> 2090 HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_SHFT, 2091 }, 2092 { /* REO_CMD */ 2093 .start_ring_id = HAL_SRNG_REO_CMD, 2094 .max_rings = 1, 2095 .entry_size = (sizeof(struct tlv_32_hdr) + 2096 sizeof(struct reo_get_queue_stats)) >> 2, 2097 .lmac_ring = FALSE, 2098 .ring_dir = HAL_SRNG_SRC_RING, 2099 .reg_start = { 2100 HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR( 2101 SEQ_WCSS_UMAC_REO_REG_OFFSET), 2102 HWIO_REO_R2_REO_CMD_RING_HP_ADDR( 2103 SEQ_WCSS_UMAC_REO_REG_OFFSET), 2104 }, 2105 /* Single ring - provide ring size if multiple rings of this 2106 * type are supported 2107 */ 2108 .reg_size = {}, 2109 .max_size = 2110 HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_BMSK >> 2111 HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_SHFT, 2112 }, 2113 { /* REO_STATUS */ 2114 .start_ring_id = HAL_SRNG_REO_STATUS, 2115 .max_rings = 1, 2116 .entry_size = (sizeof(struct tlv_32_hdr) + 2117 sizeof(struct reo_get_queue_stats_status)) >> 2, 2118 .lmac_ring = FALSE, 2119 .ring_dir = HAL_SRNG_DST_RING, 2120 .reg_start = { 2121 HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR( 2122 SEQ_WCSS_UMAC_REO_REG_OFFSET), 2123 HWIO_REO_R2_REO_STATUS_RING_HP_ADDR( 2124 SEQ_WCSS_UMAC_REO_REG_OFFSET), 2125 }, 2126 /* Single ring - provide ring size if multiple rings of this 2127 * type are supported 2128 */ 2129 .reg_size = {}, 2130 .max_size = 2131 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> 2132 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, 2133 }, 2134 { /* TCL_DATA */ 2135 .start_ring_id = HAL_SRNG_SW2TCL1, 2136 .max_rings = 3, 2137 .entry_size = (sizeof(struct tlv_32_hdr) + 2138 sizeof(struct tcl_data_cmd)) >> 2, 2139 .lmac_ring = FALSE, 2140 .ring_dir = HAL_SRNG_SRC_RING, 2141 .reg_start = { 2142 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR( 2143 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 2144 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR( 2145 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 2146 }, 2147 .reg_size = { 2148 HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(0) - 2149 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(0), 2150 HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(0) - 2151 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(0), 2152 }, 2153 .max_size = 2154 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK >> 2155 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT, 2156 }, 2157 { /* TCL_CMD */ 2158 .start_ring_id = HAL_SRNG_SW2TCL_CMD, 2159 .max_rings = 1, 2160 .entry_size = (sizeof(struct tlv_32_hdr) + 2161 sizeof(struct tcl_gse_cmd)) >> 2, 2162 .lmac_ring = FALSE, 2163 .ring_dir = HAL_SRNG_SRC_RING, 2164 .reg_start = { 2165 HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_ADDR( 2166 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 2167 HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_ADDR( 2168 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 2169 }, 2170 /* Single ring - provide ring size if multiple rings of this 2171 * type are supported 2172 */ 2173 .reg_size = {}, 2174 .max_size = 2175 HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_SIZE_BMSK >> 2176 HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_SIZE_SHFT, 2177 }, 2178 { /* TCL_STATUS */ 2179 .start_ring_id = HAL_SRNG_TCL_STATUS, 2180 .max_rings = 1, 2181 .entry_size = (sizeof(struct tlv_32_hdr) + 2182 sizeof(struct tcl_status_ring)) >> 2, 2183 .lmac_ring = FALSE, 2184 .ring_dir = HAL_SRNG_DST_RING, 2185 .reg_start = { 2186 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR( 2187 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 2188 HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR( 2189 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 2190 }, 2191 /* Single ring - provide ring size if multiple rings of this 2192 * type are supported 2193 */ 2194 .reg_size = {}, 2195 .max_size = 2196 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_BMSK >> 2197 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_SHFT, 2198 }, 2199 { /* CE_SRC */ 2200 .start_ring_id = HAL_SRNG_CE_0_SRC, 2201 .max_rings = 12, 2202 .entry_size = sizeof(struct ce_src_desc) >> 2, 2203 .lmac_ring = FALSE, 2204 .ring_dir = HAL_SRNG_SRC_RING, 2205 .reg_start = { 2206 HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR, 2207 HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR, 2208 }, 2209 .reg_size = { 2210 HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR - 2211 HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR, 2212 HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR - 2213 HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR, 2214 }, 2215 .max_size = 2216 HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >> 2217 HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT 2218 }, 2219 { /* CE_DST */ 2220 .start_ring_id = HAL_SRNG_CE_0_DST, 2221 .max_rings = 12, 2222 .entry_size = 8 >> 2, 2223 /*TODO: entry_size above should actually be 2224 * sizeof(struct ce_dst_desc) >> 2, but couldn't find definition 2225 * of struct ce_dst_desc in HW header files 2226 */ 2227 .lmac_ring = FALSE, 2228 .ring_dir = HAL_SRNG_SRC_RING, 2229 .reg_start = { 2230 HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, 2231 HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR, 2232 }, 2233 .reg_size = { 2234 HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR - 2235 HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, 2236 HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR - 2237 HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR 2238 }, 2239 .max_size = 2240 HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >> 2241 HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT 2242 }, 2243 { /* CE_DST_STATUS */ 2244 .start_ring_id = HAL_SRNG_CE_0_DST_STATUS, 2245 .max_rings = 12, 2246 .entry_size = sizeof(struct ce_stat_desc) >> 2, 2247 .lmac_ring = FALSE, 2248 .ring_dir = HAL_SRNG_DST_RING, 2249 .reg_start = { 2250 HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR, 2251 HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR, 2252 }, 2253 /* TODO: check destination status ring registers */ 2254 .reg_size = { 2255 HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR - 2256 HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, 2257 HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR - 2258 HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR 2259 }, 2260 .max_size = 2261 HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> 2262 HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, 2263 }, 2264 { /* WBM_IDLE_LINK */ 2265 .start_ring_id = HAL_SRNG_WBM_IDLE_LINK, 2266 .max_rings = 1, 2267 .entry_size = sizeof(struct wbm_link_descriptor_ring) >> 2, 2268 .lmac_ring = FALSE, 2269 .ring_dir = HAL_SRNG_SRC_RING, 2270 .reg_start = { 2271 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2272 HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2273 }, 2274 /* Single ring - provide ring size if multiple rings of this 2275 * type are supported 2276 */ 2277 .reg_size = {}, 2278 .max_size = 2279 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_BMSK >> 2280 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_SHFT, 2281 }, 2282 { /* SW2WBM_RELEASE */ 2283 .start_ring_id = HAL_SRNG_WBM_SW_RELEASE, 2284 .max_rings = 1, 2285 .entry_size = sizeof(struct wbm_release_ring) >> 2, 2286 .lmac_ring = FALSE, 2287 .ring_dir = HAL_SRNG_SRC_RING, 2288 .reg_start = { 2289 HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2290 HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2291 }, 2292 /* Single ring - provide ring size if multiple rings of this 2293 * type are supported 2294 */ 2295 .reg_size = {}, 2296 .max_size = 2297 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> 2298 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, 2299 }, 2300 { /* WBM2SW_RELEASE */ 2301 .start_ring_id = HAL_SRNG_WBM2SW0_RELEASE, 2302 .max_rings = 4, 2303 .entry_size = sizeof(struct wbm_release_ring) >> 2, 2304 .lmac_ring = FALSE, 2305 .ring_dir = HAL_SRNG_DST_RING, 2306 .reg_start = { 2307 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2308 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2309 }, 2310 .reg_size = { 2311 HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) - 2312 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2313 HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) - 2314 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2315 }, 2316 .max_size = 2317 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> 2318 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, 2319 }, 2320 { /* RXDMA_BUF */ 2321 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA0_BUF0, 2322 #ifdef IPA_OFFLOAD 2323 .max_rings = 3, 2324 #else 2325 .max_rings = 2, 2326 #endif 2327 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 2328 .lmac_ring = TRUE, 2329 .ring_dir = HAL_SRNG_SRC_RING, 2330 /* reg_start is not set because LMAC rings are not accessed 2331 * from host 2332 */ 2333 .reg_start = {}, 2334 .reg_size = {}, 2335 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2336 }, 2337 { /* RXDMA_DST */ 2338 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW0, 2339 .max_rings = 1, 2340 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 2341 .lmac_ring = TRUE, 2342 .ring_dir = HAL_SRNG_DST_RING, 2343 /* reg_start is not set because LMAC rings are not accessed 2344 * from host 2345 */ 2346 .reg_start = {}, 2347 .reg_size = {}, 2348 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2349 }, 2350 { /* RXDMA_MONITOR_BUF */ 2351 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA2_BUF, 2352 .max_rings = 1, 2353 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 2354 .lmac_ring = TRUE, 2355 .ring_dir = HAL_SRNG_SRC_RING, 2356 /* reg_start is not set because LMAC rings are not accessed 2357 * from host 2358 */ 2359 .reg_start = {}, 2360 .reg_size = {}, 2361 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2362 }, 2363 { /* RXDMA_MONITOR_STATUS */ 2364 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_STATBUF, 2365 .max_rings = 1, 2366 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 2367 .lmac_ring = TRUE, 2368 .ring_dir = HAL_SRNG_SRC_RING, 2369 /* reg_start is not set because LMAC rings are not accessed 2370 * from host 2371 */ 2372 .reg_start = {}, 2373 .reg_size = {}, 2374 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2375 }, 2376 { /* RXDMA_MONITOR_DST */ 2377 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW1, 2378 .max_rings = 1, 2379 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 2380 .lmac_ring = TRUE, 2381 .ring_dir = HAL_SRNG_DST_RING, 2382 /* reg_start is not set because LMAC rings are not accessed 2383 * from host 2384 */ 2385 .reg_start = {}, 2386 .reg_size = {}, 2387 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2388 }, 2389 { /* RXDMA_MONITOR_DESC */ 2390 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_DESC, 2391 .max_rings = 1, 2392 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 2393 .lmac_ring = TRUE, 2394 .ring_dir = HAL_SRNG_SRC_RING, 2395 /* reg_start is not set because LMAC rings are not accessed 2396 * from host 2397 */ 2398 .reg_start = {}, 2399 .reg_size = {}, 2400 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2401 }, 2402 { /* DIR_BUF_RX_DMA_SRC */ 2403 .start_ring_id = HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING, 2404 /* 2405 * one ring is for spectral scan 2406 * the other is for cfr 2407 */ 2408 .max_rings = 2, 2409 .entry_size = 2, 2410 .lmac_ring = TRUE, 2411 .ring_dir = HAL_SRNG_SRC_RING, 2412 /* reg_start is not set because LMAC rings are not accessed 2413 * from host 2414 */ 2415 .reg_start = {}, 2416 .reg_size = {}, 2417 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2418 }, 2419 #ifdef WLAN_FEATURE_CIF_CFR 2420 { /* WIFI_POS_SRC */ 2421 .start_ring_id = HAL_SRNG_WIFI_POS_SRC_DMA_RING, 2422 .max_rings = 1, 2423 .entry_size = sizeof(wmi_oem_dma_buf_release_entry) >> 2, 2424 .lmac_ring = TRUE, 2425 .ring_dir = HAL_SRNG_SRC_RING, 2426 /* reg_start is not set because LMAC rings are not accessed 2427 * from host 2428 */ 2429 .reg_start = {}, 2430 .reg_size = {}, 2431 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2432 }, 2433 #endif 2434 { /* REO2PPE */ 0}, 2435 { /* PPE2TCL */ 0}, 2436 { /* PPE_RELEASE */ 0}, 2437 { /* TX_MONITOR_BUF */ 0}, 2438 { /* TX_MONITOR_DST */ 0}, 2439 { /* SW2RXDMA_NEW */ 0}, 2440 }; 2441 2442 /** 2443 * hal_qca6750_attach() - Attach 6750 target specific hal_soc ops, 2444 * offset and srng table 2445 */ 2446 void hal_qca6750_attach(struct hal_soc *hal_soc) 2447 { 2448 hal_soc->hw_srng_table = hw_srng_table_6750; 2449 hal_srng_hw_reg_offset_init_generic(hal_soc); 2450 hal_hw_txrx_default_ops_attach_li(hal_soc); 2451 hal_hw_txrx_ops_attach_qca6750(hal_soc); 2452 } 2453