1 /* 2 * Copyright (c) 2019-2020 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #ifndef _HAL_6490_RX_H_ 20 #define _HAL_6490_RX_H_ 21 #include "qdf_util.h" 22 #include "qdf_types.h" 23 #include "qdf_lock.h" 24 #include "qdf_mem.h" 25 #include "qdf_nbuf.h" 26 #include "tcl_data_cmd.h" 27 #include "mac_tcl_reg_seq_hwioreg.h" 28 #include "phyrx_rssi_legacy.h" 29 #include "rx_msdu_start.h" 30 #include "tlv_tag_def.h" 31 #include "hal_hw_headers.h" 32 #include "hal_internal.h" 33 #include "cdp_txrx_mon_struct.h" 34 #include "qdf_trace.h" 35 #include "hal_rx.h" 36 #include "hal_tx.h" 37 #include "dp_types.h" 38 #include "hal_api_mon.h" 39 #include "phyrx_other_receive_info_ru_details.h" 40 41 #define HAL_RX_MSDU_START_MIMO_SS_BITMAP(_rx_msdu_start)\ 42 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start),\ 43 RX_MSDU_START_5_MIMO_SS_BITMAP_OFFSET)), \ 44 RX_MSDU_START_5_MIMO_SS_BITMAP_MASK, \ 45 RX_MSDU_START_5_MIMO_SS_BITMAP_LSB)) 46 47 #define HAL_RX_MPDU_GET_SEQUENCE_NUMBER(_rx_mpdu_info) \ 48 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 49 RX_MPDU_INFO_11_MPDU_SEQUENCE_NUMBER_OFFSET)), \ 50 RX_MPDU_INFO_11_MPDU_SEQUENCE_NUMBER_MASK, \ 51 RX_MPDU_INFO_11_MPDU_SEQUENCE_NUMBER_LSB)) 52 53 #define HAL_RX_MSDU_END_DA_IS_MCBC_GET(_rx_msdu_end) \ 54 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 55 RX_MSDU_END_10_DA_IS_MCBC_OFFSET)), \ 56 RX_MSDU_END_10_DA_IS_MCBC_MASK, \ 57 RX_MSDU_END_10_DA_IS_MCBC_LSB)) 58 59 #define HAL_RX_MSDU_END_SA_IS_VALID_GET(_rx_msdu_end) \ 60 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 61 RX_MSDU_END_10_SA_IS_VALID_OFFSET)), \ 62 RX_MSDU_END_10_SA_IS_VALID_MASK, \ 63 RX_MSDU_END_10_SA_IS_VALID_LSB)) 64 65 #define HAL_RX_MSDU_END_SA_IDX_GET(_rx_msdu_end) \ 66 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 67 RX_MSDU_END_11_SA_IDX_OFFSET)), \ 68 RX_MSDU_END_11_SA_IDX_MASK, \ 69 RX_MSDU_END_11_SA_IDX_LSB)) 70 71 #define HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(_rx_msdu_end) \ 72 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 73 RX_MSDU_END_10_L3_HEADER_PADDING_OFFSET)), \ 74 RX_MSDU_END_10_L3_HEADER_PADDING_MASK, \ 75 RX_MSDU_END_10_L3_HEADER_PADDING_LSB)) 76 77 #define HAL_RX_MPDU_ENCRYPTION_INFO_VALID(_rx_mpdu_info) \ 78 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 79 RX_MPDU_INFO_11_FRAME_ENCRYPTION_INFO_VALID_OFFSET)), \ 80 RX_MPDU_INFO_11_FRAME_ENCRYPTION_INFO_VALID_MASK, \ 81 RX_MPDU_INFO_11_FRAME_ENCRYPTION_INFO_VALID_LSB)) 82 83 #define HAL_RX_MPDU_PN_31_0_GET(_rx_mpdu_info) \ 84 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 85 RX_MPDU_INFO_3_PN_31_0_OFFSET)), \ 86 RX_MPDU_INFO_3_PN_31_0_MASK, \ 87 RX_MPDU_INFO_3_PN_31_0_LSB)) 88 89 #define HAL_RX_MPDU_PN_63_32_GET(_rx_mpdu_info) \ 90 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 91 RX_MPDU_INFO_4_PN_63_32_OFFSET)), \ 92 RX_MPDU_INFO_4_PN_63_32_MASK, \ 93 RX_MPDU_INFO_4_PN_63_32_LSB)) 94 95 #define HAL_RX_MPDU_PN_95_64_GET(_rx_mpdu_info) \ 96 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 97 RX_MPDU_INFO_5_PN_95_64_OFFSET)), \ 98 RX_MPDU_INFO_5_PN_95_64_MASK, \ 99 RX_MPDU_INFO_5_PN_95_64_LSB)) 100 101 #define HAL_RX_MPDU_PN_127_96_GET(_rx_mpdu_info) \ 102 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 103 RX_MPDU_INFO_6_PN_127_96_OFFSET)), \ 104 RX_MPDU_INFO_6_PN_127_96_MASK, \ 105 RX_MPDU_INFO_6_PN_127_96_LSB)) 106 107 #define HAL_RX_MSDU_END_FIRST_MSDU_GET(_rx_msdu_end) \ 108 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 109 RX_MSDU_END_10_FIRST_MSDU_OFFSET)), \ 110 RX_MSDU_END_10_FIRST_MSDU_MASK, \ 111 RX_MSDU_END_10_FIRST_MSDU_LSB)) 112 113 #define HAL_RX_MSDU_END_DA_IS_VALID_GET(_rx_msdu_end) \ 114 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 115 RX_MSDU_END_10_DA_IS_VALID_OFFSET)), \ 116 RX_MSDU_END_10_DA_IS_VALID_MASK, \ 117 RX_MSDU_END_10_DA_IS_VALID_LSB)) 118 119 #define HAL_RX_MSDU_END_LAST_MSDU_GET(_rx_msdu_end) \ 120 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 121 RX_MSDU_END_10_LAST_MSDU_OFFSET)), \ 122 RX_MSDU_END_10_LAST_MSDU_MASK, \ 123 RX_MSDU_END_10_LAST_MSDU_LSB)) 124 125 #define HAL_RX_MPDU_GET_MAC_AD4_VALID(_rx_mpdu_info) \ 126 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 127 RX_MPDU_INFO_11_MAC_ADDR_AD4_VALID_OFFSET)), \ 128 RX_MPDU_INFO_11_MAC_ADDR_AD4_VALID_MASK, \ 129 RX_MPDU_INFO_11_MAC_ADDR_AD4_VALID_LSB)) 130 131 #define HAL_RX_MPDU_INFO_SW_PEER_ID_GET(_rx_mpdu_info) \ 132 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_info), \ 133 RX_MPDU_INFO_10_SW_PEER_ID_OFFSET)), \ 134 RX_MPDU_INFO_10_SW_PEER_ID_MASK, \ 135 RX_MPDU_INFO_10_SW_PEER_ID_LSB)) 136 137 #define HAL_RX_MPDU_GET_TODS(_rx_mpdu_info) \ 138 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 139 RX_MPDU_INFO_11_TO_DS_OFFSET)), \ 140 RX_MPDU_INFO_11_TO_DS_MASK, \ 141 RX_MPDU_INFO_11_TO_DS_LSB)) 142 143 #define HAL_RX_MPDU_GET_FROMDS(_rx_mpdu_info) \ 144 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 145 RX_MPDU_INFO_11_FR_DS_OFFSET)), \ 146 RX_MPDU_INFO_11_FR_DS_MASK, \ 147 RX_MPDU_INFO_11_FR_DS_LSB)) 148 149 #define HAL_RX_MPDU_GET_FRAME_CONTROL_VALID(_rx_mpdu_info) \ 150 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 151 RX_MPDU_INFO_11_MPDU_FRAME_CONTROL_VALID_OFFSET)), \ 152 RX_MPDU_INFO_11_MPDU_FRAME_CONTROL_VALID_MASK, \ 153 RX_MPDU_INFO_11_MPDU_FRAME_CONTROL_VALID_LSB)) 154 155 #define HAL_RX_MPDU_MAC_ADDR_AD1_VALID_GET(_rx_mpdu_info) \ 156 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 157 RX_MPDU_INFO_11_MAC_ADDR_AD1_VALID_OFFSET)), \ 158 RX_MPDU_INFO_11_MAC_ADDR_AD1_VALID_MASK, \ 159 RX_MPDU_INFO_11_MAC_ADDR_AD1_VALID_LSB)) 160 161 #define HAL_RX_MPDU_AD1_31_0_GET(_rx_mpdu_info) \ 162 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 163 RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_OFFSET)), \ 164 RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_MASK, \ 165 RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_LSB)) 166 167 #define HAL_RX_MPDU_AD1_47_32_GET(_rx_mpdu_info) \ 168 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 169 RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_OFFSET)), \ 170 RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_MASK, \ 171 RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_LSB)) 172 173 #define HAL_RX_MPDU_MAC_ADDR_AD2_VALID_GET(_rx_mpdu_info) \ 174 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 175 RX_MPDU_INFO_11_MAC_ADDR_AD2_VALID_OFFSET)), \ 176 RX_MPDU_INFO_11_MAC_ADDR_AD2_VALID_MASK, \ 177 RX_MPDU_INFO_11_MAC_ADDR_AD2_VALID_LSB)) 178 179 #define HAL_RX_MPDU_AD2_15_0_GET(_rx_mpdu_info) \ 180 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 181 RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_OFFSET)), \ 182 RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_MASK, \ 183 RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_LSB)) 184 185 #define HAL_RX_MPDU_AD2_47_16_GET(_rx_mpdu_info) \ 186 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 187 RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_OFFSET)), \ 188 RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_MASK, \ 189 RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_LSB)) 190 191 #define HAL_RX_MPDU_MAC_ADDR_AD3_VALID_GET(_rx_mpdu_info) \ 192 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 193 RX_MPDU_INFO_11_MAC_ADDR_AD3_VALID_OFFSET)), \ 194 RX_MPDU_INFO_11_MAC_ADDR_AD3_VALID_MASK, \ 195 RX_MPDU_INFO_11_MAC_ADDR_AD3_VALID_LSB)) 196 197 #define HAL_RX_MPDU_AD3_31_0_GET(_rx_mpdu_info) \ 198 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 199 RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_OFFSET)), \ 200 RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_MASK, \ 201 RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_LSB)) 202 203 #define HAL_RX_MPDU_AD3_47_32_GET(_rx_mpdu_info) \ 204 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 205 RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_OFFSET)), \ 206 RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_MASK, \ 207 RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_LSB)) 208 209 #define HAL_RX_MPDU_MAC_ADDR_AD4_VALID_GET(_rx_mpdu_info) \ 210 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 211 RX_MPDU_INFO_11_MAC_ADDR_AD4_VALID_OFFSET)), \ 212 RX_MPDU_INFO_11_MAC_ADDR_AD4_VALID_MASK, \ 213 RX_MPDU_INFO_11_MAC_ADDR_AD4_VALID_LSB)) 214 215 #define HAL_RX_MPDU_AD4_31_0_GET(_rx_mpdu_info) \ 216 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 217 RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_OFFSET)), \ 218 RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_MASK, \ 219 RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_LSB)) 220 221 #define HAL_RX_MPDU_AD4_47_32_GET(_rx_mpdu_info) \ 222 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 223 RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_OFFSET)), \ 224 RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_MASK, \ 225 RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_LSB)) 226 227 #define HAL_RX_MPDU_GET_SEQUENCE_CONTROL_VALID(_rx_mpdu_info) \ 228 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 229 RX_MPDU_INFO_11_MPDU_SEQUENCE_CONTROL_VALID_OFFSET)), \ 230 RX_MPDU_INFO_11_MPDU_SEQUENCE_CONTROL_VALID_MASK, \ 231 RX_MPDU_INFO_11_MPDU_SEQUENCE_CONTROL_VALID_LSB)) 232 233 #define HAL_RX_MPDU_INFO_QOS_CONTROL_VALID_GET(_rx_mpdu_info) \ 234 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_info), \ 235 RX_MPDU_INFO_11_MPDU_QOS_CONTROL_VALID_OFFSET)),\ 236 RX_MPDU_INFO_11_MPDU_QOS_CONTROL_VALID_MASK, \ 237 RX_MPDU_INFO_11_MPDU_QOS_CONTROL_VALID_LSB)) 238 239 #define HAL_RX_MSDU_END_SA_SW_PEER_ID_GET(_rx_msdu_end) \ 240 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 241 RX_MSDU_END_14_SA_SW_PEER_ID_OFFSET)), \ 242 RX_MSDU_END_14_SA_SW_PEER_ID_MASK, \ 243 RX_MSDU_END_14_SA_SW_PEER_ID_LSB)) 244 245 #define HAL_RX_MSDU0_BUFFER_ADDR_LSB(link_desc_va) \ 246 (uint8_t *)(link_desc_va) + \ 247 RX_MSDU_LINK_8_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 248 249 #define HAL_RX_MSDU_DESC_INFO_PTR_GET(msdu0) \ 250 (uint8_t *)(msdu0) + \ 251 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 252 253 #define HAL_ENT_MPDU_DESC_INFO(ent_ring_desc) \ 254 (uint8_t *)(ent_ring_desc) + \ 255 RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_OFFSET 256 257 #define HAL_DST_MPDU_DESC_INFO(dst_ring_desc) \ 258 (uint8_t *)(dst_ring_desc) + \ 259 REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 260 261 #define HAL_RX_GET_FC_VALID(rx_mpdu_start) \ 262 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_11, MPDU_FRAME_CONTROL_VALID) 263 264 #define HAL_RX_GET_TO_DS_FLAG(rx_mpdu_start) \ 265 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_11, TO_DS) 266 267 #define HAL_RX_GET_MAC_ADDR1_VALID(rx_mpdu_start) \ 268 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_11, MAC_ADDR_AD1_VALID) 269 270 #define HAL_RX_GET_MAC_ADDR2_VALID(rx_mpdu_start) \ 271 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_11, MAC_ADDR_AD2_VALID) 272 273 #define HAL_RX_GET_FILTER_CATEGORY(rx_mpdu_start) \ 274 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_9, RXPCU_MPDU_FILTER_IN_CATEGORY) 275 276 #define HAL_RX_GET_PPDU_ID(rx_mpdu_start) \ 277 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_9, PHY_PPDU_ID) 278 279 #define HAL_RX_GET_SW_FRAME_GROUP_ID(rx_mpdu_start) \ 280 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_9, SW_FRAME_GROUP_ID) 281 282 #define HAL_REO_R0_CONFIG(soc, reg_val, reo_params) \ 283 do { \ 284 reg_val &= \ 285 ~(HWIO_REO_R0_GENERAL_ENABLE_AGING_LIST_ENABLE_BMSK |\ 286 HWIO_REO_R0_GENERAL_ENABLE_AGING_FLUSH_ENABLE_BMSK); \ 287 reg_val |= \ 288 HAL_SM(HWIO_REO_R0_GENERAL_ENABLE, \ 289 AGING_LIST_ENABLE, 1) |\ 290 HAL_SM(HWIO_REO_R0_GENERAL_ENABLE, \ 291 AGING_FLUSH_ENABLE, 1);\ 292 HAL_REG_WRITE((soc), \ 293 HWIO_REO_R0_GENERAL_ENABLE_ADDR( \ 294 SEQ_WCSS_UMAC_REO_REG_OFFSET), \ 295 (reg_val)); \ 296 reg_val = \ 297 HAL_REG_READ((soc), \ 298 HWIO_REO_R0_MISC_CTL_ADDR( \ 299 SEQ_WCSS_UMAC_REO_REG_OFFSET)); \ 300 reg_val &= \ 301 ~(HWIO_REO_R0_MISC_CTL_FRAGMENT_DEST_RING_BMSK); \ 302 reg_val |= \ 303 HAL_SM(HWIO_REO_R0_MISC_CTL, \ 304 FRAGMENT_DEST_RING, \ 305 (reo_params)->frag_dst_ring); \ 306 HAL_REG_WRITE((soc), \ 307 HWIO_REO_R0_MISC_CTL_ADDR( \ 308 SEQ_WCSS_UMAC_REO_REG_OFFSET), \ 309 (reg_val)); \ 310 reg_val = \ 311 HAL_REG_READ((soc), \ 312 HWIO_REO_R0_GENERAL_ENABLE_ADDR( \ 313 SEQ_WCSS_UMAC_REO_REG_OFFSET)); \ 314 reg_val &= \ 315 (~HWIO_REO_R0_GENERAL_ENABLE_BAR_DEST_RING_BMSK |\ 316 (REO_REMAP_TCL << HWIO_REO_R0_GENERAL_ENABLE_BAR_DEST_RING_SHFT)); \ 317 HAL_REG_WRITE((soc), \ 318 HWIO_REO_R0_GENERAL_ENABLE_ADDR( \ 319 SEQ_WCSS_UMAC_REO_REG_OFFSET), \ 320 (reg_val)); \ 321 } while (0) 322 323 #define HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr) \ 324 ((struct rx_msdu_desc_info *) \ 325 _OFFSET_TO_BYTE_PTR(msdu_details_ptr, \ 326 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_OFFSET)) 327 328 #define HAL_RX_LINK_DESC_MSDU0_PTR(link_desc) \ 329 ((struct rx_msdu_details *) \ 330 _OFFSET_TO_BYTE_PTR((link_desc),\ 331 RX_MSDU_LINK_8_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET)) 332 333 #define HAL_RX_MSDU_END_FLOW_IDX_GET(_rx_msdu_end) \ 334 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 335 RX_MSDU_END_12_FLOW_IDX_OFFSET)), \ 336 RX_MSDU_END_12_FLOW_IDX_MASK, \ 337 RX_MSDU_END_12_FLOW_IDX_LSB)) 338 339 #define HAL_RX_MSDU_END_REO_DEST_IND_GET(_rx_msdu_end) \ 340 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 341 RX_MSDU_END_12_REO_DESTINATION_INDICATION_OFFSET)), \ 342 RX_MSDU_END_12_REO_DESTINATION_INDICATION_MASK, \ 343 RX_MSDU_END_12_REO_DESTINATION_INDICATION_LSB)) 344 345 #define HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(_rx_msdu_end) \ 346 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 347 RX_MSDU_END_10_FLOW_IDX_INVALID_OFFSET)), \ 348 RX_MSDU_END_10_FLOW_IDX_INVALID_MASK, \ 349 RX_MSDU_END_10_FLOW_IDX_INVALID_LSB)) 350 351 #define HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(_rx_msdu_end) \ 352 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 353 RX_MSDU_END_10_FLOW_IDX_TIMEOUT_OFFSET)), \ 354 RX_MSDU_END_10_FLOW_IDX_TIMEOUT_MASK, \ 355 RX_MSDU_END_10_FLOW_IDX_TIMEOUT_LSB)) 356 357 #define HAL_RX_MSDU_END_FSE_METADATA_GET(_rx_msdu_end) \ 358 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 359 RX_MSDU_END_13_FSE_METADATA_OFFSET)), \ 360 RX_MSDU_END_13_FSE_METADATA_MASK, \ 361 RX_MSDU_END_13_FSE_METADATA_LSB)) 362 363 #define HAL_RX_MSDU_END_CCE_METADATA_GET(_rx_msdu_end) \ 364 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 365 RX_MSDU_END_14_CCE_METADATA_OFFSET)), \ 366 RX_MSDU_END_14_CCE_METADATA_MASK, \ 367 RX_MSDU_END_14_CCE_METADATA_LSB)) 368 369 #define HAL_RX_TLV_GET_TCP_CHKSUM(buf) \ 370 (_HAL_MS( \ 371 (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ 372 msdu_end_tlv.rx_msdu_end), \ 373 RX_MSDU_END_10_TCP_UDP_CHKSUM_OFFSET)), \ 374 RX_MSDU_END_10_TCP_UDP_CHKSUM_MASK, \ 375 RX_MSDU_END_10_TCP_UDP_CHKSUM_LSB)) 376 377 #define HAL_RX_MSDU_END_DA_IDX_GET(_rx_msdu_end) \ 378 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 379 RX_MSDU_END_11_DA_IDX_OR_SW_PEER_ID_OFFSET)), \ 380 RX_MSDU_END_11_DA_IDX_OR_SW_PEER_ID_MASK, \ 381 RX_MSDU_END_11_DA_IDX_OR_SW_PEER_ID_LSB)) 382 383 #define HAL_RX_TLV_GET_FLOW_AGGR_CONT(buf) \ 384 (_HAL_MS( \ 385 (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ 386 msdu_end_tlv.rx_msdu_end), \ 387 RX_MSDU_END_17_FLOW_AGGREGATION_CONTINUATION_OFFSET)), \ 388 RX_MSDU_END_17_FLOW_AGGREGATION_CONTINUATION_MASK, \ 389 RX_MSDU_END_17_FLOW_AGGREGATION_CONTINUATION_LSB)) 390 391 #define HAL_RX_TLV_GET_FLOW_AGGR_COUNT(buf) \ 392 (_HAL_MS( \ 393 (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ 394 msdu_end_tlv.rx_msdu_end), \ 395 RX_MSDU_END_17_AGGREGATION_COUNT_OFFSET)), \ 396 RX_MSDU_END_17_AGGREGATION_COUNT_MASK, \ 397 RX_MSDU_END_17_AGGREGATION_COUNT_LSB)) 398 399 #define HAL_RX_TLV_GET_FISA_TIMEOUT(buf) \ 400 (_HAL_MS( \ 401 (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ 402 msdu_end_tlv.rx_msdu_end), \ 403 RX_MSDU_END_17_FISA_TIMEOUT_OFFSET)), \ 404 RX_MSDU_END_17_FISA_TIMEOUT_MASK, \ 405 RX_MSDU_END_17_FISA_TIMEOUT_LSB)) 406 407 #define HAL_RX_TLV_GET_FISA_CUMULATIVE_L4_CHECKSUM(buf) \ 408 (_HAL_MS( \ 409 (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ 410 msdu_end_tlv.rx_msdu_end), \ 411 RX_MSDU_END_18_CUMULATIVE_L4_CHECKSUM_OFFSET)), \ 412 RX_MSDU_END_18_CUMULATIVE_L4_CHECKSUM_MASK, \ 413 RX_MSDU_END_18_CUMULATIVE_L4_CHECKSUM_LSB)) 414 415 #define HAL_RX_TLV_GET_FISA_CUMULATIVE_IP_LENGTH(buf) \ 416 (_HAL_MS( \ 417 (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ 418 msdu_end_tlv.rx_msdu_end), \ 419 RX_MSDU_END_18_CUMULATIVE_IP_LENGTH_OFFSET)), \ 420 RX_MSDU_END_18_CUMULATIVE_IP_LENGTH_MASK, \ 421 RX_MSDU_END_18_CUMULATIVE_IP_LENGTH_LSB)) 422 423 #if defined(QCA_WIFI_QCA6490) && defined(WLAN_CFR_ENABLE) && \ 424 defined(WLAN_ENH_CFR_ENABLE) 425 static inline 426 void hal_rx_get_bb_info_6490(void *rx_tlv, 427 void *ppdu_info_hdl) 428 { 429 struct hal_rx_ppdu_info *ppdu_info = ppdu_info_hdl; 430 431 ppdu_info->cfr_info.bb_captured_channel = 432 HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_3, BB_CAPTURED_CHANNEL); 433 434 ppdu_info->cfr_info.bb_captured_timeout = 435 HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_3, BB_CAPTURED_TIMEOUT); 436 437 ppdu_info->cfr_info.bb_captured_reason = 438 HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_3, BB_CAPTURED_REASON); 439 } 440 441 static inline 442 void hal_rx_get_rtt_info_6490(void *rx_tlv, 443 void *ppdu_info_hdl) 444 { 445 struct hal_rx_ppdu_info *ppdu_info = ppdu_info_hdl; 446 447 ppdu_info->cfr_info.rx_location_info_valid = 448 HAL_RX_GET(rx_tlv, PHYRX_PKT_END_13_RX_PKT_END_DETAILS, 449 RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID); 450 451 ppdu_info->cfr_info.rtt_che_buffer_pointer_low32 = 452 HAL_RX_GET(rx_tlv, 453 PHYRX_PKT_END_12_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS, 454 RTT_CHE_BUFFER_POINTER_LOW32); 455 456 ppdu_info->cfr_info.rtt_che_buffer_pointer_high8 = 457 HAL_RX_GET(rx_tlv, 458 PHYRX_PKT_END_11_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS, 459 RTT_CHE_BUFFER_POINTER_HIGH8); 460 461 ppdu_info->cfr_info.chan_capture_status = 462 HAL_RX_GET(rx_tlv, 463 PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS, 464 RESERVED_8); 465 } 466 #endif 467 #endif 468