1 /* 2 * Copyright (c) 2019-2020 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #include "qdf_types.h" 20 #include "qdf_util.h" 21 #include "qdf_types.h" 22 #include "qdf_lock.h" 23 #include "qdf_mem.h" 24 #include "qdf_nbuf.h" 25 #include "hal_hw_headers.h" 26 #include "hal_internal.h" 27 #include "hal_api.h" 28 #include "target_type.h" 29 #include "wcss_version.h" 30 #include "qdf_module.h" 31 32 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_OFFSET \ 33 RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_OFFSET 34 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_MASK \ 35 RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_MASK 36 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_LSB \ 37 RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_LSB 38 #define UNIFIED_PHYRX_HT_SIG_0_HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS_OFFSET \ 39 PHYRX_L_SIG_B_0_PHYRX_L_SIG_B_INFO_DETAILS_RATE_OFFSET 40 #define UNIFIED_PHYRX_L_SIG_B_0_L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS_OFFSET \ 41 PHYRX_L_SIG_B_0_PHYRX_L_SIG_B_INFO_DETAILS_RATE_OFFSET 42 #define UNIFIED_PHYRX_L_SIG_A_0_L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS_OFFSET \ 43 PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_RATE_OFFSET 44 #define UNIFIED_PHYRX_VHT_SIG_A_0_VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS_OFFSET \ 45 PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_OFFSET 46 #define UNIFIED_PHYRX_HE_SIG_A_SU_0_HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS_OFFSET \ 47 PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_OFFSET 48 #define UNIFIED_PHYRX_HE_SIG_A_MU_DL_0_HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_OFFSET \ 49 PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_OFFSET 50 #define UNIFIED_PHYRX_HE_SIG_B1_MU_0_HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_OFFSET \ 51 PHYRX_HE_SIG_B1_MU_0_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_OFFSET 52 #define UNIFIED_PHYRX_HE_SIG_B2_MU_0_HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_OFFSET \ 53 PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_OFFSET 54 #define UNIFIED_PHYRX_HE_SIG_B2_OFDMA_0_HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_OFFSET \ 55 PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_OFFSET 56 57 #define UNIFIED_PHYRX_RSSI_LEGACY_3_RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS_OFFSET \ 58 PHYRX_RSSI_LEGACY_3_RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS_OFFSET 59 #define UNIFIED_PHYRX_RSSI_LEGACY_19_RECEIVE_RSSI_INFO_PREAMBLE_RSSI_INFO_DETAILS_OFFSET \ 60 PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 61 #define UNIFIED_RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET \ 62 RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 63 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 64 RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET 65 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ 66 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET 67 #define UNIFIED_RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 68 RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET 69 #define UNIFIED_REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 70 REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET 71 #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC \ 72 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER 73 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ 74 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET 75 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 76 RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET 77 #define UNIFIED_TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 78 TCL_DATA_CMD_0_BUF_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 79 #define UNIFIED_TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 80 TCL_DATA_CMD_1_BUF_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 81 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET \ 82 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET 83 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB \ 84 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB 85 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK \ 86 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK 87 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB \ 88 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB 89 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK \ 90 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK 91 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB \ 92 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB 93 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK \ 94 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK 95 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB \ 96 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB 97 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK \ 98 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK 99 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB \ 100 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB 101 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK \ 102 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK 103 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_MASK \ 104 WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MASK 105 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_OFFSET \ 106 WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_OFFSET 107 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_LSB \ 108 WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_LSB 109 110 #include "hal_6490_tx.h" 111 #include "hal_6490_rx.h" 112 #include <hal_generic_api.h> 113 #include <hal_wbm.h> 114 115 /* 116 * hal_rx_msdu_start_nss_get_6490(): API to get the NSS 117 * Interval from rx_msdu_start 118 * 119 * @buf: pointer to the start of RX PKT TLV header 120 * Return: uint32_t(nss) 121 */ 122 static uint32_t 123 hal_rx_msdu_start_nss_get_6490(uint8_t *buf) 124 { 125 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 126 struct rx_msdu_start *msdu_start = 127 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 128 uint8_t mimo_ss_bitmap; 129 130 mimo_ss_bitmap = HAL_RX_MSDU_START_MIMO_SS_BITMAP(msdu_start); 131 132 return qdf_get_hweight8(mimo_ss_bitmap); 133 } 134 135 /** 136 * hal_rx_mon_hw_desc_get_mpdu_status_6490(): Retrieve MPDU status 137 * 138 * @ hw_desc_addr: Start address of Rx HW TLVs 139 * @ rs: Status for monitor mode 140 * 141 * Return: void 142 */ 143 static void hal_rx_mon_hw_desc_get_mpdu_status_6490(void *hw_desc_addr, 144 struct mon_rx_status *rs) 145 { 146 struct rx_msdu_start *rx_msdu_start; 147 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr; 148 uint32_t reg_value; 149 const uint32_t sgi_hw_to_cdp[] = { 150 CDP_SGI_0_8_US, 151 CDP_SGI_0_4_US, 152 CDP_SGI_1_6_US, 153 CDP_SGI_3_2_US, 154 }; 155 156 rx_msdu_start = &rx_desc->msdu_start_tlv.rx_msdu_start; 157 158 HAL_RX_GET_MSDU_AGGREGATION(rx_desc, rs); 159 160 rs->ant_signal_db = HAL_RX_GET(rx_msdu_start, 161 RX_MSDU_START_5, USER_RSSI); 162 rs->is_stbc = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, STBC); 163 164 reg_value = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, SGI); 165 rs->sgi = sgi_hw_to_cdp[reg_value]; 166 167 reg_value = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, RECEPTION_TYPE); 168 rs->beamformed = (reg_value == HAL_RX_RECEPTION_TYPE_MU_MIMO) ? 1 : 0; 169 /* TODO: rs->beamformed should be set for SU beamforming also */ 170 } 171 172 #define LINK_DESC_SIZE (NUM_OF_DWORDS_RX_MSDU_LINK << 2) 173 174 static uint32_t hal_get_link_desc_size_6490(void) 175 { 176 return LINK_DESC_SIZE; 177 } 178 179 /* 180 * hal_rx_get_tlv_6490(): API to get the tlv 181 * 182 * @rx_tlv: TLV data extracted from the rx packet 183 * Return: uint8_t 184 */ 185 static uint8_t hal_rx_get_tlv_6490(void *rx_tlv) 186 { 187 return HAL_RX_GET(rx_tlv, PHYRX_RSSI_LEGACY_0, RECEIVE_BANDWIDTH); 188 } 189 190 /** 191 * hal_rx_proc_phyrx_other_receive_info_tlv_6490() 192 * - process other receive info TLV 193 * @rx_tlv_hdr: pointer to TLV header 194 * @ppdu_info: pointer to ppdu_info 195 * 196 * Return: None 197 */ 198 static 199 void hal_rx_proc_phyrx_other_receive_info_tlv_6490(void *rx_tlv_hdr, 200 void *ppdu_info_handle) 201 { 202 uint32_t tlv_tag, tlv_len; 203 uint32_t temp_len, other_tlv_len, other_tlv_tag; 204 void *rx_tlv = (uint8_t *)rx_tlv_hdr + HAL_RX_TLV32_HDR_SIZE; 205 void *other_tlv_hdr = NULL; 206 void *other_tlv = NULL; 207 208 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv_hdr); 209 tlv_len = HAL_RX_GET_USER_TLV32_LEN(rx_tlv_hdr); 210 temp_len = 0; 211 212 other_tlv_hdr = rx_tlv + HAL_RX_TLV32_HDR_SIZE; 213 214 other_tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(other_tlv_hdr); 215 other_tlv_len = HAL_RX_GET_USER_TLV32_LEN(other_tlv_hdr); 216 temp_len += other_tlv_len; 217 other_tlv = other_tlv_hdr + HAL_RX_TLV32_HDR_SIZE; 218 219 switch (other_tlv_tag) { 220 default: 221 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR, 222 "%s unhandled TLV type: %d, TLV len:%d", 223 __func__, other_tlv_tag, other_tlv_len); 224 break; 225 } 226 } 227 228 /** 229 * hal_rx_dump_msdu_start_tlv_6490() : dump RX msdu_start TLV in structured 230 * human readable format. 231 * @ msdu_start: pointer the msdu_start TLV in pkt. 232 * @ dbg_level: log level. 233 * 234 * Return: void 235 */ 236 static void hal_rx_dump_msdu_start_tlv_6490(void *msdustart, uint8_t dbg_level) 237 { 238 struct rx_msdu_start *msdu_start = (struct rx_msdu_start *)msdustart; 239 240 hal_verbose_debug( 241 "rx_msdu_start tlv (1/2) - " 242 "rxpcu_mpdu_filter_in_category: %x " 243 "sw_frame_group_id: %x " 244 "phy_ppdu_id: %x " 245 "msdu_length: %x " 246 "ipsec_esp: %x " 247 "l3_offset: %x " 248 "ipsec_ah: %x " 249 "l4_offset: %x " 250 "msdu_number: %x " 251 "decap_format: %x " 252 "ipv4_proto: %x " 253 "ipv6_proto: %x " 254 "tcp_proto: %x " 255 "udp_proto: %x " 256 "ip_frag: %x " 257 "tcp_only_ack: %x " 258 "da_is_bcast_mcast: %x " 259 "ip4_protocol_ip6_next_header: %x " 260 "toeplitz_hash_2_or_4: %x " 261 "flow_id_toeplitz: %x " 262 "user_rssi: %x " 263 "pkt_type: %x " 264 "stbc: %x " 265 "sgi: %x " 266 "rate_mcs: %x " 267 "receive_bandwidth: %x " 268 "reception_type: %x " 269 "ppdu_start_timestamp: %u ", 270 msdu_start->rxpcu_mpdu_filter_in_category, 271 msdu_start->sw_frame_group_id, 272 msdu_start->phy_ppdu_id, 273 msdu_start->msdu_length, 274 msdu_start->ipsec_esp, 275 msdu_start->l3_offset, 276 msdu_start->ipsec_ah, 277 msdu_start->l4_offset, 278 msdu_start->msdu_number, 279 msdu_start->decap_format, 280 msdu_start->ipv4_proto, 281 msdu_start->ipv6_proto, 282 msdu_start->tcp_proto, 283 msdu_start->udp_proto, 284 msdu_start->ip_frag, 285 msdu_start->tcp_only_ack, 286 msdu_start->da_is_bcast_mcast, 287 msdu_start->ip4_protocol_ip6_next_header, 288 msdu_start->toeplitz_hash_2_or_4, 289 msdu_start->flow_id_toeplitz, 290 msdu_start->user_rssi, 291 msdu_start->pkt_type, 292 msdu_start->stbc, 293 msdu_start->sgi, 294 msdu_start->rate_mcs, 295 msdu_start->receive_bandwidth, 296 msdu_start->reception_type, 297 msdu_start->ppdu_start_timestamp); 298 299 hal_verbose_debug( 300 "rx_msdu_start tlv (2/2) - " 301 "sw_phy_meta_data: %x ", 302 msdu_start->sw_phy_meta_data); 303 } 304 305 /** 306 * hal_rx_dump_msdu_end_tlv_6490: dump RX msdu_end TLV in structured 307 * human readable format. 308 * @ msdu_end: pointer the msdu_end TLV in pkt. 309 * @ dbg_level: log level. 310 * 311 * Return: void 312 */ 313 static void hal_rx_dump_msdu_end_tlv_6490(void *msduend, 314 uint8_t dbg_level) 315 { 316 struct rx_msdu_end *msdu_end = (struct rx_msdu_end *)msduend; 317 318 QDF_TRACE(QDF_MODULE_ID_DP, dbg_level, 319 "rx_msdu_end tlv (1/2) - " 320 "rxpcu_mpdu_filter_in_category: %x " 321 "sw_frame_group_id: %x " 322 "phy_ppdu_id: %x " 323 "ip_hdr_chksum: %x " 324 "tcp_udp_chksum: %x " 325 "key_id_octet: %x " 326 "cce_super_rule: %x " 327 "cce_classify_not_done_truncat: %x " 328 "cce_classify_not_done_cce_dis: %x " 329 "ext_wapi_pn_63_48: %x " 330 "ext_wapi_pn_95_64: %x " 331 "ext_wapi_pn_127_96: %x " 332 "reported_mpdu_length: %x " 333 "first_msdu: %x " 334 "last_msdu: %x " 335 "sa_idx_timeout: %x " 336 "da_idx_timeout: %x " 337 "msdu_limit_error: %x " 338 "flow_idx_timeout: %x " 339 "flow_idx_invalid: %x " 340 "wifi_parser_error: %x " 341 "amsdu_parser_error: %x", 342 msdu_end->rxpcu_mpdu_filter_in_category, 343 msdu_end->sw_frame_group_id, 344 msdu_end->phy_ppdu_id, 345 msdu_end->ip_hdr_chksum, 346 msdu_end->tcp_udp_chksum, 347 msdu_end->key_id_octet, 348 msdu_end->cce_super_rule, 349 msdu_end->cce_classify_not_done_truncate, 350 msdu_end->cce_classify_not_done_cce_dis, 351 msdu_end->ext_wapi_pn_63_48, 352 msdu_end->ext_wapi_pn_95_64, 353 msdu_end->ext_wapi_pn_127_96, 354 msdu_end->reported_mpdu_length, 355 msdu_end->first_msdu, 356 msdu_end->last_msdu, 357 msdu_end->sa_idx_timeout, 358 msdu_end->da_idx_timeout, 359 msdu_end->msdu_limit_error, 360 msdu_end->flow_idx_timeout, 361 msdu_end->flow_idx_invalid, 362 msdu_end->wifi_parser_error, 363 msdu_end->amsdu_parser_error); 364 365 QDF_TRACE(QDF_MODULE_ID_DP, dbg_level, 366 "rx_msdu_end tlv (2/2)- " 367 "sa_is_valid: %x " 368 "da_is_valid: %x " 369 "da_is_mcbc: %x " 370 "l3_header_padding: %x " 371 "ipv6_options_crc: %x " 372 "tcp_seq_number: %x " 373 "tcp_ack_number: %x " 374 "tcp_flag: %x " 375 "lro_eligible: %x " 376 "window_size: %x " 377 "da_offset: %x " 378 "sa_offset: %x " 379 "da_offset_valid: %x " 380 "sa_offset_valid: %x " 381 "rule_indication_31_0: %x " 382 "rule_indication_63_32: %x " 383 "sa_idx: %x " 384 "da_idx: %x " 385 "msdu_drop: %x " 386 "reo_destination_indication: %x " 387 "flow_idx: %x " 388 "fse_metadata: %x " 389 "cce_metadata: %x " 390 "sa_sw_peer_id: %x ", 391 msdu_end->sa_is_valid, 392 msdu_end->da_is_valid, 393 msdu_end->da_is_mcbc, 394 msdu_end->l3_header_padding, 395 msdu_end->ipv6_options_crc, 396 msdu_end->tcp_seq_number, 397 msdu_end->tcp_ack_number, 398 msdu_end->tcp_flag, 399 msdu_end->lro_eligible, 400 msdu_end->window_size, 401 msdu_end->da_offset, 402 msdu_end->sa_offset, 403 msdu_end->da_offset_valid, 404 msdu_end->sa_offset_valid, 405 msdu_end->rule_indication_31_0, 406 msdu_end->rule_indication_63_32, 407 msdu_end->sa_idx, 408 msdu_end->da_idx_or_sw_peer_id, 409 msdu_end->msdu_drop, 410 msdu_end->reo_destination_indication, 411 msdu_end->flow_idx, 412 msdu_end->fse_metadata, 413 msdu_end->cce_metadata, 414 msdu_end->sa_sw_peer_id); 415 } 416 417 /* 418 * Get tid from RX_MPDU_START 419 */ 420 #define HAL_RX_MPDU_INFO_TID_GET(_rx_mpdu_info) \ 421 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_info), \ 422 RX_MPDU_INFO_7_TID_OFFSET)), \ 423 RX_MPDU_INFO_7_TID_MASK, \ 424 RX_MPDU_INFO_7_TID_LSB)) 425 426 static uint32_t hal_rx_mpdu_start_tid_get_6490(uint8_t *buf) 427 { 428 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 429 struct rx_mpdu_start *mpdu_start = 430 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 431 uint32_t tid; 432 433 tid = HAL_RX_MPDU_INFO_TID_GET(&mpdu_start->rx_mpdu_info_details); 434 435 return tid; 436 } 437 438 #define HAL_RX_MSDU_START_RECEPTION_TYPE_GET(_rx_msdu_start) \ 439 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start), \ 440 RX_MSDU_START_5_RECEPTION_TYPE_OFFSET)), \ 441 RX_MSDU_START_5_RECEPTION_TYPE_MASK, \ 442 RX_MSDU_START_5_RECEPTION_TYPE_LSB)) 443 444 /* 445 * hal_rx_msdu_start_reception_type_get(): API to get the reception type 446 * Interval from rx_msdu_start 447 * 448 * @buf: pointer to the start of RX PKT TLV header 449 * Return: uint32_t(reception_type) 450 */ 451 static 452 uint32_t hal_rx_msdu_start_reception_type_get_6490(uint8_t *buf) 453 { 454 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 455 struct rx_msdu_start *msdu_start = 456 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 457 uint32_t reception_type; 458 459 reception_type = HAL_RX_MSDU_START_RECEPTION_TYPE_GET(msdu_start); 460 461 return reception_type; 462 } 463 464 /** 465 * hal_rx_msdu_end_da_idx_get_6490: API to get da_idx 466 * from rx_msdu_end TLV 467 * 468 * @ buf: pointer to the start of RX PKT TLV headers 469 * Return: da index 470 */ 471 static uint16_t hal_rx_msdu_end_da_idx_get_6490(uint8_t *buf) 472 { 473 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 474 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 475 uint16_t da_idx; 476 477 da_idx = HAL_RX_MSDU_END_DA_IDX_GET(msdu_end); 478 479 return da_idx; 480 } 481 /** 482 * hal_rx_get_rx_fragment_number_6490(): Function to retrieve rx fragment number 483 * 484 * @nbuf: Network buffer 485 * Returns: rx fragment number 486 */ 487 static 488 uint8_t hal_rx_get_rx_fragment_number_6490(uint8_t *buf) 489 { 490 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 491 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 492 493 /* Return first 4 bits as fragment number */ 494 return (HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info) & 495 DOT11_SEQ_FRAG_MASK); 496 } 497 498 /** 499 * hal_rx_msdu_end_da_is_mcbc_get_6490(): API to check if pkt is MCBC 500 * from rx_msdu_end TLV 501 * 502 * @ buf: pointer to the start of RX PKT TLV headers 503 * Return: da_is_mcbc 504 */ 505 static uint8_t 506 hal_rx_msdu_end_da_is_mcbc_get_6490(uint8_t *buf) 507 { 508 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 509 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 510 511 return HAL_RX_MSDU_END_DA_IS_MCBC_GET(msdu_end); 512 } 513 514 /** 515 * hal_rx_msdu_end_sa_is_valid_get_6490(): API to get_6490 the 516 * sa_is_valid bit from rx_msdu_end TLV 517 * 518 * @ buf: pointer to the start of RX PKT TLV headers 519 * Return: sa_is_valid bit 520 */ 521 static uint8_t 522 hal_rx_msdu_end_sa_is_valid_get_6490(uint8_t *buf) 523 { 524 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 525 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 526 uint8_t sa_is_valid; 527 528 sa_is_valid = HAL_RX_MSDU_END_SA_IS_VALID_GET(msdu_end); 529 530 return sa_is_valid; 531 } 532 533 /** 534 * hal_rx_msdu_end_sa_idx_get_6490(): API to get_6490 the 535 * sa_idx from rx_msdu_end TLV 536 * 537 * @ buf: pointer to the start of RX PKT TLV headers 538 * Return: sa_idx (SA AST index) 539 */ 540 static 541 uint16_t hal_rx_msdu_end_sa_idx_get_6490(uint8_t *buf) 542 { 543 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 544 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 545 uint16_t sa_idx; 546 547 sa_idx = HAL_RX_MSDU_END_SA_IDX_GET(msdu_end); 548 549 return sa_idx; 550 } 551 552 /** 553 * hal_rx_desc_is_first_msdu_6490() - Check if first msdu 554 * 555 * @hal_soc_hdl: hal_soc handle 556 * @hw_desc_addr: hardware descriptor address 557 * 558 * Return: 0 - success/ non-zero failure 559 */ 560 static uint32_t hal_rx_desc_is_first_msdu_6490(void *hw_desc_addr) 561 { 562 struct rx_pkt_tlvs *rx_tlvs = (struct rx_pkt_tlvs *)hw_desc_addr; 563 struct rx_msdu_end *msdu_end = &rx_tlvs->msdu_end_tlv.rx_msdu_end; 564 565 return HAL_RX_GET(msdu_end, RX_MSDU_END_10, FIRST_MSDU); 566 } 567 568 /** 569 * hal_rx_msdu_end_l3_hdr_padding_get_6490(): API to get_6490 the 570 * l3_header padding from rx_msdu_end TLV 571 * 572 * @ buf: pointer to the start of RX PKT TLV headers 573 * Return: number of l3 header padding bytes 574 */ 575 static uint32_t hal_rx_msdu_end_l3_hdr_padding_get_6490(uint8_t *buf) 576 { 577 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 578 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 579 uint32_t l3_header_padding; 580 581 l3_header_padding = HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(msdu_end); 582 583 return l3_header_padding; 584 } 585 586 /* 587 * @ hal_rx_encryption_info_valid_6490: Returns encryption type. 588 * 589 * @ buf: rx_tlv_hdr of the received packet 590 * @ Return: encryption type 591 */ 592 static uint32_t hal_rx_encryption_info_valid_6490(uint8_t *buf) 593 { 594 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 595 struct rx_mpdu_start *mpdu_start = 596 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 597 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 598 uint32_t encryption_info = HAL_RX_MPDU_ENCRYPTION_INFO_VALID(mpdu_info); 599 600 return encryption_info; 601 } 602 603 /* 604 * @ hal_rx_print_pn_6490: Prints the PN of rx packet. 605 * 606 * @ buf: rx_tlv_hdr of the received packet 607 * @ Return: void 608 */ 609 static void hal_rx_print_pn_6490(uint8_t *buf) 610 { 611 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 612 struct rx_mpdu_start *mpdu_start = 613 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 614 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 615 616 uint32_t pn_31_0 = HAL_RX_MPDU_PN_31_0_GET(mpdu_info); 617 uint32_t pn_63_32 = HAL_RX_MPDU_PN_63_32_GET(mpdu_info); 618 uint32_t pn_95_64 = HAL_RX_MPDU_PN_95_64_GET(mpdu_info); 619 uint32_t pn_127_96 = HAL_RX_MPDU_PN_127_96_GET(mpdu_info); 620 621 hal_debug("PN number pn_127_96 0x%x pn_95_64 0x%x pn_63_32 0x%x pn_31_0 0x%x ", 622 pn_127_96, pn_95_64, pn_63_32, pn_31_0); 623 } 624 625 /** 626 * hal_rx_msdu_end_first_msdu_get_6490: API to get first msdu status 627 * from rx_msdu_end TLV 628 * 629 * @ buf: pointer to the start of RX PKT TLV headers 630 * Return: first_msdu 631 */ 632 static uint8_t hal_rx_msdu_end_first_msdu_get_6490(uint8_t *buf) 633 { 634 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 635 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 636 uint8_t first_msdu; 637 638 first_msdu = HAL_RX_MSDU_END_FIRST_MSDU_GET(msdu_end); 639 640 return first_msdu; 641 } 642 643 /** 644 * hal_rx_msdu_end_da_is_valid_get_6490: API to check if da is valid 645 * from rx_msdu_end TLV 646 * 647 * @ buf: pointer to the start of RX PKT TLV headers 648 * Return: da_is_valid 649 */ 650 static uint8_t hal_rx_msdu_end_da_is_valid_get_6490(uint8_t *buf) 651 { 652 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 653 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 654 uint8_t da_is_valid; 655 656 da_is_valid = HAL_RX_MSDU_END_DA_IS_VALID_GET(msdu_end); 657 658 return da_is_valid; 659 } 660 661 /** 662 * hal_rx_msdu_end_last_msdu_get_6490: API to get last msdu status 663 * from rx_msdu_end TLV 664 * 665 * @ buf: pointer to the start of RX PKT TLV headers 666 * Return: last_msdu 667 */ 668 static uint8_t hal_rx_msdu_end_last_msdu_get_6490(uint8_t *buf) 669 { 670 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 671 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 672 uint8_t last_msdu; 673 674 last_msdu = HAL_RX_MSDU_END_LAST_MSDU_GET(msdu_end); 675 676 return last_msdu; 677 } 678 679 /* 680 * hal_rx_get_mpdu_mac_ad4_valid_6490(): Retrieves if mpdu 4th addr is valid 681 * 682 * @nbuf: Network buffer 683 * Returns: value of mpdu 4th address valid field 684 */ 685 static bool hal_rx_get_mpdu_mac_ad4_valid_6490(uint8_t *buf) 686 { 687 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 688 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 689 bool ad4_valid = 0; 690 691 ad4_valid = HAL_RX_MPDU_GET_MAC_AD4_VALID(rx_mpdu_info); 692 693 return ad4_valid; 694 } 695 696 /** 697 * hal_rx_mpdu_start_sw_peer_id_get_6490: Retrieve sw peer_id 698 * @buf: network buffer 699 * 700 * Return: sw peer_id 701 */ 702 static uint32_t hal_rx_mpdu_start_sw_peer_id_get_6490(uint8_t *buf) 703 { 704 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 705 struct rx_mpdu_start *mpdu_start = 706 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 707 708 return HAL_RX_MPDU_INFO_SW_PEER_ID_GET( 709 &mpdu_start->rx_mpdu_info_details); 710 } 711 712 /** 713 * hal_rx_mpdu_get_to_ds_6490(): API to get the tods info 714 * from rx_mpdu_start 715 * 716 * @buf: pointer to the start of RX PKT TLV header 717 * Return: uint32_t(to_ds) 718 */ 719 static uint32_t hal_rx_mpdu_get_to_ds_6490(uint8_t *buf) 720 { 721 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 722 struct rx_mpdu_start *mpdu_start = 723 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 724 725 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 726 727 return HAL_RX_MPDU_GET_TODS(mpdu_info); 728 } 729 730 /* 731 * hal_rx_mpdu_get_fr_ds_6490(): API to get the from ds info 732 * from rx_mpdu_start 733 * 734 * @buf: pointer to the start of RX PKT TLV header 735 * Return: uint32_t(fr_ds) 736 */ 737 static uint32_t hal_rx_mpdu_get_fr_ds_6490(uint8_t *buf) 738 { 739 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 740 struct rx_mpdu_start *mpdu_start = 741 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 742 743 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 744 745 return HAL_RX_MPDU_GET_FROMDS(mpdu_info); 746 } 747 748 /* 749 * hal_rx_get_mpdu_frame_control_valid_6490(): Retrieves mpdu 750 * frame control valid 751 * 752 * @nbuf: Network buffer 753 * Returns: value of frame control valid field 754 */ 755 static uint8_t hal_rx_get_mpdu_frame_control_valid_6490(uint8_t *buf) 756 { 757 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 758 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 759 760 return HAL_RX_MPDU_GET_FRAME_CONTROL_VALID(rx_mpdu_info); 761 } 762 763 /* 764 * hal_rx_mpdu_get_addr1_6490(): API to check get address1 of the mpdu 765 * 766 * @buf: pointer to the start of RX PKT TLV headera 767 * @mac_addr: pointer to mac address 768 * Return: success/failure 769 */ 770 static QDF_STATUS hal_rx_mpdu_get_addr1_6490(uint8_t *buf, uint8_t *mac_addr) 771 { 772 struct __attribute__((__packed__)) hal_addr1 { 773 uint32_t ad1_31_0; 774 uint16_t ad1_47_32; 775 }; 776 777 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 778 struct rx_mpdu_start *mpdu_start = 779 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 780 781 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 782 struct hal_addr1 *addr = (struct hal_addr1 *)mac_addr; 783 uint32_t mac_addr_ad1_valid; 784 785 mac_addr_ad1_valid = HAL_RX_MPDU_MAC_ADDR_AD1_VALID_GET(mpdu_info); 786 787 if (mac_addr_ad1_valid) { 788 addr->ad1_31_0 = HAL_RX_MPDU_AD1_31_0_GET(mpdu_info); 789 addr->ad1_47_32 = HAL_RX_MPDU_AD1_47_32_GET(mpdu_info); 790 return QDF_STATUS_SUCCESS; 791 } 792 793 return QDF_STATUS_E_FAILURE; 794 } 795 796 /* 797 * hal_rx_mpdu_get_addr2_6490(): API to check get address2 of the mpdu 798 * in the packet 799 * 800 * @buf: pointer to the start of RX PKT TLV header 801 * @mac_addr: pointer to mac address 802 * Return: success/failure 803 */ 804 static QDF_STATUS hal_rx_mpdu_get_addr2_6490(uint8_t *buf, 805 uint8_t *mac_addr) 806 { 807 struct __attribute__((__packed__)) hal_addr2 { 808 uint16_t ad2_15_0; 809 uint32_t ad2_47_16; 810 }; 811 812 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 813 struct rx_mpdu_start *mpdu_start = 814 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 815 816 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 817 struct hal_addr2 *addr = (struct hal_addr2 *)mac_addr; 818 uint32_t mac_addr_ad2_valid; 819 820 mac_addr_ad2_valid = HAL_RX_MPDU_MAC_ADDR_AD2_VALID_GET(mpdu_info); 821 822 if (mac_addr_ad2_valid) { 823 addr->ad2_15_0 = HAL_RX_MPDU_AD2_15_0_GET(mpdu_info); 824 addr->ad2_47_16 = HAL_RX_MPDU_AD2_47_16_GET(mpdu_info); 825 return QDF_STATUS_SUCCESS; 826 } 827 828 return QDF_STATUS_E_FAILURE; 829 } 830 831 /* 832 * hal_rx_mpdu_get_addr3_6490(): API to get address3 of the mpdu 833 * in the packet 834 * 835 * @buf: pointer to the start of RX PKT TLV header 836 * @mac_addr: pointer to mac address 837 * Return: success/failure 838 */ 839 static QDF_STATUS hal_rx_mpdu_get_addr3_6490(uint8_t *buf, uint8_t *mac_addr) 840 { 841 struct __attribute__((__packed__)) hal_addr3 { 842 uint32_t ad3_31_0; 843 uint16_t ad3_47_32; 844 }; 845 846 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 847 struct rx_mpdu_start *mpdu_start = 848 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 849 850 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 851 struct hal_addr3 *addr = (struct hal_addr3 *)mac_addr; 852 uint32_t mac_addr_ad3_valid; 853 854 mac_addr_ad3_valid = HAL_RX_MPDU_MAC_ADDR_AD3_VALID_GET(mpdu_info); 855 856 if (mac_addr_ad3_valid) { 857 addr->ad3_31_0 = HAL_RX_MPDU_AD3_31_0_GET(mpdu_info); 858 addr->ad3_47_32 = HAL_RX_MPDU_AD3_47_32_GET(mpdu_info); 859 return QDF_STATUS_SUCCESS; 860 } 861 862 return QDF_STATUS_E_FAILURE; 863 } 864 865 /* 866 * hal_rx_mpdu_get_addr4_6490(): API to get address4 of the mpdu 867 * in the packet 868 * 869 * @buf: pointer to the start of RX PKT TLV header 870 * @mac_addr: pointer to mac address 871 * Return: success/failure 872 */ 873 static QDF_STATUS hal_rx_mpdu_get_addr4_6490(uint8_t *buf, uint8_t *mac_addr) 874 { 875 struct __attribute__((__packed__)) hal_addr4 { 876 uint32_t ad4_31_0; 877 uint16_t ad4_47_32; 878 }; 879 880 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 881 struct rx_mpdu_start *mpdu_start = 882 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 883 884 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 885 struct hal_addr4 *addr = (struct hal_addr4 *)mac_addr; 886 uint32_t mac_addr_ad4_valid; 887 888 mac_addr_ad4_valid = HAL_RX_MPDU_MAC_ADDR_AD4_VALID_GET(mpdu_info); 889 890 if (mac_addr_ad4_valid) { 891 addr->ad4_31_0 = HAL_RX_MPDU_AD4_31_0_GET(mpdu_info); 892 addr->ad4_47_32 = HAL_RX_MPDU_AD4_47_32_GET(mpdu_info); 893 return QDF_STATUS_SUCCESS; 894 } 895 896 return QDF_STATUS_E_FAILURE; 897 } 898 899 /* 900 * hal_rx_get_mpdu_sequence_control_valid_6490(): Get mpdu 901 * sequence control valid 902 * 903 * @nbuf: Network buffer 904 * Returns: value of sequence control valid field 905 */ 906 static uint8_t hal_rx_get_mpdu_sequence_control_valid_6490(uint8_t *buf) 907 { 908 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 909 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 910 911 return HAL_RX_MPDU_GET_SEQUENCE_CONTROL_VALID(rx_mpdu_info); 912 } 913 914 /** 915 * hal_rx_is_unicast_6490: check packet is unicast frame or not. 916 * 917 * @ buf: pointer to rx pkt TLV. 918 * 919 * Return: true on unicast. 920 */ 921 static bool hal_rx_is_unicast_6490(uint8_t *buf) 922 { 923 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 924 struct rx_mpdu_start *mpdu_start = 925 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 926 uint32_t grp_id; 927 uint8_t *rx_mpdu_info = (uint8_t *)&mpdu_start->rx_mpdu_info_details; 928 929 grp_id = (_HAL_MS((*_OFFSET_TO_WORD_PTR((rx_mpdu_info), 930 RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_OFFSET)), 931 RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_MASK, 932 RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_LSB)); 933 934 return (HAL_MPDU_SW_FRAME_GROUP_UNICAST_DATA == grp_id) ? true : false; 935 } 936 937 /** 938 * hal_rx_tid_get_6490: get tid based on qos control valid. 939 * @hal_soc_hdl: hal_soc handle 940 * @ buf: pointer to rx pkt TLV. 941 * 942 * Return: tid 943 */ 944 static uint32_t hal_rx_tid_get_6490(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 945 { 946 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 947 struct rx_mpdu_start *mpdu_start = 948 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 949 uint8_t *rx_mpdu_info = (uint8_t *)&mpdu_start->rx_mpdu_info_details; 950 uint8_t qos_control_valid = 951 (_HAL_MS((*_OFFSET_TO_WORD_PTR((rx_mpdu_info), 952 RX_MPDU_INFO_11_MPDU_QOS_CONTROL_VALID_OFFSET)), 953 RX_MPDU_INFO_11_MPDU_QOS_CONTROL_VALID_MASK, 954 RX_MPDU_INFO_11_MPDU_QOS_CONTROL_VALID_LSB)); 955 956 if (qos_control_valid) 957 return hal_rx_mpdu_start_tid_get_6490(buf); 958 959 return HAL_RX_NON_QOS_TID; 960 } 961 962 /** 963 * hal_rx_hw_desc_get_ppduid_get_6490(): retrieve ppdu id 964 * @hw_desc_addr: hw addr 965 * 966 * Return: ppdu id 967 */ 968 static uint32_t hal_rx_hw_desc_get_ppduid_get_6490(void *hw_desc_addr) 969 { 970 struct rx_mpdu_info *rx_mpdu_info; 971 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr; 972 973 rx_mpdu_info = 974 &rx_desc->mpdu_start_tlv.rx_mpdu_start.rx_mpdu_info_details; 975 976 return HAL_RX_GET(rx_mpdu_info, RX_MPDU_INFO_9, PHY_PPDU_ID); 977 } 978 979 /** 980 * hal_reo_status_get_header_6490 - Process reo desc info 981 * @d - Pointer to reo descriptior 982 * @b - tlv type info 983 * @h1 - Pointer to hal_reo_status_header where info to be stored 984 * 985 * Return - none. 986 * 987 */ 988 static void hal_reo_status_get_header_6490(uint32_t *d, int b, void *h1) 989 { 990 uint32_t val1 = 0; 991 struct hal_reo_status_header *h = 992 (struct hal_reo_status_header *)h1; 993 994 switch (b) { 995 case HAL_REO_QUEUE_STATS_STATUS_TLV: 996 val1 = d[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_0, 997 STATUS_HEADER_REO_STATUS_NUMBER)]; 998 break; 999 case HAL_REO_FLUSH_QUEUE_STATUS_TLV: 1000 val1 = d[HAL_OFFSET_DW(REO_FLUSH_QUEUE_STATUS_0, 1001 STATUS_HEADER_REO_STATUS_NUMBER)]; 1002 break; 1003 case HAL_REO_FLUSH_CACHE_STATUS_TLV: 1004 val1 = d[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_0, 1005 STATUS_HEADER_REO_STATUS_NUMBER)]; 1006 break; 1007 case HAL_REO_UNBLK_CACHE_STATUS_TLV: 1008 val1 = d[HAL_OFFSET_DW(REO_UNBLOCK_CACHE_STATUS_0, 1009 STATUS_HEADER_REO_STATUS_NUMBER)]; 1010 break; 1011 case HAL_REO_TIMOUT_LIST_STATUS_TLV: 1012 val1 = d[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_0, 1013 STATUS_HEADER_REO_STATUS_NUMBER)]; 1014 break; 1015 case HAL_REO_DESC_THRES_STATUS_TLV: 1016 val1 = 1017 d[HAL_OFFSET_DW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0, 1018 STATUS_HEADER_REO_STATUS_NUMBER)]; 1019 break; 1020 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: 1021 val1 = d[HAL_OFFSET_DW(REO_UPDATE_RX_REO_QUEUE_STATUS_0, 1022 STATUS_HEADER_REO_STATUS_NUMBER)]; 1023 break; 1024 default: 1025 qdf_nofl_err("ERROR: Unknown tlv\n"); 1026 break; 1027 } 1028 h->cmd_num = 1029 HAL_GET_FIELD( 1030 UNIFORM_REO_STATUS_HEADER_0, REO_STATUS_NUMBER, 1031 val1); 1032 h->exec_time = 1033 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_0, 1034 CMD_EXECUTION_TIME, val1); 1035 h->status = 1036 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_0, 1037 REO_CMD_EXECUTION_STATUS, val1); 1038 switch (b) { 1039 case HAL_REO_QUEUE_STATS_STATUS_TLV: 1040 val1 = d[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_1, 1041 STATUS_HEADER_TIMESTAMP)]; 1042 break; 1043 case HAL_REO_FLUSH_QUEUE_STATUS_TLV: 1044 val1 = d[HAL_OFFSET_DW(REO_FLUSH_QUEUE_STATUS_1, 1045 STATUS_HEADER_TIMESTAMP)]; 1046 break; 1047 case HAL_REO_FLUSH_CACHE_STATUS_TLV: 1048 val1 = d[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_1, 1049 STATUS_HEADER_TIMESTAMP)]; 1050 break; 1051 case HAL_REO_UNBLK_CACHE_STATUS_TLV: 1052 val1 = d[HAL_OFFSET_DW(REO_UNBLOCK_CACHE_STATUS_1, 1053 STATUS_HEADER_TIMESTAMP)]; 1054 break; 1055 case HAL_REO_TIMOUT_LIST_STATUS_TLV: 1056 val1 = d[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_1, 1057 STATUS_HEADER_TIMESTAMP)]; 1058 break; 1059 case HAL_REO_DESC_THRES_STATUS_TLV: 1060 val1 = 1061 d[HAL_OFFSET_DW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_1, 1062 STATUS_HEADER_TIMESTAMP)]; 1063 break; 1064 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: 1065 val1 = d[HAL_OFFSET_DW(REO_UPDATE_RX_REO_QUEUE_STATUS_1, 1066 STATUS_HEADER_TIMESTAMP)]; 1067 break; 1068 default: 1069 qdf_nofl_err("ERROR: Unknown tlv\n"); 1070 break; 1071 } 1072 h->tstamp = 1073 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_1, TIMESTAMP, val1); 1074 } 1075 1076 /** 1077 * hal_tx_desc_set_mesh_en_6490 - Set mesh_enable flag in Tx descriptor 1078 * @desc: Handle to Tx Descriptor 1079 * @en: For raw WiFi frames, this indicates transmission to a mesh STA, 1080 * enabling the interpretation of the 'Mesh Control Present' bit 1081 * (bit 8) of QoS Control (otherwise this bit is ignored), 1082 * For native WiFi frames, this indicates that a 'Mesh Control' field 1083 * is present between the header and the LLC. 1084 * 1085 * Return: void 1086 */ 1087 static inline 1088 void hal_tx_desc_set_mesh_en_6490(void *desc, uint8_t en) 1089 { 1090 HAL_SET_FLD(desc, TCL_DATA_CMD_5, MESH_ENABLE) |= 1091 HAL_TX_SM(TCL_DATA_CMD_5, MESH_ENABLE, en); 1092 } 1093 1094 static 1095 void *hal_rx_msdu0_buffer_addr_lsb_6490(void *link_desc_va) 1096 { 1097 return (void *)HAL_RX_MSDU0_BUFFER_ADDR_LSB(link_desc_va); 1098 } 1099 1100 static 1101 void *hal_rx_msdu_desc_info_ptr_get_6490(void *msdu0) 1102 { 1103 return (void *)HAL_RX_MSDU_DESC_INFO_PTR_GET(msdu0); 1104 } 1105 1106 static 1107 void *hal_ent_mpdu_desc_info_6490(void *ent_ring_desc) 1108 { 1109 return (void *)HAL_ENT_MPDU_DESC_INFO(ent_ring_desc); 1110 } 1111 1112 static 1113 void *hal_dst_mpdu_desc_info_6490(void *dst_ring_desc) 1114 { 1115 return (void *)HAL_DST_MPDU_DESC_INFO(dst_ring_desc); 1116 } 1117 1118 static 1119 uint8_t hal_rx_get_fc_valid_6490(uint8_t *buf) 1120 { 1121 return HAL_RX_GET_FC_VALID(buf); 1122 } 1123 1124 static uint8_t hal_rx_get_to_ds_flag_6490(uint8_t *buf) 1125 { 1126 return HAL_RX_GET_TO_DS_FLAG(buf); 1127 } 1128 1129 static uint8_t hal_rx_get_mac_addr2_valid_6490(uint8_t *buf) 1130 { 1131 return HAL_RX_GET_MAC_ADDR2_VALID(buf); 1132 } 1133 1134 static uint8_t hal_rx_get_filter_category_6490(uint8_t *buf) 1135 { 1136 return HAL_RX_GET_FILTER_CATEGORY(buf); 1137 } 1138 1139 static uint32_t 1140 hal_rx_get_ppdu_id_6490(uint8_t *buf) 1141 { 1142 return HAL_RX_GET_PPDU_ID(buf); 1143 } 1144 1145 /** 1146 * hal_reo_config_6490(): Set reo config parameters 1147 * @soc: hal soc handle 1148 * @reg_val: value to be set 1149 * @reo_params: reo parameters 1150 * 1151 * Return: void 1152 */ 1153 static 1154 void hal_reo_config_6490(struct hal_soc *soc, 1155 uint32_t reg_val, 1156 struct hal_reo_params *reo_params) 1157 { 1158 HAL_REO_R0_CONFIG(soc, reg_val, reo_params); 1159 } 1160 1161 /** 1162 * hal_rx_msdu_desc_info_get_ptr_6490() - Get msdu desc info ptr 1163 * @msdu_details_ptr - Pointer to msdu_details_ptr 1164 * 1165 * Return - Pointer to rx_msdu_desc_info structure. 1166 * 1167 */ 1168 static void *hal_rx_msdu_desc_info_get_ptr_6490(void *msdu_details_ptr) 1169 { 1170 return HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr); 1171 } 1172 1173 /** 1174 * hal_rx_link_desc_msdu0_ptr_6490 - Get pointer to rx_msdu details 1175 * @link_desc - Pointer to link desc 1176 * 1177 * Return - Pointer to rx_msdu_details structure 1178 * 1179 */ 1180 static void *hal_rx_link_desc_msdu0_ptr_6490(void *link_desc) 1181 { 1182 return HAL_RX_LINK_DESC_MSDU0_PTR(link_desc); 1183 } 1184 1185 /** 1186 * hal_rx_msdu_flow_idx_get_6490: API to get flow index 1187 * from rx_msdu_end TLV 1188 * @buf: pointer to the start of RX PKT TLV headers 1189 * 1190 * Return: flow index value from MSDU END TLV 1191 */ 1192 static inline uint32_t hal_rx_msdu_flow_idx_get_6490(uint8_t *buf) 1193 { 1194 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1195 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1196 1197 return HAL_RX_MSDU_END_FLOW_IDX_GET(msdu_end); 1198 } 1199 1200 /** 1201 * hal_rx_msdu_flow_idx_invalid_6490: API to get flow index invalid 1202 * from rx_msdu_end TLV 1203 * @buf: pointer to the start of RX PKT TLV headers 1204 * 1205 * Return: flow index invalid value from MSDU END TLV 1206 */ 1207 static bool hal_rx_msdu_flow_idx_invalid_6490(uint8_t *buf) 1208 { 1209 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1210 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1211 1212 return HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(msdu_end); 1213 } 1214 1215 /** 1216 * hal_rx_msdu_flow_idx_timeout_6490: API to get flow index timeout 1217 * from rx_msdu_end TLV 1218 * @buf: pointer to the start of RX PKT TLV headers 1219 * 1220 * Return: flow index timeout value from MSDU END TLV 1221 */ 1222 static bool hal_rx_msdu_flow_idx_timeout_6490(uint8_t *buf) 1223 { 1224 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1225 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1226 1227 return HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(msdu_end); 1228 } 1229 1230 /** 1231 * hal_rx_msdu_fse_metadata_get_6490: API to get FSE metadata 1232 * from rx_msdu_end TLV 1233 * @buf: pointer to the start of RX PKT TLV headers 1234 * 1235 * Return: fse metadata value from MSDU END TLV 1236 */ 1237 static uint32_t hal_rx_msdu_fse_metadata_get_6490(uint8_t *buf) 1238 { 1239 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1240 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1241 1242 return HAL_RX_MSDU_END_FSE_METADATA_GET(msdu_end); 1243 } 1244 1245 /** 1246 * hal_rx_msdu_cce_metadata_get_6490: API to get CCE metadata 1247 * from rx_msdu_end TLV 1248 * @buf: pointer to the start of RX PKT TLV headers 1249 * 1250 * Return: cce_metadata 1251 */ 1252 static uint16_t 1253 hal_rx_msdu_cce_metadata_get_6490(uint8_t *buf) 1254 { 1255 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1256 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1257 1258 return HAL_RX_MSDU_END_CCE_METADATA_GET(msdu_end); 1259 } 1260 1261 /** 1262 * hal_rx_tlv_get_tcp_chksum_6490() - API to get tcp checksum 1263 * @buf: rx_tlv_hdr 1264 * 1265 * Return: tcp checksum 1266 */ 1267 static uint16_t 1268 hal_rx_tlv_get_tcp_chksum_6490(uint8_t *buf) 1269 { 1270 return HAL_RX_TLV_GET_TCP_CHKSUM(buf); 1271 } 1272 1273 /** 1274 * hal_rx_get_rx_sequence_6490(): Function to retrieve rx sequence number 1275 * 1276 * @nbuf: Network buffer 1277 * Returns: rx sequence number 1278 */ 1279 static 1280 uint16_t hal_rx_get_rx_sequence_6490(uint8_t *buf) 1281 { 1282 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 1283 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 1284 1285 return HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info); 1286 } 1287 1288 /** 1289 * hal_get_window_address_6490(): Function to get hp/tp address 1290 * @hal_soc: Pointer to hal_soc 1291 * @addr: address offset of register 1292 * 1293 * Return: modified address offset of register 1294 */ 1295 static inline qdf_iomem_t hal_get_window_address_6490(struct hal_soc *hal_soc, 1296 qdf_iomem_t addr) 1297 { 1298 return addr; 1299 } 1300 1301 struct hal_hw_txrx_ops qca6490_hal_hw_txrx_ops = { 1302 /* init and setup */ 1303 hal_srng_dst_hw_init_generic, 1304 hal_srng_src_hw_init_generic, 1305 hal_get_hw_hptp_generic, 1306 hal_reo_setup_generic, 1307 hal_setup_link_idle_list_generic, 1308 hal_get_window_address_6490, 1309 1310 /* tx */ 1311 hal_tx_desc_set_dscp_tid_table_id_6490, 1312 hal_tx_set_dscp_tid_map_6490, 1313 hal_tx_update_dscp_tid_6490, 1314 hal_tx_desc_set_lmac_id_6490, 1315 hal_tx_desc_set_buf_addr_generic, 1316 hal_tx_desc_set_search_type_generic, 1317 hal_tx_desc_set_search_index_generic, 1318 hal_tx_desc_set_cache_set_num_generic, 1319 hal_tx_comp_get_status_generic, 1320 hal_tx_comp_get_release_reason_generic, 1321 hal_get_wbm_internal_error_generic, 1322 hal_tx_desc_set_mesh_en_6490, 1323 1324 /* rx */ 1325 hal_rx_msdu_start_nss_get_6490, 1326 hal_rx_mon_hw_desc_get_mpdu_status_6490, 1327 hal_rx_get_tlv_6490, 1328 hal_rx_proc_phyrx_other_receive_info_tlv_6490, 1329 hal_rx_dump_msdu_start_tlv_6490, 1330 hal_rx_dump_msdu_end_tlv_6490, 1331 hal_get_link_desc_size_6490, 1332 hal_rx_mpdu_start_tid_get_6490, 1333 hal_rx_msdu_start_reception_type_get_6490, 1334 hal_rx_msdu_end_da_idx_get_6490, 1335 hal_rx_msdu_desc_info_get_ptr_6490, 1336 hal_rx_link_desc_msdu0_ptr_6490, 1337 hal_reo_status_get_header_6490, 1338 hal_rx_status_get_tlv_info_generic, 1339 hal_rx_wbm_err_info_get_generic, 1340 hal_rx_dump_mpdu_start_tlv_generic, 1341 1342 hal_tx_set_pcp_tid_map_generic, 1343 hal_tx_update_pcp_tid_generic, 1344 hal_tx_update_tidmap_prty_generic, 1345 hal_rx_get_rx_fragment_number_6490, 1346 hal_rx_msdu_end_da_is_mcbc_get_6490, 1347 hal_rx_msdu_end_sa_is_valid_get_6490, 1348 hal_rx_msdu_end_sa_idx_get_6490, 1349 hal_rx_desc_is_first_msdu_6490, 1350 hal_rx_msdu_end_l3_hdr_padding_get_6490, 1351 hal_rx_encryption_info_valid_6490, 1352 hal_rx_print_pn_6490, 1353 hal_rx_msdu_end_first_msdu_get_6490, 1354 hal_rx_msdu_end_da_is_valid_get_6490, 1355 hal_rx_msdu_end_last_msdu_get_6490, 1356 hal_rx_get_mpdu_mac_ad4_valid_6490, 1357 hal_rx_mpdu_start_sw_peer_id_get_6490, 1358 hal_rx_mpdu_get_to_ds_6490, 1359 hal_rx_mpdu_get_fr_ds_6490, 1360 hal_rx_get_mpdu_frame_control_valid_6490, 1361 hal_rx_mpdu_get_addr1_6490, 1362 hal_rx_mpdu_get_addr2_6490, 1363 hal_rx_mpdu_get_addr3_6490, 1364 hal_rx_mpdu_get_addr4_6490, 1365 hal_rx_get_mpdu_sequence_control_valid_6490, 1366 hal_rx_is_unicast_6490, 1367 hal_rx_tid_get_6490, 1368 hal_rx_hw_desc_get_ppduid_get_6490, 1369 NULL, 1370 NULL, 1371 hal_rx_msdu0_buffer_addr_lsb_6490, 1372 hal_rx_msdu_desc_info_ptr_get_6490, 1373 hal_ent_mpdu_desc_info_6490, 1374 hal_dst_mpdu_desc_info_6490, 1375 hal_rx_get_fc_valid_6490, 1376 hal_rx_get_to_ds_flag_6490, 1377 hal_rx_get_mac_addr2_valid_6490, 1378 hal_rx_get_filter_category_6490, 1379 hal_rx_get_ppdu_id_6490, 1380 hal_reo_config_6490, 1381 hal_rx_msdu_flow_idx_get_6490, 1382 hal_rx_msdu_flow_idx_invalid_6490, 1383 hal_rx_msdu_flow_idx_timeout_6490, 1384 hal_rx_msdu_fse_metadata_get_6490, 1385 hal_rx_msdu_cce_metadata_get_6490, 1386 NULL, 1387 hal_rx_tlv_get_tcp_chksum_6490, 1388 hal_rx_get_rx_sequence_6490, 1389 NULL, 1390 NULL, 1391 /* rx - msdu end fast path info fields */ 1392 hal_rx_msdu_packet_metadata_get_generic, 1393 }; 1394 1395 struct hal_hw_srng_config hw_srng_table_6490[] = { 1396 /* TODO: max_rings can populated by querying HW capabilities */ 1397 { /* REO_DST */ 1398 .start_ring_id = HAL_SRNG_REO2SW1, 1399 .max_rings = 4, 1400 .entry_size = sizeof(struct reo_destination_ring) >> 2, 1401 .lmac_ring = FALSE, 1402 .ring_dir = HAL_SRNG_DST_RING, 1403 .reg_start = { 1404 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR( 1405 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1406 HWIO_REO_R2_REO2SW1_RING_HP_ADDR( 1407 SEQ_WCSS_UMAC_REO_REG_OFFSET) 1408 }, 1409 .reg_size = { 1410 HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(0) - 1411 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(0), 1412 HWIO_REO_R2_REO2SW2_RING_HP_ADDR(0) - 1413 HWIO_REO_R2_REO2SW1_RING_HP_ADDR(0), 1414 }, 1415 .max_size = 1416 HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_BMSK >> 1417 HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_SHFT, 1418 }, 1419 { /* REO_EXCEPTION */ 1420 /* Designating REO2TCL ring as exception ring. This ring is 1421 * similar to other REO2SW rings though it is named as REO2TCL. 1422 * Any of theREO2SW rings can be used as exception ring. 1423 */ 1424 .start_ring_id = HAL_SRNG_REO2TCL, 1425 .max_rings = 1, 1426 .entry_size = sizeof(struct reo_destination_ring) >> 2, 1427 .lmac_ring = FALSE, 1428 .ring_dir = HAL_SRNG_DST_RING, 1429 .reg_start = { 1430 HWIO_REO_R0_REO2TCL_RING_BASE_LSB_ADDR( 1431 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1432 HWIO_REO_R2_REO2TCL_RING_HP_ADDR( 1433 SEQ_WCSS_UMAC_REO_REG_OFFSET) 1434 }, 1435 /* Single ring - provide ring size if multiple rings of this 1436 * type are supported 1437 */ 1438 .reg_size = {}, 1439 .max_size = 1440 HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_BMSK >> 1441 HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_SHFT, 1442 }, 1443 { /* REO_REINJECT */ 1444 .start_ring_id = HAL_SRNG_SW2REO, 1445 .max_rings = 1, 1446 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 1447 .lmac_ring = FALSE, 1448 .ring_dir = HAL_SRNG_SRC_RING, 1449 .reg_start = { 1450 HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR( 1451 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1452 HWIO_REO_R2_SW2REO_RING_HP_ADDR( 1453 SEQ_WCSS_UMAC_REO_REG_OFFSET) 1454 }, 1455 /* Single ring - provide ring size if multiple rings of this 1456 * type are supported 1457 */ 1458 .reg_size = {}, 1459 .max_size = HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_BMSK >> 1460 HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_SHFT, 1461 }, 1462 { /* REO_CMD */ 1463 .start_ring_id = HAL_SRNG_REO_CMD, 1464 .max_rings = 1, 1465 .entry_size = (sizeof(struct tlv_32_hdr) + 1466 sizeof(struct reo_get_queue_stats)) >> 2, 1467 .lmac_ring = FALSE, 1468 .ring_dir = HAL_SRNG_SRC_RING, 1469 .reg_start = { 1470 HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR( 1471 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1472 HWIO_REO_R2_REO_CMD_RING_HP_ADDR( 1473 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1474 }, 1475 /* Single ring - provide ring size if multiple rings of this 1476 * type are supported 1477 */ 1478 .reg_size = {}, 1479 .max_size = 1480 HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_BMSK >> 1481 HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_SHFT, 1482 }, 1483 { /* REO_STATUS */ 1484 .start_ring_id = HAL_SRNG_REO_STATUS, 1485 .max_rings = 1, 1486 .entry_size = (sizeof(struct tlv_32_hdr) + 1487 sizeof(struct reo_get_queue_stats_status)) >> 2, 1488 .lmac_ring = FALSE, 1489 .ring_dir = HAL_SRNG_DST_RING, 1490 .reg_start = { 1491 HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR( 1492 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1493 HWIO_REO_R2_REO_STATUS_RING_HP_ADDR( 1494 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1495 }, 1496 /* Single ring - provide ring size if multiple rings of this 1497 * type are supported 1498 */ 1499 .reg_size = {}, 1500 .max_size = 1501 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> 1502 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, 1503 }, 1504 { /* TCL_DATA */ 1505 .start_ring_id = HAL_SRNG_SW2TCL1, 1506 .max_rings = 3, 1507 .entry_size = (sizeof(struct tlv_32_hdr) + 1508 sizeof(struct tcl_data_cmd)) >> 2, 1509 .lmac_ring = FALSE, 1510 .ring_dir = HAL_SRNG_SRC_RING, 1511 .reg_start = { 1512 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR( 1513 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1514 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR( 1515 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1516 }, 1517 .reg_size = { 1518 HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(0) - 1519 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(0), 1520 HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(0) - 1521 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(0), 1522 }, 1523 .max_size = 1524 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK >> 1525 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT, 1526 }, 1527 { /* TCL_CMD */ 1528 .start_ring_id = HAL_SRNG_SW2TCL_CMD, 1529 .max_rings = 1, 1530 .entry_size = (sizeof(struct tlv_32_hdr) + 1531 sizeof(struct tcl_gse_cmd)) >> 2, 1532 .lmac_ring = FALSE, 1533 .ring_dir = HAL_SRNG_SRC_RING, 1534 .reg_start = { 1535 HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_ADDR( 1536 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1537 HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_ADDR( 1538 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1539 }, 1540 /* Single ring - provide ring size if multiple rings of this 1541 * type are supported 1542 */ 1543 .reg_size = {}, 1544 .max_size = 1545 HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_SIZE_BMSK >> 1546 HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_SIZE_SHFT, 1547 }, 1548 { /* TCL_STATUS */ 1549 .start_ring_id = HAL_SRNG_TCL_STATUS, 1550 .max_rings = 1, 1551 .entry_size = (sizeof(struct tlv_32_hdr) + 1552 sizeof(struct tcl_status_ring)) >> 2, 1553 .lmac_ring = FALSE, 1554 .ring_dir = HAL_SRNG_DST_RING, 1555 .reg_start = { 1556 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR( 1557 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1558 HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR( 1559 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1560 }, 1561 /* Single ring - provide ring size if multiple rings of this 1562 * type are supported 1563 */ 1564 .reg_size = {}, 1565 .max_size = 1566 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_BMSK >> 1567 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_SHFT, 1568 }, 1569 { /* CE_SRC */ 1570 .start_ring_id = HAL_SRNG_CE_0_SRC, 1571 .max_rings = 12, 1572 .entry_size = sizeof(struct ce_src_desc) >> 2, 1573 .lmac_ring = FALSE, 1574 .ring_dir = HAL_SRNG_SRC_RING, 1575 .reg_start = { 1576 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR( 1577 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET), 1578 HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR( 1579 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET), 1580 }, 1581 .reg_size = { 1582 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET - 1583 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET, 1584 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET - 1585 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET, 1586 }, 1587 .max_size = 1588 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >> 1589 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT, 1590 }, 1591 { /* CE_DST */ 1592 .start_ring_id = HAL_SRNG_CE_0_DST, 1593 .max_rings = 12, 1594 .entry_size = 8 >> 2, 1595 /*TODO: entry_size above should actually be 1596 * sizeof(struct ce_dst_desc) >> 2, but couldn't find definition 1597 * of struct ce_dst_desc in HW header files 1598 */ 1599 .lmac_ring = FALSE, 1600 .ring_dir = HAL_SRNG_SRC_RING, 1601 .reg_start = { 1602 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR( 1603 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 1604 HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR( 1605 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 1606 }, 1607 .reg_size = { 1608 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 1609 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 1610 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 1611 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 1612 }, 1613 .max_size = 1614 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >> 1615 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT, 1616 }, 1617 { /* CE_DST_STATUS */ 1618 .start_ring_id = HAL_SRNG_CE_0_DST_STATUS, 1619 .max_rings = 12, 1620 .entry_size = sizeof(struct ce_stat_desc) >> 2, 1621 .lmac_ring = FALSE, 1622 .ring_dir = HAL_SRNG_DST_RING, 1623 .reg_start = { 1624 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR( 1625 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 1626 HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR( 1627 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 1628 }, 1629 /* TODO: check destination status ring registers */ 1630 .reg_size = { 1631 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 1632 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 1633 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 1634 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 1635 }, 1636 .max_size = 1637 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> 1638 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, 1639 }, 1640 { /* WBM_IDLE_LINK */ 1641 .start_ring_id = HAL_SRNG_WBM_IDLE_LINK, 1642 .max_rings = 1, 1643 .entry_size = sizeof(struct wbm_link_descriptor_ring) >> 2, 1644 .lmac_ring = FALSE, 1645 .ring_dir = HAL_SRNG_SRC_RING, 1646 .reg_start = { 1647 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1648 HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1649 }, 1650 /* Single ring - provide ring size if multiple rings of this 1651 * type are supported 1652 */ 1653 .reg_size = {}, 1654 .max_size = 1655 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_BMSK >> 1656 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_SHFT, 1657 }, 1658 { /* SW2WBM_RELEASE */ 1659 .start_ring_id = HAL_SRNG_WBM_SW_RELEASE, 1660 .max_rings = 1, 1661 .entry_size = sizeof(struct wbm_release_ring) >> 2, 1662 .lmac_ring = FALSE, 1663 .ring_dir = HAL_SRNG_SRC_RING, 1664 .reg_start = { 1665 HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1666 HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1667 }, 1668 /* Single ring - provide ring size if multiple rings of this 1669 * type are supported 1670 */ 1671 .reg_size = {}, 1672 .max_size = 1673 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> 1674 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, 1675 }, 1676 { /* WBM2SW_RELEASE */ 1677 .start_ring_id = HAL_SRNG_WBM2SW0_RELEASE, 1678 .max_rings = 4, 1679 .entry_size = sizeof(struct wbm_release_ring) >> 2, 1680 .lmac_ring = FALSE, 1681 .ring_dir = HAL_SRNG_DST_RING, 1682 .reg_start = { 1683 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1684 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1685 }, 1686 .reg_size = { 1687 HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) - 1688 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1689 HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) - 1690 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1691 }, 1692 .max_size = 1693 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> 1694 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, 1695 }, 1696 { /* RXDMA_BUF */ 1697 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA0_BUF0, 1698 #ifdef IPA_OFFLOAD 1699 .max_rings = 3, 1700 #else 1701 .max_rings = 2, 1702 #endif 1703 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 1704 .lmac_ring = TRUE, 1705 .ring_dir = HAL_SRNG_SRC_RING, 1706 /* reg_start is not set because LMAC rings are not accessed 1707 * from host 1708 */ 1709 .reg_start = {}, 1710 .reg_size = {}, 1711 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1712 }, 1713 { /* RXDMA_DST */ 1714 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW0, 1715 .max_rings = 1, 1716 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 1717 .lmac_ring = TRUE, 1718 .ring_dir = HAL_SRNG_DST_RING, 1719 /* reg_start is not set because LMAC rings are not accessed 1720 * from host 1721 */ 1722 .reg_start = {}, 1723 .reg_size = {}, 1724 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1725 }, 1726 { /* RXDMA_MONITOR_BUF */ 1727 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA2_BUF, 1728 .max_rings = 1, 1729 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 1730 .lmac_ring = TRUE, 1731 .ring_dir = HAL_SRNG_SRC_RING, 1732 /* reg_start is not set because LMAC rings are not accessed 1733 * from host 1734 */ 1735 .reg_start = {}, 1736 .reg_size = {}, 1737 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1738 }, 1739 { /* RXDMA_MONITOR_STATUS */ 1740 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_STATBUF, 1741 .max_rings = 1, 1742 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 1743 .lmac_ring = TRUE, 1744 .ring_dir = HAL_SRNG_SRC_RING, 1745 /* reg_start is not set because LMAC rings are not accessed 1746 * from host 1747 */ 1748 .reg_start = {}, 1749 .reg_size = {}, 1750 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1751 }, 1752 { /* RXDMA_MONITOR_DST */ 1753 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW1, 1754 .max_rings = 1, 1755 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 1756 .lmac_ring = TRUE, 1757 .ring_dir = HAL_SRNG_DST_RING, 1758 /* reg_start is not set because LMAC rings are not accessed 1759 * from host 1760 */ 1761 .reg_start = {}, 1762 .reg_size = {}, 1763 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1764 }, 1765 { /* RXDMA_MONITOR_DESC */ 1766 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_DESC, 1767 .max_rings = 1, 1768 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 1769 .lmac_ring = TRUE, 1770 .ring_dir = HAL_SRNG_SRC_RING, 1771 /* reg_start is not set because LMAC rings are not accessed 1772 * from host 1773 */ 1774 .reg_start = {}, 1775 .reg_size = {}, 1776 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1777 }, 1778 { /* DIR_BUF_RX_DMA_SRC */ 1779 .start_ring_id = HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING, 1780 .max_rings = 1, 1781 .entry_size = 2, 1782 .lmac_ring = TRUE, 1783 .ring_dir = HAL_SRNG_SRC_RING, 1784 /* reg_start is not set because LMAC rings are not accessed 1785 * from host 1786 */ 1787 .reg_start = {}, 1788 .reg_size = {}, 1789 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1790 }, 1791 #ifdef WLAN_FEATURE_CIF_CFR 1792 { /* WIFI_POS_SRC */ 1793 .start_ring_id = HAL_SRNG_WIFI_POS_SRC_DMA_RING, 1794 .max_rings = 1, 1795 .entry_size = sizeof(wmi_oem_dma_buf_release_entry) >> 2, 1796 .lmac_ring = TRUE, 1797 .ring_dir = HAL_SRNG_SRC_RING, 1798 /* reg_start is not set because LMAC rings are not accessed 1799 * from host 1800 */ 1801 .reg_start = {}, 1802 .reg_size = {}, 1803 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1804 }, 1805 #endif 1806 }; 1807 1808 int32_t hal_hw_reg_offset_qca6490[] = { 1809 /* dst */ 1810 REG_OFFSET(DST, HP), 1811 REG_OFFSET(DST, TP), 1812 REG_OFFSET(DST, ID), 1813 REG_OFFSET(DST, MISC), 1814 REG_OFFSET(DST, HP_ADDR_LSB), 1815 REG_OFFSET(DST, HP_ADDR_MSB), 1816 REG_OFFSET(DST, MSI1_BASE_LSB), 1817 REG_OFFSET(DST, MSI1_BASE_MSB), 1818 REG_OFFSET(DST, MSI1_DATA), 1819 REG_OFFSET(DST, BASE_LSB), 1820 REG_OFFSET(DST, BASE_MSB), 1821 REG_OFFSET(DST, PRODUCER_INT_SETUP), 1822 /* src */ 1823 REG_OFFSET(SRC, HP), 1824 REG_OFFSET(SRC, TP), 1825 REG_OFFSET(SRC, ID), 1826 REG_OFFSET(SRC, MISC), 1827 REG_OFFSET(SRC, TP_ADDR_LSB), 1828 REG_OFFSET(SRC, TP_ADDR_MSB), 1829 REG_OFFSET(SRC, MSI1_BASE_LSB), 1830 REG_OFFSET(SRC, MSI1_BASE_MSB), 1831 REG_OFFSET(SRC, MSI1_DATA), 1832 REG_OFFSET(SRC, BASE_LSB), 1833 REG_OFFSET(SRC, BASE_MSB), 1834 REG_OFFSET(SRC, CONSUMER_INT_SETUP_IX0), 1835 REG_OFFSET(SRC, CONSUMER_INT_SETUP_IX1), 1836 }; 1837 1838 /** 1839 * hal_qca6490_attach() - Attach 6490 target specific hal_soc ops, 1840 * offset and srng table 1841 */ 1842 void hal_qca6490_attach(struct hal_soc *hal_soc) 1843 { 1844 hal_soc->hw_srng_table = hw_srng_table_6490; 1845 hal_soc->hal_hw_reg_offset = hal_hw_reg_offset_qca6490; 1846 hal_soc->ops = &qca6490_hal_hw_txrx_ops; 1847 } 1848