1 /* 2 * Copyright (c) 2019-2020 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #include "qdf_types.h" 20 #include "qdf_util.h" 21 #include "qdf_types.h" 22 #include "qdf_lock.h" 23 #include "qdf_mem.h" 24 #include "qdf_nbuf.h" 25 #include "hal_hw_headers.h" 26 #include "hal_internal.h" 27 #include "hal_api.h" 28 #include "target_type.h" 29 #include "wcss_version.h" 30 #include "qdf_module.h" 31 #include "hal_flow.h" 32 #include "rx_flow_search_entry.h" 33 #include "hal_rx_flow_info.h" 34 35 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_OFFSET \ 36 RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_OFFSET 37 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_MASK \ 38 RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_MASK 39 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_LSB \ 40 RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_LSB 41 #define UNIFIED_PHYRX_HT_SIG_0_HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS_OFFSET \ 42 PHYRX_L_SIG_B_0_PHYRX_L_SIG_B_INFO_DETAILS_RATE_OFFSET 43 #define UNIFIED_PHYRX_L_SIG_B_0_L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS_OFFSET \ 44 PHYRX_L_SIG_B_0_PHYRX_L_SIG_B_INFO_DETAILS_RATE_OFFSET 45 #define UNIFIED_PHYRX_L_SIG_A_0_L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS_OFFSET \ 46 PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_RATE_OFFSET 47 #define UNIFIED_PHYRX_VHT_SIG_A_0_VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS_OFFSET \ 48 PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_OFFSET 49 #define UNIFIED_PHYRX_HE_SIG_A_SU_0_HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS_OFFSET \ 50 PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_OFFSET 51 #define UNIFIED_PHYRX_HE_SIG_A_MU_DL_0_HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_OFFSET \ 52 PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_OFFSET 53 #define UNIFIED_PHYRX_HE_SIG_B1_MU_0_HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_OFFSET \ 54 PHYRX_HE_SIG_B1_MU_0_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_OFFSET 55 #define UNIFIED_PHYRX_HE_SIG_B2_MU_0_HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_OFFSET \ 56 PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_OFFSET 57 #define UNIFIED_PHYRX_HE_SIG_B2_OFDMA_0_HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_OFFSET \ 58 PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_OFFSET 59 60 #define UNIFIED_PHYRX_RSSI_LEGACY_3_RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS_OFFSET \ 61 PHYRX_RSSI_LEGACY_3_RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS_OFFSET 62 #define UNIFIED_PHYRX_RSSI_LEGACY_19_RECEIVE_RSSI_INFO_PREAMBLE_RSSI_INFO_DETAILS_OFFSET \ 63 PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 64 #define UNIFIED_RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET \ 65 RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 66 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 67 RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET 68 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ 69 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET 70 #define UNIFIED_RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 71 RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET 72 #define UNIFIED_REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 73 REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET 74 #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC \ 75 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER 76 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ 77 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET 78 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 79 RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET 80 #define UNIFIED_TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 81 TCL_DATA_CMD_0_BUF_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 82 #define UNIFIED_TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 83 TCL_DATA_CMD_1_BUF_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 84 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET \ 85 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET 86 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB \ 87 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB 88 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK \ 89 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK 90 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB \ 91 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB 92 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK \ 93 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK 94 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB \ 95 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB 96 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK \ 97 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK 98 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB \ 99 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB 100 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK \ 101 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK 102 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB \ 103 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB 104 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK \ 105 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK 106 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_MASK \ 107 WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MASK 108 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_OFFSET \ 109 WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_OFFSET 110 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_LSB \ 111 WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_LSB 112 113 #include "hal_6490_tx.h" 114 #include "hal_6490_rx.h" 115 #include <hal_generic_api.h> 116 #include <hal_wbm.h> 117 118 /* 119 * hal_rx_msdu_start_nss_get_6490(): API to get the NSS 120 * Interval from rx_msdu_start 121 * 122 * @buf: pointer to the start of RX PKT TLV header 123 * Return: uint32_t(nss) 124 */ 125 static uint32_t 126 hal_rx_msdu_start_nss_get_6490(uint8_t *buf) 127 { 128 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 129 struct rx_msdu_start *msdu_start = 130 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 131 uint8_t mimo_ss_bitmap; 132 133 mimo_ss_bitmap = HAL_RX_MSDU_START_MIMO_SS_BITMAP(msdu_start); 134 135 return qdf_get_hweight8(mimo_ss_bitmap); 136 } 137 138 /** 139 * hal_rx_mon_hw_desc_get_mpdu_status_6490(): Retrieve MPDU status 140 * 141 * @ hw_desc_addr: Start address of Rx HW TLVs 142 * @ rs: Status for monitor mode 143 * 144 * Return: void 145 */ 146 static void hal_rx_mon_hw_desc_get_mpdu_status_6490(void *hw_desc_addr, 147 struct mon_rx_status *rs) 148 { 149 struct rx_msdu_start *rx_msdu_start; 150 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr; 151 uint32_t reg_value; 152 const uint32_t sgi_hw_to_cdp[] = { 153 CDP_SGI_0_8_US, 154 CDP_SGI_0_4_US, 155 CDP_SGI_1_6_US, 156 CDP_SGI_3_2_US, 157 }; 158 159 rx_msdu_start = &rx_desc->msdu_start_tlv.rx_msdu_start; 160 161 HAL_RX_GET_MSDU_AGGREGATION(rx_desc, rs); 162 163 rs->ant_signal_db = HAL_RX_GET(rx_msdu_start, 164 RX_MSDU_START_5, USER_RSSI); 165 rs->is_stbc = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, STBC); 166 167 reg_value = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, SGI); 168 rs->sgi = sgi_hw_to_cdp[reg_value]; 169 170 reg_value = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, RECEPTION_TYPE); 171 rs->beamformed = (reg_value == HAL_RX_RECEPTION_TYPE_MU_MIMO) ? 1 : 0; 172 /* TODO: rs->beamformed should be set for SU beamforming also */ 173 } 174 175 #define LINK_DESC_SIZE (NUM_OF_DWORDS_RX_MSDU_LINK << 2) 176 177 static uint32_t hal_get_link_desc_size_6490(void) 178 { 179 return LINK_DESC_SIZE; 180 } 181 182 /* 183 * hal_rx_get_tlv_6490(): API to get the tlv 184 * 185 * @rx_tlv: TLV data extracted from the rx packet 186 * Return: uint8_t 187 */ 188 static uint8_t hal_rx_get_tlv_6490(void *rx_tlv) 189 { 190 return HAL_RX_GET(rx_tlv, PHYRX_RSSI_LEGACY_0, RECEIVE_BANDWIDTH); 191 } 192 193 /** 194 * hal_rx_proc_phyrx_other_receive_info_tlv_6490() 195 * - process other receive info TLV 196 * @rx_tlv_hdr: pointer to TLV header 197 * @ppdu_info: pointer to ppdu_info 198 * 199 * Return: None 200 */ 201 static 202 void hal_rx_proc_phyrx_other_receive_info_tlv_6490(void *rx_tlv_hdr, 203 void *ppdu_info_handle) 204 { 205 uint32_t tlv_tag, tlv_len; 206 uint32_t temp_len, other_tlv_len, other_tlv_tag; 207 void *rx_tlv = (uint8_t *)rx_tlv_hdr + HAL_RX_TLV32_HDR_SIZE; 208 void *other_tlv_hdr = NULL; 209 void *other_tlv = NULL; 210 211 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv_hdr); 212 tlv_len = HAL_RX_GET_USER_TLV32_LEN(rx_tlv_hdr); 213 temp_len = 0; 214 215 other_tlv_hdr = rx_tlv + HAL_RX_TLV32_HDR_SIZE; 216 217 other_tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(other_tlv_hdr); 218 other_tlv_len = HAL_RX_GET_USER_TLV32_LEN(other_tlv_hdr); 219 temp_len += other_tlv_len; 220 other_tlv = other_tlv_hdr + HAL_RX_TLV32_HDR_SIZE; 221 222 switch (other_tlv_tag) { 223 default: 224 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR, 225 "%s unhandled TLV type: %d, TLV len:%d", 226 __func__, other_tlv_tag, other_tlv_len); 227 break; 228 } 229 } 230 231 /** 232 * hal_rx_dump_msdu_start_tlv_6490() : dump RX msdu_start TLV in structured 233 * human readable format. 234 * @ msdu_start: pointer the msdu_start TLV in pkt. 235 * @ dbg_level: log level. 236 * 237 * Return: void 238 */ 239 static void hal_rx_dump_msdu_start_tlv_6490(void *msdustart, uint8_t dbg_level) 240 { 241 struct rx_msdu_start *msdu_start = (struct rx_msdu_start *)msdustart; 242 243 __QDF_TRACE_RL(dbg_level, QDF_MODULE_ID_DP, 244 "rx_msdu_start tlv (1/2) - " 245 "rxpcu_mpdu_filter_in_category: %x " 246 "sw_frame_group_id: %x " 247 "phy_ppdu_id: %x " 248 "msdu_length: %x " 249 "ipsec_esp: %x " 250 "l3_offset: %x " 251 "ipsec_ah: %x " 252 "l4_offset: %x " 253 "msdu_number: %x " 254 "decap_format: %x " 255 "ipv4_proto: %x " 256 "ipv6_proto: %x " 257 "tcp_proto: %x " 258 "udp_proto: %x " 259 "ip_frag: %x " 260 "tcp_only_ack: %x " 261 "da_is_bcast_mcast: %x " 262 "ip4_protocol_ip6_next_header: %x " 263 "toeplitz_hash_2_or_4: %x " 264 "flow_id_toeplitz: %x " 265 "user_rssi: %x " 266 "pkt_type: %x " 267 "stbc: %x " 268 "sgi: %x " 269 "rate_mcs: %x " 270 "receive_bandwidth: %x " 271 "reception_type: %x " 272 "ppdu_start_timestamp: %u ", 273 msdu_start->rxpcu_mpdu_filter_in_category, 274 msdu_start->sw_frame_group_id, 275 msdu_start->phy_ppdu_id, 276 msdu_start->msdu_length, 277 msdu_start->ipsec_esp, 278 msdu_start->l3_offset, 279 msdu_start->ipsec_ah, 280 msdu_start->l4_offset, 281 msdu_start->msdu_number, 282 msdu_start->decap_format, 283 msdu_start->ipv4_proto, 284 msdu_start->ipv6_proto, 285 msdu_start->tcp_proto, 286 msdu_start->udp_proto, 287 msdu_start->ip_frag, 288 msdu_start->tcp_only_ack, 289 msdu_start->da_is_bcast_mcast, 290 msdu_start->ip4_protocol_ip6_next_header, 291 msdu_start->toeplitz_hash_2_or_4, 292 msdu_start->flow_id_toeplitz, 293 msdu_start->user_rssi, 294 msdu_start->pkt_type, 295 msdu_start->stbc, 296 msdu_start->sgi, 297 msdu_start->rate_mcs, 298 msdu_start->receive_bandwidth, 299 msdu_start->reception_type, 300 msdu_start->ppdu_start_timestamp); 301 302 __QDF_TRACE_RL(dbg_level, QDF_MODULE_ID_DP, 303 "rx_msdu_start tlv (2/2) - " 304 "sw_phy_meta_data: %x ", 305 msdu_start->sw_phy_meta_data); 306 } 307 308 /** 309 * hal_rx_dump_msdu_end_tlv_6490: dump RX msdu_end TLV in structured 310 * human readable format. 311 * @ msdu_end: pointer the msdu_end TLV in pkt. 312 * @ dbg_level: log level. 313 * 314 * Return: void 315 */ 316 static void hal_rx_dump_msdu_end_tlv_6490(void *msduend, 317 uint8_t dbg_level) 318 { 319 struct rx_msdu_end *msdu_end = (struct rx_msdu_end *)msduend; 320 321 __QDF_TRACE_RL(dbg_level, QDF_MODULE_ID_DP, 322 "rx_msdu_end tlv (1/3) - " 323 "rxpcu_mpdu_filter_in_category: %x " 324 "sw_frame_group_id: %x " 325 "phy_ppdu_id: %x " 326 "ip_hdr_chksum: %x " 327 "tcp_udp_chksum: %x " 328 "key_id_octet: %x " 329 "cce_super_rule: %x " 330 "cce_classify_not_done_truncat: %x " 331 "cce_classify_not_done_cce_dis: %x " 332 "ext_wapi_pn_63_48: %x " 333 "ext_wapi_pn_95_64: %x " 334 "ext_wapi_pn_127_96: %x " 335 "reported_mpdu_length: %x " 336 "first_msdu: %x " 337 "last_msdu: %x " 338 "sa_idx_timeout: %x " 339 "da_idx_timeout: %x " 340 "msdu_limit_error: %x " 341 "flow_idx_timeout: %x " 342 "flow_idx_invalid: %x " 343 "wifi_parser_error: %x " 344 "amsdu_parser_error: %x", 345 msdu_end->rxpcu_mpdu_filter_in_category, 346 msdu_end->sw_frame_group_id, 347 msdu_end->phy_ppdu_id, 348 msdu_end->ip_hdr_chksum, 349 msdu_end->tcp_udp_chksum, 350 msdu_end->key_id_octet, 351 msdu_end->cce_super_rule, 352 msdu_end->cce_classify_not_done_truncate, 353 msdu_end->cce_classify_not_done_cce_dis, 354 msdu_end->ext_wapi_pn_63_48, 355 msdu_end->ext_wapi_pn_95_64, 356 msdu_end->ext_wapi_pn_127_96, 357 msdu_end->reported_mpdu_length, 358 msdu_end->first_msdu, 359 msdu_end->last_msdu, 360 msdu_end->sa_idx_timeout, 361 msdu_end->da_idx_timeout, 362 msdu_end->msdu_limit_error, 363 msdu_end->flow_idx_timeout, 364 msdu_end->flow_idx_invalid, 365 msdu_end->wifi_parser_error, 366 msdu_end->amsdu_parser_error); 367 368 __QDF_TRACE_RL(dbg_level, QDF_MODULE_ID_DP, 369 "rx_msdu_end tlv (2/3)- " 370 "sa_is_valid: %x " 371 "da_is_valid: %x " 372 "da_is_mcbc: %x " 373 "l3_header_padding: %x " 374 "ipv6_options_crc: %x " 375 "tcp_seq_number: %x " 376 "tcp_ack_number: %x " 377 "tcp_flag: %x " 378 "lro_eligible: %x " 379 "window_size: %x " 380 "da_offset: %x " 381 "sa_offset: %x " 382 "da_offset_valid: %x " 383 "sa_offset_valid: %x " 384 "rule_indication_31_0: %x " 385 "rule_indication_63_32: %x " 386 "sa_idx: %x " 387 "da_idx: %x " 388 "msdu_drop: %x " 389 "reo_destination_indication: %x " 390 "flow_idx: %x " 391 "fse_metadata: %x " 392 "cce_metadata: %x " 393 "sa_sw_peer_id: %x ", 394 msdu_end->sa_is_valid, 395 msdu_end->da_is_valid, 396 msdu_end->da_is_mcbc, 397 msdu_end->l3_header_padding, 398 msdu_end->ipv6_options_crc, 399 msdu_end->tcp_seq_number, 400 msdu_end->tcp_ack_number, 401 msdu_end->tcp_flag, 402 msdu_end->lro_eligible, 403 msdu_end->window_size, 404 msdu_end->da_offset, 405 msdu_end->sa_offset, 406 msdu_end->da_offset_valid, 407 msdu_end->sa_offset_valid, 408 msdu_end->rule_indication_31_0, 409 msdu_end->rule_indication_63_32, 410 msdu_end->sa_idx, 411 msdu_end->da_idx_or_sw_peer_id, 412 msdu_end->msdu_drop, 413 msdu_end->reo_destination_indication, 414 msdu_end->flow_idx, 415 msdu_end->fse_metadata, 416 msdu_end->cce_metadata, 417 msdu_end->sa_sw_peer_id); 418 __QDF_TRACE_RL(dbg_level, QDF_MODULE_ID_DP, 419 "rx_msdu_end tlv (3/3)" 420 "aggregation_count %x " 421 "flow_aggregation_continuation %x " 422 "fisa_timeout %x " 423 "cumulative_l4_checksum %x " 424 "cumulative_ip_length %x", 425 msdu_end->aggregation_count, 426 msdu_end->flow_aggregation_continuation, 427 msdu_end->fisa_timeout, 428 msdu_end->cumulative_l4_checksum, 429 msdu_end->cumulative_ip_length); 430 } 431 432 /* 433 * Get tid from RX_MPDU_START 434 */ 435 #define HAL_RX_MPDU_INFO_TID_GET(_rx_mpdu_info) \ 436 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_info), \ 437 RX_MPDU_INFO_7_TID_OFFSET)), \ 438 RX_MPDU_INFO_7_TID_MASK, \ 439 RX_MPDU_INFO_7_TID_LSB)) 440 441 static uint32_t hal_rx_mpdu_start_tid_get_6490(uint8_t *buf) 442 { 443 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 444 struct rx_mpdu_start *mpdu_start = 445 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 446 uint32_t tid; 447 448 tid = HAL_RX_MPDU_INFO_TID_GET(&mpdu_start->rx_mpdu_info_details); 449 450 return tid; 451 } 452 453 #define HAL_RX_MSDU_START_RECEPTION_TYPE_GET(_rx_msdu_start) \ 454 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start), \ 455 RX_MSDU_START_5_RECEPTION_TYPE_OFFSET)), \ 456 RX_MSDU_START_5_RECEPTION_TYPE_MASK, \ 457 RX_MSDU_START_5_RECEPTION_TYPE_LSB)) 458 459 /* 460 * hal_rx_msdu_start_reception_type_get(): API to get the reception type 461 * Interval from rx_msdu_start 462 * 463 * @buf: pointer to the start of RX PKT TLV header 464 * Return: uint32_t(reception_type) 465 */ 466 static 467 uint32_t hal_rx_msdu_start_reception_type_get_6490(uint8_t *buf) 468 { 469 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 470 struct rx_msdu_start *msdu_start = 471 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 472 uint32_t reception_type; 473 474 reception_type = HAL_RX_MSDU_START_RECEPTION_TYPE_GET(msdu_start); 475 476 return reception_type; 477 } 478 479 /** 480 * hal_rx_msdu_end_da_idx_get_6490: API to get da_idx 481 * from rx_msdu_end TLV 482 * 483 * @ buf: pointer to the start of RX PKT TLV headers 484 * Return: da index 485 */ 486 static uint16_t hal_rx_msdu_end_da_idx_get_6490(uint8_t *buf) 487 { 488 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 489 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 490 uint16_t da_idx; 491 492 da_idx = HAL_RX_MSDU_END_DA_IDX_GET(msdu_end); 493 494 return da_idx; 495 } 496 /** 497 * hal_rx_get_rx_fragment_number_6490(): Function to retrieve rx fragment number 498 * 499 * @nbuf: Network buffer 500 * Returns: rx fragment number 501 */ 502 static 503 uint8_t hal_rx_get_rx_fragment_number_6490(uint8_t *buf) 504 { 505 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 506 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 507 508 /* Return first 4 bits as fragment number */ 509 return (HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info) & 510 DOT11_SEQ_FRAG_MASK); 511 } 512 513 /** 514 * hal_rx_msdu_end_da_is_mcbc_get_6490(): API to check if pkt is MCBC 515 * from rx_msdu_end TLV 516 * 517 * @ buf: pointer to the start of RX PKT TLV headers 518 * Return: da_is_mcbc 519 */ 520 static uint8_t 521 hal_rx_msdu_end_da_is_mcbc_get_6490(uint8_t *buf) 522 { 523 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 524 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 525 526 return HAL_RX_MSDU_END_DA_IS_MCBC_GET(msdu_end); 527 } 528 529 /** 530 * hal_rx_msdu_end_sa_is_valid_get_6490(): API to get_6490 the 531 * sa_is_valid bit from rx_msdu_end TLV 532 * 533 * @ buf: pointer to the start of RX PKT TLV headers 534 * Return: sa_is_valid bit 535 */ 536 static uint8_t 537 hal_rx_msdu_end_sa_is_valid_get_6490(uint8_t *buf) 538 { 539 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 540 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 541 uint8_t sa_is_valid; 542 543 sa_is_valid = HAL_RX_MSDU_END_SA_IS_VALID_GET(msdu_end); 544 545 return sa_is_valid; 546 } 547 548 /** 549 * hal_rx_msdu_end_sa_idx_get_6490(): API to get_6490 the 550 * sa_idx from rx_msdu_end TLV 551 * 552 * @ buf: pointer to the start of RX PKT TLV headers 553 * Return: sa_idx (SA AST index) 554 */ 555 static 556 uint16_t hal_rx_msdu_end_sa_idx_get_6490(uint8_t *buf) 557 { 558 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 559 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 560 uint16_t sa_idx; 561 562 sa_idx = HAL_RX_MSDU_END_SA_IDX_GET(msdu_end); 563 564 return sa_idx; 565 } 566 567 /** 568 * hal_rx_desc_is_first_msdu_6490() - Check if first msdu 569 * 570 * @hal_soc_hdl: hal_soc handle 571 * @hw_desc_addr: hardware descriptor address 572 * 573 * Return: 0 - success/ non-zero failure 574 */ 575 static uint32_t hal_rx_desc_is_first_msdu_6490(void *hw_desc_addr) 576 { 577 struct rx_pkt_tlvs *rx_tlvs = (struct rx_pkt_tlvs *)hw_desc_addr; 578 struct rx_msdu_end *msdu_end = &rx_tlvs->msdu_end_tlv.rx_msdu_end; 579 580 return HAL_RX_GET(msdu_end, RX_MSDU_END_10, FIRST_MSDU); 581 } 582 583 /** 584 * hal_rx_msdu_end_l3_hdr_padding_get_6490(): API to get_6490 the 585 * l3_header padding from rx_msdu_end TLV 586 * 587 * @ buf: pointer to the start of RX PKT TLV headers 588 * Return: number of l3 header padding bytes 589 */ 590 static uint32_t hal_rx_msdu_end_l3_hdr_padding_get_6490(uint8_t *buf) 591 { 592 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 593 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 594 uint32_t l3_header_padding; 595 596 l3_header_padding = HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(msdu_end); 597 598 return l3_header_padding; 599 } 600 601 /* 602 * @ hal_rx_encryption_info_valid_6490: Returns encryption type. 603 * 604 * @ buf: rx_tlv_hdr of the received packet 605 * @ Return: encryption type 606 */ 607 static uint32_t hal_rx_encryption_info_valid_6490(uint8_t *buf) 608 { 609 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 610 struct rx_mpdu_start *mpdu_start = 611 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 612 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 613 uint32_t encryption_info = HAL_RX_MPDU_ENCRYPTION_INFO_VALID(mpdu_info); 614 615 return encryption_info; 616 } 617 618 /* 619 * @ hal_rx_print_pn_6490: Prints the PN of rx packet. 620 * 621 * @ buf: rx_tlv_hdr of the received packet 622 * @ Return: void 623 */ 624 static void hal_rx_print_pn_6490(uint8_t *buf) 625 { 626 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 627 struct rx_mpdu_start *mpdu_start = 628 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 629 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 630 631 uint32_t pn_31_0 = HAL_RX_MPDU_PN_31_0_GET(mpdu_info); 632 uint32_t pn_63_32 = HAL_RX_MPDU_PN_63_32_GET(mpdu_info); 633 uint32_t pn_95_64 = HAL_RX_MPDU_PN_95_64_GET(mpdu_info); 634 uint32_t pn_127_96 = HAL_RX_MPDU_PN_127_96_GET(mpdu_info); 635 636 hal_debug("PN number pn_127_96 0x%x pn_95_64 0x%x pn_63_32 0x%x pn_31_0 0x%x ", 637 pn_127_96, pn_95_64, pn_63_32, pn_31_0); 638 } 639 640 /** 641 * hal_rx_msdu_end_first_msdu_get_6490: API to get first msdu status 642 * from rx_msdu_end TLV 643 * 644 * @ buf: pointer to the start of RX PKT TLV headers 645 * Return: first_msdu 646 */ 647 static uint8_t hal_rx_msdu_end_first_msdu_get_6490(uint8_t *buf) 648 { 649 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 650 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 651 uint8_t first_msdu; 652 653 first_msdu = HAL_RX_MSDU_END_FIRST_MSDU_GET(msdu_end); 654 655 return first_msdu; 656 } 657 658 /** 659 * hal_rx_msdu_end_da_is_valid_get_6490: API to check if da is valid 660 * from rx_msdu_end TLV 661 * 662 * @ buf: pointer to the start of RX PKT TLV headers 663 * Return: da_is_valid 664 */ 665 static uint8_t hal_rx_msdu_end_da_is_valid_get_6490(uint8_t *buf) 666 { 667 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 668 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 669 uint8_t da_is_valid; 670 671 da_is_valid = HAL_RX_MSDU_END_DA_IS_VALID_GET(msdu_end); 672 673 return da_is_valid; 674 } 675 676 /** 677 * hal_rx_msdu_end_last_msdu_get_6490: API to get last msdu status 678 * from rx_msdu_end TLV 679 * 680 * @ buf: pointer to the start of RX PKT TLV headers 681 * Return: last_msdu 682 */ 683 static uint8_t hal_rx_msdu_end_last_msdu_get_6490(uint8_t *buf) 684 { 685 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 686 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 687 uint8_t last_msdu; 688 689 last_msdu = HAL_RX_MSDU_END_LAST_MSDU_GET(msdu_end); 690 691 return last_msdu; 692 } 693 694 /* 695 * hal_rx_get_mpdu_mac_ad4_valid_6490(): Retrieves if mpdu 4th addr is valid 696 * 697 * @nbuf: Network buffer 698 * Returns: value of mpdu 4th address valid field 699 */ 700 static bool hal_rx_get_mpdu_mac_ad4_valid_6490(uint8_t *buf) 701 { 702 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 703 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 704 bool ad4_valid = 0; 705 706 ad4_valid = HAL_RX_MPDU_GET_MAC_AD4_VALID(rx_mpdu_info); 707 708 return ad4_valid; 709 } 710 711 /** 712 * hal_rx_mpdu_start_sw_peer_id_get_6490: Retrieve sw peer_id 713 * @buf: network buffer 714 * 715 * Return: sw peer_id 716 */ 717 static uint32_t hal_rx_mpdu_start_sw_peer_id_get_6490(uint8_t *buf) 718 { 719 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 720 struct rx_mpdu_start *mpdu_start = 721 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 722 723 return HAL_RX_MPDU_INFO_SW_PEER_ID_GET( 724 &mpdu_start->rx_mpdu_info_details); 725 } 726 727 /** 728 * hal_rx_mpdu_get_to_ds_6490(): API to get the tods info 729 * from rx_mpdu_start 730 * 731 * @buf: pointer to the start of RX PKT TLV header 732 * Return: uint32_t(to_ds) 733 */ 734 static uint32_t hal_rx_mpdu_get_to_ds_6490(uint8_t *buf) 735 { 736 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 737 struct rx_mpdu_start *mpdu_start = 738 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 739 740 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 741 742 return HAL_RX_MPDU_GET_TODS(mpdu_info); 743 } 744 745 /* 746 * hal_rx_mpdu_get_fr_ds_6490(): API to get the from ds info 747 * from rx_mpdu_start 748 * 749 * @buf: pointer to the start of RX PKT TLV header 750 * Return: uint32_t(fr_ds) 751 */ 752 static uint32_t hal_rx_mpdu_get_fr_ds_6490(uint8_t *buf) 753 { 754 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 755 struct rx_mpdu_start *mpdu_start = 756 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 757 758 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 759 760 return HAL_RX_MPDU_GET_FROMDS(mpdu_info); 761 } 762 763 /* 764 * hal_rx_get_mpdu_frame_control_valid_6490(): Retrieves mpdu 765 * frame control valid 766 * 767 * @nbuf: Network buffer 768 * Returns: value of frame control valid field 769 */ 770 static uint8_t hal_rx_get_mpdu_frame_control_valid_6490(uint8_t *buf) 771 { 772 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 773 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 774 775 return HAL_RX_MPDU_GET_FRAME_CONTROL_VALID(rx_mpdu_info); 776 } 777 778 /* 779 * hal_rx_mpdu_get_addr1_6490(): API to check get address1 of the mpdu 780 * 781 * @buf: pointer to the start of RX PKT TLV headera 782 * @mac_addr: pointer to mac address 783 * Return: success/failure 784 */ 785 static QDF_STATUS hal_rx_mpdu_get_addr1_6490(uint8_t *buf, uint8_t *mac_addr) 786 { 787 struct __attribute__((__packed__)) hal_addr1 { 788 uint32_t ad1_31_0; 789 uint16_t ad1_47_32; 790 }; 791 792 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 793 struct rx_mpdu_start *mpdu_start = 794 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 795 796 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 797 struct hal_addr1 *addr = (struct hal_addr1 *)mac_addr; 798 uint32_t mac_addr_ad1_valid; 799 800 mac_addr_ad1_valid = HAL_RX_MPDU_MAC_ADDR_AD1_VALID_GET(mpdu_info); 801 802 if (mac_addr_ad1_valid) { 803 addr->ad1_31_0 = HAL_RX_MPDU_AD1_31_0_GET(mpdu_info); 804 addr->ad1_47_32 = HAL_RX_MPDU_AD1_47_32_GET(mpdu_info); 805 return QDF_STATUS_SUCCESS; 806 } 807 808 return QDF_STATUS_E_FAILURE; 809 } 810 811 /* 812 * hal_rx_mpdu_get_addr2_6490(): API to check get address2 of the mpdu 813 * in the packet 814 * 815 * @buf: pointer to the start of RX PKT TLV header 816 * @mac_addr: pointer to mac address 817 * Return: success/failure 818 */ 819 static QDF_STATUS hal_rx_mpdu_get_addr2_6490(uint8_t *buf, 820 uint8_t *mac_addr) 821 { 822 struct __attribute__((__packed__)) hal_addr2 { 823 uint16_t ad2_15_0; 824 uint32_t ad2_47_16; 825 }; 826 827 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 828 struct rx_mpdu_start *mpdu_start = 829 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 830 831 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 832 struct hal_addr2 *addr = (struct hal_addr2 *)mac_addr; 833 uint32_t mac_addr_ad2_valid; 834 835 mac_addr_ad2_valid = HAL_RX_MPDU_MAC_ADDR_AD2_VALID_GET(mpdu_info); 836 837 if (mac_addr_ad2_valid) { 838 addr->ad2_15_0 = HAL_RX_MPDU_AD2_15_0_GET(mpdu_info); 839 addr->ad2_47_16 = HAL_RX_MPDU_AD2_47_16_GET(mpdu_info); 840 return QDF_STATUS_SUCCESS; 841 } 842 843 return QDF_STATUS_E_FAILURE; 844 } 845 846 /* 847 * hal_rx_mpdu_get_addr3_6490(): API to get address3 of the mpdu 848 * in the packet 849 * 850 * @buf: pointer to the start of RX PKT TLV header 851 * @mac_addr: pointer to mac address 852 * Return: success/failure 853 */ 854 static QDF_STATUS hal_rx_mpdu_get_addr3_6490(uint8_t *buf, uint8_t *mac_addr) 855 { 856 struct __attribute__((__packed__)) hal_addr3 { 857 uint32_t ad3_31_0; 858 uint16_t ad3_47_32; 859 }; 860 861 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 862 struct rx_mpdu_start *mpdu_start = 863 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 864 865 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 866 struct hal_addr3 *addr = (struct hal_addr3 *)mac_addr; 867 uint32_t mac_addr_ad3_valid; 868 869 mac_addr_ad3_valid = HAL_RX_MPDU_MAC_ADDR_AD3_VALID_GET(mpdu_info); 870 871 if (mac_addr_ad3_valid) { 872 addr->ad3_31_0 = HAL_RX_MPDU_AD3_31_0_GET(mpdu_info); 873 addr->ad3_47_32 = HAL_RX_MPDU_AD3_47_32_GET(mpdu_info); 874 return QDF_STATUS_SUCCESS; 875 } 876 877 return QDF_STATUS_E_FAILURE; 878 } 879 880 /* 881 * hal_rx_mpdu_get_addr4_6490(): API to get address4 of the mpdu 882 * in the packet 883 * 884 * @buf: pointer to the start of RX PKT TLV header 885 * @mac_addr: pointer to mac address 886 * Return: success/failure 887 */ 888 static QDF_STATUS hal_rx_mpdu_get_addr4_6490(uint8_t *buf, uint8_t *mac_addr) 889 { 890 struct __attribute__((__packed__)) hal_addr4 { 891 uint32_t ad4_31_0; 892 uint16_t ad4_47_32; 893 }; 894 895 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 896 struct rx_mpdu_start *mpdu_start = 897 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 898 899 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 900 struct hal_addr4 *addr = (struct hal_addr4 *)mac_addr; 901 uint32_t mac_addr_ad4_valid; 902 903 mac_addr_ad4_valid = HAL_RX_MPDU_MAC_ADDR_AD4_VALID_GET(mpdu_info); 904 905 if (mac_addr_ad4_valid) { 906 addr->ad4_31_0 = HAL_RX_MPDU_AD4_31_0_GET(mpdu_info); 907 addr->ad4_47_32 = HAL_RX_MPDU_AD4_47_32_GET(mpdu_info); 908 return QDF_STATUS_SUCCESS; 909 } 910 911 return QDF_STATUS_E_FAILURE; 912 } 913 914 /* 915 * hal_rx_get_mpdu_sequence_control_valid_6490(): Get mpdu 916 * sequence control valid 917 * 918 * @nbuf: Network buffer 919 * Returns: value of sequence control valid field 920 */ 921 static uint8_t hal_rx_get_mpdu_sequence_control_valid_6490(uint8_t *buf) 922 { 923 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 924 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 925 926 return HAL_RX_MPDU_GET_SEQUENCE_CONTROL_VALID(rx_mpdu_info); 927 } 928 929 /** 930 * hal_rx_is_unicast_6490: check packet is unicast frame or not. 931 * 932 * @ buf: pointer to rx pkt TLV. 933 * 934 * Return: true on unicast. 935 */ 936 static bool hal_rx_is_unicast_6490(uint8_t *buf) 937 { 938 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 939 struct rx_mpdu_start *mpdu_start = 940 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 941 uint32_t grp_id; 942 uint8_t *rx_mpdu_info = (uint8_t *)&mpdu_start->rx_mpdu_info_details; 943 944 grp_id = (_HAL_MS((*_OFFSET_TO_WORD_PTR((rx_mpdu_info), 945 RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_OFFSET)), 946 RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_MASK, 947 RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_LSB)); 948 949 return (HAL_MPDU_SW_FRAME_GROUP_UNICAST_DATA == grp_id) ? true : false; 950 } 951 952 /** 953 * hal_rx_tid_get_6490: get tid based on qos control valid. 954 * @hal_soc_hdl: hal_soc handle 955 * @ buf: pointer to rx pkt TLV. 956 * 957 * Return: tid 958 */ 959 static uint32_t hal_rx_tid_get_6490(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 960 { 961 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 962 struct rx_mpdu_start *mpdu_start = 963 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 964 uint8_t *rx_mpdu_info = (uint8_t *)&mpdu_start->rx_mpdu_info_details; 965 uint8_t qos_control_valid = 966 (_HAL_MS((*_OFFSET_TO_WORD_PTR((rx_mpdu_info), 967 RX_MPDU_INFO_11_MPDU_QOS_CONTROL_VALID_OFFSET)), 968 RX_MPDU_INFO_11_MPDU_QOS_CONTROL_VALID_MASK, 969 RX_MPDU_INFO_11_MPDU_QOS_CONTROL_VALID_LSB)); 970 971 if (qos_control_valid) 972 return hal_rx_mpdu_start_tid_get_6490(buf); 973 974 return HAL_RX_NON_QOS_TID; 975 } 976 977 /** 978 * hal_rx_hw_desc_get_ppduid_get_6490(): retrieve ppdu id 979 * @rx_tlv_hdr: start address of rx_pkt_tlvs 980 * @rxdma_dst_ring_desc: Rx HW descriptor 981 * 982 * Return: ppdu id 983 */ 984 static uint32_t hal_rx_hw_desc_get_ppduid_get_6490(void *rx_tlv_hdr, 985 void *rxdma_dst_ring_desc) 986 { 987 struct rx_mpdu_info *rx_mpdu_info; 988 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)rx_tlv_hdr; 989 990 rx_mpdu_info = 991 &rx_desc->mpdu_start_tlv.rx_mpdu_start.rx_mpdu_info_details; 992 993 return HAL_RX_GET(rx_mpdu_info, RX_MPDU_INFO_9, PHY_PPDU_ID); 994 } 995 996 /** 997 * hal_reo_status_get_header_6490 - Process reo desc info 998 * @d - Pointer to reo descriptior 999 * @b - tlv type info 1000 * @h1 - Pointer to hal_reo_status_header where info to be stored 1001 * 1002 * Return - none. 1003 * 1004 */ 1005 static void hal_reo_status_get_header_6490(uint32_t *d, int b, void *h1) 1006 { 1007 uint32_t val1 = 0; 1008 struct hal_reo_status_header *h = 1009 (struct hal_reo_status_header *)h1; 1010 1011 switch (b) { 1012 case HAL_REO_QUEUE_STATS_STATUS_TLV: 1013 val1 = d[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_0, 1014 STATUS_HEADER_REO_STATUS_NUMBER)]; 1015 break; 1016 case HAL_REO_FLUSH_QUEUE_STATUS_TLV: 1017 val1 = d[HAL_OFFSET_DW(REO_FLUSH_QUEUE_STATUS_0, 1018 STATUS_HEADER_REO_STATUS_NUMBER)]; 1019 break; 1020 case HAL_REO_FLUSH_CACHE_STATUS_TLV: 1021 val1 = d[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_0, 1022 STATUS_HEADER_REO_STATUS_NUMBER)]; 1023 break; 1024 case HAL_REO_UNBLK_CACHE_STATUS_TLV: 1025 val1 = d[HAL_OFFSET_DW(REO_UNBLOCK_CACHE_STATUS_0, 1026 STATUS_HEADER_REO_STATUS_NUMBER)]; 1027 break; 1028 case HAL_REO_TIMOUT_LIST_STATUS_TLV: 1029 val1 = d[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_0, 1030 STATUS_HEADER_REO_STATUS_NUMBER)]; 1031 break; 1032 case HAL_REO_DESC_THRES_STATUS_TLV: 1033 val1 = 1034 d[HAL_OFFSET_DW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0, 1035 STATUS_HEADER_REO_STATUS_NUMBER)]; 1036 break; 1037 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: 1038 val1 = d[HAL_OFFSET_DW(REO_UPDATE_RX_REO_QUEUE_STATUS_0, 1039 STATUS_HEADER_REO_STATUS_NUMBER)]; 1040 break; 1041 default: 1042 qdf_nofl_err("ERROR: Unknown tlv\n"); 1043 break; 1044 } 1045 h->cmd_num = 1046 HAL_GET_FIELD( 1047 UNIFORM_REO_STATUS_HEADER_0, REO_STATUS_NUMBER, 1048 val1); 1049 h->exec_time = 1050 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_0, 1051 CMD_EXECUTION_TIME, val1); 1052 h->status = 1053 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_0, 1054 REO_CMD_EXECUTION_STATUS, val1); 1055 switch (b) { 1056 case HAL_REO_QUEUE_STATS_STATUS_TLV: 1057 val1 = d[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_1, 1058 STATUS_HEADER_TIMESTAMP)]; 1059 break; 1060 case HAL_REO_FLUSH_QUEUE_STATUS_TLV: 1061 val1 = d[HAL_OFFSET_DW(REO_FLUSH_QUEUE_STATUS_1, 1062 STATUS_HEADER_TIMESTAMP)]; 1063 break; 1064 case HAL_REO_FLUSH_CACHE_STATUS_TLV: 1065 val1 = d[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_1, 1066 STATUS_HEADER_TIMESTAMP)]; 1067 break; 1068 case HAL_REO_UNBLK_CACHE_STATUS_TLV: 1069 val1 = d[HAL_OFFSET_DW(REO_UNBLOCK_CACHE_STATUS_1, 1070 STATUS_HEADER_TIMESTAMP)]; 1071 break; 1072 case HAL_REO_TIMOUT_LIST_STATUS_TLV: 1073 val1 = d[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_1, 1074 STATUS_HEADER_TIMESTAMP)]; 1075 break; 1076 case HAL_REO_DESC_THRES_STATUS_TLV: 1077 val1 = 1078 d[HAL_OFFSET_DW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_1, 1079 STATUS_HEADER_TIMESTAMP)]; 1080 break; 1081 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: 1082 val1 = d[HAL_OFFSET_DW(REO_UPDATE_RX_REO_QUEUE_STATUS_1, 1083 STATUS_HEADER_TIMESTAMP)]; 1084 break; 1085 default: 1086 qdf_nofl_err("ERROR: Unknown tlv\n"); 1087 break; 1088 } 1089 h->tstamp = 1090 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_1, TIMESTAMP, val1); 1091 } 1092 1093 /** 1094 * hal_tx_desc_set_mesh_en_6490 - Set mesh_enable flag in Tx descriptor 1095 * @desc: Handle to Tx Descriptor 1096 * @en: For raw WiFi frames, this indicates transmission to a mesh STA, 1097 * enabling the interpretation of the 'Mesh Control Present' bit 1098 * (bit 8) of QoS Control (otherwise this bit is ignored), 1099 * For native WiFi frames, this indicates that a 'Mesh Control' field 1100 * is present between the header and the LLC. 1101 * 1102 * Return: void 1103 */ 1104 static inline 1105 void hal_tx_desc_set_mesh_en_6490(void *desc, uint8_t en) 1106 { 1107 HAL_SET_FLD(desc, TCL_DATA_CMD_5, MESH_ENABLE) |= 1108 HAL_TX_SM(TCL_DATA_CMD_5, MESH_ENABLE, en); 1109 } 1110 1111 static 1112 void *hal_rx_msdu0_buffer_addr_lsb_6490(void *link_desc_va) 1113 { 1114 return (void *)HAL_RX_MSDU0_BUFFER_ADDR_LSB(link_desc_va); 1115 } 1116 1117 static 1118 void *hal_rx_msdu_desc_info_ptr_get_6490(void *msdu0) 1119 { 1120 return (void *)HAL_RX_MSDU_DESC_INFO_PTR_GET(msdu0); 1121 } 1122 1123 static 1124 void *hal_ent_mpdu_desc_info_6490(void *ent_ring_desc) 1125 { 1126 return (void *)HAL_ENT_MPDU_DESC_INFO(ent_ring_desc); 1127 } 1128 1129 static 1130 void *hal_dst_mpdu_desc_info_6490(void *dst_ring_desc) 1131 { 1132 return (void *)HAL_DST_MPDU_DESC_INFO(dst_ring_desc); 1133 } 1134 1135 static 1136 uint8_t hal_rx_get_fc_valid_6490(uint8_t *buf) 1137 { 1138 return HAL_RX_GET_FC_VALID(buf); 1139 } 1140 1141 static uint8_t hal_rx_get_to_ds_flag_6490(uint8_t *buf) 1142 { 1143 return HAL_RX_GET_TO_DS_FLAG(buf); 1144 } 1145 1146 static uint8_t hal_rx_get_mac_addr2_valid_6490(uint8_t *buf) 1147 { 1148 return HAL_RX_GET_MAC_ADDR2_VALID(buf); 1149 } 1150 1151 static uint8_t hal_rx_get_filter_category_6490(uint8_t *buf) 1152 { 1153 return HAL_RX_GET_FILTER_CATEGORY(buf); 1154 } 1155 1156 static uint32_t 1157 hal_rx_get_ppdu_id_6490(uint8_t *buf) 1158 { 1159 return HAL_RX_GET_PPDU_ID(buf); 1160 } 1161 1162 /** 1163 * hal_reo_config_6490(): Set reo config parameters 1164 * @soc: hal soc handle 1165 * @reg_val: value to be set 1166 * @reo_params: reo parameters 1167 * 1168 * Return: void 1169 */ 1170 static 1171 void hal_reo_config_6490(struct hal_soc *soc, 1172 uint32_t reg_val, 1173 struct hal_reo_params *reo_params) 1174 { 1175 HAL_REO_R0_CONFIG(soc, reg_val, reo_params); 1176 } 1177 1178 /** 1179 * hal_rx_msdu_desc_info_get_ptr_6490() - Get msdu desc info ptr 1180 * @msdu_details_ptr - Pointer to msdu_details_ptr 1181 * 1182 * Return - Pointer to rx_msdu_desc_info structure. 1183 * 1184 */ 1185 static void *hal_rx_msdu_desc_info_get_ptr_6490(void *msdu_details_ptr) 1186 { 1187 return HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr); 1188 } 1189 1190 /** 1191 * hal_rx_link_desc_msdu0_ptr_6490 - Get pointer to rx_msdu details 1192 * @link_desc - Pointer to link desc 1193 * 1194 * Return - Pointer to rx_msdu_details structure 1195 * 1196 */ 1197 static void *hal_rx_link_desc_msdu0_ptr_6490(void *link_desc) 1198 { 1199 return HAL_RX_LINK_DESC_MSDU0_PTR(link_desc); 1200 } 1201 1202 /** 1203 * hal_rx_msdu_flow_idx_get_6490: API to get flow index 1204 * from rx_msdu_end TLV 1205 * @buf: pointer to the start of RX PKT TLV headers 1206 * 1207 * Return: flow index value from MSDU END TLV 1208 */ 1209 static inline uint32_t hal_rx_msdu_flow_idx_get_6490(uint8_t *buf) 1210 { 1211 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1212 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1213 1214 return HAL_RX_MSDU_END_FLOW_IDX_GET(msdu_end); 1215 } 1216 1217 /** 1218 * hal_rx_msdu_get_reo_destination_indication_6490: API to get 1219 * reo_destination_indication from rx_msdu_end TLV 1220 * @buf: pointer to the start of RX PKT TLV headers 1221 * @reo_destination_indication: pointer to return value of reo_destination_indication 1222 * 1223 * Return: none 1224 */ 1225 static inline void 1226 hal_rx_msdu_get_reo_destination_indication_6490(uint8_t *buf, 1227 uint32_t *reo_destination_indication) 1228 { 1229 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1230 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1231 1232 *reo_destination_indication = HAL_RX_MSDU_END_REO_DEST_IND_GET(msdu_end); 1233 } 1234 1235 /** 1236 * hal_rx_msdu_flow_idx_invalid_6490: API to get flow index invalid 1237 * from rx_msdu_end TLV 1238 * @buf: pointer to the start of RX PKT TLV headers 1239 * 1240 * Return: flow index invalid value from MSDU END TLV 1241 */ 1242 static bool hal_rx_msdu_flow_idx_invalid_6490(uint8_t *buf) 1243 { 1244 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1245 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1246 1247 return HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(msdu_end); 1248 } 1249 1250 /** 1251 * hal_rx_msdu_flow_idx_timeout_6490: API to get flow index timeout 1252 * from rx_msdu_end TLV 1253 * @buf: pointer to the start of RX PKT TLV headers 1254 * 1255 * Return: flow index timeout value from MSDU END TLV 1256 */ 1257 static bool hal_rx_msdu_flow_idx_timeout_6490(uint8_t *buf) 1258 { 1259 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1260 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1261 1262 return HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(msdu_end); 1263 } 1264 1265 /** 1266 * hal_rx_msdu_fse_metadata_get_6490: API to get FSE metadata 1267 * from rx_msdu_end TLV 1268 * @buf: pointer to the start of RX PKT TLV headers 1269 * 1270 * Return: fse metadata value from MSDU END TLV 1271 */ 1272 static uint32_t hal_rx_msdu_fse_metadata_get_6490(uint8_t *buf) 1273 { 1274 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1275 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1276 1277 return HAL_RX_MSDU_END_FSE_METADATA_GET(msdu_end); 1278 } 1279 1280 /** 1281 * hal_rx_msdu_cce_metadata_get_6490: API to get CCE metadata 1282 * from rx_msdu_end TLV 1283 * @buf: pointer to the start of RX PKT TLV headers 1284 * 1285 * Return: cce_metadata 1286 */ 1287 static uint16_t 1288 hal_rx_msdu_cce_metadata_get_6490(uint8_t *buf) 1289 { 1290 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1291 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1292 1293 return HAL_RX_MSDU_END_CCE_METADATA_GET(msdu_end); 1294 } 1295 1296 /** 1297 * hal_rx_msdu_get_flow_params_6490: API to get flow index, flow index invalid 1298 * and flow index timeout from rx_msdu_end TLV 1299 * @buf: pointer to the start of RX PKT TLV headers 1300 * @flow_invalid: pointer to return value of flow_idx_valid 1301 * @flow_timeout: pointer to return value of flow_idx_timeout 1302 * @flow_index: pointer to return value of flow_idx 1303 * 1304 * Return: none 1305 */ 1306 static inline void 1307 hal_rx_msdu_get_flow_params_6490(uint8_t *buf, 1308 bool *flow_invalid, 1309 bool *flow_timeout, 1310 uint32_t *flow_index) 1311 { 1312 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1313 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1314 1315 *flow_invalid = HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(msdu_end); 1316 *flow_timeout = HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(msdu_end); 1317 *flow_index = HAL_RX_MSDU_END_FLOW_IDX_GET(msdu_end); 1318 } 1319 1320 /** 1321 * hal_rx_tlv_get_tcp_chksum_6490() - API to get tcp checksum 1322 * @buf: rx_tlv_hdr 1323 * 1324 * Return: tcp checksum 1325 */ 1326 static uint16_t 1327 hal_rx_tlv_get_tcp_chksum_6490(uint8_t *buf) 1328 { 1329 return HAL_RX_TLV_GET_TCP_CHKSUM(buf); 1330 } 1331 1332 /** 1333 * hal_rx_get_rx_sequence_6490(): Function to retrieve rx sequence number 1334 * 1335 * @nbuf: Network buffer 1336 * Returns: rx sequence number 1337 */ 1338 static 1339 uint16_t hal_rx_get_rx_sequence_6490(uint8_t *buf) 1340 { 1341 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 1342 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 1343 1344 return HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info); 1345 } 1346 1347 /** 1348 * hal_get_window_address_6490(): Function to get hp/tp address 1349 * @hal_soc: Pointer to hal_soc 1350 * @addr: address offset of register 1351 * 1352 * Return: modified address offset of register 1353 */ 1354 static inline qdf_iomem_t hal_get_window_address_6490(struct hal_soc *hal_soc, 1355 qdf_iomem_t addr) 1356 { 1357 return addr; 1358 } 1359 1360 /** 1361 * hal_rx_get_fisa_cumulative_l4_checksum_6490() - Retrieve cumulative 1362 * checksum 1363 * @buf: buffer pointer 1364 * 1365 * Return: cumulative checksum 1366 */ 1367 static inline 1368 uint16_t hal_rx_get_fisa_cumulative_l4_checksum_6490(uint8_t *buf) 1369 { 1370 return HAL_RX_TLV_GET_FISA_CUMULATIVE_L4_CHECKSUM(buf); 1371 } 1372 1373 /** 1374 * hal_rx_get_fisa_cumulative_ip_length_6490() - Retrieve cumulative 1375 * ip length 1376 * @buf: buffer pointer 1377 * 1378 * Return: cumulative length 1379 */ 1380 static inline 1381 uint16_t hal_rx_get_fisa_cumulative_ip_length_6490(uint8_t *buf) 1382 { 1383 return HAL_RX_TLV_GET_FISA_CUMULATIVE_IP_LENGTH(buf); 1384 } 1385 1386 /** 1387 * hal_rx_get_udp_proto_6490() - Retrieve udp proto value 1388 * @buf: buffer 1389 * 1390 * Return: udp proto bit 1391 */ 1392 static inline 1393 bool hal_rx_get_udp_proto_6490(uint8_t *buf) 1394 { 1395 return HAL_RX_TLV_GET_UDP_PROTO(buf); 1396 } 1397 1398 /** 1399 * hal_rx_get_flow_agg_continuation_6490() - retrieve flow agg 1400 * continuation 1401 * @buf: buffer 1402 * 1403 * Return: flow agg 1404 */ 1405 static inline 1406 bool hal_rx_get_flow_agg_continuation_6490(uint8_t *buf) 1407 { 1408 return HAL_RX_TLV_GET_FLOW_AGGR_CONT(buf); 1409 } 1410 1411 /** 1412 * hal_rx_get_flow_agg_count_6490()- Retrieve flow agg count 1413 * @buf: buffer 1414 * 1415 * Return: flow agg count 1416 */ 1417 static inline 1418 uint8_t hal_rx_get_flow_agg_count_6490(uint8_t *buf) 1419 { 1420 return HAL_RX_TLV_GET_FLOW_AGGR_COUNT(buf); 1421 } 1422 1423 /** 1424 * hal_rx_get_fisa_timeout_6490() - Retrieve fisa timeout 1425 * @buf: buffer 1426 * 1427 * Return: fisa timeout 1428 */ 1429 static inline 1430 bool hal_rx_get_fisa_timeout_6490(uint8_t *buf) 1431 { 1432 return HAL_RX_TLV_GET_FISA_TIMEOUT(buf); 1433 } 1434 1435 /** 1436 * hal_rx_mpdu_start_tlv_tag_valid_6490 () - API to check if RX_MPDU_START 1437 * tlv tag is valid 1438 * 1439 *@rx_tlv_hdr: start address of rx_pkt_tlvs 1440 * 1441 * Return: true if RX_MPDU_START is valied, else false. 1442 */ 1443 static uint8_t hal_rx_mpdu_start_tlv_tag_valid_6490(void *rx_tlv_hdr) 1444 { 1445 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)rx_tlv_hdr; 1446 uint32_t tlv_tag; 1447 1448 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(&rx_desc->mpdu_start_tlv); 1449 1450 return tlv_tag == WIFIRX_MPDU_START_E ? true : false; 1451 } 1452 1453 /** 1454 * hal_reo_set_err_dst_remap_6490(): Function to set REO error destination 1455 * ring remap register 1456 * @hal_soc: Pointer to hal_soc 1457 * 1458 * Return: none. 1459 */ 1460 static void 1461 hal_reo_set_err_dst_remap_6490(void *hal_soc) 1462 { 1463 /* 1464 * Set REO error 2k jump (error code 5) / OOR (error code 7) 1465 * frame routed to REO2TCL ring. 1466 */ 1467 uint32_t dst_remap_ix0 = 1468 HAL_REO_ERR_REMAP_IX0(REO_REMAP_RELEASE, 0) | 1469 HAL_REO_ERR_REMAP_IX0(REO_REMAP_RELEASE, 1) | 1470 HAL_REO_ERR_REMAP_IX0(REO_REMAP_RELEASE, 2) | 1471 HAL_REO_ERR_REMAP_IX0(REO_REMAP_RELEASE, 3) | 1472 HAL_REO_ERR_REMAP_IX0(REO_REMAP_RELEASE, 4) | 1473 HAL_REO_ERR_REMAP_IX0(REO_REMAP_TCL, 5) | 1474 HAL_REO_ERR_REMAP_IX0(REO_REMAP_TCL, 6) | 1475 HAL_REO_ERR_REMAP_IX0(REO_REMAP_TCL, 7); 1476 1477 uint32_t dst_remap_ix1 = 1478 HAL_REO_ERR_REMAP_IX1(REO_REMAP_RELEASE, 14) | 1479 HAL_REO_ERR_REMAP_IX1(REO_REMAP_RELEASE, 13) | 1480 HAL_REO_ERR_REMAP_IX1(REO_REMAP_RELEASE, 12) | 1481 HAL_REO_ERR_REMAP_IX1(REO_REMAP_RELEASE, 11) | 1482 HAL_REO_ERR_REMAP_IX1(REO_REMAP_RELEASE, 10) | 1483 HAL_REO_ERR_REMAP_IX1(REO_REMAP_RELEASE, 9) | 1484 HAL_REO_ERR_REMAP_IX1(REO_REMAP_TCL, 8); 1485 1486 HAL_REG_WRITE(hal_soc, 1487 HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ADDR( 1488 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1489 dst_remap_ix0); 1490 1491 hal_info("HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0 0x%x", 1492 HAL_REG_READ( 1493 hal_soc, 1494 HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ADDR( 1495 SEQ_WCSS_UMAC_REO_REG_OFFSET))); 1496 1497 HAL_REG_WRITE(hal_soc, 1498 HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ADDR( 1499 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1500 dst_remap_ix1); 1501 1502 hal_info("HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1 0x%x", 1503 HAL_REG_READ( 1504 hal_soc, 1505 HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ADDR( 1506 SEQ_WCSS_UMAC_REO_REG_OFFSET))); 1507 } 1508 1509 /** 1510 * hal_rx_flow_setup_fse_6490() - Setup a flow search entry in HW FST 1511 * @fst: Pointer to the Rx Flow Search Table 1512 * @table_offset: offset into the table where the flow is to be setup 1513 * @flow: Flow Parameters 1514 * 1515 * Flow table entry fields are updated in host byte order, little endian order. 1516 * 1517 * Return: Success/Failure 1518 */ 1519 static void * 1520 hal_rx_flow_setup_fse_6490(uint8_t *rx_fst, uint32_t table_offset, 1521 uint8_t *rx_flow) 1522 { 1523 struct hal_rx_fst *fst = (struct hal_rx_fst *)rx_fst; 1524 struct hal_rx_flow *flow = (struct hal_rx_flow *)rx_flow; 1525 uint8_t *fse; 1526 bool fse_valid; 1527 1528 if (table_offset >= fst->max_entries) { 1529 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR, 1530 "HAL FSE table offset %u exceeds max entries %u", 1531 table_offset, fst->max_entries); 1532 return NULL; 1533 } 1534 1535 fse = (uint8_t *)fst->base_vaddr + 1536 (table_offset * HAL_RX_FST_ENTRY_SIZE); 1537 1538 fse_valid = HAL_GET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, VALID); 1539 1540 if (fse_valid) { 1541 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_DEBUG, 1542 "HAL FSE %pK already valid", fse); 1543 return NULL; 1544 } 1545 1546 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_0, SRC_IP_127_96) = 1547 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_0, SRC_IP_127_96, 1548 (flow->tuple_info.src_ip_127_96)); 1549 1550 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_1, SRC_IP_95_64) = 1551 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_1, SRC_IP_95_64, 1552 (flow->tuple_info.src_ip_95_64)); 1553 1554 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_2, SRC_IP_63_32) = 1555 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_2, SRC_IP_63_32, 1556 (flow->tuple_info.src_ip_63_32)); 1557 1558 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_3, SRC_IP_31_0) = 1559 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_3, SRC_IP_31_0, 1560 (flow->tuple_info.src_ip_31_0)); 1561 1562 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_4, DEST_IP_127_96) = 1563 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_4, DEST_IP_127_96, 1564 (flow->tuple_info.dest_ip_127_96)); 1565 1566 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_5, DEST_IP_95_64) = 1567 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_5, DEST_IP_95_64, 1568 (flow->tuple_info.dest_ip_95_64)); 1569 1570 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_6, DEST_IP_63_32) = 1571 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_6, DEST_IP_63_32, 1572 (flow->tuple_info.dest_ip_63_32)); 1573 1574 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_7, DEST_IP_31_0) = 1575 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_7, DEST_IP_31_0, 1576 (flow->tuple_info.dest_ip_31_0)); 1577 1578 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, DEST_PORT); 1579 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, DEST_PORT) |= 1580 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_8, DEST_PORT, 1581 (flow->tuple_info.dest_port)); 1582 1583 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, SRC_PORT); 1584 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, SRC_PORT) |= 1585 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_8, SRC_PORT, 1586 (flow->tuple_info.src_port)); 1587 1588 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, L4_PROTOCOL); 1589 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, L4_PROTOCOL) |= 1590 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, L4_PROTOCOL, 1591 flow->tuple_info.l4_protocol); 1592 1593 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_HANDLER); 1594 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_HANDLER) |= 1595 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_HANDLER, 1596 flow->reo_destination_handler); 1597 1598 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, VALID); 1599 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, VALID) |= 1600 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, VALID, 1); 1601 1602 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_10, METADATA); 1603 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_10, METADATA) = 1604 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_10, METADATA, 1605 (flow->fse_metadata)); 1606 1607 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_INDICATION); 1608 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_INDICATION) |= 1609 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, 1610 REO_DESTINATION_INDICATION, 1611 flow->reo_destination_indication); 1612 1613 /* Reset all the other fields in FSE */ 1614 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, RESERVED_9); 1615 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, MSDU_DROP); 1616 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_11, MSDU_COUNT); 1617 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_12, MSDU_BYTE_COUNT); 1618 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_13, TIMESTAMP); 1619 1620 return fse; 1621 } 1622 1623 static 1624 void hal_compute_reo_remap_ix2_ix3_6490(uint32_t *ring, uint32_t num_rings, 1625 uint32_t *remap1, uint32_t *remap2) 1626 { 1627 switch (num_rings) { 1628 case 3: 1629 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 1630 HAL_REO_REMAP_IX2(ring[1], 17) | 1631 HAL_REO_REMAP_IX2(ring[2], 18) | 1632 HAL_REO_REMAP_IX2(ring[0], 19) | 1633 HAL_REO_REMAP_IX2(ring[1], 20) | 1634 HAL_REO_REMAP_IX2(ring[2], 21) | 1635 HAL_REO_REMAP_IX2(ring[0], 22) | 1636 HAL_REO_REMAP_IX2(ring[1], 23); 1637 1638 *remap2 = HAL_REO_REMAP_IX3(ring[2], 24) | 1639 HAL_REO_REMAP_IX3(ring[0], 25) | 1640 HAL_REO_REMAP_IX3(ring[1], 26) | 1641 HAL_REO_REMAP_IX3(ring[2], 27) | 1642 HAL_REO_REMAP_IX3(ring[0], 28) | 1643 HAL_REO_REMAP_IX3(ring[1], 29) | 1644 HAL_REO_REMAP_IX3(ring[2], 30) | 1645 HAL_REO_REMAP_IX3(ring[0], 31); 1646 break; 1647 case 4: 1648 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 1649 HAL_REO_REMAP_IX2(ring[1], 17) | 1650 HAL_REO_REMAP_IX2(ring[2], 18) | 1651 HAL_REO_REMAP_IX2(ring[3], 19) | 1652 HAL_REO_REMAP_IX2(ring[0], 20) | 1653 HAL_REO_REMAP_IX2(ring[1], 21) | 1654 HAL_REO_REMAP_IX2(ring[2], 22) | 1655 HAL_REO_REMAP_IX2(ring[3], 23); 1656 1657 *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) | 1658 HAL_REO_REMAP_IX3(ring[1], 25) | 1659 HAL_REO_REMAP_IX3(ring[2], 26) | 1660 HAL_REO_REMAP_IX3(ring[3], 27) | 1661 HAL_REO_REMAP_IX3(ring[0], 28) | 1662 HAL_REO_REMAP_IX3(ring[1], 29) | 1663 HAL_REO_REMAP_IX3(ring[2], 30) | 1664 HAL_REO_REMAP_IX3(ring[3], 31); 1665 break; 1666 } 1667 } 1668 1669 struct hal_hw_txrx_ops qca6490_hal_hw_txrx_ops = { 1670 /* init and setup */ 1671 hal_srng_dst_hw_init_generic, 1672 hal_srng_src_hw_init_generic, 1673 hal_get_hw_hptp_generic, 1674 hal_reo_setup_generic, 1675 hal_setup_link_idle_list_generic, 1676 hal_get_window_address_6490, 1677 hal_reo_set_err_dst_remap_6490, 1678 1679 /* tx */ 1680 hal_tx_desc_set_dscp_tid_table_id_6490, 1681 hal_tx_set_dscp_tid_map_6490, 1682 hal_tx_update_dscp_tid_6490, 1683 hal_tx_desc_set_lmac_id_6490, 1684 hal_tx_desc_set_buf_addr_generic, 1685 hal_tx_desc_set_search_type_generic, 1686 hal_tx_desc_set_search_index_generic, 1687 hal_tx_desc_set_cache_set_num_generic, 1688 hal_tx_comp_get_status_generic, 1689 hal_tx_comp_get_release_reason_generic, 1690 hal_get_wbm_internal_error_generic, 1691 hal_tx_desc_set_mesh_en_6490, 1692 hal_tx_init_cmd_credit_ring_6490, 1693 1694 /* rx */ 1695 hal_rx_msdu_start_nss_get_6490, 1696 hal_rx_mon_hw_desc_get_mpdu_status_6490, 1697 hal_rx_get_tlv_6490, 1698 hal_rx_proc_phyrx_other_receive_info_tlv_6490, 1699 hal_rx_dump_msdu_start_tlv_6490, 1700 hal_rx_dump_msdu_end_tlv_6490, 1701 hal_get_link_desc_size_6490, 1702 hal_rx_mpdu_start_tid_get_6490, 1703 hal_rx_msdu_start_reception_type_get_6490, 1704 hal_rx_msdu_end_da_idx_get_6490, 1705 hal_rx_msdu_desc_info_get_ptr_6490, 1706 hal_rx_link_desc_msdu0_ptr_6490, 1707 hal_reo_status_get_header_6490, 1708 hal_rx_status_get_tlv_info_generic, 1709 hal_rx_wbm_err_info_get_generic, 1710 hal_rx_dump_mpdu_start_tlv_generic, 1711 1712 hal_tx_set_pcp_tid_map_generic, 1713 hal_tx_update_pcp_tid_generic, 1714 hal_tx_update_tidmap_prty_generic, 1715 hal_rx_get_rx_fragment_number_6490, 1716 hal_rx_msdu_end_da_is_mcbc_get_6490, 1717 hal_rx_msdu_end_sa_is_valid_get_6490, 1718 hal_rx_msdu_end_sa_idx_get_6490, 1719 hal_rx_desc_is_first_msdu_6490, 1720 hal_rx_msdu_end_l3_hdr_padding_get_6490, 1721 hal_rx_encryption_info_valid_6490, 1722 hal_rx_print_pn_6490, 1723 hal_rx_msdu_end_first_msdu_get_6490, 1724 hal_rx_msdu_end_da_is_valid_get_6490, 1725 hal_rx_msdu_end_last_msdu_get_6490, 1726 hal_rx_get_mpdu_mac_ad4_valid_6490, 1727 hal_rx_mpdu_start_sw_peer_id_get_6490, 1728 hal_rx_mpdu_get_to_ds_6490, 1729 hal_rx_mpdu_get_fr_ds_6490, 1730 hal_rx_get_mpdu_frame_control_valid_6490, 1731 hal_rx_mpdu_get_addr1_6490, 1732 hal_rx_mpdu_get_addr2_6490, 1733 hal_rx_mpdu_get_addr3_6490, 1734 hal_rx_mpdu_get_addr4_6490, 1735 hal_rx_get_mpdu_sequence_control_valid_6490, 1736 hal_rx_is_unicast_6490, 1737 hal_rx_tid_get_6490, 1738 hal_rx_hw_desc_get_ppduid_get_6490, 1739 NULL, 1740 NULL, 1741 hal_rx_msdu0_buffer_addr_lsb_6490, 1742 hal_rx_msdu_desc_info_ptr_get_6490, 1743 hal_ent_mpdu_desc_info_6490, 1744 hal_dst_mpdu_desc_info_6490, 1745 hal_rx_get_fc_valid_6490, 1746 hal_rx_get_to_ds_flag_6490, 1747 hal_rx_get_mac_addr2_valid_6490, 1748 hal_rx_get_filter_category_6490, 1749 hal_rx_get_ppdu_id_6490, 1750 hal_reo_config_6490, 1751 hal_rx_msdu_flow_idx_get_6490, 1752 hal_rx_msdu_flow_idx_invalid_6490, 1753 hal_rx_msdu_flow_idx_timeout_6490, 1754 hal_rx_msdu_fse_metadata_get_6490, 1755 hal_rx_msdu_cce_metadata_get_6490, 1756 hal_rx_msdu_get_flow_params_6490, 1757 hal_rx_tlv_get_tcp_chksum_6490, 1758 hal_rx_get_rx_sequence_6490, 1759 #if defined(QCA_WIFI_QCA6490) && defined(WLAN_CFR_ENABLE) && \ 1760 defined(WLAN_ENH_CFR_ENABLE) 1761 hal_rx_get_bb_info_6490, 1762 hal_rx_get_rtt_info_6490, 1763 #else 1764 NULL, 1765 NULL, 1766 #endif 1767 /* rx - msdu end fast path info fields */ 1768 hal_rx_msdu_packet_metadata_get_generic, 1769 hal_rx_get_fisa_cumulative_l4_checksum_6490, 1770 hal_rx_get_fisa_cumulative_ip_length_6490, 1771 hal_rx_get_udp_proto_6490, 1772 hal_rx_get_flow_agg_continuation_6490, 1773 hal_rx_get_flow_agg_count_6490, 1774 hal_rx_get_fisa_timeout_6490, 1775 hal_rx_mpdu_start_tlv_tag_valid_6490, 1776 NULL, 1777 NULL, 1778 1779 /* rx - TLV struct offsets */ 1780 hal_rx_msdu_end_offset_get_generic, 1781 hal_rx_attn_offset_get_generic, 1782 hal_rx_msdu_start_offset_get_generic, 1783 hal_rx_mpdu_start_offset_get_generic, 1784 hal_rx_mpdu_end_offset_get_generic, 1785 hal_rx_flow_setup_fse_6490, 1786 hal_compute_reo_remap_ix2_ix3_6490, 1787 NULL, 1788 NULL, 1789 NULL, 1790 hal_rx_msdu_get_reo_destination_indication_6490 1791 }; 1792 1793 struct hal_hw_srng_config hw_srng_table_6490[] = { 1794 /* TODO: max_rings can populated by querying HW capabilities */ 1795 { /* REO_DST */ 1796 .start_ring_id = HAL_SRNG_REO2SW1, 1797 .max_rings = 4, 1798 .entry_size = sizeof(struct reo_destination_ring) >> 2, 1799 .lmac_ring = FALSE, 1800 .ring_dir = HAL_SRNG_DST_RING, 1801 .reg_start = { 1802 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR( 1803 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1804 HWIO_REO_R2_REO2SW1_RING_HP_ADDR( 1805 SEQ_WCSS_UMAC_REO_REG_OFFSET) 1806 }, 1807 .reg_size = { 1808 HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(0) - 1809 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(0), 1810 HWIO_REO_R2_REO2SW2_RING_HP_ADDR(0) - 1811 HWIO_REO_R2_REO2SW1_RING_HP_ADDR(0), 1812 }, 1813 .max_size = 1814 HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_BMSK >> 1815 HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_SHFT, 1816 }, 1817 { /* REO_EXCEPTION */ 1818 /* Designating REO2TCL ring as exception ring. This ring is 1819 * similar to other REO2SW rings though it is named as REO2TCL. 1820 * Any of theREO2SW rings can be used as exception ring. 1821 */ 1822 .start_ring_id = HAL_SRNG_REO2TCL, 1823 .max_rings = 1, 1824 .entry_size = sizeof(struct reo_destination_ring) >> 2, 1825 .lmac_ring = FALSE, 1826 .ring_dir = HAL_SRNG_DST_RING, 1827 .reg_start = { 1828 HWIO_REO_R0_REO2TCL_RING_BASE_LSB_ADDR( 1829 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1830 HWIO_REO_R2_REO2TCL_RING_HP_ADDR( 1831 SEQ_WCSS_UMAC_REO_REG_OFFSET) 1832 }, 1833 /* Single ring - provide ring size if multiple rings of this 1834 * type are supported 1835 */ 1836 .reg_size = {}, 1837 .max_size = 1838 HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_BMSK >> 1839 HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_SHFT, 1840 }, 1841 { /* REO_REINJECT */ 1842 .start_ring_id = HAL_SRNG_SW2REO, 1843 .max_rings = 1, 1844 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 1845 .lmac_ring = FALSE, 1846 .ring_dir = HAL_SRNG_SRC_RING, 1847 .reg_start = { 1848 HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR( 1849 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1850 HWIO_REO_R2_SW2REO_RING_HP_ADDR( 1851 SEQ_WCSS_UMAC_REO_REG_OFFSET) 1852 }, 1853 /* Single ring - provide ring size if multiple rings of this 1854 * type are supported 1855 */ 1856 .reg_size = {}, 1857 .max_size = HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_BMSK >> 1858 HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_SHFT, 1859 }, 1860 { /* REO_CMD */ 1861 .start_ring_id = HAL_SRNG_REO_CMD, 1862 .max_rings = 1, 1863 .entry_size = (sizeof(struct tlv_32_hdr) + 1864 sizeof(struct reo_get_queue_stats)) >> 2, 1865 .lmac_ring = FALSE, 1866 .ring_dir = HAL_SRNG_SRC_RING, 1867 .reg_start = { 1868 HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR( 1869 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1870 HWIO_REO_R2_REO_CMD_RING_HP_ADDR( 1871 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1872 }, 1873 /* Single ring - provide ring size if multiple rings of this 1874 * type are supported 1875 */ 1876 .reg_size = {}, 1877 .max_size = 1878 HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_BMSK >> 1879 HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_SHFT, 1880 }, 1881 { /* REO_STATUS */ 1882 .start_ring_id = HAL_SRNG_REO_STATUS, 1883 .max_rings = 1, 1884 .entry_size = (sizeof(struct tlv_32_hdr) + 1885 sizeof(struct reo_get_queue_stats_status)) >> 2, 1886 .lmac_ring = FALSE, 1887 .ring_dir = HAL_SRNG_DST_RING, 1888 .reg_start = { 1889 HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR( 1890 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1891 HWIO_REO_R2_REO_STATUS_RING_HP_ADDR( 1892 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1893 }, 1894 /* Single ring - provide ring size if multiple rings of this 1895 * type are supported 1896 */ 1897 .reg_size = {}, 1898 .max_size = 1899 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> 1900 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, 1901 }, 1902 { /* TCL_DATA */ 1903 .start_ring_id = HAL_SRNG_SW2TCL1, 1904 .max_rings = 3, 1905 .entry_size = (sizeof(struct tlv_32_hdr) + 1906 sizeof(struct tcl_data_cmd)) >> 2, 1907 .lmac_ring = FALSE, 1908 .ring_dir = HAL_SRNG_SRC_RING, 1909 .reg_start = { 1910 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR( 1911 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1912 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR( 1913 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1914 }, 1915 .reg_size = { 1916 HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(0) - 1917 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(0), 1918 HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(0) - 1919 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(0), 1920 }, 1921 .max_size = 1922 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK >> 1923 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT, 1924 }, 1925 { /* TCL_CMD */ 1926 .start_ring_id = HAL_SRNG_SW2TCL_CMD, 1927 .max_rings = 1, 1928 .entry_size = (sizeof(struct tlv_32_hdr) + 1929 sizeof(struct tcl_gse_cmd)) >> 2, 1930 .lmac_ring = FALSE, 1931 .ring_dir = HAL_SRNG_SRC_RING, 1932 .reg_start = { 1933 HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_ADDR( 1934 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1935 HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_ADDR( 1936 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1937 }, 1938 /* Single ring - provide ring size if multiple rings of this 1939 * type are supported 1940 */ 1941 .reg_size = {}, 1942 .max_size = 1943 HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_SIZE_BMSK >> 1944 HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_SIZE_SHFT, 1945 }, 1946 { /* TCL_STATUS */ 1947 .start_ring_id = HAL_SRNG_TCL_STATUS, 1948 .max_rings = 1, 1949 .entry_size = (sizeof(struct tlv_32_hdr) + 1950 sizeof(struct tcl_status_ring)) >> 2, 1951 .lmac_ring = FALSE, 1952 .ring_dir = HAL_SRNG_DST_RING, 1953 .reg_start = { 1954 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR( 1955 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1956 HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR( 1957 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1958 }, 1959 /* Single ring - provide ring size if multiple rings of this 1960 * type are supported 1961 */ 1962 .reg_size = {}, 1963 .max_size = 1964 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_BMSK >> 1965 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_SHFT, 1966 }, 1967 { /* CE_SRC */ 1968 .start_ring_id = HAL_SRNG_CE_0_SRC, 1969 .max_rings = 12, 1970 .entry_size = sizeof(struct ce_src_desc) >> 2, 1971 .lmac_ring = FALSE, 1972 .ring_dir = HAL_SRNG_SRC_RING, 1973 .reg_start = { 1974 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR( 1975 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET), 1976 HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR( 1977 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET), 1978 }, 1979 .reg_size = { 1980 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET - 1981 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET, 1982 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET - 1983 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET, 1984 }, 1985 .max_size = 1986 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >> 1987 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT, 1988 }, 1989 { /* CE_DST */ 1990 .start_ring_id = HAL_SRNG_CE_0_DST, 1991 .max_rings = 12, 1992 .entry_size = 8 >> 2, 1993 /*TODO: entry_size above should actually be 1994 * sizeof(struct ce_dst_desc) >> 2, but couldn't find definition 1995 * of struct ce_dst_desc in HW header files 1996 */ 1997 .lmac_ring = FALSE, 1998 .ring_dir = HAL_SRNG_SRC_RING, 1999 .reg_start = { 2000 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR( 2001 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 2002 HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR( 2003 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 2004 }, 2005 .reg_size = { 2006 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 2007 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 2008 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 2009 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 2010 }, 2011 .max_size = 2012 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >> 2013 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT, 2014 }, 2015 { /* CE_DST_STATUS */ 2016 .start_ring_id = HAL_SRNG_CE_0_DST_STATUS, 2017 .max_rings = 12, 2018 .entry_size = sizeof(struct ce_stat_desc) >> 2, 2019 .lmac_ring = FALSE, 2020 .ring_dir = HAL_SRNG_DST_RING, 2021 .reg_start = { 2022 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR( 2023 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 2024 HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR( 2025 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 2026 }, 2027 /* TODO: check destination status ring registers */ 2028 .reg_size = { 2029 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 2030 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 2031 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 2032 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 2033 }, 2034 .max_size = 2035 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> 2036 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, 2037 }, 2038 { /* WBM_IDLE_LINK */ 2039 .start_ring_id = HAL_SRNG_WBM_IDLE_LINK, 2040 .max_rings = 1, 2041 .entry_size = sizeof(struct wbm_link_descriptor_ring) >> 2, 2042 .lmac_ring = FALSE, 2043 .ring_dir = HAL_SRNG_SRC_RING, 2044 .reg_start = { 2045 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2046 HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2047 }, 2048 /* Single ring - provide ring size if multiple rings of this 2049 * type are supported 2050 */ 2051 .reg_size = {}, 2052 .max_size = 2053 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_BMSK >> 2054 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_SHFT, 2055 }, 2056 { /* SW2WBM_RELEASE */ 2057 .start_ring_id = HAL_SRNG_WBM_SW_RELEASE, 2058 .max_rings = 1, 2059 .entry_size = sizeof(struct wbm_release_ring) >> 2, 2060 .lmac_ring = FALSE, 2061 .ring_dir = HAL_SRNG_SRC_RING, 2062 .reg_start = { 2063 HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2064 HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2065 }, 2066 /* Single ring - provide ring size if multiple rings of this 2067 * type are supported 2068 */ 2069 .reg_size = {}, 2070 .max_size = 2071 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> 2072 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, 2073 }, 2074 { /* WBM2SW_RELEASE */ 2075 .start_ring_id = HAL_SRNG_WBM2SW0_RELEASE, 2076 .max_rings = 4, 2077 .entry_size = sizeof(struct wbm_release_ring) >> 2, 2078 .lmac_ring = FALSE, 2079 .ring_dir = HAL_SRNG_DST_RING, 2080 .reg_start = { 2081 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2082 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2083 }, 2084 .reg_size = { 2085 HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) - 2086 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2087 HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) - 2088 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2089 }, 2090 .max_size = 2091 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> 2092 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, 2093 }, 2094 { /* RXDMA_BUF */ 2095 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA0_BUF0, 2096 #ifdef IPA_OFFLOAD 2097 .max_rings = 3, 2098 #else 2099 .max_rings = 2, 2100 #endif 2101 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 2102 .lmac_ring = TRUE, 2103 .ring_dir = HAL_SRNG_SRC_RING, 2104 /* reg_start is not set because LMAC rings are not accessed 2105 * from host 2106 */ 2107 .reg_start = {}, 2108 .reg_size = {}, 2109 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2110 }, 2111 { /* RXDMA_DST */ 2112 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW0, 2113 .max_rings = 1, 2114 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 2115 .lmac_ring = TRUE, 2116 .ring_dir = HAL_SRNG_DST_RING, 2117 /* reg_start is not set because LMAC rings are not accessed 2118 * from host 2119 */ 2120 .reg_start = {}, 2121 .reg_size = {}, 2122 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2123 }, 2124 { /* RXDMA_MONITOR_BUF */ 2125 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA2_BUF, 2126 .max_rings = 1, 2127 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 2128 .lmac_ring = TRUE, 2129 .ring_dir = HAL_SRNG_SRC_RING, 2130 /* reg_start is not set because LMAC rings are not accessed 2131 * from host 2132 */ 2133 .reg_start = {}, 2134 .reg_size = {}, 2135 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2136 }, 2137 { /* RXDMA_MONITOR_STATUS */ 2138 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_STATBUF, 2139 .max_rings = 1, 2140 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 2141 .lmac_ring = TRUE, 2142 .ring_dir = HAL_SRNG_SRC_RING, 2143 /* reg_start is not set because LMAC rings are not accessed 2144 * from host 2145 */ 2146 .reg_start = {}, 2147 .reg_size = {}, 2148 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2149 }, 2150 { /* RXDMA_MONITOR_DST */ 2151 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW1, 2152 .max_rings = 1, 2153 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 2154 .lmac_ring = TRUE, 2155 .ring_dir = HAL_SRNG_DST_RING, 2156 /* reg_start is not set because LMAC rings are not accessed 2157 * from host 2158 */ 2159 .reg_start = {}, 2160 .reg_size = {}, 2161 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2162 }, 2163 { /* RXDMA_MONITOR_DESC */ 2164 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_DESC, 2165 .max_rings = 1, 2166 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 2167 .lmac_ring = TRUE, 2168 .ring_dir = HAL_SRNG_SRC_RING, 2169 /* reg_start is not set because LMAC rings are not accessed 2170 * from host 2171 */ 2172 .reg_start = {}, 2173 .reg_size = {}, 2174 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2175 }, 2176 { /* DIR_BUF_RX_DMA_SRC */ 2177 .start_ring_id = HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING, 2178 /* 2179 * one ring is for spectral scan 2180 * the other is for cfr 2181 */ 2182 .max_rings = 2, 2183 .entry_size = 2, 2184 .lmac_ring = TRUE, 2185 .ring_dir = HAL_SRNG_SRC_RING, 2186 /* reg_start is not set because LMAC rings are not accessed 2187 * from host 2188 */ 2189 .reg_start = {}, 2190 .reg_size = {}, 2191 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2192 }, 2193 #ifdef WLAN_FEATURE_CIF_CFR 2194 { /* WIFI_POS_SRC */ 2195 .start_ring_id = HAL_SRNG_WIFI_POS_SRC_DMA_RING, 2196 .max_rings = 1, 2197 .entry_size = sizeof(wmi_oem_dma_buf_release_entry) >> 2, 2198 .lmac_ring = TRUE, 2199 .ring_dir = HAL_SRNG_SRC_RING, 2200 /* reg_start is not set because LMAC rings are not accessed 2201 * from host 2202 */ 2203 .reg_start = {}, 2204 .reg_size = {}, 2205 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2206 }, 2207 #endif 2208 }; 2209 2210 int32_t hal_hw_reg_offset_qca6490[] = { 2211 /* dst */ 2212 REG_OFFSET(DST, HP), 2213 REG_OFFSET(DST, TP), 2214 REG_OFFSET(DST, ID), 2215 REG_OFFSET(DST, MISC), 2216 REG_OFFSET(DST, HP_ADDR_LSB), 2217 REG_OFFSET(DST, HP_ADDR_MSB), 2218 REG_OFFSET(DST, MSI1_BASE_LSB), 2219 REG_OFFSET(DST, MSI1_BASE_MSB), 2220 REG_OFFSET(DST, MSI1_DATA), 2221 REG_OFFSET(DST, BASE_LSB), 2222 REG_OFFSET(DST, BASE_MSB), 2223 REG_OFFSET(DST, PRODUCER_INT_SETUP), 2224 /* src */ 2225 REG_OFFSET(SRC, HP), 2226 REG_OFFSET(SRC, TP), 2227 REG_OFFSET(SRC, ID), 2228 REG_OFFSET(SRC, MISC), 2229 REG_OFFSET(SRC, TP_ADDR_LSB), 2230 REG_OFFSET(SRC, TP_ADDR_MSB), 2231 REG_OFFSET(SRC, MSI1_BASE_LSB), 2232 REG_OFFSET(SRC, MSI1_BASE_MSB), 2233 REG_OFFSET(SRC, MSI1_DATA), 2234 REG_OFFSET(SRC, BASE_LSB), 2235 REG_OFFSET(SRC, BASE_MSB), 2236 REG_OFFSET(SRC, CONSUMER_INT_SETUP_IX0), 2237 REG_OFFSET(SRC, CONSUMER_INT_SETUP_IX1), 2238 }; 2239 2240 /** 2241 * hal_qca6490_attach() - Attach 6490 target specific hal_soc ops, 2242 * offset and srng table 2243 */ 2244 void hal_qca6490_attach(struct hal_soc *hal_soc) 2245 { 2246 hal_soc->hw_srng_table = hw_srng_table_6490; 2247 hal_soc->hal_hw_reg_offset = hal_hw_reg_offset_qca6490; 2248 hal_soc->ops = &qca6490_hal_hw_txrx_ops; 2249 } 2250