1 /* 2 * Copyright (c) 2019-2021 The Linux Foundation. All rights reserved. 3 * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #include "qdf_types.h" 21 #include "qdf_util.h" 22 #include "qdf_types.h" 23 #include "qdf_lock.h" 24 #include "qdf_mem.h" 25 #include "qdf_nbuf.h" 26 #include "hal_li_hw_headers.h" 27 #include "hal_internal.h" 28 #include "hal_api.h" 29 #include "target_type.h" 30 #include "wcss_version.h" 31 #include "qdf_module.h" 32 #include "hal_flow.h" 33 #include "rx_flow_search_entry.h" 34 #include "hal_rx_flow_info.h" 35 36 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_OFFSET \ 37 RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_OFFSET 38 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_MASK \ 39 RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_MASK 40 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_LSB \ 41 RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_LSB 42 #define UNIFIED_PHYRX_HT_SIG_0_HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS_OFFSET \ 43 PHYRX_L_SIG_B_0_PHYRX_L_SIG_B_INFO_DETAILS_RATE_OFFSET 44 #define UNIFIED_PHYRX_L_SIG_B_0_L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS_OFFSET \ 45 PHYRX_L_SIG_B_0_PHYRX_L_SIG_B_INFO_DETAILS_RATE_OFFSET 46 #define UNIFIED_PHYRX_L_SIG_A_0_L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS_OFFSET \ 47 PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_RATE_OFFSET 48 #define UNIFIED_PHYRX_VHT_SIG_A_0_VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS_OFFSET \ 49 PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_OFFSET 50 #define UNIFIED_PHYRX_HE_SIG_A_SU_0_HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS_OFFSET \ 51 PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_OFFSET 52 #define UNIFIED_PHYRX_HE_SIG_A_MU_DL_0_HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_OFFSET \ 53 PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_OFFSET 54 #define UNIFIED_PHYRX_HE_SIG_B1_MU_0_HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_OFFSET \ 55 PHYRX_HE_SIG_B1_MU_0_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_OFFSET 56 #define UNIFIED_PHYRX_HE_SIG_B2_MU_0_HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_OFFSET \ 57 PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_OFFSET 58 #define UNIFIED_PHYRX_HE_SIG_B2_OFDMA_0_HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_OFFSET \ 59 PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_OFFSET 60 61 #define UNIFIED_PHYRX_RSSI_LEGACY_3_RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS_OFFSET \ 62 PHYRX_RSSI_LEGACY_3_RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS_OFFSET 63 #define UNIFIED_PHYRX_RSSI_LEGACY_19_RECEIVE_RSSI_INFO_PREAMBLE_RSSI_INFO_DETAILS_OFFSET \ 64 PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 65 #define UNIFIED_RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET \ 66 RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 67 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 68 RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET 69 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ 70 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET 71 #define UNIFIED_RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 72 RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET 73 #define UNIFIED_REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 74 REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET 75 #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC \ 76 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER 77 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ 78 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET 79 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 80 RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET 81 #define UNIFIED_TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 82 TCL_DATA_CMD_0_BUF_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 83 #define UNIFIED_TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 84 TCL_DATA_CMD_1_BUF_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 85 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET \ 86 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET 87 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB \ 88 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB 89 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK \ 90 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK 91 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB \ 92 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB 93 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK \ 94 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK 95 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB \ 96 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB 97 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK \ 98 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK 99 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB \ 100 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB 101 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK \ 102 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK 103 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB \ 104 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB 105 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK \ 106 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK 107 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_MASK \ 108 WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MASK 109 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_OFFSET \ 110 WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_OFFSET 111 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_LSB \ 112 WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_LSB 113 114 #include "hal_6490_tx.h" 115 #include "hal_6490_rx.h" 116 #include <hal_generic_api.h> 117 #include "hal_li_rx.h" 118 #include "hal_li_api.h" 119 #include "hal_li_generic_api.h" 120 121 /* 122 * hal_rx_msdu_start_nss_get_6490(): API to get the NSS 123 * Interval from rx_msdu_start 124 * 125 * @buf: pointer to the start of RX PKT TLV header 126 * Return: uint32_t(nss) 127 */ 128 static uint32_t 129 hal_rx_msdu_start_nss_get_6490(uint8_t *buf) 130 { 131 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 132 struct rx_msdu_start *msdu_start = 133 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 134 uint8_t mimo_ss_bitmap; 135 136 mimo_ss_bitmap = HAL_RX_MSDU_START_MIMO_SS_BITMAP(msdu_start); 137 138 return qdf_get_hweight8(mimo_ss_bitmap); 139 } 140 141 /** 142 * hal_rx_msdu_start_get_len_6490(): API to get the MSDU length 143 * from rx_msdu_start TLV 144 * 145 * @ buf: pointer to the start of RX PKT TLV headers 146 * Return: (uint32_t)msdu length 147 */ 148 static uint32_t hal_rx_msdu_start_get_len_6490(uint8_t *buf) 149 { 150 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 151 struct rx_msdu_start *msdu_start = 152 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 153 uint32_t msdu_len; 154 155 msdu_len = HAL_RX_MSDU_START_MSDU_LEN_GET(msdu_start); 156 157 return msdu_len; 158 } 159 160 /** 161 * hal_rx_mon_hw_desc_get_mpdu_status_6490(): Retrieve MPDU status 162 * 163 * @ hw_desc_addr: Start address of Rx HW TLVs 164 * @ rs: Status for monitor mode 165 * 166 * Return: void 167 */ 168 static void hal_rx_mon_hw_desc_get_mpdu_status_6490(void *hw_desc_addr, 169 struct mon_rx_status *rs) 170 { 171 struct rx_msdu_start *rx_msdu_start; 172 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr; 173 uint32_t reg_value; 174 const uint32_t sgi_hw_to_cdp[] = { 175 CDP_SGI_0_8_US, 176 CDP_SGI_0_4_US, 177 CDP_SGI_1_6_US, 178 CDP_SGI_3_2_US, 179 }; 180 181 rx_msdu_start = &rx_desc->msdu_start_tlv.rx_msdu_start; 182 183 HAL_RX_GET_MSDU_AGGREGATION(rx_desc, rs); 184 185 rs->ant_signal_db = HAL_RX_GET(rx_msdu_start, 186 RX_MSDU_START_5, USER_RSSI); 187 if (!rs->vht_flags) { 188 rs->is_stbc = HAL_RX_GET(rx_msdu_start, 189 RX_MSDU_START_5, STBC); 190 191 reg_value = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, SGI); 192 rs->sgi = sgi_hw_to_cdp[reg_value]; 193 194 reg_value = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, 195 RECEPTION_TYPE); 196 rs->beamformed = 197 (reg_value == HAL_RX_RECEPTION_TYPE_MU_MIMO) ? 1 : 0; 198 } 199 /* TODO: rs->beamformed should be set for SU beamforming also */ 200 } 201 202 #define LINK_DESC_SIZE (NUM_OF_DWORDS_RX_MSDU_LINK << 2) 203 204 static uint32_t hal_get_link_desc_size_6490(void) 205 { 206 return LINK_DESC_SIZE; 207 } 208 209 /* 210 * hal_rx_get_tlv_6490(): API to get the tlv 211 * 212 * @rx_tlv: TLV data extracted from the rx packet 213 * Return: uint8_t 214 */ 215 static uint8_t hal_rx_get_tlv_6490(void *rx_tlv) 216 { 217 return HAL_RX_GET(rx_tlv, PHYRX_RSSI_LEGACY_0, RECEIVE_BANDWIDTH); 218 } 219 220 /** 221 * hal_rx_proc_phyrx_other_receive_info_tlv_6490() 222 * - process other receive info TLV 223 * @rx_tlv_hdr: pointer to TLV header 224 * @ppdu_info: pointer to ppdu_info 225 * 226 * Return: None 227 */ 228 static 229 void hal_rx_proc_phyrx_other_receive_info_tlv_6490(void *rx_tlv_hdr, 230 void *ppdu_info_handle) 231 { 232 uint32_t tlv_tag, tlv_len; 233 uint32_t temp_len, other_tlv_len, other_tlv_tag; 234 void *rx_tlv = (uint8_t *)rx_tlv_hdr + HAL_RX_TLV32_HDR_SIZE; 235 void *other_tlv_hdr = NULL; 236 void *other_tlv = NULL; 237 238 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv_hdr); 239 tlv_len = HAL_RX_GET_USER_TLV32_LEN(rx_tlv_hdr); 240 temp_len = 0; 241 242 other_tlv_hdr = rx_tlv + HAL_RX_TLV32_HDR_SIZE; 243 244 other_tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(other_tlv_hdr); 245 other_tlv_len = HAL_RX_GET_USER_TLV32_LEN(other_tlv_hdr); 246 temp_len += other_tlv_len; 247 other_tlv = other_tlv_hdr + HAL_RX_TLV32_HDR_SIZE; 248 249 switch (other_tlv_tag) { 250 default: 251 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR, 252 "%s unhandled TLV type: %d, TLV len:%d", 253 __func__, other_tlv_tag, other_tlv_len); 254 break; 255 } 256 } 257 258 /** 259 * hal_rx_dump_msdu_start_tlv_6490() : dump RX msdu_start TLV in structured 260 * human readable format. 261 * @ msdu_start: pointer the msdu_start TLV in pkt. 262 * @ dbg_level: log level. 263 * 264 * Return: void 265 */ 266 static void hal_rx_dump_msdu_start_tlv_6490(void *msdustart, uint8_t dbg_level) 267 { 268 struct rx_msdu_start *msdu_start = (struct rx_msdu_start *)msdustart; 269 270 __QDF_TRACE_RL(dbg_level, QDF_MODULE_ID_DP, 271 "rx_msdu_start tlv (1/2) - " 272 "rxpcu_mpdu_filter_in_category: %x " 273 "sw_frame_group_id: %x " 274 "phy_ppdu_id: %x " 275 "msdu_length: %x " 276 "ipsec_esp: %x " 277 "l3_offset: %x " 278 "ipsec_ah: %x " 279 "l4_offset: %x " 280 "msdu_number: %x " 281 "decap_format: %x " 282 "ipv4_proto: %x " 283 "ipv6_proto: %x " 284 "tcp_proto: %x " 285 "udp_proto: %x " 286 "ip_frag: %x " 287 "tcp_only_ack: %x " 288 "da_is_bcast_mcast: %x " 289 "ip4_protocol_ip6_next_header: %x " 290 "toeplitz_hash_2_or_4: %x " 291 "flow_id_toeplitz: %x " 292 "user_rssi: %x " 293 "pkt_type: %x " 294 "stbc: %x " 295 "sgi: %x " 296 "rate_mcs: %x " 297 "receive_bandwidth: %x " 298 "reception_type: %x " 299 "ppdu_start_timestamp: %u ", 300 msdu_start->rxpcu_mpdu_filter_in_category, 301 msdu_start->sw_frame_group_id, 302 msdu_start->phy_ppdu_id, 303 msdu_start->msdu_length, 304 msdu_start->ipsec_esp, 305 msdu_start->l3_offset, 306 msdu_start->ipsec_ah, 307 msdu_start->l4_offset, 308 msdu_start->msdu_number, 309 msdu_start->decap_format, 310 msdu_start->ipv4_proto, 311 msdu_start->ipv6_proto, 312 msdu_start->tcp_proto, 313 msdu_start->udp_proto, 314 msdu_start->ip_frag, 315 msdu_start->tcp_only_ack, 316 msdu_start->da_is_bcast_mcast, 317 msdu_start->ip4_protocol_ip6_next_header, 318 msdu_start->toeplitz_hash_2_or_4, 319 msdu_start->flow_id_toeplitz, 320 msdu_start->user_rssi, 321 msdu_start->pkt_type, 322 msdu_start->stbc, 323 msdu_start->sgi, 324 msdu_start->rate_mcs, 325 msdu_start->receive_bandwidth, 326 msdu_start->reception_type, 327 msdu_start->ppdu_start_timestamp); 328 329 __QDF_TRACE_RL(dbg_level, QDF_MODULE_ID_DP, 330 "rx_msdu_start tlv (2/2) - " 331 "sw_phy_meta_data: %x ", 332 msdu_start->sw_phy_meta_data); 333 } 334 335 /** 336 * hal_rx_dump_msdu_end_tlv_6490: dump RX msdu_end TLV in structured 337 * human readable format. 338 * @ msdu_end: pointer the msdu_end TLV in pkt. 339 * @ dbg_level: log level. 340 * 341 * Return: void 342 */ 343 static void hal_rx_dump_msdu_end_tlv_6490(void *msduend, 344 uint8_t dbg_level) 345 { 346 struct rx_msdu_end *msdu_end = (struct rx_msdu_end *)msduend; 347 348 __QDF_TRACE_RL(dbg_level, QDF_MODULE_ID_DP, 349 "rx_msdu_end tlv (1/3) - " 350 "rxpcu_mpdu_filter_in_category: %x " 351 "sw_frame_group_id: %x " 352 "phy_ppdu_id: %x " 353 "ip_hdr_chksum: %x " 354 "tcp_udp_chksum: %x " 355 "key_id_octet: %x " 356 "cce_super_rule: %x " 357 "cce_classify_not_done_truncat: %x " 358 "cce_classify_not_done_cce_dis: %x " 359 "ext_wapi_pn_63_48: %x " 360 "ext_wapi_pn_95_64: %x " 361 "ext_wapi_pn_127_96: %x " 362 "reported_mpdu_length: %x " 363 "first_msdu: %x " 364 "last_msdu: %x " 365 "sa_idx_timeout: %x " 366 "da_idx_timeout: %x " 367 "msdu_limit_error: %x " 368 "flow_idx_timeout: %x " 369 "flow_idx_invalid: %x " 370 "wifi_parser_error: %x " 371 "amsdu_parser_error: %x", 372 msdu_end->rxpcu_mpdu_filter_in_category, 373 msdu_end->sw_frame_group_id, 374 msdu_end->phy_ppdu_id, 375 msdu_end->ip_hdr_chksum, 376 msdu_end->tcp_udp_chksum, 377 msdu_end->key_id_octet, 378 msdu_end->cce_super_rule, 379 msdu_end->cce_classify_not_done_truncate, 380 msdu_end->cce_classify_not_done_cce_dis, 381 msdu_end->ext_wapi_pn_63_48, 382 msdu_end->ext_wapi_pn_95_64, 383 msdu_end->ext_wapi_pn_127_96, 384 msdu_end->reported_mpdu_length, 385 msdu_end->first_msdu, 386 msdu_end->last_msdu, 387 msdu_end->sa_idx_timeout, 388 msdu_end->da_idx_timeout, 389 msdu_end->msdu_limit_error, 390 msdu_end->flow_idx_timeout, 391 msdu_end->flow_idx_invalid, 392 msdu_end->wifi_parser_error, 393 msdu_end->amsdu_parser_error); 394 395 __QDF_TRACE_RL(dbg_level, QDF_MODULE_ID_DP, 396 "rx_msdu_end tlv (2/3)- " 397 "sa_is_valid: %x " 398 "da_is_valid: %x " 399 "da_is_mcbc: %x " 400 "l3_header_padding: %x " 401 "ipv6_options_crc: %x " 402 "tcp_seq_number: %x " 403 "tcp_ack_number: %x " 404 "tcp_flag: %x " 405 "lro_eligible: %x " 406 "window_size: %x " 407 "da_offset: %x " 408 "sa_offset: %x " 409 "da_offset_valid: %x " 410 "sa_offset_valid: %x " 411 "rule_indication_31_0: %x " 412 "rule_indication_63_32: %x " 413 "sa_idx: %x " 414 "da_idx: %x " 415 "msdu_drop: %x " 416 "reo_destination_indication: %x " 417 "flow_idx: %x " 418 "fse_metadata: %x " 419 "cce_metadata: %x " 420 "sa_sw_peer_id: %x ", 421 msdu_end->sa_is_valid, 422 msdu_end->da_is_valid, 423 msdu_end->da_is_mcbc, 424 msdu_end->l3_header_padding, 425 msdu_end->ipv6_options_crc, 426 msdu_end->tcp_seq_number, 427 msdu_end->tcp_ack_number, 428 msdu_end->tcp_flag, 429 msdu_end->lro_eligible, 430 msdu_end->window_size, 431 msdu_end->da_offset, 432 msdu_end->sa_offset, 433 msdu_end->da_offset_valid, 434 msdu_end->sa_offset_valid, 435 msdu_end->rule_indication_31_0, 436 msdu_end->rule_indication_63_32, 437 msdu_end->sa_idx, 438 msdu_end->da_idx_or_sw_peer_id, 439 msdu_end->msdu_drop, 440 msdu_end->reo_destination_indication, 441 msdu_end->flow_idx, 442 msdu_end->fse_metadata, 443 msdu_end->cce_metadata, 444 msdu_end->sa_sw_peer_id); 445 __QDF_TRACE_RL(dbg_level, QDF_MODULE_ID_DP, 446 "rx_msdu_end tlv (3/3)" 447 "aggregation_count %x " 448 "flow_aggregation_continuation %x " 449 "fisa_timeout %x " 450 "cumulative_l4_checksum %x " 451 "cumulative_ip_length %x", 452 msdu_end->aggregation_count, 453 msdu_end->flow_aggregation_continuation, 454 msdu_end->fisa_timeout, 455 msdu_end->cumulative_l4_checksum, 456 msdu_end->cumulative_ip_length); 457 } 458 459 /* 460 * Get tid from RX_MPDU_START 461 */ 462 #define HAL_RX_MPDU_INFO_TID_GET(_rx_mpdu_info) \ 463 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_info), \ 464 RX_MPDU_INFO_7_TID_OFFSET)), \ 465 RX_MPDU_INFO_7_TID_MASK, \ 466 RX_MPDU_INFO_7_TID_LSB)) 467 468 static uint32_t hal_rx_mpdu_start_tid_get_6490(uint8_t *buf) 469 { 470 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 471 struct rx_mpdu_start *mpdu_start = 472 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 473 uint32_t tid; 474 475 tid = HAL_RX_MPDU_INFO_TID_GET(&mpdu_start->rx_mpdu_info_details); 476 477 return tid; 478 } 479 480 #define HAL_RX_MSDU_START_RECEPTION_TYPE_GET(_rx_msdu_start) \ 481 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start), \ 482 RX_MSDU_START_5_RECEPTION_TYPE_OFFSET)), \ 483 RX_MSDU_START_5_RECEPTION_TYPE_MASK, \ 484 RX_MSDU_START_5_RECEPTION_TYPE_LSB)) 485 486 /* 487 * hal_rx_msdu_start_reception_type_get(): API to get the reception type 488 * Interval from rx_msdu_start 489 * 490 * @buf: pointer to the start of RX PKT TLV header 491 * Return: uint32_t(reception_type) 492 */ 493 static 494 uint32_t hal_rx_msdu_start_reception_type_get_6490(uint8_t *buf) 495 { 496 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 497 struct rx_msdu_start *msdu_start = 498 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 499 uint32_t reception_type; 500 501 reception_type = HAL_RX_MSDU_START_RECEPTION_TYPE_GET(msdu_start); 502 503 return reception_type; 504 } 505 506 /** 507 * hal_rx_msdu_end_da_idx_get_6490: API to get da_idx 508 * from rx_msdu_end TLV 509 * 510 * @ buf: pointer to the start of RX PKT TLV headers 511 * Return: da index 512 */ 513 static uint16_t hal_rx_msdu_end_da_idx_get_6490(uint8_t *buf) 514 { 515 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 516 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 517 uint16_t da_idx; 518 519 da_idx = HAL_RX_MSDU_END_DA_IDX_GET(msdu_end); 520 521 return da_idx; 522 } 523 /** 524 * hal_rx_get_rx_fragment_number_6490(): Function to retrieve rx fragment number 525 * 526 * @nbuf: Network buffer 527 * Returns: rx fragment number 528 */ 529 static 530 uint8_t hal_rx_get_rx_fragment_number_6490(uint8_t *buf) 531 { 532 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 533 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 534 535 /* Return first 4 bits as fragment number */ 536 return (HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info) & 537 DOT11_SEQ_FRAG_MASK); 538 } 539 540 /** 541 * hal_rx_msdu_end_da_is_mcbc_get_6490(): API to check if pkt is MCBC 542 * from rx_msdu_end TLV 543 * 544 * @ buf: pointer to the start of RX PKT TLV headers 545 * Return: da_is_mcbc 546 */ 547 static uint8_t 548 hal_rx_msdu_end_da_is_mcbc_get_6490(uint8_t *buf) 549 { 550 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 551 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 552 553 return HAL_RX_MSDU_END_DA_IS_MCBC_GET(msdu_end); 554 } 555 556 /** 557 * hal_rx_msdu_end_sa_is_valid_get_6490(): API to get_6490 the 558 * sa_is_valid bit from rx_msdu_end TLV 559 * 560 * @ buf: pointer to the start of RX PKT TLV headers 561 * Return: sa_is_valid bit 562 */ 563 static uint8_t 564 hal_rx_msdu_end_sa_is_valid_get_6490(uint8_t *buf) 565 { 566 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 567 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 568 uint8_t sa_is_valid; 569 570 sa_is_valid = HAL_RX_MSDU_END_SA_IS_VALID_GET(msdu_end); 571 572 return sa_is_valid; 573 } 574 575 /** 576 * hal_rx_msdu_end_sa_idx_get_6490(): API to get_6490 the 577 * sa_idx from rx_msdu_end TLV 578 * 579 * @ buf: pointer to the start of RX PKT TLV headers 580 * Return: sa_idx (SA AST index) 581 */ 582 static 583 uint16_t hal_rx_msdu_end_sa_idx_get_6490(uint8_t *buf) 584 { 585 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 586 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 587 uint16_t sa_idx; 588 589 sa_idx = HAL_RX_MSDU_END_SA_IDX_GET(msdu_end); 590 591 return sa_idx; 592 } 593 594 /** 595 * hal_rx_desc_is_first_msdu_6490() - Check if first msdu 596 * 597 * @hal_soc_hdl: hal_soc handle 598 * @hw_desc_addr: hardware descriptor address 599 * 600 * Return: 0 - success/ non-zero failure 601 */ 602 static uint32_t hal_rx_desc_is_first_msdu_6490(void *hw_desc_addr) 603 { 604 struct rx_pkt_tlvs *rx_tlvs = (struct rx_pkt_tlvs *)hw_desc_addr; 605 struct rx_msdu_end *msdu_end = &rx_tlvs->msdu_end_tlv.rx_msdu_end; 606 607 return HAL_RX_GET(msdu_end, RX_MSDU_END_10, FIRST_MSDU); 608 } 609 610 /** 611 * hal_rx_msdu_end_l3_hdr_padding_get_6490(): API to get_6490 the 612 * l3_header padding from rx_msdu_end TLV 613 * 614 * @ buf: pointer to the start of RX PKT TLV headers 615 * Return: number of l3 header padding bytes 616 */ 617 static uint32_t hal_rx_msdu_end_l3_hdr_padding_get_6490(uint8_t *buf) 618 { 619 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 620 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 621 uint32_t l3_header_padding; 622 623 l3_header_padding = HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(msdu_end); 624 625 return l3_header_padding; 626 } 627 628 /* 629 * @ hal_rx_encryption_info_valid_6490: Returns encryption type. 630 * 631 * @ buf: rx_tlv_hdr of the received packet 632 * @ Return: encryption type 633 */ 634 static uint32_t hal_rx_encryption_info_valid_6490(uint8_t *buf) 635 { 636 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 637 struct rx_mpdu_start *mpdu_start = 638 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 639 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 640 uint32_t encryption_info = HAL_RX_MPDU_ENCRYPTION_INFO_VALID(mpdu_info); 641 642 return encryption_info; 643 } 644 645 /* 646 * @ hal_rx_print_pn_6490: Prints the PN of rx packet. 647 * 648 * @ buf: rx_tlv_hdr of the received packet 649 * @ Return: void 650 */ 651 static void hal_rx_print_pn_6490(uint8_t *buf) 652 { 653 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 654 struct rx_mpdu_start *mpdu_start = 655 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 656 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 657 658 uint32_t pn_31_0 = HAL_RX_MPDU_PN_31_0_GET(mpdu_info); 659 uint32_t pn_63_32 = HAL_RX_MPDU_PN_63_32_GET(mpdu_info); 660 uint32_t pn_95_64 = HAL_RX_MPDU_PN_95_64_GET(mpdu_info); 661 uint32_t pn_127_96 = HAL_RX_MPDU_PN_127_96_GET(mpdu_info); 662 663 hal_debug("PN number pn_127_96 0x%x pn_95_64 0x%x pn_63_32 0x%x pn_31_0 0x%x ", 664 pn_127_96, pn_95_64, pn_63_32, pn_31_0); 665 } 666 667 /** 668 * hal_rx_msdu_end_first_msdu_get_6490: API to get first msdu status 669 * from rx_msdu_end TLV 670 * 671 * @ buf: pointer to the start of RX PKT TLV headers 672 * Return: first_msdu 673 */ 674 static uint8_t hal_rx_msdu_end_first_msdu_get_6490(uint8_t *buf) 675 { 676 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 677 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 678 uint8_t first_msdu; 679 680 first_msdu = HAL_RX_MSDU_END_FIRST_MSDU_GET(msdu_end); 681 682 return first_msdu; 683 } 684 685 /** 686 * hal_rx_msdu_end_da_is_valid_get_6490: API to check if da is valid 687 * from rx_msdu_end TLV 688 * 689 * @ buf: pointer to the start of RX PKT TLV headers 690 * Return: da_is_valid 691 */ 692 static uint8_t hal_rx_msdu_end_da_is_valid_get_6490(uint8_t *buf) 693 { 694 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 695 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 696 uint8_t da_is_valid; 697 698 da_is_valid = HAL_RX_MSDU_END_DA_IS_VALID_GET(msdu_end); 699 700 return da_is_valid; 701 } 702 703 /** 704 * hal_rx_msdu_end_last_msdu_get_6490: API to get last msdu status 705 * from rx_msdu_end TLV 706 * 707 * @ buf: pointer to the start of RX PKT TLV headers 708 * Return: last_msdu 709 */ 710 static uint8_t hal_rx_msdu_end_last_msdu_get_6490(uint8_t *buf) 711 { 712 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 713 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 714 uint8_t last_msdu; 715 716 last_msdu = HAL_RX_MSDU_END_LAST_MSDU_GET(msdu_end); 717 718 return last_msdu; 719 } 720 721 /* 722 * hal_rx_get_mpdu_mac_ad4_valid_6490(): Retrieves if mpdu 4th addr is valid 723 * 724 * @nbuf: Network buffer 725 * Returns: value of mpdu 4th address valid field 726 */ 727 static bool hal_rx_get_mpdu_mac_ad4_valid_6490(uint8_t *buf) 728 { 729 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 730 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 731 bool ad4_valid = 0; 732 733 ad4_valid = HAL_RX_MPDU_GET_MAC_AD4_VALID(rx_mpdu_info); 734 735 return ad4_valid; 736 } 737 738 /** 739 * hal_rx_mpdu_start_sw_peer_id_get_6490: Retrieve sw peer_id 740 * @buf: network buffer 741 * 742 * Return: sw peer_id 743 */ 744 static uint32_t hal_rx_mpdu_start_sw_peer_id_get_6490(uint8_t *buf) 745 { 746 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 747 struct rx_mpdu_start *mpdu_start = 748 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 749 750 return HAL_RX_MPDU_INFO_SW_PEER_ID_GET( 751 &mpdu_start->rx_mpdu_info_details); 752 } 753 754 /** 755 * hal_rx_mpdu_get_to_ds_6490(): API to get the tods info 756 * from rx_mpdu_start 757 * 758 * @buf: pointer to the start of RX PKT TLV header 759 * Return: uint32_t(to_ds) 760 */ 761 static uint32_t hal_rx_mpdu_get_to_ds_6490(uint8_t *buf) 762 { 763 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 764 struct rx_mpdu_start *mpdu_start = 765 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 766 767 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 768 769 return HAL_RX_MPDU_GET_TODS(mpdu_info); 770 } 771 772 /* 773 * hal_rx_mpdu_get_fr_ds_6490(): API to get the from ds info 774 * from rx_mpdu_start 775 * 776 * @buf: pointer to the start of RX PKT TLV header 777 * Return: uint32_t(fr_ds) 778 */ 779 static uint32_t hal_rx_mpdu_get_fr_ds_6490(uint8_t *buf) 780 { 781 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 782 struct rx_mpdu_start *mpdu_start = 783 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 784 785 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 786 787 return HAL_RX_MPDU_GET_FROMDS(mpdu_info); 788 } 789 790 /* 791 * hal_rx_get_mpdu_frame_control_valid_6490(): Retrieves mpdu 792 * frame control valid 793 * 794 * @nbuf: Network buffer 795 * Returns: value of frame control valid field 796 */ 797 static uint8_t hal_rx_get_mpdu_frame_control_valid_6490(uint8_t *buf) 798 { 799 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 800 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 801 802 return HAL_RX_MPDU_GET_FRAME_CONTROL_VALID(rx_mpdu_info); 803 } 804 805 /* 806 * hal_rx_mpdu_get_addr1_6490(): API to check get address1 of the mpdu 807 * 808 * @buf: pointer to the start of RX PKT TLV headera 809 * @mac_addr: pointer to mac address 810 * Return: success/failure 811 */ 812 static QDF_STATUS hal_rx_mpdu_get_addr1_6490(uint8_t *buf, uint8_t *mac_addr) 813 { 814 struct __attribute__((__packed__)) hal_addr1 { 815 uint32_t ad1_31_0; 816 uint16_t ad1_47_32; 817 }; 818 819 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 820 struct rx_mpdu_start *mpdu_start = 821 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 822 823 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 824 struct hal_addr1 *addr = (struct hal_addr1 *)mac_addr; 825 uint32_t mac_addr_ad1_valid; 826 827 mac_addr_ad1_valid = HAL_RX_MPDU_MAC_ADDR_AD1_VALID_GET(mpdu_info); 828 829 if (mac_addr_ad1_valid) { 830 addr->ad1_31_0 = HAL_RX_MPDU_AD1_31_0_GET(mpdu_info); 831 addr->ad1_47_32 = HAL_RX_MPDU_AD1_47_32_GET(mpdu_info); 832 return QDF_STATUS_SUCCESS; 833 } 834 835 return QDF_STATUS_E_FAILURE; 836 } 837 838 /* 839 * hal_rx_mpdu_get_addr2_6490(): API to check get address2 of the mpdu 840 * in the packet 841 * 842 * @buf: pointer to the start of RX PKT TLV header 843 * @mac_addr: pointer to mac address 844 * Return: success/failure 845 */ 846 static QDF_STATUS hal_rx_mpdu_get_addr2_6490(uint8_t *buf, 847 uint8_t *mac_addr) 848 { 849 struct __attribute__((__packed__)) hal_addr2 { 850 uint16_t ad2_15_0; 851 uint32_t ad2_47_16; 852 }; 853 854 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 855 struct rx_mpdu_start *mpdu_start = 856 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 857 858 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 859 struct hal_addr2 *addr = (struct hal_addr2 *)mac_addr; 860 uint32_t mac_addr_ad2_valid; 861 862 mac_addr_ad2_valid = HAL_RX_MPDU_MAC_ADDR_AD2_VALID_GET(mpdu_info); 863 864 if (mac_addr_ad2_valid) { 865 addr->ad2_15_0 = HAL_RX_MPDU_AD2_15_0_GET(mpdu_info); 866 addr->ad2_47_16 = HAL_RX_MPDU_AD2_47_16_GET(mpdu_info); 867 return QDF_STATUS_SUCCESS; 868 } 869 870 return QDF_STATUS_E_FAILURE; 871 } 872 873 /* 874 * hal_rx_mpdu_get_addr3_6490(): API to get address3 of the mpdu 875 * in the packet 876 * 877 * @buf: pointer to the start of RX PKT TLV header 878 * @mac_addr: pointer to mac address 879 * Return: success/failure 880 */ 881 static QDF_STATUS hal_rx_mpdu_get_addr3_6490(uint8_t *buf, uint8_t *mac_addr) 882 { 883 struct __attribute__((__packed__)) hal_addr3 { 884 uint32_t ad3_31_0; 885 uint16_t ad3_47_32; 886 }; 887 888 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 889 struct rx_mpdu_start *mpdu_start = 890 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 891 892 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 893 struct hal_addr3 *addr = (struct hal_addr3 *)mac_addr; 894 uint32_t mac_addr_ad3_valid; 895 896 mac_addr_ad3_valid = HAL_RX_MPDU_MAC_ADDR_AD3_VALID_GET(mpdu_info); 897 898 if (mac_addr_ad3_valid) { 899 addr->ad3_31_0 = HAL_RX_MPDU_AD3_31_0_GET(mpdu_info); 900 addr->ad3_47_32 = HAL_RX_MPDU_AD3_47_32_GET(mpdu_info); 901 return QDF_STATUS_SUCCESS; 902 } 903 904 return QDF_STATUS_E_FAILURE; 905 } 906 907 /* 908 * hal_rx_mpdu_get_addr4_6490(): API to get address4 of the mpdu 909 * in the packet 910 * 911 * @buf: pointer to the start of RX PKT TLV header 912 * @mac_addr: pointer to mac address 913 * Return: success/failure 914 */ 915 static QDF_STATUS hal_rx_mpdu_get_addr4_6490(uint8_t *buf, uint8_t *mac_addr) 916 { 917 struct __attribute__((__packed__)) hal_addr4 { 918 uint32_t ad4_31_0; 919 uint16_t ad4_47_32; 920 }; 921 922 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 923 struct rx_mpdu_start *mpdu_start = 924 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 925 926 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 927 struct hal_addr4 *addr = (struct hal_addr4 *)mac_addr; 928 uint32_t mac_addr_ad4_valid; 929 930 mac_addr_ad4_valid = HAL_RX_MPDU_MAC_ADDR_AD4_VALID_GET(mpdu_info); 931 932 if (mac_addr_ad4_valid) { 933 addr->ad4_31_0 = HAL_RX_MPDU_AD4_31_0_GET(mpdu_info); 934 addr->ad4_47_32 = HAL_RX_MPDU_AD4_47_32_GET(mpdu_info); 935 return QDF_STATUS_SUCCESS; 936 } 937 938 return QDF_STATUS_E_FAILURE; 939 } 940 941 /* 942 * hal_rx_get_mpdu_sequence_control_valid_6490(): Get mpdu 943 * sequence control valid 944 * 945 * @nbuf: Network buffer 946 * Returns: value of sequence control valid field 947 */ 948 static uint8_t hal_rx_get_mpdu_sequence_control_valid_6490(uint8_t *buf) 949 { 950 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 951 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 952 953 return HAL_RX_MPDU_GET_SEQUENCE_CONTROL_VALID(rx_mpdu_info); 954 } 955 956 /** 957 * hal_rx_is_unicast_6490: check packet is unicast frame or not. 958 * 959 * @ buf: pointer to rx pkt TLV. 960 * 961 * Return: true on unicast. 962 */ 963 static bool hal_rx_is_unicast_6490(uint8_t *buf) 964 { 965 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 966 struct rx_mpdu_start *mpdu_start = 967 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 968 uint32_t grp_id; 969 uint8_t *rx_mpdu_info = (uint8_t *)&mpdu_start->rx_mpdu_info_details; 970 971 grp_id = (_HAL_MS((*_OFFSET_TO_WORD_PTR((rx_mpdu_info), 972 RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_OFFSET)), 973 RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_MASK, 974 RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_LSB)); 975 976 return (HAL_MPDU_SW_FRAME_GROUP_UNICAST_DATA == grp_id) ? true : false; 977 } 978 979 /** 980 * hal_rx_tid_get_6490: get tid based on qos control valid. 981 * @hal_soc_hdl: hal_soc handle 982 * @ buf: pointer to rx pkt TLV. 983 * 984 * Return: tid 985 */ 986 static uint32_t hal_rx_tid_get_6490(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 987 { 988 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 989 struct rx_mpdu_start *mpdu_start = 990 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 991 uint8_t *rx_mpdu_info = (uint8_t *)&mpdu_start->rx_mpdu_info_details; 992 uint8_t qos_control_valid = 993 (_HAL_MS((*_OFFSET_TO_WORD_PTR((rx_mpdu_info), 994 RX_MPDU_INFO_11_MPDU_QOS_CONTROL_VALID_OFFSET)), 995 RX_MPDU_INFO_11_MPDU_QOS_CONTROL_VALID_MASK, 996 RX_MPDU_INFO_11_MPDU_QOS_CONTROL_VALID_LSB)); 997 998 if (qos_control_valid) 999 return hal_rx_mpdu_start_tid_get_6490(buf); 1000 1001 return HAL_RX_NON_QOS_TID; 1002 } 1003 1004 /** 1005 * hal_rx_hw_desc_get_ppduid_get_6490(): retrieve ppdu id 1006 * @rx_tlv_hdr: start address of rx_pkt_tlvs 1007 * @rxdma_dst_ring_desc: Rx HW descriptor 1008 * 1009 * Return: ppdu id 1010 */ 1011 static uint32_t hal_rx_hw_desc_get_ppduid_get_6490(void *rx_tlv_hdr, 1012 void *rxdma_dst_ring_desc) 1013 { 1014 struct rx_mpdu_info *rx_mpdu_info; 1015 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)rx_tlv_hdr; 1016 1017 rx_mpdu_info = 1018 &rx_desc->mpdu_start_tlv.rx_mpdu_start.rx_mpdu_info_details; 1019 1020 return HAL_RX_GET(rx_mpdu_info, RX_MPDU_INFO_9, PHY_PPDU_ID); 1021 } 1022 1023 /** 1024 * hal_reo_status_get_header_6490 - Process reo desc info 1025 * @ring_desc: REO status ring descriptor 1026 * @b - tlv type info 1027 * @h1 - Pointer to hal_reo_status_header where info to be stored 1028 * 1029 * Return - none. 1030 * 1031 */ 1032 static void hal_reo_status_get_header_6490(hal_ring_desc_t ring_desc, int b, 1033 void *h1) 1034 { 1035 uint32_t *d = (uint32_t *)ring_desc; 1036 uint32_t val1 = 0; 1037 struct hal_reo_status_header *h = 1038 (struct hal_reo_status_header *)h1; 1039 1040 /* Offsets of descriptor fields defined in HW headers start 1041 * from the field after TLV header 1042 */ 1043 d += HAL_GET_NUM_DWORDS(sizeof(struct tlv_32_hdr)); 1044 1045 switch (b) { 1046 case HAL_REO_QUEUE_STATS_STATUS_TLV: 1047 val1 = d[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_0, 1048 STATUS_HEADER_REO_STATUS_NUMBER)]; 1049 break; 1050 case HAL_REO_FLUSH_QUEUE_STATUS_TLV: 1051 val1 = d[HAL_OFFSET_DW(REO_FLUSH_QUEUE_STATUS_0, 1052 STATUS_HEADER_REO_STATUS_NUMBER)]; 1053 break; 1054 case HAL_REO_FLUSH_CACHE_STATUS_TLV: 1055 val1 = d[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_0, 1056 STATUS_HEADER_REO_STATUS_NUMBER)]; 1057 break; 1058 case HAL_REO_UNBLK_CACHE_STATUS_TLV: 1059 val1 = d[HAL_OFFSET_DW(REO_UNBLOCK_CACHE_STATUS_0, 1060 STATUS_HEADER_REO_STATUS_NUMBER)]; 1061 break; 1062 case HAL_REO_TIMOUT_LIST_STATUS_TLV: 1063 val1 = d[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_0, 1064 STATUS_HEADER_REO_STATUS_NUMBER)]; 1065 break; 1066 case HAL_REO_DESC_THRES_STATUS_TLV: 1067 val1 = 1068 d[HAL_OFFSET_DW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0, 1069 STATUS_HEADER_REO_STATUS_NUMBER)]; 1070 break; 1071 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: 1072 val1 = d[HAL_OFFSET_DW(REO_UPDATE_RX_REO_QUEUE_STATUS_0, 1073 STATUS_HEADER_REO_STATUS_NUMBER)]; 1074 break; 1075 default: 1076 qdf_nofl_err("ERROR: Unknown tlv\n"); 1077 break; 1078 } 1079 h->cmd_num = 1080 HAL_GET_FIELD( 1081 UNIFORM_REO_STATUS_HEADER_0, REO_STATUS_NUMBER, 1082 val1); 1083 h->exec_time = 1084 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_0, 1085 CMD_EXECUTION_TIME, val1); 1086 h->status = 1087 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_0, 1088 REO_CMD_EXECUTION_STATUS, val1); 1089 switch (b) { 1090 case HAL_REO_QUEUE_STATS_STATUS_TLV: 1091 val1 = d[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_1, 1092 STATUS_HEADER_TIMESTAMP)]; 1093 break; 1094 case HAL_REO_FLUSH_QUEUE_STATUS_TLV: 1095 val1 = d[HAL_OFFSET_DW(REO_FLUSH_QUEUE_STATUS_1, 1096 STATUS_HEADER_TIMESTAMP)]; 1097 break; 1098 case HAL_REO_FLUSH_CACHE_STATUS_TLV: 1099 val1 = d[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_1, 1100 STATUS_HEADER_TIMESTAMP)]; 1101 break; 1102 case HAL_REO_UNBLK_CACHE_STATUS_TLV: 1103 val1 = d[HAL_OFFSET_DW(REO_UNBLOCK_CACHE_STATUS_1, 1104 STATUS_HEADER_TIMESTAMP)]; 1105 break; 1106 case HAL_REO_TIMOUT_LIST_STATUS_TLV: 1107 val1 = d[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_1, 1108 STATUS_HEADER_TIMESTAMP)]; 1109 break; 1110 case HAL_REO_DESC_THRES_STATUS_TLV: 1111 val1 = 1112 d[HAL_OFFSET_DW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_1, 1113 STATUS_HEADER_TIMESTAMP)]; 1114 break; 1115 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: 1116 val1 = d[HAL_OFFSET_DW(REO_UPDATE_RX_REO_QUEUE_STATUS_1, 1117 STATUS_HEADER_TIMESTAMP)]; 1118 break; 1119 default: 1120 qdf_nofl_err("ERROR: Unknown tlv\n"); 1121 break; 1122 } 1123 h->tstamp = 1124 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_1, TIMESTAMP, val1); 1125 } 1126 1127 /** 1128 * hal_tx_desc_set_mesh_en_6490 - Set mesh_enable flag in Tx descriptor 1129 * @desc: Handle to Tx Descriptor 1130 * @en: For raw WiFi frames, this indicates transmission to a mesh STA, 1131 * enabling the interpretation of the 'Mesh Control Present' bit 1132 * (bit 8) of QoS Control (otherwise this bit is ignored), 1133 * For native WiFi frames, this indicates that a 'Mesh Control' field 1134 * is present between the header and the LLC. 1135 * 1136 * Return: void 1137 */ 1138 static inline 1139 void hal_tx_desc_set_mesh_en_6490(void *desc, uint8_t en) 1140 { 1141 HAL_SET_FLD(desc, TCL_DATA_CMD_5, MESH_ENABLE) |= 1142 HAL_TX_SM(TCL_DATA_CMD_5, MESH_ENABLE, en); 1143 } 1144 1145 static 1146 void *hal_rx_msdu0_buffer_addr_lsb_6490(void *link_desc_va) 1147 { 1148 return (void *)HAL_RX_MSDU0_BUFFER_ADDR_LSB(link_desc_va); 1149 } 1150 1151 static 1152 void *hal_rx_msdu_desc_info_ptr_get_6490(void *msdu0) 1153 { 1154 return (void *)HAL_RX_MSDU_DESC_INFO_PTR_GET(msdu0); 1155 } 1156 1157 static 1158 void *hal_ent_mpdu_desc_info_6490(void *ent_ring_desc) 1159 { 1160 return (void *)HAL_ENT_MPDU_DESC_INFO(ent_ring_desc); 1161 } 1162 1163 static 1164 void *hal_dst_mpdu_desc_info_6490(void *dst_ring_desc) 1165 { 1166 return (void *)HAL_DST_MPDU_DESC_INFO(dst_ring_desc); 1167 } 1168 1169 static 1170 uint8_t hal_rx_get_fc_valid_6490(uint8_t *buf) 1171 { 1172 return HAL_RX_GET_FC_VALID(buf); 1173 } 1174 1175 static uint8_t hal_rx_get_to_ds_flag_6490(uint8_t *buf) 1176 { 1177 return HAL_RX_GET_TO_DS_FLAG(buf); 1178 } 1179 1180 static uint8_t hal_rx_get_mac_addr2_valid_6490(uint8_t *buf) 1181 { 1182 return HAL_RX_GET_MAC_ADDR2_VALID(buf); 1183 } 1184 1185 static uint8_t hal_rx_get_filter_category_6490(uint8_t *buf) 1186 { 1187 return HAL_RX_GET_FILTER_CATEGORY(buf); 1188 } 1189 1190 static uint32_t 1191 hal_rx_get_ppdu_id_6490(uint8_t *buf) 1192 { 1193 return HAL_RX_GET_PPDU_ID(buf); 1194 } 1195 1196 /** 1197 * hal_reo_config_6490(): Set reo config parameters 1198 * @soc: hal soc handle 1199 * @reg_val: value to be set 1200 * @reo_params: reo parameters 1201 * 1202 * Return: void 1203 */ 1204 static 1205 void hal_reo_config_6490(struct hal_soc *soc, 1206 uint32_t reg_val, 1207 struct hal_reo_params *reo_params) 1208 { 1209 HAL_REO_R0_CONFIG(soc, reg_val, reo_params); 1210 } 1211 1212 /** 1213 * hal_rx_msdu_desc_info_get_ptr_6490() - Get msdu desc info ptr 1214 * @msdu_details_ptr - Pointer to msdu_details_ptr 1215 * 1216 * Return - Pointer to rx_msdu_desc_info structure. 1217 * 1218 */ 1219 static void *hal_rx_msdu_desc_info_get_ptr_6490(void *msdu_details_ptr) 1220 { 1221 return HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr); 1222 } 1223 1224 /** 1225 * hal_rx_link_desc_msdu0_ptr_6490 - Get pointer to rx_msdu details 1226 * @link_desc - Pointer to link desc 1227 * 1228 * Return - Pointer to rx_msdu_details structure 1229 * 1230 */ 1231 static void *hal_rx_link_desc_msdu0_ptr_6490(void *link_desc) 1232 { 1233 return HAL_RX_LINK_DESC_MSDU0_PTR(link_desc); 1234 } 1235 1236 /** 1237 * hal_rx_msdu_flow_idx_get_6490: API to get flow index 1238 * from rx_msdu_end TLV 1239 * @buf: pointer to the start of RX PKT TLV headers 1240 * 1241 * Return: flow index value from MSDU END TLV 1242 */ 1243 static inline uint32_t hal_rx_msdu_flow_idx_get_6490(uint8_t *buf) 1244 { 1245 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1246 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1247 1248 return HAL_RX_MSDU_END_FLOW_IDX_GET(msdu_end); 1249 } 1250 1251 /** 1252 * hal_rx_msdu_get_reo_destination_indication_6490: API to get 1253 * reo_destination_indication from rx_msdu_end TLV 1254 * @buf: pointer to the start of RX PKT TLV headers 1255 * @reo_destination_indication: pointer to return value of reo_destination_indication 1256 * 1257 * Return: none 1258 */ 1259 static inline void 1260 hal_rx_msdu_get_reo_destination_indication_6490(uint8_t *buf, 1261 uint32_t *reo_destination_indication) 1262 { 1263 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1264 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1265 1266 *reo_destination_indication = HAL_RX_MSDU_END_REO_DEST_IND_GET(msdu_end); 1267 } 1268 1269 /** 1270 * hal_rx_msdu_flow_idx_invalid_6490: API to get flow index invalid 1271 * from rx_msdu_end TLV 1272 * @buf: pointer to the start of RX PKT TLV headers 1273 * 1274 * Return: flow index invalid value from MSDU END TLV 1275 */ 1276 static bool hal_rx_msdu_flow_idx_invalid_6490(uint8_t *buf) 1277 { 1278 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1279 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1280 1281 return HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(msdu_end); 1282 } 1283 1284 /** 1285 * hal_rx_msdu_flow_idx_timeout_6490: API to get flow index timeout 1286 * from rx_msdu_end TLV 1287 * @buf: pointer to the start of RX PKT TLV headers 1288 * 1289 * Return: flow index timeout value from MSDU END TLV 1290 */ 1291 static bool hal_rx_msdu_flow_idx_timeout_6490(uint8_t *buf) 1292 { 1293 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1294 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1295 1296 return HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(msdu_end); 1297 } 1298 1299 /** 1300 * hal_rx_msdu_fse_metadata_get_6490: API to get FSE metadata 1301 * from rx_msdu_end TLV 1302 * @buf: pointer to the start of RX PKT TLV headers 1303 * 1304 * Return: fse metadata value from MSDU END TLV 1305 */ 1306 static uint32_t hal_rx_msdu_fse_metadata_get_6490(uint8_t *buf) 1307 { 1308 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1309 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1310 1311 return HAL_RX_MSDU_END_FSE_METADATA_GET(msdu_end); 1312 } 1313 1314 /** 1315 * hal_rx_msdu_cce_metadata_get_6490: API to get CCE metadata 1316 * from rx_msdu_end TLV 1317 * @buf: pointer to the start of RX PKT TLV headers 1318 * 1319 * Return: cce_metadata 1320 */ 1321 static uint16_t 1322 hal_rx_msdu_cce_metadata_get_6490(uint8_t *buf) 1323 { 1324 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1325 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1326 1327 return HAL_RX_MSDU_END_CCE_METADATA_GET(msdu_end); 1328 } 1329 1330 /** 1331 * hal_rx_msdu_get_flow_params_6490: API to get flow index, flow index invalid 1332 * and flow index timeout from rx_msdu_end TLV 1333 * @buf: pointer to the start of RX PKT TLV headers 1334 * @flow_invalid: pointer to return value of flow_idx_valid 1335 * @flow_timeout: pointer to return value of flow_idx_timeout 1336 * @flow_index: pointer to return value of flow_idx 1337 * 1338 * Return: none 1339 */ 1340 static inline void 1341 hal_rx_msdu_get_flow_params_6490(uint8_t *buf, 1342 bool *flow_invalid, 1343 bool *flow_timeout, 1344 uint32_t *flow_index) 1345 { 1346 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1347 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1348 1349 *flow_invalid = HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(msdu_end); 1350 *flow_timeout = HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(msdu_end); 1351 *flow_index = HAL_RX_MSDU_END_FLOW_IDX_GET(msdu_end); 1352 } 1353 1354 /** 1355 * hal_rx_tlv_get_tcp_chksum_6490() - API to get tcp checksum 1356 * @buf: rx_tlv_hdr 1357 * 1358 * Return: tcp checksum 1359 */ 1360 static uint16_t 1361 hal_rx_tlv_get_tcp_chksum_6490(uint8_t *buf) 1362 { 1363 return HAL_RX_TLV_GET_TCP_CHKSUM(buf); 1364 } 1365 1366 /** 1367 * hal_rx_get_rx_sequence_6490(): Function to retrieve rx sequence number 1368 * 1369 * @nbuf: Network buffer 1370 * Returns: rx sequence number 1371 */ 1372 static 1373 uint16_t hal_rx_get_rx_sequence_6490(uint8_t *buf) 1374 { 1375 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 1376 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 1377 1378 return HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info); 1379 } 1380 1381 /** 1382 * hal_get_window_address_6490(): Function to get hp/tp address 1383 * @hal_soc: Pointer to hal_soc 1384 * @addr: address offset of register 1385 * 1386 * Return: modified address offset of register 1387 */ 1388 static inline qdf_iomem_t hal_get_window_address_6490(struct hal_soc *hal_soc, 1389 qdf_iomem_t addr) 1390 { 1391 return addr; 1392 } 1393 1394 /** 1395 * hal_rx_get_fisa_cumulative_l4_checksum_6490() - Retrieve cumulative 1396 * checksum 1397 * @buf: buffer pointer 1398 * 1399 * Return: cumulative checksum 1400 */ 1401 static inline 1402 uint16_t hal_rx_get_fisa_cumulative_l4_checksum_6490(uint8_t *buf) 1403 { 1404 return HAL_RX_TLV_GET_FISA_CUMULATIVE_L4_CHECKSUM(buf); 1405 } 1406 1407 /** 1408 * hal_rx_get_fisa_cumulative_ip_length_6490() - Retrieve cumulative 1409 * ip length 1410 * @buf: buffer pointer 1411 * 1412 * Return: cumulative length 1413 */ 1414 static inline 1415 uint16_t hal_rx_get_fisa_cumulative_ip_length_6490(uint8_t *buf) 1416 { 1417 return HAL_RX_TLV_GET_FISA_CUMULATIVE_IP_LENGTH(buf); 1418 } 1419 1420 /** 1421 * hal_rx_get_udp_proto_6490() - Retrieve udp proto value 1422 * @buf: buffer 1423 * 1424 * Return: udp proto bit 1425 */ 1426 static inline 1427 bool hal_rx_get_udp_proto_6490(uint8_t *buf) 1428 { 1429 return HAL_RX_TLV_GET_UDP_PROTO(buf); 1430 } 1431 1432 /** 1433 * hal_rx_get_flow_agg_continuation_6490() - retrieve flow agg 1434 * continuation 1435 * @buf: buffer 1436 * 1437 * Return: flow agg 1438 */ 1439 static inline 1440 bool hal_rx_get_flow_agg_continuation_6490(uint8_t *buf) 1441 { 1442 return HAL_RX_TLV_GET_FLOW_AGGR_CONT(buf); 1443 } 1444 1445 /** 1446 * hal_rx_get_flow_agg_count_6490()- Retrieve flow agg count 1447 * @buf: buffer 1448 * 1449 * Return: flow agg count 1450 */ 1451 static inline 1452 uint8_t hal_rx_get_flow_agg_count_6490(uint8_t *buf) 1453 { 1454 return HAL_RX_TLV_GET_FLOW_AGGR_COUNT(buf); 1455 } 1456 1457 /** 1458 * hal_rx_get_fisa_timeout_6490() - Retrieve fisa timeout 1459 * @buf: buffer 1460 * 1461 * Return: fisa timeout 1462 */ 1463 static inline 1464 bool hal_rx_get_fisa_timeout_6490(uint8_t *buf) 1465 { 1466 return HAL_RX_TLV_GET_FISA_TIMEOUT(buf); 1467 } 1468 1469 /** 1470 * hal_rx_mpdu_start_tlv_tag_valid_6490 () - API to check if RX_MPDU_START 1471 * tlv tag is valid 1472 * 1473 *@rx_tlv_hdr: start address of rx_pkt_tlvs 1474 * 1475 * Return: true if RX_MPDU_START is valied, else false. 1476 */ 1477 static uint8_t hal_rx_mpdu_start_tlv_tag_valid_6490(void *rx_tlv_hdr) 1478 { 1479 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)rx_tlv_hdr; 1480 uint32_t tlv_tag; 1481 1482 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(&rx_desc->mpdu_start_tlv); 1483 1484 return tlv_tag == WIFIRX_MPDU_START_E ? true : false; 1485 } 1486 1487 /** 1488 * hal_reo_set_err_dst_remap_6490(): Function to set REO error destination 1489 * ring remap register 1490 * @hal_soc: Pointer to hal_soc 1491 * 1492 * Return: none. 1493 */ 1494 static void 1495 hal_reo_set_err_dst_remap_6490(void *hal_soc) 1496 { 1497 /* 1498 * Set REO error 2k jump (error code 5) / OOR (error code 7) 1499 * frame routed to REO2TCL ring. 1500 */ 1501 uint32_t dst_remap_ix0 = 1502 HAL_REO_ERR_REMAP_IX0(REO_REMAP_RELEASE, 0) | 1503 HAL_REO_ERR_REMAP_IX0(REO_REMAP_RELEASE, 1) | 1504 HAL_REO_ERR_REMAP_IX0(REO_REMAP_RELEASE, 2) | 1505 HAL_REO_ERR_REMAP_IX0(REO_REMAP_RELEASE, 3) | 1506 HAL_REO_ERR_REMAP_IX0(REO_REMAP_RELEASE, 4) | 1507 HAL_REO_ERR_REMAP_IX0(REO_REMAP_TCL, 5) | 1508 HAL_REO_ERR_REMAP_IX0(REO_REMAP_TCL, 6) | 1509 HAL_REO_ERR_REMAP_IX0(REO_REMAP_TCL, 7); 1510 1511 uint32_t dst_remap_ix1 = 1512 HAL_REO_ERR_REMAP_IX1(REO_REMAP_RELEASE, 14) | 1513 HAL_REO_ERR_REMAP_IX1(REO_REMAP_RELEASE, 13) | 1514 HAL_REO_ERR_REMAP_IX1(REO_REMAP_RELEASE, 12) | 1515 HAL_REO_ERR_REMAP_IX1(REO_REMAP_RELEASE, 11) | 1516 HAL_REO_ERR_REMAP_IX1(REO_REMAP_RELEASE, 10) | 1517 HAL_REO_ERR_REMAP_IX1(REO_REMAP_RELEASE, 9) | 1518 HAL_REO_ERR_REMAP_IX1(REO_REMAP_TCL, 8); 1519 1520 HAL_REG_WRITE(hal_soc, 1521 HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ADDR( 1522 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1523 dst_remap_ix0); 1524 1525 hal_info("HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0 0x%x", 1526 HAL_REG_READ( 1527 hal_soc, 1528 HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ADDR( 1529 SEQ_WCSS_UMAC_REO_REG_OFFSET))); 1530 1531 HAL_REG_WRITE(hal_soc, 1532 HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ADDR( 1533 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1534 dst_remap_ix1); 1535 1536 hal_info("HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1 0x%x", 1537 HAL_REG_READ( 1538 hal_soc, 1539 HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ADDR( 1540 SEQ_WCSS_UMAC_REO_REG_OFFSET))); 1541 } 1542 1543 /** 1544 * hal_rx_flow_setup_fse_6490() - Setup a flow search entry in HW FST 1545 * @fst: Pointer to the Rx Flow Search Table 1546 * @table_offset: offset into the table where the flow is to be setup 1547 * @flow: Flow Parameters 1548 * 1549 * Flow table entry fields are updated in host byte order, little endian order. 1550 * 1551 * Return: Success/Failure 1552 */ 1553 static void * 1554 hal_rx_flow_setup_fse_6490(uint8_t *rx_fst, uint32_t table_offset, 1555 uint8_t *rx_flow) 1556 { 1557 struct hal_rx_fst *fst = (struct hal_rx_fst *)rx_fst; 1558 struct hal_rx_flow *flow = (struct hal_rx_flow *)rx_flow; 1559 uint8_t *fse; 1560 bool fse_valid; 1561 1562 if (table_offset >= fst->max_entries) { 1563 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR, 1564 "HAL FSE table offset %u exceeds max entries %u", 1565 table_offset, fst->max_entries); 1566 return NULL; 1567 } 1568 1569 fse = (uint8_t *)fst->base_vaddr + 1570 (table_offset * HAL_RX_FST_ENTRY_SIZE); 1571 1572 fse_valid = HAL_GET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, VALID); 1573 1574 if (fse_valid) { 1575 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_DEBUG, 1576 "HAL FSE %pK already valid", fse); 1577 return NULL; 1578 } 1579 1580 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_0, SRC_IP_127_96) = 1581 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_0, SRC_IP_127_96, 1582 (flow->tuple_info.src_ip_127_96)); 1583 1584 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_1, SRC_IP_95_64) = 1585 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_1, SRC_IP_95_64, 1586 (flow->tuple_info.src_ip_95_64)); 1587 1588 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_2, SRC_IP_63_32) = 1589 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_2, SRC_IP_63_32, 1590 (flow->tuple_info.src_ip_63_32)); 1591 1592 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_3, SRC_IP_31_0) = 1593 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_3, SRC_IP_31_0, 1594 (flow->tuple_info.src_ip_31_0)); 1595 1596 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_4, DEST_IP_127_96) = 1597 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_4, DEST_IP_127_96, 1598 (flow->tuple_info.dest_ip_127_96)); 1599 1600 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_5, DEST_IP_95_64) = 1601 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_5, DEST_IP_95_64, 1602 (flow->tuple_info.dest_ip_95_64)); 1603 1604 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_6, DEST_IP_63_32) = 1605 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_6, DEST_IP_63_32, 1606 (flow->tuple_info.dest_ip_63_32)); 1607 1608 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_7, DEST_IP_31_0) = 1609 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_7, DEST_IP_31_0, 1610 (flow->tuple_info.dest_ip_31_0)); 1611 1612 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, DEST_PORT); 1613 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, DEST_PORT) |= 1614 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_8, DEST_PORT, 1615 (flow->tuple_info.dest_port)); 1616 1617 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, SRC_PORT); 1618 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, SRC_PORT) |= 1619 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_8, SRC_PORT, 1620 (flow->tuple_info.src_port)); 1621 1622 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, L4_PROTOCOL); 1623 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, L4_PROTOCOL) |= 1624 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, L4_PROTOCOL, 1625 flow->tuple_info.l4_protocol); 1626 1627 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_HANDLER); 1628 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_HANDLER) |= 1629 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_HANDLER, 1630 flow->reo_destination_handler); 1631 1632 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, VALID); 1633 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, VALID) |= 1634 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, VALID, 1); 1635 1636 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_10, METADATA); 1637 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_10, METADATA) = 1638 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_10, METADATA, 1639 (flow->fse_metadata)); 1640 1641 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_INDICATION); 1642 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_INDICATION) |= 1643 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, 1644 REO_DESTINATION_INDICATION, 1645 flow->reo_destination_indication); 1646 1647 /* Reset all the other fields in FSE */ 1648 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, RESERVED_9); 1649 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, MSDU_DROP); 1650 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_11, MSDU_COUNT); 1651 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_12, MSDU_BYTE_COUNT); 1652 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_13, TIMESTAMP); 1653 1654 return fse; 1655 } 1656 1657 static 1658 void hal_compute_reo_remap_ix2_ix3_6490(uint32_t *ring, uint32_t num_rings, 1659 uint32_t *remap1, uint32_t *remap2) 1660 { 1661 switch (num_rings) { 1662 case 3: 1663 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 1664 HAL_REO_REMAP_IX2(ring[1], 17) | 1665 HAL_REO_REMAP_IX2(ring[2], 18) | 1666 HAL_REO_REMAP_IX2(ring[0], 19) | 1667 HAL_REO_REMAP_IX2(ring[1], 20) | 1668 HAL_REO_REMAP_IX2(ring[2], 21) | 1669 HAL_REO_REMAP_IX2(ring[0], 22) | 1670 HAL_REO_REMAP_IX2(ring[1], 23); 1671 1672 *remap2 = HAL_REO_REMAP_IX3(ring[2], 24) | 1673 HAL_REO_REMAP_IX3(ring[0], 25) | 1674 HAL_REO_REMAP_IX3(ring[1], 26) | 1675 HAL_REO_REMAP_IX3(ring[2], 27) | 1676 HAL_REO_REMAP_IX3(ring[0], 28) | 1677 HAL_REO_REMAP_IX3(ring[1], 29) | 1678 HAL_REO_REMAP_IX3(ring[2], 30) | 1679 HAL_REO_REMAP_IX3(ring[0], 31); 1680 break; 1681 case 4: 1682 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 1683 HAL_REO_REMAP_IX2(ring[1], 17) | 1684 HAL_REO_REMAP_IX2(ring[2], 18) | 1685 HAL_REO_REMAP_IX2(ring[3], 19) | 1686 HAL_REO_REMAP_IX2(ring[0], 20) | 1687 HAL_REO_REMAP_IX2(ring[1], 21) | 1688 HAL_REO_REMAP_IX2(ring[2], 22) | 1689 HAL_REO_REMAP_IX2(ring[3], 23); 1690 1691 *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) | 1692 HAL_REO_REMAP_IX3(ring[1], 25) | 1693 HAL_REO_REMAP_IX3(ring[2], 26) | 1694 HAL_REO_REMAP_IX3(ring[3], 27) | 1695 HAL_REO_REMAP_IX3(ring[0], 28) | 1696 HAL_REO_REMAP_IX3(ring[1], 29) | 1697 HAL_REO_REMAP_IX3(ring[2], 30) | 1698 HAL_REO_REMAP_IX3(ring[3], 31); 1699 break; 1700 } 1701 } 1702 1703 static 1704 void hal_compute_reo_remap_ix0_6490(uint32_t *remap0) 1705 { 1706 *remap0 = HAL_REO_REMAP_IX0(REO_REMAP_SW1, 0) | 1707 HAL_REO_REMAP_IX0(REO_REMAP_SW1, 1) | 1708 HAL_REO_REMAP_IX0(REO_REMAP_SW2, 2) | 1709 HAL_REO_REMAP_IX0(REO_REMAP_SW3, 3) | 1710 HAL_REO_REMAP_IX0(REO_REMAP_SW2, 4) | 1711 HAL_REO_REMAP_IX0(REO_REMAP_RELEASE, 5) | 1712 HAL_REO_REMAP_IX0(REO_REMAP_FW, 6) | 1713 HAL_REO_REMAP_IX0(REO_REMAP_FW, 7); 1714 } 1715 1716 #ifdef WLAN_FEATURE_MARK_FIRST_WAKEUP_PACKET 1717 /** 1718 * hal_get_first_wow_wakeup_packet_6490(): Function to retrieve 1719 * rx_msdu_end_1_reserved_1a 1720 * 1721 * reserved_1a is used by target to tag the first packet that wakes up host from 1722 * WoW 1723 * 1724 * @buf: Network buffer 1725 * 1726 * Returns: 1 to indicate it is first packet received that wakes up host from 1727 * WoW. Otherwise 0 1728 */ 1729 static uint8_t hal_get_first_wow_wakeup_packet_6490(uint8_t *buf) 1730 { 1731 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 1732 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1733 1734 return HAL_RX_MSDU_END_RESERVED_1A_GET(msdu_end); 1735 } 1736 #endif 1737 1738 /** 1739 * hal_rx_tlv_l3_type_get_6490(): Function to retrieve l3_type 1740 * 1741 * @buf: Network buffer 1742 * 1743 * Returns: l3_type 1744 */ 1745 static uint32_t hal_rx_tlv_l3_type_get_6490(uint8_t *buf) 1746 { 1747 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 1748 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1749 1750 return HAL_RX_MSDU_END_L3_TYPE_GET(msdu_end); 1751 } 1752 1753 static void hal_hw_txrx_ops_attach_qca6490(struct hal_soc *hal_soc) 1754 { 1755 /* init and setup */ 1756 hal_soc->ops->hal_srng_dst_hw_init = hal_srng_dst_hw_init_generic; 1757 hal_soc->ops->hal_srng_src_hw_init = hal_srng_src_hw_init_generic; 1758 hal_soc->ops->hal_get_hw_hptp = hal_get_hw_hptp_generic; 1759 hal_soc->ops->hal_reo_setup = hal_reo_setup_generic_li; 1760 hal_soc->ops->hal_get_window_address = hal_get_window_address_6490; 1761 hal_soc->ops->hal_reo_set_err_dst_remap = 1762 hal_reo_set_err_dst_remap_6490; 1763 1764 /* tx */ 1765 hal_soc->ops->hal_tx_desc_set_dscp_tid_table_id = 1766 hal_tx_desc_set_dscp_tid_table_id_6490; 1767 hal_soc->ops->hal_tx_set_dscp_tid_map = hal_tx_set_dscp_tid_map_6490; 1768 hal_soc->ops->hal_tx_update_dscp_tid = hal_tx_update_dscp_tid_6490; 1769 hal_soc->ops->hal_tx_desc_set_lmac_id = hal_tx_desc_set_lmac_id_6490; 1770 hal_soc->ops->hal_tx_desc_set_buf_addr = 1771 hal_tx_desc_set_buf_addr_generic_li; 1772 hal_soc->ops->hal_tx_desc_set_search_type = 1773 hal_tx_desc_set_search_type_generic_li; 1774 hal_soc->ops->hal_tx_desc_set_search_index = 1775 hal_tx_desc_set_search_index_generic_li; 1776 hal_soc->ops->hal_tx_desc_set_cache_set_num = 1777 hal_tx_desc_set_cache_set_num_generic_li; 1778 hal_soc->ops->hal_tx_comp_get_status = 1779 hal_tx_comp_get_status_generic_li; 1780 hal_soc->ops->hal_tx_comp_get_release_reason = 1781 hal_tx_comp_get_release_reason_generic_li; 1782 hal_soc->ops->hal_get_wbm_internal_error = 1783 hal_get_wbm_internal_error_generic_li; 1784 hal_soc->ops->hal_tx_desc_set_mesh_en = hal_tx_desc_set_mesh_en_6490; 1785 hal_soc->ops->hal_tx_init_cmd_credit_ring = 1786 hal_tx_init_cmd_credit_ring_6490; 1787 1788 /* rx */ 1789 hal_soc->ops->hal_rx_msdu_start_nss_get = 1790 hal_rx_msdu_start_nss_get_6490; 1791 hal_soc->ops->hal_rx_mon_hw_desc_get_mpdu_status = 1792 hal_rx_mon_hw_desc_get_mpdu_status_6490; 1793 hal_soc->ops->hal_rx_get_tlv = hal_rx_get_tlv_6490; 1794 hal_soc->ops->hal_rx_proc_phyrx_other_receive_info_tlv = 1795 hal_rx_proc_phyrx_other_receive_info_tlv_6490; 1796 hal_soc->ops->hal_rx_dump_msdu_start_tlv = 1797 hal_rx_dump_msdu_start_tlv_6490; 1798 hal_soc->ops->hal_rx_dump_msdu_end_tlv = hal_rx_dump_msdu_end_tlv_6490; 1799 hal_soc->ops->hal_get_link_desc_size = hal_get_link_desc_size_6490; 1800 hal_soc->ops->hal_rx_mpdu_start_tid_get = 1801 hal_rx_mpdu_start_tid_get_6490; 1802 hal_soc->ops->hal_rx_msdu_start_reception_type_get = 1803 hal_rx_msdu_start_reception_type_get_6490; 1804 hal_soc->ops->hal_rx_msdu_end_da_idx_get = 1805 hal_rx_msdu_end_da_idx_get_6490; 1806 hal_soc->ops->hal_rx_msdu_desc_info_get_ptr = 1807 hal_rx_msdu_desc_info_get_ptr_6490; 1808 hal_soc->ops->hal_rx_link_desc_msdu0_ptr = 1809 hal_rx_link_desc_msdu0_ptr_6490; 1810 hal_soc->ops->hal_reo_status_get_header = 1811 hal_reo_status_get_header_6490; 1812 hal_soc->ops->hal_rx_status_get_tlv_info = 1813 hal_rx_status_get_tlv_info_generic_li; 1814 hal_soc->ops->hal_rx_wbm_err_info_get = 1815 hal_rx_wbm_err_info_get_generic_li; 1816 hal_soc->ops->hal_rx_dump_mpdu_start_tlv = 1817 hal_rx_dump_mpdu_start_tlv_generic_li; 1818 1819 hal_soc->ops->hal_tx_set_pcp_tid_map = 1820 hal_tx_set_pcp_tid_map_generic_li; 1821 hal_soc->ops->hal_tx_update_pcp_tid_map = 1822 hal_tx_update_pcp_tid_generic_li; 1823 hal_soc->ops->hal_tx_set_tidmap_prty = 1824 hal_tx_update_tidmap_prty_generic_li; 1825 hal_soc->ops->hal_rx_get_rx_fragment_number = 1826 hal_rx_get_rx_fragment_number_6490; 1827 hal_soc->ops->hal_rx_msdu_end_da_is_mcbc_get = 1828 hal_rx_msdu_end_da_is_mcbc_get_6490; 1829 hal_soc->ops->hal_rx_msdu_end_sa_is_valid_get = 1830 hal_rx_msdu_end_sa_is_valid_get_6490; 1831 hal_soc->ops->hal_rx_msdu_end_sa_idx_get = 1832 hal_rx_msdu_end_sa_idx_get_6490; 1833 hal_soc->ops->hal_rx_desc_is_first_msdu = 1834 hal_rx_desc_is_first_msdu_6490; 1835 hal_soc->ops->hal_rx_msdu_end_l3_hdr_padding_get = 1836 hal_rx_msdu_end_l3_hdr_padding_get_6490; 1837 hal_soc->ops->hal_rx_encryption_info_valid = 1838 hal_rx_encryption_info_valid_6490; 1839 hal_soc->ops->hal_rx_print_pn = hal_rx_print_pn_6490; 1840 hal_soc->ops->hal_rx_msdu_end_first_msdu_get = 1841 hal_rx_msdu_end_first_msdu_get_6490; 1842 hal_soc->ops->hal_rx_msdu_end_da_is_valid_get = 1843 hal_rx_msdu_end_da_is_valid_get_6490; 1844 hal_soc->ops->hal_rx_msdu_end_last_msdu_get = 1845 hal_rx_msdu_end_last_msdu_get_6490; 1846 hal_soc->ops->hal_rx_get_mpdu_mac_ad4_valid = 1847 hal_rx_get_mpdu_mac_ad4_valid_6490; 1848 hal_soc->ops->hal_rx_mpdu_start_sw_peer_id_get = 1849 hal_rx_mpdu_start_sw_peer_id_get_6490; 1850 hal_soc->ops->hal_rx_tlv_peer_meta_data_get = 1851 hal_rx_mpdu_peer_meta_data_get_li; 1852 hal_soc->ops->hal_rx_mpdu_get_to_ds = hal_rx_mpdu_get_to_ds_6490; 1853 hal_soc->ops->hal_rx_mpdu_get_fr_ds = hal_rx_mpdu_get_fr_ds_6490; 1854 hal_soc->ops->hal_rx_get_mpdu_frame_control_valid = 1855 hal_rx_get_mpdu_frame_control_valid_6490; 1856 hal_soc->ops->hal_rx_get_frame_ctrl_field = 1857 hal_rx_get_frame_ctrl_field_li; 1858 hal_soc->ops->hal_rx_mpdu_get_addr1 = hal_rx_mpdu_get_addr1_6490; 1859 hal_soc->ops->hal_rx_mpdu_get_addr2 = hal_rx_mpdu_get_addr2_6490; 1860 hal_soc->ops->hal_rx_mpdu_get_addr3 = hal_rx_mpdu_get_addr3_6490; 1861 hal_soc->ops->hal_rx_mpdu_get_addr4 = hal_rx_mpdu_get_addr4_6490; 1862 hal_soc->ops->hal_rx_get_mpdu_sequence_control_valid = 1863 hal_rx_get_mpdu_sequence_control_valid_6490; 1864 hal_soc->ops->hal_rx_is_unicast = hal_rx_is_unicast_6490; 1865 hal_soc->ops->hal_rx_tid_get = hal_rx_tid_get_6490; 1866 hal_soc->ops->hal_rx_hw_desc_get_ppduid_get = 1867 hal_rx_hw_desc_get_ppduid_get_6490; 1868 hal_soc->ops->hal_rx_msdu0_buffer_addr_lsb = 1869 hal_rx_msdu0_buffer_addr_lsb_6490; 1870 hal_soc->ops->hal_rx_msdu_desc_info_ptr_get = 1871 hal_rx_msdu_desc_info_ptr_get_6490; 1872 hal_soc->ops->hal_ent_mpdu_desc_info = hal_ent_mpdu_desc_info_6490; 1873 hal_soc->ops->hal_dst_mpdu_desc_info = hal_dst_mpdu_desc_info_6490; 1874 hal_soc->ops->hal_rx_get_fc_valid = hal_rx_get_fc_valid_6490; 1875 hal_soc->ops->hal_rx_get_to_ds_flag = hal_rx_get_to_ds_flag_6490; 1876 hal_soc->ops->hal_rx_get_mac_addr2_valid = 1877 hal_rx_get_mac_addr2_valid_6490; 1878 hal_soc->ops->hal_rx_get_filter_category = 1879 hal_rx_get_filter_category_6490; 1880 hal_soc->ops->hal_rx_get_ppdu_id = hal_rx_get_ppdu_id_6490; 1881 hal_soc->ops->hal_reo_config = hal_reo_config_6490; 1882 hal_soc->ops->hal_rx_msdu_flow_idx_get = hal_rx_msdu_flow_idx_get_6490; 1883 hal_soc->ops->hal_rx_msdu_flow_idx_invalid = 1884 hal_rx_msdu_flow_idx_invalid_6490; 1885 hal_soc->ops->hal_rx_msdu_flow_idx_timeout = 1886 hal_rx_msdu_flow_idx_timeout_6490; 1887 hal_soc->ops->hal_rx_msdu_fse_metadata_get = 1888 hal_rx_msdu_fse_metadata_get_6490; 1889 hal_soc->ops->hal_rx_msdu_cce_match_get = 1890 hal_rx_msdu_cce_match_get_li; 1891 hal_soc->ops->hal_rx_msdu_cce_metadata_get = 1892 hal_rx_msdu_cce_metadata_get_6490; 1893 hal_soc->ops->hal_rx_msdu_get_flow_params = 1894 hal_rx_msdu_get_flow_params_6490; 1895 hal_soc->ops->hal_rx_tlv_get_tcp_chksum = 1896 hal_rx_tlv_get_tcp_chksum_6490; 1897 hal_soc->ops->hal_rx_get_rx_sequence = hal_rx_get_rx_sequence_6490; 1898 #if defined(QCA_WIFI_QCA6490) && defined(WLAN_CFR_ENABLE) && \ 1899 defined(WLAN_ENH_CFR_ENABLE) 1900 hal_soc->ops->hal_rx_get_bb_info = hal_rx_get_bb_info_6490; 1901 hal_soc->ops->hal_rx_get_rtt_info = hal_rx_get_rtt_info_6490; 1902 #endif 1903 /* rx - msdu end fast path info fields */ 1904 hal_soc->ops->hal_rx_msdu_packet_metadata_get = 1905 hal_rx_msdu_packet_metadata_get_generic_li; 1906 hal_soc->ops->hal_rx_get_fisa_cumulative_l4_checksum = 1907 hal_rx_get_fisa_cumulative_l4_checksum_6490; 1908 hal_soc->ops->hal_rx_get_fisa_cumulative_ip_length = 1909 hal_rx_get_fisa_cumulative_ip_length_6490; 1910 hal_soc->ops->hal_rx_get_udp_proto = hal_rx_get_udp_proto_6490; 1911 hal_soc->ops->hal_rx_get_fisa_flow_agg_continuation = 1912 hal_rx_get_flow_agg_continuation_6490; 1913 hal_soc->ops->hal_rx_get_fisa_flow_agg_count = 1914 hal_rx_get_flow_agg_count_6490; 1915 hal_soc->ops->hal_rx_get_fisa_timeout = hal_rx_get_fisa_timeout_6490; 1916 hal_soc->ops->hal_rx_mpdu_start_tlv_tag_valid = 1917 hal_rx_mpdu_start_tlv_tag_valid_6490; 1918 1919 /* rx - TLV struct offsets */ 1920 hal_soc->ops->hal_rx_msdu_end_offset_get = 1921 hal_rx_msdu_end_offset_get_generic; 1922 hal_soc->ops->hal_rx_attn_offset_get = hal_rx_attn_offset_get_generic; 1923 hal_soc->ops->hal_rx_msdu_start_offset_get = 1924 hal_rx_msdu_start_offset_get_generic; 1925 hal_soc->ops->hal_rx_mpdu_start_offset_get = 1926 hal_rx_mpdu_start_offset_get_generic; 1927 hal_soc->ops->hal_rx_mpdu_end_offset_get = 1928 hal_rx_mpdu_end_offset_get_generic; 1929 #ifndef NO_RX_PKT_HDR_TLV 1930 hal_soc->ops->hal_rx_pkt_tlv_offset_get = 1931 hal_rx_pkt_tlv_offset_get_generic; 1932 #endif 1933 hal_soc->ops->hal_rx_flow_setup_fse = hal_rx_flow_setup_fse_6490; 1934 hal_soc->ops->hal_rx_flow_get_tuple_info = 1935 hal_rx_flow_get_tuple_info_li; 1936 hal_soc->ops->hal_rx_flow_delete_entry = 1937 hal_rx_flow_delete_entry_li; 1938 hal_soc->ops->hal_rx_fst_get_fse_size = hal_rx_fst_get_fse_size_li; 1939 hal_soc->ops->hal_compute_reo_remap_ix2_ix3 = 1940 hal_compute_reo_remap_ix2_ix3_6490; 1941 hal_soc->ops->hal_rx_msdu_get_reo_destination_indication = 1942 hal_rx_msdu_get_reo_destination_indication_6490; 1943 hal_soc->ops->hal_setup_link_idle_list = 1944 hal_setup_link_idle_list_generic_li; 1945 #ifdef WLAN_FEATURE_MARK_FIRST_WAKEUP_PACKET 1946 hal_soc->ops->hal_get_first_wow_wakeup_packet = 1947 hal_get_first_wow_wakeup_packet_6490; 1948 #endif 1949 hal_soc->ops->hal_compute_reo_remap_ix0 = 1950 hal_compute_reo_remap_ix0_6490; 1951 hal_soc->ops->hal_rx_tlv_l3_type_get = 1952 hal_rx_tlv_l3_type_get_6490; 1953 hal_soc->ops->hal_rx_tlv_msdu_len_get = 1954 hal_rx_msdu_start_get_len_6490; 1955 }; 1956 1957 struct hal_hw_srng_config hw_srng_table_6490[] = { 1958 /* TODO: max_rings can populated by querying HW capabilities */ 1959 { /* REO_DST */ 1960 .start_ring_id = HAL_SRNG_REO2SW1, 1961 .max_rings = 4, 1962 .entry_size = sizeof(struct reo_destination_ring) >> 2, 1963 .lmac_ring = FALSE, 1964 .ring_dir = HAL_SRNG_DST_RING, 1965 .reg_start = { 1966 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR( 1967 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1968 HWIO_REO_R2_REO2SW1_RING_HP_ADDR( 1969 SEQ_WCSS_UMAC_REO_REG_OFFSET) 1970 }, 1971 .reg_size = { 1972 HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(0) - 1973 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(0), 1974 HWIO_REO_R2_REO2SW2_RING_HP_ADDR(0) - 1975 HWIO_REO_R2_REO2SW1_RING_HP_ADDR(0), 1976 }, 1977 .max_size = 1978 HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_BMSK >> 1979 HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_SHFT, 1980 }, 1981 { /* REO_EXCEPTION */ 1982 /* Designating REO2TCL ring as exception ring. This ring is 1983 * similar to other REO2SW rings though it is named as REO2TCL. 1984 * Any of theREO2SW rings can be used as exception ring. 1985 */ 1986 .start_ring_id = HAL_SRNG_REO2TCL, 1987 .max_rings = 1, 1988 .entry_size = sizeof(struct reo_destination_ring) >> 2, 1989 .lmac_ring = FALSE, 1990 .ring_dir = HAL_SRNG_DST_RING, 1991 .reg_start = { 1992 HWIO_REO_R0_REO2TCL_RING_BASE_LSB_ADDR( 1993 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1994 HWIO_REO_R2_REO2TCL_RING_HP_ADDR( 1995 SEQ_WCSS_UMAC_REO_REG_OFFSET) 1996 }, 1997 /* Single ring - provide ring size if multiple rings of this 1998 * type are supported 1999 */ 2000 .reg_size = {}, 2001 .max_size = 2002 HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_BMSK >> 2003 HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_SHFT, 2004 }, 2005 { /* REO_REINJECT */ 2006 .start_ring_id = HAL_SRNG_SW2REO, 2007 .max_rings = 1, 2008 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 2009 .lmac_ring = FALSE, 2010 .ring_dir = HAL_SRNG_SRC_RING, 2011 .reg_start = { 2012 HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR( 2013 SEQ_WCSS_UMAC_REO_REG_OFFSET), 2014 HWIO_REO_R2_SW2REO_RING_HP_ADDR( 2015 SEQ_WCSS_UMAC_REO_REG_OFFSET) 2016 }, 2017 /* Single ring - provide ring size if multiple rings of this 2018 * type are supported 2019 */ 2020 .reg_size = {}, 2021 .max_size = HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_BMSK >> 2022 HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_SHFT, 2023 }, 2024 { /* REO_CMD */ 2025 .start_ring_id = HAL_SRNG_REO_CMD, 2026 .max_rings = 1, 2027 .entry_size = (sizeof(struct tlv_32_hdr) + 2028 sizeof(struct reo_get_queue_stats)) >> 2, 2029 .lmac_ring = FALSE, 2030 .ring_dir = HAL_SRNG_SRC_RING, 2031 .reg_start = { 2032 HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR( 2033 SEQ_WCSS_UMAC_REO_REG_OFFSET), 2034 HWIO_REO_R2_REO_CMD_RING_HP_ADDR( 2035 SEQ_WCSS_UMAC_REO_REG_OFFSET), 2036 }, 2037 /* Single ring - provide ring size if multiple rings of this 2038 * type are supported 2039 */ 2040 .reg_size = {}, 2041 .max_size = 2042 HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_BMSK >> 2043 HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_SHFT, 2044 }, 2045 { /* REO_STATUS */ 2046 .start_ring_id = HAL_SRNG_REO_STATUS, 2047 .max_rings = 1, 2048 .entry_size = (sizeof(struct tlv_32_hdr) + 2049 sizeof(struct reo_get_queue_stats_status)) >> 2, 2050 .lmac_ring = FALSE, 2051 .ring_dir = HAL_SRNG_DST_RING, 2052 .reg_start = { 2053 HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR( 2054 SEQ_WCSS_UMAC_REO_REG_OFFSET), 2055 HWIO_REO_R2_REO_STATUS_RING_HP_ADDR( 2056 SEQ_WCSS_UMAC_REO_REG_OFFSET), 2057 }, 2058 /* Single ring - provide ring size if multiple rings of this 2059 * type are supported 2060 */ 2061 .reg_size = {}, 2062 .max_size = 2063 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> 2064 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, 2065 }, 2066 { /* TCL_DATA */ 2067 .start_ring_id = HAL_SRNG_SW2TCL1, 2068 .max_rings = 3, 2069 .entry_size = (sizeof(struct tlv_32_hdr) + 2070 sizeof(struct tcl_data_cmd)) >> 2, 2071 .lmac_ring = FALSE, 2072 .ring_dir = HAL_SRNG_SRC_RING, 2073 .reg_start = { 2074 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR( 2075 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 2076 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR( 2077 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 2078 }, 2079 .reg_size = { 2080 HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(0) - 2081 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(0), 2082 HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(0) - 2083 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(0), 2084 }, 2085 .max_size = 2086 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK >> 2087 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT, 2088 }, 2089 { /* TCL_CMD */ 2090 .start_ring_id = HAL_SRNG_SW2TCL_CMD, 2091 .max_rings = 1, 2092 .entry_size = (sizeof(struct tlv_32_hdr) + 2093 sizeof(struct tcl_gse_cmd)) >> 2, 2094 .lmac_ring = FALSE, 2095 .ring_dir = HAL_SRNG_SRC_RING, 2096 .reg_start = { 2097 HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_ADDR( 2098 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 2099 HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_ADDR( 2100 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 2101 }, 2102 /* Single ring - provide ring size if multiple rings of this 2103 * type are supported 2104 */ 2105 .reg_size = {}, 2106 .max_size = 2107 HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_SIZE_BMSK >> 2108 HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_SIZE_SHFT, 2109 }, 2110 { /* TCL_STATUS */ 2111 .start_ring_id = HAL_SRNG_TCL_STATUS, 2112 .max_rings = 1, 2113 .entry_size = (sizeof(struct tlv_32_hdr) + 2114 sizeof(struct tcl_status_ring)) >> 2, 2115 .lmac_ring = FALSE, 2116 .ring_dir = HAL_SRNG_DST_RING, 2117 .reg_start = { 2118 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR( 2119 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 2120 HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR( 2121 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 2122 }, 2123 /* Single ring - provide ring size if multiple rings of this 2124 * type are supported 2125 */ 2126 .reg_size = {}, 2127 .max_size = 2128 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_BMSK >> 2129 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_SHFT, 2130 }, 2131 { /* CE_SRC */ 2132 .start_ring_id = HAL_SRNG_CE_0_SRC, 2133 .max_rings = 12, 2134 .entry_size = sizeof(struct ce_src_desc) >> 2, 2135 .lmac_ring = FALSE, 2136 .ring_dir = HAL_SRNG_SRC_RING, 2137 .reg_start = { 2138 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR( 2139 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET), 2140 HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR( 2141 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET), 2142 }, 2143 .reg_size = { 2144 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET - 2145 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET, 2146 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET - 2147 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET, 2148 }, 2149 .max_size = 2150 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >> 2151 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT, 2152 }, 2153 { /* CE_DST */ 2154 .start_ring_id = HAL_SRNG_CE_0_DST, 2155 .max_rings = 12, 2156 .entry_size = 8 >> 2, 2157 /*TODO: entry_size above should actually be 2158 * sizeof(struct ce_dst_desc) >> 2, but couldn't find definition 2159 * of struct ce_dst_desc in HW header files 2160 */ 2161 .lmac_ring = FALSE, 2162 .ring_dir = HAL_SRNG_SRC_RING, 2163 .reg_start = { 2164 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR( 2165 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 2166 HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR( 2167 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 2168 }, 2169 .reg_size = { 2170 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 2171 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 2172 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 2173 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 2174 }, 2175 .max_size = 2176 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >> 2177 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT, 2178 }, 2179 { /* CE_DST_STATUS */ 2180 .start_ring_id = HAL_SRNG_CE_0_DST_STATUS, 2181 .max_rings = 12, 2182 .entry_size = sizeof(struct ce_stat_desc) >> 2, 2183 .lmac_ring = FALSE, 2184 .ring_dir = HAL_SRNG_DST_RING, 2185 .reg_start = { 2186 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR( 2187 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 2188 HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR( 2189 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 2190 }, 2191 /* TODO: check destination status ring registers */ 2192 .reg_size = { 2193 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 2194 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 2195 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 2196 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 2197 }, 2198 .max_size = 2199 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> 2200 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, 2201 }, 2202 { /* WBM_IDLE_LINK */ 2203 .start_ring_id = HAL_SRNG_WBM_IDLE_LINK, 2204 .max_rings = 1, 2205 .entry_size = sizeof(struct wbm_link_descriptor_ring) >> 2, 2206 .lmac_ring = FALSE, 2207 .ring_dir = HAL_SRNG_SRC_RING, 2208 .reg_start = { 2209 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2210 HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2211 }, 2212 /* Single ring - provide ring size if multiple rings of this 2213 * type are supported 2214 */ 2215 .reg_size = {}, 2216 .max_size = 2217 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_BMSK >> 2218 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_SHFT, 2219 }, 2220 { /* SW2WBM_RELEASE */ 2221 .start_ring_id = HAL_SRNG_WBM_SW_RELEASE, 2222 .max_rings = 1, 2223 .entry_size = sizeof(struct wbm_release_ring) >> 2, 2224 .lmac_ring = FALSE, 2225 .ring_dir = HAL_SRNG_SRC_RING, 2226 .reg_start = { 2227 HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2228 HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2229 }, 2230 /* Single ring - provide ring size if multiple rings of this 2231 * type are supported 2232 */ 2233 .reg_size = {}, 2234 .max_size = 2235 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> 2236 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, 2237 }, 2238 { /* WBM2SW_RELEASE */ 2239 .start_ring_id = HAL_SRNG_WBM2SW0_RELEASE, 2240 #if defined(IPA_WDI3_TX_TWO_PIPES) || defined(TX_MULTI_TCL) || \ 2241 defined(CONFIG_PLD_PCIE_FW_SIM) 2242 .max_rings = 5, 2243 #else 2244 .max_rings = 4, 2245 #endif 2246 .entry_size = sizeof(struct wbm_release_ring) >> 2, 2247 .lmac_ring = FALSE, 2248 .ring_dir = HAL_SRNG_DST_RING, 2249 .reg_start = { 2250 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2251 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2252 }, 2253 .reg_size = { 2254 HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) - 2255 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2256 HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) - 2257 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2258 }, 2259 .max_size = 2260 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> 2261 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, 2262 }, 2263 { /* RXDMA_BUF */ 2264 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA0_BUF0, 2265 #ifdef IPA_OFFLOAD 2266 .max_rings = 3, 2267 #else 2268 .max_rings = 2, 2269 #endif 2270 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 2271 .lmac_ring = TRUE, 2272 .ring_dir = HAL_SRNG_SRC_RING, 2273 /* reg_start is not set because LMAC rings are not accessed 2274 * from host 2275 */ 2276 .reg_start = {}, 2277 .reg_size = {}, 2278 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2279 }, 2280 { /* RXDMA_DST */ 2281 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW0, 2282 .max_rings = 1, 2283 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 2284 .lmac_ring = TRUE, 2285 .ring_dir = HAL_SRNG_DST_RING, 2286 /* reg_start is not set because LMAC rings are not accessed 2287 * from host 2288 */ 2289 .reg_start = {}, 2290 .reg_size = {}, 2291 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2292 }, 2293 { /* RXDMA_MONITOR_BUF */ 2294 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA2_BUF, 2295 .max_rings = 1, 2296 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 2297 .lmac_ring = TRUE, 2298 .ring_dir = HAL_SRNG_SRC_RING, 2299 /* reg_start is not set because LMAC rings are not accessed 2300 * from host 2301 */ 2302 .reg_start = {}, 2303 .reg_size = {}, 2304 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2305 }, 2306 { /* RXDMA_MONITOR_STATUS */ 2307 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_STATBUF, 2308 .max_rings = 1, 2309 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 2310 .lmac_ring = TRUE, 2311 .ring_dir = HAL_SRNG_SRC_RING, 2312 /* reg_start is not set because LMAC rings are not accessed 2313 * from host 2314 */ 2315 .reg_start = {}, 2316 .reg_size = {}, 2317 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2318 }, 2319 { /* RXDMA_MONITOR_DST */ 2320 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW1, 2321 .max_rings = 1, 2322 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 2323 .lmac_ring = TRUE, 2324 .ring_dir = HAL_SRNG_DST_RING, 2325 /* reg_start is not set because LMAC rings are not accessed 2326 * from host 2327 */ 2328 .reg_start = {}, 2329 .reg_size = {}, 2330 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2331 }, 2332 { /* RXDMA_MONITOR_DESC */ 2333 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_DESC, 2334 .max_rings = 1, 2335 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 2336 .lmac_ring = TRUE, 2337 .ring_dir = HAL_SRNG_SRC_RING, 2338 /* reg_start is not set because LMAC rings are not accessed 2339 * from host 2340 */ 2341 .reg_start = {}, 2342 .reg_size = {}, 2343 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2344 }, 2345 { /* DIR_BUF_RX_DMA_SRC */ 2346 .start_ring_id = HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING, 2347 /* 2348 * one ring is for spectral scan 2349 * the other is for cfr 2350 */ 2351 .max_rings = 2, 2352 .entry_size = 2, 2353 .lmac_ring = TRUE, 2354 .ring_dir = HAL_SRNG_SRC_RING, 2355 /* reg_start is not set because LMAC rings are not accessed 2356 * from host 2357 */ 2358 .reg_start = {}, 2359 .reg_size = {}, 2360 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2361 }, 2362 #ifdef WLAN_FEATURE_CIF_CFR 2363 { /* WIFI_POS_SRC */ 2364 .start_ring_id = HAL_SRNG_WIFI_POS_SRC_DMA_RING, 2365 .max_rings = 1, 2366 .entry_size = sizeof(wmi_oem_dma_buf_release_entry) >> 2, 2367 .lmac_ring = TRUE, 2368 .ring_dir = HAL_SRNG_SRC_RING, 2369 /* reg_start is not set because LMAC rings are not accessed 2370 * from host 2371 */ 2372 .reg_start = {}, 2373 .reg_size = {}, 2374 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2375 }, 2376 #endif 2377 { /* REO2PPE */ 0}, 2378 { /* PPE2TCL */ 0}, 2379 { /* PPE_RELEASE */ 0}, 2380 { /* TX_MONITOR_BUF */ 0}, 2381 { /* TX_MONITOR_DST */ 0}, 2382 { /* SW2RXDMA_NEW */ 0}, 2383 }; 2384 2385 /** 2386 * hal_qca6490_attach() - Attach 6490 target specific hal_soc ops, 2387 * offset and srng table 2388 */ 2389 void hal_qca6490_attach(struct hal_soc *hal_soc) 2390 { 2391 hal_soc->hw_srng_table = hw_srng_table_6490; 2392 2393 hal_srng_hw_reg_offset_init_generic(hal_soc); 2394 2395 hal_hw_txrx_default_ops_attach_li(hal_soc); 2396 hal_hw_txrx_ops_attach_qca6490(hal_soc); 2397 } 2398