1 /* 2 * Copyright (c) 2019-2021 The Linux Foundation. All rights reserved. 3 * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #include "qdf_types.h" 21 #include "qdf_util.h" 22 #include "qdf_types.h" 23 #include "qdf_lock.h" 24 #include "qdf_mem.h" 25 #include "qdf_nbuf.h" 26 #include "hal_li_hw_headers.h" 27 #include "hal_internal.h" 28 #include "hal_api.h" 29 #include "target_type.h" 30 #include "wcss_version.h" 31 #include "qdf_module.h" 32 #include "hal_flow.h" 33 #include "rx_flow_search_entry.h" 34 #include "hal_rx_flow_info.h" 35 36 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_OFFSET \ 37 RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_OFFSET 38 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_MASK \ 39 RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_MASK 40 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_LSB \ 41 RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_LSB 42 #define UNIFIED_PHYRX_HT_SIG_0_HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS_OFFSET \ 43 PHYRX_L_SIG_B_0_PHYRX_L_SIG_B_INFO_DETAILS_RATE_OFFSET 44 #define UNIFIED_PHYRX_L_SIG_B_0_L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS_OFFSET \ 45 PHYRX_L_SIG_B_0_PHYRX_L_SIG_B_INFO_DETAILS_RATE_OFFSET 46 #define UNIFIED_PHYRX_L_SIG_A_0_L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS_OFFSET \ 47 PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_RATE_OFFSET 48 #define UNIFIED_PHYRX_VHT_SIG_A_0_VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS_OFFSET \ 49 PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_OFFSET 50 #define UNIFIED_PHYRX_HE_SIG_A_SU_0_HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS_OFFSET \ 51 PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_OFFSET 52 #define UNIFIED_PHYRX_HE_SIG_A_MU_DL_0_HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_OFFSET \ 53 PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_OFFSET 54 #define UNIFIED_PHYRX_HE_SIG_B1_MU_0_HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_OFFSET \ 55 PHYRX_HE_SIG_B1_MU_0_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_OFFSET 56 #define UNIFIED_PHYRX_HE_SIG_B2_MU_0_HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_OFFSET \ 57 PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_OFFSET 58 #define UNIFIED_PHYRX_HE_SIG_B2_OFDMA_0_HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_OFFSET \ 59 PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_OFFSET 60 61 #define UNIFIED_PHYRX_RSSI_LEGACY_3_RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS_OFFSET \ 62 PHYRX_RSSI_LEGACY_3_RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS_OFFSET 63 #define UNIFIED_PHYRX_RSSI_LEGACY_19_RECEIVE_RSSI_INFO_PREAMBLE_RSSI_INFO_DETAILS_OFFSET \ 64 PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 65 #define UNIFIED_RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET \ 66 RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 67 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 68 RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET 69 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ 70 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET 71 #define UNIFIED_RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 72 RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET 73 #define UNIFIED_REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 74 REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET 75 #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC \ 76 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER 77 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ 78 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET 79 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 80 RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET 81 #define UNIFIED_TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 82 TCL_DATA_CMD_0_BUF_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 83 #define UNIFIED_TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 84 TCL_DATA_CMD_1_BUF_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 85 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET \ 86 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET 87 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB \ 88 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB 89 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK \ 90 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK 91 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB \ 92 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB 93 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK \ 94 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK 95 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB \ 96 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB 97 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK \ 98 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK 99 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB \ 100 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB 101 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK \ 102 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK 103 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB \ 104 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB 105 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK \ 106 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK 107 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_MASK \ 108 WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MASK 109 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_OFFSET \ 110 WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_OFFSET 111 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_LSB \ 112 WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_LSB 113 114 #include "hal_6490_tx.h" 115 #include "hal_6490_rx.h" 116 #include <hal_generic_api.h> 117 #include "hal_li_rx.h" 118 #include "hal_li_api.h" 119 #include "hal_li_generic_api.h" 120 121 /** 122 * hal_rx_msdu_start_nss_get_6490() - API to get the NSS 123 * Interval from rx_msdu_start 124 * @buf: pointer to the start of RX PKT TLV header 125 * 126 * Return: uint32_t(nss) 127 */ 128 static uint32_t 129 hal_rx_msdu_start_nss_get_6490(uint8_t *buf) 130 { 131 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 132 struct rx_msdu_start *msdu_start = 133 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 134 uint8_t mimo_ss_bitmap; 135 136 mimo_ss_bitmap = HAL_RX_MSDU_START_MIMO_SS_BITMAP(msdu_start); 137 138 return qdf_get_hweight8(mimo_ss_bitmap); 139 } 140 141 /** 142 * hal_rx_msdu_start_get_len_6490() - API to get the MSDU length 143 * from rx_msdu_start TLV 144 * @buf: pointer to the start of RX PKT TLV headers 145 * 146 * Return: (uint32_t)msdu length 147 */ 148 static uint32_t hal_rx_msdu_start_get_len_6490(uint8_t *buf) 149 { 150 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 151 struct rx_msdu_start *msdu_start = 152 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 153 uint32_t msdu_len; 154 155 msdu_len = HAL_RX_MSDU_START_MSDU_LEN_GET(msdu_start); 156 157 return msdu_len; 158 } 159 160 /** 161 * hal_rx_mon_hw_desc_get_mpdu_status_6490() - Retrieve MPDU status 162 * @hw_desc_addr: Start address of Rx HW TLVs 163 * @rs: Status for monitor mode 164 * 165 * Return: void 166 */ 167 static void hal_rx_mon_hw_desc_get_mpdu_status_6490(void *hw_desc_addr, 168 struct mon_rx_status *rs) 169 { 170 struct rx_msdu_start *rx_msdu_start; 171 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr; 172 uint32_t reg_value; 173 const uint32_t sgi_hw_to_cdp[] = { 174 CDP_SGI_0_8_US, 175 CDP_SGI_0_4_US, 176 CDP_SGI_1_6_US, 177 CDP_SGI_3_2_US, 178 }; 179 180 rx_msdu_start = &rx_desc->msdu_start_tlv.rx_msdu_start; 181 182 HAL_RX_GET_MSDU_AGGREGATION(rx_desc, rs); 183 184 rs->ant_signal_db = HAL_RX_GET(rx_msdu_start, 185 RX_MSDU_START_5, USER_RSSI); 186 if (!rs->vht_flags) { 187 rs->is_stbc = HAL_RX_GET(rx_msdu_start, 188 RX_MSDU_START_5, STBC); 189 190 reg_value = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, SGI); 191 rs->sgi = sgi_hw_to_cdp[reg_value]; 192 193 reg_value = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, 194 RECEPTION_TYPE); 195 rs->beamformed = 196 (reg_value == HAL_RX_RECEPTION_TYPE_MU_MIMO) ? 1 : 0; 197 } 198 /* TODO: rs->beamformed should be set for SU beamforming also */ 199 } 200 201 #define LINK_DESC_SIZE (NUM_OF_DWORDS_RX_MSDU_LINK << 2) 202 203 static uint32_t hal_get_link_desc_size_6490(void) 204 { 205 return LINK_DESC_SIZE; 206 } 207 208 /** 209 * hal_rx_get_tlv_6490() - API to get the tlv 210 * @rx_tlv: TLV data extracted from the rx packet 211 * 212 * Return: uint8_t 213 */ 214 static uint8_t hal_rx_get_tlv_6490(void *rx_tlv) 215 { 216 return HAL_RX_GET(rx_tlv, PHYRX_RSSI_LEGACY_0, RECEIVE_BANDWIDTH); 217 } 218 219 /** 220 * hal_rx_phy_legacy_get_rssi_6490() - API to get RSSI from TLV 221 * WIFIPHYRX_RSSI_LEGACY_E 222 * @buf: pointer to the start of WIFIPHYRX_RSSI_LEGACY_E TLV 223 * 224 * Return: value of RSSI 225 */ 226 static int8_t hal_rx_phy_legacy_get_rssi_6490(uint8_t *buf) 227 { 228 return HAL_RX_GET(buf, PHYRX_RSSI_LEGACY_36, RSSI_COMB_PPDU); 229 } 230 231 /** 232 * hal_rx_proc_phyrx_other_receive_info_tlv_6490() 233 * - process other receive info TLV 234 * @rx_tlv_hdr: pointer to TLV header 235 * @ppdu_info_handle: pointer to ppdu_info 236 * 237 * Return: None 238 */ 239 static 240 void hal_rx_proc_phyrx_other_receive_info_tlv_6490(void *rx_tlv_hdr, 241 void *ppdu_info_handle) 242 { 243 uint32_t tlv_tag, tlv_len; 244 uint32_t temp_len, other_tlv_len, other_tlv_tag; 245 void *rx_tlv = (uint8_t *)rx_tlv_hdr + HAL_RX_TLV32_HDR_SIZE; 246 void *other_tlv_hdr = NULL; 247 void *other_tlv = NULL; 248 249 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv_hdr); 250 tlv_len = HAL_RX_GET_USER_TLV32_LEN(rx_tlv_hdr); 251 temp_len = 0; 252 253 other_tlv_hdr = rx_tlv + HAL_RX_TLV32_HDR_SIZE; 254 255 other_tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(other_tlv_hdr); 256 other_tlv_len = HAL_RX_GET_USER_TLV32_LEN(other_tlv_hdr); 257 temp_len += other_tlv_len; 258 other_tlv = other_tlv_hdr + HAL_RX_TLV32_HDR_SIZE; 259 260 switch (other_tlv_tag) { 261 default: 262 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR, 263 "%s unhandled TLV type: %d, TLV len:%d", 264 __func__, other_tlv_tag, other_tlv_len); 265 break; 266 } 267 } 268 269 /** 270 * hal_rx_dump_msdu_start_tlv_6490() - dump RX msdu_start TLV in structured 271 * human readable format. 272 * @pkttlvs: pointer to the pkttlvs. 273 * @dbg_level: log level. 274 * 275 * Return: void 276 */ 277 static void hal_rx_dump_msdu_start_tlv_6490(void *pkttlvs, uint8_t dbg_level) 278 { 279 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)pkttlvs; 280 struct rx_msdu_start *msdu_start = 281 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 282 283 __QDF_TRACE_RL(dbg_level, QDF_MODULE_ID_DP, 284 "rx_msdu_start tlv (1/2) - " 285 "rxpcu_mpdu_filter_in_category: %x " 286 "sw_frame_group_id: %x " 287 "phy_ppdu_id: %x " 288 "msdu_length: %x " 289 "ipsec_esp: %x " 290 "l3_offset: %x " 291 "ipsec_ah: %x " 292 "l4_offset: %x " 293 "msdu_number: %x " 294 "decap_format: %x " 295 "ipv4_proto: %x " 296 "ipv6_proto: %x " 297 "tcp_proto: %x " 298 "udp_proto: %x " 299 "ip_frag: %x " 300 "tcp_only_ack: %x " 301 "da_is_bcast_mcast: %x " 302 "ip4_protocol_ip6_next_header: %x " 303 "toeplitz_hash_2_or_4: %x " 304 "flow_id_toeplitz: %x " 305 "user_rssi: %x " 306 "pkt_type: %x " 307 "stbc: %x " 308 "sgi: %x " 309 "rate_mcs: %x " 310 "receive_bandwidth: %x " 311 "reception_type: %x " 312 "ppdu_start_timestamp: %u ", 313 msdu_start->rxpcu_mpdu_filter_in_category, 314 msdu_start->sw_frame_group_id, 315 msdu_start->phy_ppdu_id, 316 msdu_start->msdu_length, 317 msdu_start->ipsec_esp, 318 msdu_start->l3_offset, 319 msdu_start->ipsec_ah, 320 msdu_start->l4_offset, 321 msdu_start->msdu_number, 322 msdu_start->decap_format, 323 msdu_start->ipv4_proto, 324 msdu_start->ipv6_proto, 325 msdu_start->tcp_proto, 326 msdu_start->udp_proto, 327 msdu_start->ip_frag, 328 msdu_start->tcp_only_ack, 329 msdu_start->da_is_bcast_mcast, 330 msdu_start->ip4_protocol_ip6_next_header, 331 msdu_start->toeplitz_hash_2_or_4, 332 msdu_start->flow_id_toeplitz, 333 msdu_start->user_rssi, 334 msdu_start->pkt_type, 335 msdu_start->stbc, 336 msdu_start->sgi, 337 msdu_start->rate_mcs, 338 msdu_start->receive_bandwidth, 339 msdu_start->reception_type, 340 msdu_start->ppdu_start_timestamp); 341 342 __QDF_TRACE_RL(dbg_level, QDF_MODULE_ID_DP, 343 "rx_msdu_start tlv (2/2) - " 344 "sw_phy_meta_data: %x ", 345 msdu_start->sw_phy_meta_data); 346 } 347 348 /** 349 * hal_rx_dump_msdu_end_tlv_6490() - dump RX msdu_end TLV in structured 350 * human readable format. 351 * @pkttlvs: pointer to the pkttlvs. 352 * @dbg_level: log level. 353 * 354 * Return: void 355 */ 356 static void hal_rx_dump_msdu_end_tlv_6490(void *pkttlvs, 357 uint8_t dbg_level) 358 { 359 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)pkttlvs; 360 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 361 362 __QDF_TRACE_RL(dbg_level, QDF_MODULE_ID_DP, 363 "rx_msdu_end tlv (1/3) - " 364 "rxpcu_mpdu_filter_in_category: %x " 365 "sw_frame_group_id: %x " 366 "phy_ppdu_id: %x " 367 "ip_hdr_chksum: %x " 368 "tcp_udp_chksum: %x " 369 "key_id_octet: %x " 370 "cce_super_rule: %x " 371 "cce_classify_not_done_truncat: %x " 372 "cce_classify_not_done_cce_dis: %x " 373 "ext_wapi_pn_63_48: %x " 374 "ext_wapi_pn_95_64: %x " 375 "ext_wapi_pn_127_96: %x " 376 "reported_mpdu_length: %x " 377 "first_msdu: %x " 378 "last_msdu: %x " 379 "sa_idx_timeout: %x " 380 "da_idx_timeout: %x " 381 "msdu_limit_error: %x " 382 "flow_idx_timeout: %x " 383 "flow_idx_invalid: %x " 384 "wifi_parser_error: %x " 385 "amsdu_parser_error: %x", 386 msdu_end->rxpcu_mpdu_filter_in_category, 387 msdu_end->sw_frame_group_id, 388 msdu_end->phy_ppdu_id, 389 msdu_end->ip_hdr_chksum, 390 msdu_end->tcp_udp_chksum, 391 msdu_end->key_id_octet, 392 msdu_end->cce_super_rule, 393 msdu_end->cce_classify_not_done_truncate, 394 msdu_end->cce_classify_not_done_cce_dis, 395 msdu_end->ext_wapi_pn_63_48, 396 msdu_end->ext_wapi_pn_95_64, 397 msdu_end->ext_wapi_pn_127_96, 398 msdu_end->reported_mpdu_length, 399 msdu_end->first_msdu, 400 msdu_end->last_msdu, 401 msdu_end->sa_idx_timeout, 402 msdu_end->da_idx_timeout, 403 msdu_end->msdu_limit_error, 404 msdu_end->flow_idx_timeout, 405 msdu_end->flow_idx_invalid, 406 msdu_end->wifi_parser_error, 407 msdu_end->amsdu_parser_error); 408 409 __QDF_TRACE_RL(dbg_level, QDF_MODULE_ID_DP, 410 "rx_msdu_end tlv (2/3)- " 411 "sa_is_valid: %x " 412 "da_is_valid: %x " 413 "da_is_mcbc: %x " 414 "l3_header_padding: %x " 415 "ipv6_options_crc: %x " 416 "tcp_seq_number: %x " 417 "tcp_ack_number: %x " 418 "tcp_flag: %x " 419 "lro_eligible: %x " 420 "window_size: %x " 421 "da_offset: %x " 422 "sa_offset: %x " 423 "da_offset_valid: %x " 424 "sa_offset_valid: %x " 425 "rule_indication_31_0: %x " 426 "rule_indication_63_32: %x " 427 "sa_idx: %x " 428 "da_idx: %x " 429 "msdu_drop: %x " 430 "reo_destination_indication: %x " 431 "flow_idx: %x " 432 "fse_metadata: %x " 433 "cce_metadata: %x " 434 "sa_sw_peer_id: %x ", 435 msdu_end->sa_is_valid, 436 msdu_end->da_is_valid, 437 msdu_end->da_is_mcbc, 438 msdu_end->l3_header_padding, 439 msdu_end->ipv6_options_crc, 440 msdu_end->tcp_seq_number, 441 msdu_end->tcp_ack_number, 442 msdu_end->tcp_flag, 443 msdu_end->lro_eligible, 444 msdu_end->window_size, 445 msdu_end->da_offset, 446 msdu_end->sa_offset, 447 msdu_end->da_offset_valid, 448 msdu_end->sa_offset_valid, 449 msdu_end->rule_indication_31_0, 450 msdu_end->rule_indication_63_32, 451 msdu_end->sa_idx, 452 msdu_end->da_idx_or_sw_peer_id, 453 msdu_end->msdu_drop, 454 msdu_end->reo_destination_indication, 455 msdu_end->flow_idx, 456 msdu_end->fse_metadata, 457 msdu_end->cce_metadata, 458 msdu_end->sa_sw_peer_id); 459 __QDF_TRACE_RL(dbg_level, QDF_MODULE_ID_DP, 460 "rx_msdu_end tlv (3/3)" 461 "aggregation_count %x " 462 "flow_aggregation_continuation %x " 463 "fisa_timeout %x " 464 "cumulative_l4_checksum %x " 465 "cumulative_ip_length %x", 466 msdu_end->aggregation_count, 467 msdu_end->flow_aggregation_continuation, 468 msdu_end->fisa_timeout, 469 msdu_end->cumulative_l4_checksum, 470 msdu_end->cumulative_ip_length); 471 } 472 473 /* 474 * Get tid from RX_MPDU_START 475 */ 476 #define HAL_RX_MPDU_INFO_TID_GET(_rx_mpdu_info) \ 477 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_info), \ 478 RX_MPDU_INFO_7_TID_OFFSET)), \ 479 RX_MPDU_INFO_7_TID_MASK, \ 480 RX_MPDU_INFO_7_TID_LSB)) 481 482 static uint32_t hal_rx_mpdu_start_tid_get_6490(uint8_t *buf) 483 { 484 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 485 struct rx_mpdu_start *mpdu_start = 486 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 487 uint32_t tid; 488 489 tid = HAL_RX_MPDU_INFO_TID_GET(&mpdu_start->rx_mpdu_info_details); 490 491 return tid; 492 } 493 494 #define HAL_RX_MSDU_START_RECEPTION_TYPE_GET(_rx_msdu_start) \ 495 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start), \ 496 RX_MSDU_START_5_RECEPTION_TYPE_OFFSET)), \ 497 RX_MSDU_START_5_RECEPTION_TYPE_MASK, \ 498 RX_MSDU_START_5_RECEPTION_TYPE_LSB)) 499 500 /** 501 * hal_rx_msdu_start_reception_type_get_6490() - API to get the reception type 502 * Interval from rx_msdu_start 503 * @buf: pointer to the start of RX PKT TLV header 504 * 505 * Return: uint32_t(reception_type) 506 */ 507 static 508 uint32_t hal_rx_msdu_start_reception_type_get_6490(uint8_t *buf) 509 { 510 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 511 struct rx_msdu_start *msdu_start = 512 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 513 uint32_t reception_type; 514 515 reception_type = HAL_RX_MSDU_START_RECEPTION_TYPE_GET(msdu_start); 516 517 return reception_type; 518 } 519 520 /** 521 * hal_rx_msdu_end_da_idx_get_6490() - API to get da_idx from rx_msdu_end TLV 522 * @buf: pointer to the start of RX PKT TLV headers 523 * 524 * Return: da index 525 */ 526 static uint16_t hal_rx_msdu_end_da_idx_get_6490(uint8_t *buf) 527 { 528 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 529 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 530 uint16_t da_idx; 531 532 da_idx = HAL_RX_MSDU_END_DA_IDX_GET(msdu_end); 533 534 return da_idx; 535 } 536 537 /** 538 * hal_rx_get_rx_fragment_number_6490() - API to retrieve rx fragment number 539 * @buf: Network buffer 540 * 541 * Return: rx fragment number 542 */ 543 static 544 uint8_t hal_rx_get_rx_fragment_number_6490(uint8_t *buf) 545 { 546 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 547 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 548 549 /* Return first 4 bits as fragment number */ 550 return (HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info) & 551 DOT11_SEQ_FRAG_MASK); 552 } 553 554 /** 555 * hal_rx_msdu_end_da_is_mcbc_get_6490() - API to check if pkt is MCBC 556 * from rx_msdu_end TLV 557 * @buf: pointer to the start of RX PKT TLV headers 558 * 559 * Return: da_is_mcbc 560 */ 561 static uint8_t 562 hal_rx_msdu_end_da_is_mcbc_get_6490(uint8_t *buf) 563 { 564 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 565 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 566 567 return HAL_RX_MSDU_END_DA_IS_MCBC_GET(msdu_end); 568 } 569 570 /** 571 * hal_rx_msdu_end_sa_is_valid_get_6490() - API to get_6490 the sa_is_valid 572 * bit from rx_msdu_end TLV 573 * @buf: pointer to the start of RX PKT TLV headers 574 * 575 * Return: sa_is_valid bit 576 */ 577 static uint8_t 578 hal_rx_msdu_end_sa_is_valid_get_6490(uint8_t *buf) 579 { 580 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 581 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 582 uint8_t sa_is_valid; 583 584 sa_is_valid = HAL_RX_MSDU_END_SA_IS_VALID_GET(msdu_end); 585 586 return sa_is_valid; 587 } 588 589 /** 590 * hal_rx_msdu_end_sa_idx_get_6490() - API to get_6490 the sa_idx from 591 * rx_msdu_end TLV 592 * @buf: pointer to the start of RX PKT TLV headers 593 * 594 * Return: sa_idx (SA AST index) 595 */ 596 static 597 uint16_t hal_rx_msdu_end_sa_idx_get_6490(uint8_t *buf) 598 { 599 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 600 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 601 uint16_t sa_idx; 602 603 sa_idx = HAL_RX_MSDU_END_SA_IDX_GET(msdu_end); 604 605 return sa_idx; 606 } 607 608 /** 609 * hal_rx_desc_is_first_msdu_6490() - Check if first msdu 610 * @hw_desc_addr: hardware descriptor address 611 * 612 * Return: 0 - success/ non-zero failure 613 */ 614 static uint32_t hal_rx_desc_is_first_msdu_6490(void *hw_desc_addr) 615 { 616 struct rx_pkt_tlvs *rx_tlvs = (struct rx_pkt_tlvs *)hw_desc_addr; 617 struct rx_msdu_end *msdu_end = &rx_tlvs->msdu_end_tlv.rx_msdu_end; 618 619 return HAL_RX_GET(msdu_end, RX_MSDU_END_10, FIRST_MSDU); 620 } 621 622 /** 623 * hal_rx_msdu_end_l3_hdr_padding_get_6490() - API to get_6490 the l3_header 624 * padding from rx_msdu_end TLV 625 * @buf: pointer to the start of RX PKT TLV headers 626 * 627 * Return: number of l3 header padding bytes 628 */ 629 static uint32_t hal_rx_msdu_end_l3_hdr_padding_get_6490(uint8_t *buf) 630 { 631 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 632 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 633 uint32_t l3_header_padding; 634 635 l3_header_padding = HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(msdu_end); 636 637 return l3_header_padding; 638 } 639 640 /** 641 * hal_rx_encryption_info_valid_6490() - Returns encryption type. 642 * @buf: rx_tlv_hdr of the received packet 643 * 644 * Return: encryption type 645 */ 646 static uint32_t hal_rx_encryption_info_valid_6490(uint8_t *buf) 647 { 648 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 649 struct rx_mpdu_start *mpdu_start = 650 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 651 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 652 uint32_t encryption_info = HAL_RX_MPDU_ENCRYPTION_INFO_VALID(mpdu_info); 653 654 return encryption_info; 655 } 656 657 /** 658 * hal_rx_print_pn_6490() - Prints the PN of rx packet. 659 * @buf: rx_tlv_hdr of the received packet 660 * 661 * Return: void 662 */ 663 static void hal_rx_print_pn_6490(uint8_t *buf) 664 { 665 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 666 struct rx_mpdu_start *mpdu_start = 667 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 668 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 669 670 uint32_t pn_31_0 = HAL_RX_MPDU_PN_31_0_GET(mpdu_info); 671 uint32_t pn_63_32 = HAL_RX_MPDU_PN_63_32_GET(mpdu_info); 672 uint32_t pn_95_64 = HAL_RX_MPDU_PN_95_64_GET(mpdu_info); 673 uint32_t pn_127_96 = HAL_RX_MPDU_PN_127_96_GET(mpdu_info); 674 675 hal_debug("PN number pn_127_96 0x%x pn_95_64 0x%x pn_63_32 0x%x pn_31_0 0x%x", 676 pn_127_96, pn_95_64, pn_63_32, pn_31_0); 677 } 678 679 /** 680 * hal_rx_msdu_end_first_msdu_get_6490() - API to get first msdu status 681 * from rx_msdu_end TLV 682 * @buf: pointer to the start of RX PKT TLV headers 683 * 684 * Return: first_msdu 685 */ 686 static uint8_t hal_rx_msdu_end_first_msdu_get_6490(uint8_t *buf) 687 { 688 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 689 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 690 uint8_t first_msdu; 691 692 first_msdu = HAL_RX_MSDU_END_FIRST_MSDU_GET(msdu_end); 693 694 return first_msdu; 695 } 696 697 /** 698 * hal_rx_msdu_end_da_is_valid_get_6490() - API to check if da is valid 699 * from rx_msdu_end TLV 700 * @buf: pointer to the start of RX PKT TLV headers 701 * 702 * Return: da_is_valid 703 */ 704 static uint8_t hal_rx_msdu_end_da_is_valid_get_6490(uint8_t *buf) 705 { 706 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 707 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 708 uint8_t da_is_valid; 709 710 da_is_valid = HAL_RX_MSDU_END_DA_IS_VALID_GET(msdu_end); 711 712 return da_is_valid; 713 } 714 715 /** 716 * hal_rx_msdu_end_last_msdu_get_6490() - API to get last msdu status 717 * from rx_msdu_end TLV 718 * @buf: pointer to the start of RX PKT TLV headers 719 * 720 * Return: last_msdu 721 */ 722 static uint8_t hal_rx_msdu_end_last_msdu_get_6490(uint8_t *buf) 723 { 724 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 725 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 726 uint8_t last_msdu; 727 728 last_msdu = HAL_RX_MSDU_END_LAST_MSDU_GET(msdu_end); 729 730 return last_msdu; 731 } 732 733 /** 734 * hal_rx_get_mpdu_mac_ad4_valid_6490() - Retrieves if mpdu 4th addr is valid 735 * @buf: Network buffer 736 * 737 * Return: value of mpdu 4th address valid field 738 */ 739 static bool hal_rx_get_mpdu_mac_ad4_valid_6490(uint8_t *buf) 740 { 741 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 742 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 743 bool ad4_valid = 0; 744 745 ad4_valid = HAL_RX_MPDU_GET_MAC_AD4_VALID(rx_mpdu_info); 746 747 return ad4_valid; 748 } 749 750 /** 751 * hal_rx_mpdu_start_sw_peer_id_get_6490() - Retrieve sw peer_id 752 * @buf: network buffer 753 * 754 * Return: sw peer_id 755 */ 756 static uint32_t hal_rx_mpdu_start_sw_peer_id_get_6490(uint8_t *buf) 757 { 758 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 759 struct rx_mpdu_start *mpdu_start = 760 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 761 762 return HAL_RX_MPDU_INFO_SW_PEER_ID_GET( 763 &mpdu_start->rx_mpdu_info_details); 764 } 765 766 /** 767 * hal_rx_mpdu_get_to_ds_6490() - API to get the tods info 768 * from rx_mpdu_start 769 * @buf: pointer to the start of RX PKT TLV header 770 * 771 * Return: uint32_t(to_ds) 772 */ 773 static uint32_t hal_rx_mpdu_get_to_ds_6490(uint8_t *buf) 774 { 775 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 776 struct rx_mpdu_start *mpdu_start = 777 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 778 779 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 780 781 return HAL_RX_MPDU_GET_TODS(mpdu_info); 782 } 783 784 /** 785 * hal_rx_mpdu_get_fr_ds_6490() - API to get the from ds info 786 * from rx_mpdu_start 787 * @buf: pointer to the start of RX PKT TLV header 788 * 789 * Return: uint32_t(fr_ds) 790 */ 791 static uint32_t hal_rx_mpdu_get_fr_ds_6490(uint8_t *buf) 792 { 793 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 794 struct rx_mpdu_start *mpdu_start = 795 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 796 797 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 798 799 return HAL_RX_MPDU_GET_FROMDS(mpdu_info); 800 } 801 802 /** 803 * hal_rx_get_mpdu_frame_control_valid_6490() - Retrieves mpdu 804 * frame control valid 805 * @buf: Network buffer 806 * 807 * Return: value of frame control valid field 808 */ 809 static uint8_t hal_rx_get_mpdu_frame_control_valid_6490(uint8_t *buf) 810 { 811 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 812 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 813 814 return HAL_RX_MPDU_GET_FRAME_CONTROL_VALID(rx_mpdu_info); 815 } 816 817 /** 818 * hal_rx_mpdu_get_addr1_6490() - API to check get address1 of the mpdu 819 * @buf: pointer to the start of RX PKT TLV headera 820 * @mac_addr: pointer to mac address 821 * 822 * Return: success/failure 823 */ 824 static QDF_STATUS hal_rx_mpdu_get_addr1_6490(uint8_t *buf, uint8_t *mac_addr) 825 { 826 struct __attribute__((__packed__)) hal_addr1 { 827 uint32_t ad1_31_0; 828 uint16_t ad1_47_32; 829 }; 830 831 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 832 struct rx_mpdu_start *mpdu_start = 833 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 834 835 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 836 struct hal_addr1 *addr = (struct hal_addr1 *)mac_addr; 837 uint32_t mac_addr_ad1_valid; 838 839 mac_addr_ad1_valid = HAL_RX_MPDU_MAC_ADDR_AD1_VALID_GET(mpdu_info); 840 841 if (mac_addr_ad1_valid) { 842 addr->ad1_31_0 = HAL_RX_MPDU_AD1_31_0_GET(mpdu_info); 843 addr->ad1_47_32 = HAL_RX_MPDU_AD1_47_32_GET(mpdu_info); 844 return QDF_STATUS_SUCCESS; 845 } 846 847 return QDF_STATUS_E_FAILURE; 848 } 849 850 /** 851 * hal_rx_mpdu_get_addr2_6490() - API to check get address2 of the mpdu 852 * in the packet 853 * @buf: pointer to the start of RX PKT TLV header 854 * @mac_addr: pointer to mac address 855 * 856 * Return: success/failure 857 */ 858 static QDF_STATUS hal_rx_mpdu_get_addr2_6490(uint8_t *buf, 859 uint8_t *mac_addr) 860 { 861 struct __attribute__((__packed__)) hal_addr2 { 862 uint16_t ad2_15_0; 863 uint32_t ad2_47_16; 864 }; 865 866 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 867 struct rx_mpdu_start *mpdu_start = 868 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 869 870 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 871 struct hal_addr2 *addr = (struct hal_addr2 *)mac_addr; 872 uint32_t mac_addr_ad2_valid; 873 874 mac_addr_ad2_valid = HAL_RX_MPDU_MAC_ADDR_AD2_VALID_GET(mpdu_info); 875 876 if (mac_addr_ad2_valid) { 877 addr->ad2_15_0 = HAL_RX_MPDU_AD2_15_0_GET(mpdu_info); 878 addr->ad2_47_16 = HAL_RX_MPDU_AD2_47_16_GET(mpdu_info); 879 return QDF_STATUS_SUCCESS; 880 } 881 882 return QDF_STATUS_E_FAILURE; 883 } 884 885 /** 886 * hal_rx_mpdu_get_addr3_6490() - API to get address3 of the mpdu 887 * in the packet 888 * @buf: pointer to the start of RX PKT TLV header 889 * @mac_addr: pointer to mac address 890 * 891 * Return: success/failure 892 */ 893 static QDF_STATUS hal_rx_mpdu_get_addr3_6490(uint8_t *buf, uint8_t *mac_addr) 894 { 895 struct __attribute__((__packed__)) hal_addr3 { 896 uint32_t ad3_31_0; 897 uint16_t ad3_47_32; 898 }; 899 900 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 901 struct rx_mpdu_start *mpdu_start = 902 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 903 904 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 905 struct hal_addr3 *addr = (struct hal_addr3 *)mac_addr; 906 uint32_t mac_addr_ad3_valid; 907 908 mac_addr_ad3_valid = HAL_RX_MPDU_MAC_ADDR_AD3_VALID_GET(mpdu_info); 909 910 if (mac_addr_ad3_valid) { 911 addr->ad3_31_0 = HAL_RX_MPDU_AD3_31_0_GET(mpdu_info); 912 addr->ad3_47_32 = HAL_RX_MPDU_AD3_47_32_GET(mpdu_info); 913 return QDF_STATUS_SUCCESS; 914 } 915 916 return QDF_STATUS_E_FAILURE; 917 } 918 919 /** 920 * hal_rx_mpdu_get_addr4_6490() - API to get address4 of the mpdu 921 * in the packet 922 * @buf: pointer to the start of RX PKT TLV header 923 * @mac_addr: pointer to mac address 924 * 925 * Return: success/failure 926 */ 927 static QDF_STATUS hal_rx_mpdu_get_addr4_6490(uint8_t *buf, uint8_t *mac_addr) 928 { 929 struct __attribute__((__packed__)) hal_addr4 { 930 uint32_t ad4_31_0; 931 uint16_t ad4_47_32; 932 }; 933 934 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 935 struct rx_mpdu_start *mpdu_start = 936 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 937 938 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 939 struct hal_addr4 *addr = (struct hal_addr4 *)mac_addr; 940 uint32_t mac_addr_ad4_valid; 941 942 mac_addr_ad4_valid = HAL_RX_MPDU_MAC_ADDR_AD4_VALID_GET(mpdu_info); 943 944 if (mac_addr_ad4_valid) { 945 addr->ad4_31_0 = HAL_RX_MPDU_AD4_31_0_GET(mpdu_info); 946 addr->ad4_47_32 = HAL_RX_MPDU_AD4_47_32_GET(mpdu_info); 947 return QDF_STATUS_SUCCESS; 948 } 949 950 return QDF_STATUS_E_FAILURE; 951 } 952 953 /** 954 * hal_rx_get_mpdu_sequence_control_valid_6490() - Get mpdu sequence control 955 * valid 956 * @buf: Network buffer 957 * 958 * Return: value of sequence control valid field 959 */ 960 static uint8_t hal_rx_get_mpdu_sequence_control_valid_6490(uint8_t *buf) 961 { 962 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 963 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 964 965 return HAL_RX_MPDU_GET_SEQUENCE_CONTROL_VALID(rx_mpdu_info); 966 } 967 968 /** 969 * hal_rx_is_unicast_6490() - check packet is unicast frame or not. 970 * @buf: pointer to rx pkt TLV. 971 * 972 * Return: true on unicast. 973 */ 974 static bool hal_rx_is_unicast_6490(uint8_t *buf) 975 { 976 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 977 struct rx_mpdu_start *mpdu_start = 978 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 979 uint32_t grp_id; 980 uint8_t *rx_mpdu_info = (uint8_t *)&mpdu_start->rx_mpdu_info_details; 981 982 grp_id = (_HAL_MS((*_OFFSET_TO_WORD_PTR((rx_mpdu_info), 983 RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_OFFSET)), 984 RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_MASK, 985 RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_LSB)); 986 987 return (HAL_MPDU_SW_FRAME_GROUP_UNICAST_DATA == grp_id) ? true : false; 988 } 989 990 /** 991 * hal_rx_tid_get_6490() - get tid based on qos control valid. 992 * @hal_soc_hdl: hal_soc handle 993 * @buf: pointer to rx pkt TLV. 994 * 995 * Return: tid 996 */ 997 static uint32_t hal_rx_tid_get_6490(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 998 { 999 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1000 struct rx_mpdu_start *mpdu_start = 1001 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 1002 uint8_t *rx_mpdu_info = (uint8_t *)&mpdu_start->rx_mpdu_info_details; 1003 uint8_t qos_control_valid = 1004 (_HAL_MS((*_OFFSET_TO_WORD_PTR((rx_mpdu_info), 1005 RX_MPDU_INFO_11_MPDU_QOS_CONTROL_VALID_OFFSET)), 1006 RX_MPDU_INFO_11_MPDU_QOS_CONTROL_VALID_MASK, 1007 RX_MPDU_INFO_11_MPDU_QOS_CONTROL_VALID_LSB)); 1008 1009 if (qos_control_valid) 1010 return hal_rx_mpdu_start_tid_get_6490(buf); 1011 1012 return HAL_RX_NON_QOS_TID; 1013 } 1014 1015 /** 1016 * hal_rx_hw_desc_get_ppduid_get_6490() - retrieve ppdu id 1017 * @rx_tlv_hdr: start address of rx_pkt_tlvs 1018 * @rxdma_dst_ring_desc: Rx HW descriptor 1019 * 1020 * Return: ppdu id 1021 */ 1022 static uint32_t hal_rx_hw_desc_get_ppduid_get_6490(void *rx_tlv_hdr, 1023 void *rxdma_dst_ring_desc) 1024 { 1025 struct rx_mpdu_info *rx_mpdu_info; 1026 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)rx_tlv_hdr; 1027 1028 rx_mpdu_info = 1029 &rx_desc->mpdu_start_tlv.rx_mpdu_start.rx_mpdu_info_details; 1030 1031 return HAL_RX_GET(rx_mpdu_info, RX_MPDU_INFO_9, PHY_PPDU_ID); 1032 } 1033 1034 /** 1035 * hal_reo_status_get_header_6490() - Process reo desc info 1036 * @ring_desc: REO status ring descriptor 1037 * @b: tlv type info 1038 * @h1: Pointer to hal_reo_status_header where info to be stored 1039 * 1040 * Return - none. 1041 */ 1042 static void hal_reo_status_get_header_6490(hal_ring_desc_t ring_desc, int b, 1043 void *h1) 1044 { 1045 uint32_t *d = (uint32_t *)ring_desc; 1046 uint32_t val1 = 0; 1047 struct hal_reo_status_header *h = 1048 (struct hal_reo_status_header *)h1; 1049 1050 /* Offsets of descriptor fields defined in HW headers start 1051 * from the field after TLV header 1052 */ 1053 d += HAL_GET_NUM_DWORDS(sizeof(struct tlv_32_hdr)); 1054 1055 switch (b) { 1056 case HAL_REO_QUEUE_STATS_STATUS_TLV: 1057 val1 = d[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_0, 1058 STATUS_HEADER_REO_STATUS_NUMBER)]; 1059 break; 1060 case HAL_REO_FLUSH_QUEUE_STATUS_TLV: 1061 val1 = d[HAL_OFFSET_DW(REO_FLUSH_QUEUE_STATUS_0, 1062 STATUS_HEADER_REO_STATUS_NUMBER)]; 1063 break; 1064 case HAL_REO_FLUSH_CACHE_STATUS_TLV: 1065 val1 = d[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_0, 1066 STATUS_HEADER_REO_STATUS_NUMBER)]; 1067 break; 1068 case HAL_REO_UNBLK_CACHE_STATUS_TLV: 1069 val1 = d[HAL_OFFSET_DW(REO_UNBLOCK_CACHE_STATUS_0, 1070 STATUS_HEADER_REO_STATUS_NUMBER)]; 1071 break; 1072 case HAL_REO_TIMOUT_LIST_STATUS_TLV: 1073 val1 = d[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_0, 1074 STATUS_HEADER_REO_STATUS_NUMBER)]; 1075 break; 1076 case HAL_REO_DESC_THRES_STATUS_TLV: 1077 val1 = 1078 d[HAL_OFFSET_DW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0, 1079 STATUS_HEADER_REO_STATUS_NUMBER)]; 1080 break; 1081 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: 1082 val1 = d[HAL_OFFSET_DW(REO_UPDATE_RX_REO_QUEUE_STATUS_0, 1083 STATUS_HEADER_REO_STATUS_NUMBER)]; 1084 break; 1085 default: 1086 qdf_nofl_err("ERROR: Unknown tlv\n"); 1087 break; 1088 } 1089 h->cmd_num = 1090 HAL_GET_FIELD( 1091 UNIFORM_REO_STATUS_HEADER_0, REO_STATUS_NUMBER, 1092 val1); 1093 h->exec_time = 1094 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_0, 1095 CMD_EXECUTION_TIME, val1); 1096 h->status = 1097 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_0, 1098 REO_CMD_EXECUTION_STATUS, val1); 1099 switch (b) { 1100 case HAL_REO_QUEUE_STATS_STATUS_TLV: 1101 val1 = d[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_1, 1102 STATUS_HEADER_TIMESTAMP)]; 1103 break; 1104 case HAL_REO_FLUSH_QUEUE_STATUS_TLV: 1105 val1 = d[HAL_OFFSET_DW(REO_FLUSH_QUEUE_STATUS_1, 1106 STATUS_HEADER_TIMESTAMP)]; 1107 break; 1108 case HAL_REO_FLUSH_CACHE_STATUS_TLV: 1109 val1 = d[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_1, 1110 STATUS_HEADER_TIMESTAMP)]; 1111 break; 1112 case HAL_REO_UNBLK_CACHE_STATUS_TLV: 1113 val1 = d[HAL_OFFSET_DW(REO_UNBLOCK_CACHE_STATUS_1, 1114 STATUS_HEADER_TIMESTAMP)]; 1115 break; 1116 case HAL_REO_TIMOUT_LIST_STATUS_TLV: 1117 val1 = d[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_1, 1118 STATUS_HEADER_TIMESTAMP)]; 1119 break; 1120 case HAL_REO_DESC_THRES_STATUS_TLV: 1121 val1 = 1122 d[HAL_OFFSET_DW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_1, 1123 STATUS_HEADER_TIMESTAMP)]; 1124 break; 1125 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: 1126 val1 = d[HAL_OFFSET_DW(REO_UPDATE_RX_REO_QUEUE_STATUS_1, 1127 STATUS_HEADER_TIMESTAMP)]; 1128 break; 1129 default: 1130 qdf_nofl_err("ERROR: Unknown tlv\n"); 1131 break; 1132 } 1133 h->tstamp = 1134 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_1, TIMESTAMP, val1); 1135 } 1136 1137 /** 1138 * hal_tx_desc_set_mesh_en_6490() - Set mesh_enable flag in Tx descriptor 1139 * @desc: Handle to Tx Descriptor 1140 * @en: For raw WiFi frames, this indicates transmission to a mesh STA, 1141 * enabling the interpretation of the 'Mesh Control Present' bit 1142 * (bit 8) of QoS Control (otherwise this bit is ignored), 1143 * For native WiFi frames, this indicates that a 'Mesh Control' field 1144 * is present between the header and the LLC. 1145 * 1146 * Return: void 1147 */ 1148 static inline 1149 void hal_tx_desc_set_mesh_en_6490(void *desc, uint8_t en) 1150 { 1151 HAL_SET_FLD(desc, TCL_DATA_CMD_5, MESH_ENABLE) |= 1152 HAL_TX_SM(TCL_DATA_CMD_5, MESH_ENABLE, en); 1153 } 1154 1155 static 1156 void *hal_rx_msdu0_buffer_addr_lsb_6490(void *link_desc_va) 1157 { 1158 return (void *)HAL_RX_MSDU0_BUFFER_ADDR_LSB(link_desc_va); 1159 } 1160 1161 static 1162 void *hal_rx_msdu_desc_info_ptr_get_6490(void *msdu0) 1163 { 1164 return (void *)HAL_RX_MSDU_DESC_INFO_PTR_GET(msdu0); 1165 } 1166 1167 static 1168 void *hal_ent_mpdu_desc_info_6490(void *ent_ring_desc) 1169 { 1170 return (void *)HAL_ENT_MPDU_DESC_INFO(ent_ring_desc); 1171 } 1172 1173 static 1174 void *hal_dst_mpdu_desc_info_6490(void *dst_ring_desc) 1175 { 1176 return (void *)HAL_DST_MPDU_DESC_INFO(dst_ring_desc); 1177 } 1178 1179 static 1180 uint8_t hal_rx_get_fc_valid_6490(uint8_t *buf) 1181 { 1182 return HAL_RX_GET_FC_VALID(buf); 1183 } 1184 1185 static uint8_t hal_rx_get_to_ds_flag_6490(uint8_t *buf) 1186 { 1187 return HAL_RX_GET_TO_DS_FLAG(buf); 1188 } 1189 1190 static uint8_t hal_rx_get_mac_addr2_valid_6490(uint8_t *buf) 1191 { 1192 return HAL_RX_GET_MAC_ADDR2_VALID(buf); 1193 } 1194 1195 static uint8_t hal_rx_get_filter_category_6490(uint8_t *buf) 1196 { 1197 return HAL_RX_GET_FILTER_CATEGORY(buf); 1198 } 1199 1200 static uint32_t 1201 hal_rx_get_ppdu_id_6490(uint8_t *buf) 1202 { 1203 return HAL_RX_GET_PPDU_ID(buf); 1204 } 1205 1206 /** 1207 * hal_reo_config_6490() - Set reo config parameters 1208 * @soc: hal soc handle 1209 * @reg_val: value to be set 1210 * @reo_params: reo parameters 1211 * 1212 * Return: void 1213 */ 1214 static 1215 void hal_reo_config_6490(struct hal_soc *soc, 1216 uint32_t reg_val, 1217 struct hal_reo_params *reo_params) 1218 { 1219 HAL_REO_R0_CONFIG(soc, reg_val, reo_params); 1220 } 1221 1222 /** 1223 * hal_rx_msdu_desc_info_get_ptr_6490() - Get msdu desc info ptr 1224 * @msdu_details_ptr: Pointer to msdu_details_ptr 1225 * 1226 * Return - Pointer to rx_msdu_desc_info structure. 1227 */ 1228 static void *hal_rx_msdu_desc_info_get_ptr_6490(void *msdu_details_ptr) 1229 { 1230 return HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr); 1231 } 1232 1233 /** 1234 * hal_rx_link_desc_msdu0_ptr_6490() - Get pointer to rx_msdu details 1235 * @link_desc: Pointer to link desc 1236 * 1237 * Return - Pointer to rx_msdu_details structure 1238 */ 1239 static void *hal_rx_link_desc_msdu0_ptr_6490(void *link_desc) 1240 { 1241 return HAL_RX_LINK_DESC_MSDU0_PTR(link_desc); 1242 } 1243 1244 /** 1245 * hal_rx_msdu_flow_idx_get_6490() - API to get flow index 1246 * from rx_msdu_end TLV 1247 * @buf: pointer to the start of RX PKT TLV headers 1248 * 1249 * Return: flow index value from MSDU END TLV 1250 */ 1251 static inline uint32_t hal_rx_msdu_flow_idx_get_6490(uint8_t *buf) 1252 { 1253 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1254 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1255 1256 return HAL_RX_MSDU_END_FLOW_IDX_GET(msdu_end); 1257 } 1258 1259 /** 1260 * hal_rx_msdu_get_reo_destination_indication_6490() - API to get 1261 * reo_destination_indication from rx_msdu_end TLV 1262 * @buf: pointer to the start of RX PKT TLV headers 1263 * @reo_destination_indication: pointer to return value of 1264 * reo_destination_indication 1265 * 1266 * Return: none 1267 */ 1268 static inline void 1269 hal_rx_msdu_get_reo_destination_indication_6490(uint8_t *buf, 1270 uint32_t *reo_destination_indication) 1271 { 1272 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1273 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1274 1275 *reo_destination_indication = HAL_RX_MSDU_END_REO_DEST_IND_GET(msdu_end); 1276 } 1277 1278 /** 1279 * hal_rx_msdu_flow_idx_invalid_6490() - API to get flow index invalid 1280 * from rx_msdu_end TLV 1281 * @buf: pointer to the start of RX PKT TLV headers 1282 * 1283 * Return: flow index invalid value from MSDU END TLV 1284 */ 1285 static bool hal_rx_msdu_flow_idx_invalid_6490(uint8_t *buf) 1286 { 1287 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1288 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1289 1290 return HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(msdu_end); 1291 } 1292 1293 /** 1294 * hal_rx_msdu_flow_idx_timeout_6490() - API to get flow index timeout 1295 * from rx_msdu_end TLV 1296 * @buf: pointer to the start of RX PKT TLV headers 1297 * 1298 * Return: flow index timeout value from MSDU END TLV 1299 */ 1300 static bool hal_rx_msdu_flow_idx_timeout_6490(uint8_t *buf) 1301 { 1302 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1303 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1304 1305 return HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(msdu_end); 1306 } 1307 1308 /** 1309 * hal_rx_msdu_fse_metadata_get_6490() - API to get FSE metadata 1310 * from rx_msdu_end TLV 1311 * @buf: pointer to the start of RX PKT TLV headers 1312 * 1313 * Return: fse metadata value from MSDU END TLV 1314 */ 1315 static uint32_t hal_rx_msdu_fse_metadata_get_6490(uint8_t *buf) 1316 { 1317 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1318 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1319 1320 return HAL_RX_MSDU_END_FSE_METADATA_GET(msdu_end); 1321 } 1322 1323 /** 1324 * hal_rx_msdu_cce_metadata_get_6490() - API to get CCE metadata 1325 * from rx_msdu_end TLV 1326 * @buf: pointer to the start of RX PKT TLV headers 1327 * 1328 * Return: cce_metadata 1329 */ 1330 static uint16_t 1331 hal_rx_msdu_cce_metadata_get_6490(uint8_t *buf) 1332 { 1333 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1334 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1335 1336 return HAL_RX_MSDU_END_CCE_METADATA_GET(msdu_end); 1337 } 1338 1339 /** 1340 * hal_rx_msdu_get_flow_params_6490() - API to get flow index, flow index 1341 * invalid and flow index timeout from 1342 * rx_msdu_end TLV 1343 * @buf: pointer to the start of RX PKT TLV headers 1344 * @flow_invalid: pointer to return value of flow_idx_valid 1345 * @flow_timeout: pointer to return value of flow_idx_timeout 1346 * @flow_index: pointer to return value of flow_idx 1347 * 1348 * Return: none 1349 */ 1350 static inline void 1351 hal_rx_msdu_get_flow_params_6490(uint8_t *buf, 1352 bool *flow_invalid, 1353 bool *flow_timeout, 1354 uint32_t *flow_index) 1355 { 1356 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1357 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1358 1359 *flow_invalid = HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(msdu_end); 1360 *flow_timeout = HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(msdu_end); 1361 *flow_index = HAL_RX_MSDU_END_FLOW_IDX_GET(msdu_end); 1362 } 1363 1364 /** 1365 * hal_rx_tlv_get_tcp_chksum_6490() - API to get tcp checksum 1366 * @buf: rx_tlv_hdr 1367 * 1368 * Return: tcp checksum 1369 */ 1370 static uint16_t 1371 hal_rx_tlv_get_tcp_chksum_6490(uint8_t *buf) 1372 { 1373 return HAL_RX_TLV_GET_TCP_CHKSUM(buf); 1374 } 1375 1376 /** 1377 * hal_rx_get_rx_sequence_6490() - Function to retrieve rx sequence number 1378 * @buf: Network buffer 1379 * 1380 * Return: rx sequence number 1381 */ 1382 static 1383 uint16_t hal_rx_get_rx_sequence_6490(uint8_t *buf) 1384 { 1385 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 1386 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 1387 1388 return HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info); 1389 } 1390 1391 /** 1392 * hal_get_window_address_6490() - Function to get hp/tp address 1393 * @hal_soc: Pointer to hal_soc 1394 * @addr: address offset of register 1395 * 1396 * Return: modified address offset of register 1397 */ 1398 static inline qdf_iomem_t hal_get_window_address_6490(struct hal_soc *hal_soc, 1399 qdf_iomem_t addr) 1400 { 1401 return addr; 1402 } 1403 1404 /** 1405 * hal_rx_get_fisa_cumulative_l4_checksum_6490() - Retrieve cumulative 1406 * checksum 1407 * @buf: buffer pointer 1408 * 1409 * Return: cumulative checksum 1410 */ 1411 static inline 1412 uint16_t hal_rx_get_fisa_cumulative_l4_checksum_6490(uint8_t *buf) 1413 { 1414 return HAL_RX_TLV_GET_FISA_CUMULATIVE_L4_CHECKSUM(buf); 1415 } 1416 1417 /** 1418 * hal_rx_get_fisa_cumulative_ip_length_6490() - Retrieve cumulative 1419 * ip length 1420 * @buf: buffer pointer 1421 * 1422 * Return: cumulative length 1423 */ 1424 static inline 1425 uint16_t hal_rx_get_fisa_cumulative_ip_length_6490(uint8_t *buf) 1426 { 1427 return HAL_RX_TLV_GET_FISA_CUMULATIVE_IP_LENGTH(buf); 1428 } 1429 1430 /** 1431 * hal_rx_get_udp_proto_6490() - Retrieve udp proto value 1432 * @buf: buffer 1433 * 1434 * Return: udp proto bit 1435 */ 1436 static inline 1437 bool hal_rx_get_udp_proto_6490(uint8_t *buf) 1438 { 1439 return HAL_RX_TLV_GET_UDP_PROTO(buf); 1440 } 1441 1442 /** 1443 * hal_rx_get_flow_agg_continuation_6490() - retrieve flow agg continuation 1444 * @buf: buffer 1445 * 1446 * Return: flow agg 1447 */ 1448 static inline 1449 bool hal_rx_get_flow_agg_continuation_6490(uint8_t *buf) 1450 { 1451 return HAL_RX_TLV_GET_FLOW_AGGR_CONT(buf); 1452 } 1453 1454 /** 1455 * hal_rx_get_flow_agg_count_6490() - Retrieve flow agg count 1456 * @buf: buffer 1457 * 1458 * Return: flow agg count 1459 */ 1460 static inline 1461 uint8_t hal_rx_get_flow_agg_count_6490(uint8_t *buf) 1462 { 1463 return HAL_RX_TLV_GET_FLOW_AGGR_COUNT(buf); 1464 } 1465 1466 /** 1467 * hal_rx_get_fisa_timeout_6490() - Retrieve fisa timeout 1468 * @buf: buffer 1469 * 1470 * Return: fisa timeout 1471 */ 1472 static inline 1473 bool hal_rx_get_fisa_timeout_6490(uint8_t *buf) 1474 { 1475 return HAL_RX_TLV_GET_FISA_TIMEOUT(buf); 1476 } 1477 1478 /** 1479 * hal_rx_mpdu_start_tlv_tag_valid_6490() - API to check if RX_MPDU_START 1480 * tlv tag is valid 1481 * @rx_tlv_hdr: start address of rx_pkt_tlvs 1482 * 1483 * Return: true if RX_MPDU_START is valid, else false. 1484 */ 1485 static uint8_t hal_rx_mpdu_start_tlv_tag_valid_6490(void *rx_tlv_hdr) 1486 { 1487 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)rx_tlv_hdr; 1488 uint32_t tlv_tag; 1489 1490 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(&rx_desc->mpdu_start_tlv); 1491 1492 return tlv_tag == WIFIRX_MPDU_START_E ? true : false; 1493 } 1494 1495 /** 1496 * hal_reo_set_err_dst_remap_6490() - Function to set REO error destination 1497 * ring remap register 1498 * @hal_soc: Pointer to hal_soc 1499 * 1500 * Return: none. 1501 */ 1502 static void 1503 hal_reo_set_err_dst_remap_6490(void *hal_soc) 1504 { 1505 /* 1506 * Set REO error 2k jump (error code 5) / OOR (error code 7) 1507 * frame routed to REO2TCL ring. 1508 */ 1509 uint32_t dst_remap_ix0 = 1510 HAL_REO_ERR_REMAP_IX0(REO_REMAP_RELEASE, 0) | 1511 HAL_REO_ERR_REMAP_IX0(REO_REMAP_RELEASE, 1) | 1512 HAL_REO_ERR_REMAP_IX0(REO_REMAP_RELEASE, 2) | 1513 HAL_REO_ERR_REMAP_IX0(REO_REMAP_RELEASE, 3) | 1514 HAL_REO_ERR_REMAP_IX0(REO_REMAP_RELEASE, 4) | 1515 HAL_REO_ERR_REMAP_IX0(REO_REMAP_TCL, 5) | 1516 HAL_REO_ERR_REMAP_IX0(REO_REMAP_TCL, 6) | 1517 HAL_REO_ERR_REMAP_IX0(REO_REMAP_TCL, 7); 1518 1519 uint32_t dst_remap_ix1 = 1520 HAL_REO_ERR_REMAP_IX1(REO_REMAP_RELEASE, 14) | 1521 HAL_REO_ERR_REMAP_IX1(REO_REMAP_RELEASE, 13) | 1522 HAL_REO_ERR_REMAP_IX1(REO_REMAP_RELEASE, 12) | 1523 HAL_REO_ERR_REMAP_IX1(REO_REMAP_RELEASE, 11) | 1524 HAL_REO_ERR_REMAP_IX1(REO_REMAP_RELEASE, 10) | 1525 HAL_REO_ERR_REMAP_IX1(REO_REMAP_RELEASE, 9) | 1526 HAL_REO_ERR_REMAP_IX1(REO_REMAP_TCL, 8); 1527 1528 HAL_REG_WRITE(hal_soc, 1529 HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ADDR( 1530 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1531 dst_remap_ix0); 1532 1533 hal_info("HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0 0x%x", 1534 HAL_REG_READ( 1535 hal_soc, 1536 HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ADDR( 1537 SEQ_WCSS_UMAC_REO_REG_OFFSET))); 1538 1539 HAL_REG_WRITE(hal_soc, 1540 HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ADDR( 1541 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1542 dst_remap_ix1); 1543 1544 hal_info("HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1 0x%x", 1545 HAL_REG_READ( 1546 hal_soc, 1547 HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ADDR( 1548 SEQ_WCSS_UMAC_REO_REG_OFFSET))); 1549 } 1550 1551 /** 1552 * hal_rx_flow_setup_fse_6490() - Setup a flow search entry in HW FST 1553 * @rx_fst: Pointer to the Rx Flow Search Table 1554 * @table_offset: offset into the table where the flow is to be setup 1555 * @rx_flow: Flow Parameters 1556 * 1557 * Flow table entry fields are updated in host byte order, little endian order. 1558 * 1559 * Return: Success/Failure 1560 */ 1561 static void * 1562 hal_rx_flow_setup_fse_6490(uint8_t *rx_fst, uint32_t table_offset, 1563 uint8_t *rx_flow) 1564 { 1565 struct hal_rx_fst *fst = (struct hal_rx_fst *)rx_fst; 1566 struct hal_rx_flow *flow = (struct hal_rx_flow *)rx_flow; 1567 uint8_t *fse; 1568 bool fse_valid; 1569 1570 if (table_offset >= fst->max_entries) { 1571 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR, 1572 "HAL FSE table offset %u exceeds max entries %u", 1573 table_offset, fst->max_entries); 1574 return NULL; 1575 } 1576 1577 fse = (uint8_t *)fst->base_vaddr + 1578 (table_offset * HAL_RX_FST_ENTRY_SIZE); 1579 1580 fse_valid = HAL_GET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, VALID); 1581 1582 if (fse_valid) { 1583 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_DEBUG, 1584 "HAL FSE %pK already valid", fse); 1585 return NULL; 1586 } 1587 1588 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_0, SRC_IP_127_96) = 1589 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_0, SRC_IP_127_96, 1590 (flow->tuple_info.src_ip_127_96)); 1591 1592 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_1, SRC_IP_95_64) = 1593 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_1, SRC_IP_95_64, 1594 (flow->tuple_info.src_ip_95_64)); 1595 1596 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_2, SRC_IP_63_32) = 1597 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_2, SRC_IP_63_32, 1598 (flow->tuple_info.src_ip_63_32)); 1599 1600 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_3, SRC_IP_31_0) = 1601 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_3, SRC_IP_31_0, 1602 (flow->tuple_info.src_ip_31_0)); 1603 1604 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_4, DEST_IP_127_96) = 1605 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_4, DEST_IP_127_96, 1606 (flow->tuple_info.dest_ip_127_96)); 1607 1608 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_5, DEST_IP_95_64) = 1609 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_5, DEST_IP_95_64, 1610 (flow->tuple_info.dest_ip_95_64)); 1611 1612 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_6, DEST_IP_63_32) = 1613 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_6, DEST_IP_63_32, 1614 (flow->tuple_info.dest_ip_63_32)); 1615 1616 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_7, DEST_IP_31_0) = 1617 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_7, DEST_IP_31_0, 1618 (flow->tuple_info.dest_ip_31_0)); 1619 1620 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, DEST_PORT); 1621 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, DEST_PORT) |= 1622 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_8, DEST_PORT, 1623 (flow->tuple_info.dest_port)); 1624 1625 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, SRC_PORT); 1626 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, SRC_PORT) |= 1627 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_8, SRC_PORT, 1628 (flow->tuple_info.src_port)); 1629 1630 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, L4_PROTOCOL); 1631 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, L4_PROTOCOL) |= 1632 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, L4_PROTOCOL, 1633 flow->tuple_info.l4_protocol); 1634 1635 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_HANDLER); 1636 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_HANDLER) |= 1637 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_HANDLER, 1638 flow->reo_destination_handler); 1639 1640 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, VALID); 1641 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, VALID) |= 1642 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, VALID, 1); 1643 1644 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_10, METADATA); 1645 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_10, METADATA) = 1646 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_10, METADATA, 1647 (flow->fse_metadata)); 1648 1649 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_INDICATION); 1650 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_INDICATION) |= 1651 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, 1652 REO_DESTINATION_INDICATION, 1653 flow->reo_destination_indication); 1654 1655 /* Reset all the other fields in FSE */ 1656 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, RESERVED_9); 1657 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, MSDU_DROP); 1658 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_11, MSDU_COUNT); 1659 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_12, MSDU_BYTE_COUNT); 1660 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_13, TIMESTAMP); 1661 1662 return fse; 1663 } 1664 1665 static 1666 void hal_compute_reo_remap_ix2_ix3_6490(uint32_t *ring, uint32_t num_rings, 1667 uint32_t *remap1, uint32_t *remap2) 1668 { 1669 switch (num_rings) { 1670 case 3: 1671 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 1672 HAL_REO_REMAP_IX2(ring[1], 17) | 1673 HAL_REO_REMAP_IX2(ring[2], 18) | 1674 HAL_REO_REMAP_IX2(ring[0], 19) | 1675 HAL_REO_REMAP_IX2(ring[1], 20) | 1676 HAL_REO_REMAP_IX2(ring[2], 21) | 1677 HAL_REO_REMAP_IX2(ring[0], 22) | 1678 HAL_REO_REMAP_IX2(ring[1], 23); 1679 1680 *remap2 = HAL_REO_REMAP_IX3(ring[2], 24) | 1681 HAL_REO_REMAP_IX3(ring[0], 25) | 1682 HAL_REO_REMAP_IX3(ring[1], 26) | 1683 HAL_REO_REMAP_IX3(ring[2], 27) | 1684 HAL_REO_REMAP_IX3(ring[0], 28) | 1685 HAL_REO_REMAP_IX3(ring[1], 29) | 1686 HAL_REO_REMAP_IX3(ring[2], 30) | 1687 HAL_REO_REMAP_IX3(ring[0], 31); 1688 break; 1689 case 4: 1690 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 1691 HAL_REO_REMAP_IX2(ring[1], 17) | 1692 HAL_REO_REMAP_IX2(ring[2], 18) | 1693 HAL_REO_REMAP_IX2(ring[3], 19) | 1694 HAL_REO_REMAP_IX2(ring[0], 20) | 1695 HAL_REO_REMAP_IX2(ring[1], 21) | 1696 HAL_REO_REMAP_IX2(ring[2], 22) | 1697 HAL_REO_REMAP_IX2(ring[3], 23); 1698 1699 *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) | 1700 HAL_REO_REMAP_IX3(ring[1], 25) | 1701 HAL_REO_REMAP_IX3(ring[2], 26) | 1702 HAL_REO_REMAP_IX3(ring[3], 27) | 1703 HAL_REO_REMAP_IX3(ring[0], 28) | 1704 HAL_REO_REMAP_IX3(ring[1], 29) | 1705 HAL_REO_REMAP_IX3(ring[2], 30) | 1706 HAL_REO_REMAP_IX3(ring[3], 31); 1707 break; 1708 } 1709 } 1710 1711 static 1712 void hal_compute_reo_remap_ix0_6490(uint32_t *remap0) 1713 { 1714 *remap0 = HAL_REO_REMAP_IX0(REO_REMAP_SW1, 0) | 1715 HAL_REO_REMAP_IX0(REO_REMAP_SW1, 1) | 1716 HAL_REO_REMAP_IX0(REO_REMAP_SW2, 2) | 1717 HAL_REO_REMAP_IX0(REO_REMAP_SW3, 3) | 1718 HAL_REO_REMAP_IX0(REO_REMAP_SW2, 4) | 1719 HAL_REO_REMAP_IX0(REO_REMAP_RELEASE, 5) | 1720 HAL_REO_REMAP_IX0(REO_REMAP_FW, 6) | 1721 HAL_REO_REMAP_IX0(REO_REMAP_FW, 7); 1722 } 1723 1724 #ifdef WLAN_FEATURE_MARK_FIRST_WAKEUP_PACKET 1725 /** 1726 * hal_get_first_wow_wakeup_packet_6490() - Function to retrieve 1727 * rx_msdu_end_1_reserved_1a 1728 * @buf: Network buffer 1729 * 1730 * reserved_1a is used by target to tag the first packet that wakes up host from 1731 * WoW 1732 * 1733 * Return: 1 to indicate it is first packet received that wakes up host from 1734 * WoW. Otherwise 0 1735 */ 1736 static uint8_t hal_get_first_wow_wakeup_packet_6490(uint8_t *buf) 1737 { 1738 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 1739 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1740 1741 return HAL_RX_MSDU_END_RESERVED_1A_GET(msdu_end); 1742 } 1743 #endif 1744 1745 /** 1746 * hal_rx_tlv_l3_type_get_6490() - Function to retrieve l3_type 1747 * @buf: Network buffer 1748 * 1749 * Return: l3_type 1750 */ 1751 static uint32_t hal_rx_tlv_l3_type_get_6490(uint8_t *buf) 1752 { 1753 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 1754 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1755 1756 return HAL_RX_MSDU_END_L3_TYPE_GET(msdu_end); 1757 } 1758 1759 static void hal_hw_txrx_ops_attach_qca6490(struct hal_soc *hal_soc) 1760 { 1761 /* init and setup */ 1762 hal_soc->ops->hal_srng_dst_hw_init = hal_srng_dst_hw_init_generic; 1763 hal_soc->ops->hal_srng_src_hw_init = hal_srng_src_hw_init_generic; 1764 hal_soc->ops->hal_get_hw_hptp = hal_get_hw_hptp_generic; 1765 hal_soc->ops->hal_reo_setup = hal_reo_setup_generic_li; 1766 hal_soc->ops->hal_get_window_address = hal_get_window_address_6490; 1767 hal_soc->ops->hal_reo_set_err_dst_remap = 1768 hal_reo_set_err_dst_remap_6490; 1769 1770 /* tx */ 1771 hal_soc->ops->hal_tx_desc_set_dscp_tid_table_id = 1772 hal_tx_desc_set_dscp_tid_table_id_6490; 1773 hal_soc->ops->hal_tx_set_dscp_tid_map = hal_tx_set_dscp_tid_map_6490; 1774 hal_soc->ops->hal_tx_update_dscp_tid = hal_tx_update_dscp_tid_6490; 1775 hal_soc->ops->hal_tx_desc_set_lmac_id = hal_tx_desc_set_lmac_id_6490; 1776 hal_soc->ops->hal_tx_desc_set_buf_addr = 1777 hal_tx_desc_set_buf_addr_generic_li; 1778 hal_soc->ops->hal_tx_desc_set_search_type = 1779 hal_tx_desc_set_search_type_generic_li; 1780 hal_soc->ops->hal_tx_desc_set_search_index = 1781 hal_tx_desc_set_search_index_generic_li; 1782 hal_soc->ops->hal_tx_desc_set_cache_set_num = 1783 hal_tx_desc_set_cache_set_num_generic_li; 1784 hal_soc->ops->hal_tx_comp_get_status = 1785 hal_tx_comp_get_status_generic_li; 1786 hal_soc->ops->hal_tx_comp_get_release_reason = 1787 hal_tx_comp_get_release_reason_generic_li; 1788 hal_soc->ops->hal_get_wbm_internal_error = 1789 hal_get_wbm_internal_error_generic_li; 1790 hal_soc->ops->hal_tx_desc_set_mesh_en = hal_tx_desc_set_mesh_en_6490; 1791 hal_soc->ops->hal_tx_init_cmd_credit_ring = 1792 hal_tx_init_cmd_credit_ring_6490; 1793 1794 /* rx */ 1795 hal_soc->ops->hal_rx_msdu_start_nss_get = 1796 hal_rx_msdu_start_nss_get_6490; 1797 hal_soc->ops->hal_rx_mon_hw_desc_get_mpdu_status = 1798 hal_rx_mon_hw_desc_get_mpdu_status_6490; 1799 hal_soc->ops->hal_rx_get_tlv = hal_rx_get_tlv_6490; 1800 hal_soc->ops->hal_rx_proc_phyrx_other_receive_info_tlv = 1801 hal_rx_proc_phyrx_other_receive_info_tlv_6490; 1802 1803 hal_soc->ops->hal_rx_dump_msdu_end_tlv = hal_rx_dump_msdu_end_tlv_6490; 1804 hal_soc->ops->hal_rx_dump_rx_attention_tlv = 1805 hal_rx_dump_rx_attention_tlv_generic_li; 1806 hal_soc->ops->hal_rx_dump_msdu_start_tlv = 1807 hal_rx_dump_msdu_start_tlv_6490; 1808 hal_soc->ops->hal_rx_dump_mpdu_start_tlv = 1809 hal_rx_dump_mpdu_start_tlv_generic_li; 1810 hal_soc->ops->hal_rx_dump_mpdu_end_tlv = 1811 hal_rx_dump_mpdu_end_tlv_generic_li; 1812 hal_soc->ops->hal_rx_dump_pkt_hdr_tlv = 1813 hal_rx_dump_pkt_hdr_tlv_generic_li; 1814 1815 hal_soc->ops->hal_get_link_desc_size = hal_get_link_desc_size_6490; 1816 hal_soc->ops->hal_rx_mpdu_start_tid_get = 1817 hal_rx_mpdu_start_tid_get_6490; 1818 hal_soc->ops->hal_rx_msdu_start_reception_type_get = 1819 hal_rx_msdu_start_reception_type_get_6490; 1820 hal_soc->ops->hal_rx_msdu_end_da_idx_get = 1821 hal_rx_msdu_end_da_idx_get_6490; 1822 hal_soc->ops->hal_rx_msdu_desc_info_get_ptr = 1823 hal_rx_msdu_desc_info_get_ptr_6490; 1824 hal_soc->ops->hal_rx_link_desc_msdu0_ptr = 1825 hal_rx_link_desc_msdu0_ptr_6490; 1826 hal_soc->ops->hal_reo_status_get_header = 1827 hal_reo_status_get_header_6490; 1828 hal_soc->ops->hal_rx_status_get_tlv_info = 1829 hal_rx_status_get_tlv_info_generic_li; 1830 hal_soc->ops->hal_rx_wbm_err_info_get = 1831 hal_rx_wbm_err_info_get_generic_li; 1832 1833 hal_soc->ops->hal_tx_set_pcp_tid_map = 1834 hal_tx_set_pcp_tid_map_generic_li; 1835 hal_soc->ops->hal_tx_update_pcp_tid_map = 1836 hal_tx_update_pcp_tid_generic_li; 1837 hal_soc->ops->hal_tx_set_tidmap_prty = 1838 hal_tx_update_tidmap_prty_generic_li; 1839 hal_soc->ops->hal_rx_get_rx_fragment_number = 1840 hal_rx_get_rx_fragment_number_6490; 1841 hal_soc->ops->hal_rx_msdu_end_da_is_mcbc_get = 1842 hal_rx_msdu_end_da_is_mcbc_get_6490; 1843 hal_soc->ops->hal_rx_msdu_end_sa_is_valid_get = 1844 hal_rx_msdu_end_sa_is_valid_get_6490; 1845 hal_soc->ops->hal_rx_msdu_end_sa_idx_get = 1846 hal_rx_msdu_end_sa_idx_get_6490; 1847 hal_soc->ops->hal_rx_desc_is_first_msdu = 1848 hal_rx_desc_is_first_msdu_6490; 1849 hal_soc->ops->hal_rx_msdu_end_l3_hdr_padding_get = 1850 hal_rx_msdu_end_l3_hdr_padding_get_6490; 1851 hal_soc->ops->hal_rx_encryption_info_valid = 1852 hal_rx_encryption_info_valid_6490; 1853 hal_soc->ops->hal_rx_print_pn = hal_rx_print_pn_6490; 1854 hal_soc->ops->hal_rx_msdu_end_first_msdu_get = 1855 hal_rx_msdu_end_first_msdu_get_6490; 1856 hal_soc->ops->hal_rx_msdu_end_da_is_valid_get = 1857 hal_rx_msdu_end_da_is_valid_get_6490; 1858 hal_soc->ops->hal_rx_msdu_end_last_msdu_get = 1859 hal_rx_msdu_end_last_msdu_get_6490; 1860 hal_soc->ops->hal_rx_get_mpdu_mac_ad4_valid = 1861 hal_rx_get_mpdu_mac_ad4_valid_6490; 1862 hal_soc->ops->hal_rx_mpdu_start_sw_peer_id_get = 1863 hal_rx_mpdu_start_sw_peer_id_get_6490; 1864 hal_soc->ops->hal_rx_tlv_peer_meta_data_get = 1865 hal_rx_mpdu_peer_meta_data_get_li; 1866 hal_soc->ops->hal_rx_mpdu_get_to_ds = hal_rx_mpdu_get_to_ds_6490; 1867 hal_soc->ops->hal_rx_mpdu_get_fr_ds = hal_rx_mpdu_get_fr_ds_6490; 1868 hal_soc->ops->hal_rx_get_mpdu_frame_control_valid = 1869 hal_rx_get_mpdu_frame_control_valid_6490; 1870 hal_soc->ops->hal_rx_get_frame_ctrl_field = 1871 hal_rx_get_frame_ctrl_field_li; 1872 hal_soc->ops->hal_rx_mpdu_get_addr1 = hal_rx_mpdu_get_addr1_6490; 1873 hal_soc->ops->hal_rx_mpdu_get_addr2 = hal_rx_mpdu_get_addr2_6490; 1874 hal_soc->ops->hal_rx_mpdu_get_addr3 = hal_rx_mpdu_get_addr3_6490; 1875 hal_soc->ops->hal_rx_mpdu_get_addr4 = hal_rx_mpdu_get_addr4_6490; 1876 hal_soc->ops->hal_rx_get_mpdu_sequence_control_valid = 1877 hal_rx_get_mpdu_sequence_control_valid_6490; 1878 hal_soc->ops->hal_rx_is_unicast = hal_rx_is_unicast_6490; 1879 hal_soc->ops->hal_rx_tid_get = hal_rx_tid_get_6490; 1880 hal_soc->ops->hal_rx_hw_desc_get_ppduid_get = 1881 hal_rx_hw_desc_get_ppduid_get_6490; 1882 hal_soc->ops->hal_rx_msdu0_buffer_addr_lsb = 1883 hal_rx_msdu0_buffer_addr_lsb_6490; 1884 hal_soc->ops->hal_rx_msdu_desc_info_ptr_get = 1885 hal_rx_msdu_desc_info_ptr_get_6490; 1886 hal_soc->ops->hal_ent_mpdu_desc_info = hal_ent_mpdu_desc_info_6490; 1887 hal_soc->ops->hal_dst_mpdu_desc_info = hal_dst_mpdu_desc_info_6490; 1888 hal_soc->ops->hal_rx_phy_legacy_get_rssi = 1889 hal_rx_phy_legacy_get_rssi_6490; 1890 hal_soc->ops->hal_rx_get_fc_valid = hal_rx_get_fc_valid_6490; 1891 hal_soc->ops->hal_rx_get_to_ds_flag = hal_rx_get_to_ds_flag_6490; 1892 hal_soc->ops->hal_rx_get_mac_addr2_valid = 1893 hal_rx_get_mac_addr2_valid_6490; 1894 hal_soc->ops->hal_rx_get_filter_category = 1895 hal_rx_get_filter_category_6490; 1896 hal_soc->ops->hal_rx_get_ppdu_id = hal_rx_get_ppdu_id_6490; 1897 hal_soc->ops->hal_reo_config = hal_reo_config_6490; 1898 hal_soc->ops->hal_rx_msdu_flow_idx_get = hal_rx_msdu_flow_idx_get_6490; 1899 hal_soc->ops->hal_rx_msdu_flow_idx_invalid = 1900 hal_rx_msdu_flow_idx_invalid_6490; 1901 hal_soc->ops->hal_rx_msdu_flow_idx_timeout = 1902 hal_rx_msdu_flow_idx_timeout_6490; 1903 hal_soc->ops->hal_rx_msdu_fse_metadata_get = 1904 hal_rx_msdu_fse_metadata_get_6490; 1905 hal_soc->ops->hal_rx_msdu_cce_match_get = 1906 hal_rx_msdu_cce_match_get_li; 1907 hal_soc->ops->hal_rx_msdu_cce_metadata_get = 1908 hal_rx_msdu_cce_metadata_get_6490; 1909 hal_soc->ops->hal_rx_msdu_get_flow_params = 1910 hal_rx_msdu_get_flow_params_6490; 1911 hal_soc->ops->hal_rx_tlv_get_tcp_chksum = 1912 hal_rx_tlv_get_tcp_chksum_6490; 1913 hal_soc->ops->hal_rx_get_rx_sequence = hal_rx_get_rx_sequence_6490; 1914 #if defined(QCA_WIFI_QCA6490) && defined(WLAN_CFR_ENABLE) && \ 1915 defined(WLAN_ENH_CFR_ENABLE) 1916 hal_soc->ops->hal_rx_get_bb_info = hal_rx_get_bb_info_6490; 1917 hal_soc->ops->hal_rx_get_rtt_info = hal_rx_get_rtt_info_6490; 1918 #endif 1919 /* rx - msdu end fast path info fields */ 1920 hal_soc->ops->hal_rx_msdu_packet_metadata_get = 1921 hal_rx_msdu_packet_metadata_get_generic_li; 1922 hal_soc->ops->hal_rx_get_fisa_cumulative_l4_checksum = 1923 hal_rx_get_fisa_cumulative_l4_checksum_6490; 1924 hal_soc->ops->hal_rx_get_fisa_cumulative_ip_length = 1925 hal_rx_get_fisa_cumulative_ip_length_6490; 1926 hal_soc->ops->hal_rx_get_udp_proto = hal_rx_get_udp_proto_6490; 1927 hal_soc->ops->hal_rx_get_fisa_flow_agg_continuation = 1928 hal_rx_get_flow_agg_continuation_6490; 1929 hal_soc->ops->hal_rx_get_fisa_flow_agg_count = 1930 hal_rx_get_flow_agg_count_6490; 1931 hal_soc->ops->hal_rx_get_fisa_timeout = hal_rx_get_fisa_timeout_6490; 1932 hal_soc->ops->hal_rx_mpdu_start_tlv_tag_valid = 1933 hal_rx_mpdu_start_tlv_tag_valid_6490; 1934 1935 /* rx - TLV struct offsets */ 1936 hal_soc->ops->hal_rx_msdu_end_offset_get = 1937 hal_rx_msdu_end_offset_get_generic; 1938 hal_soc->ops->hal_rx_attn_offset_get = hal_rx_attn_offset_get_generic; 1939 hal_soc->ops->hal_rx_msdu_start_offset_get = 1940 hal_rx_msdu_start_offset_get_generic; 1941 hal_soc->ops->hal_rx_mpdu_start_offset_get = 1942 hal_rx_mpdu_start_offset_get_generic; 1943 hal_soc->ops->hal_rx_mpdu_end_offset_get = 1944 hal_rx_mpdu_end_offset_get_generic; 1945 #ifndef NO_RX_PKT_HDR_TLV 1946 hal_soc->ops->hal_rx_pkt_tlv_offset_get = 1947 hal_rx_pkt_tlv_offset_get_generic; 1948 #endif 1949 hal_soc->ops->hal_rx_flow_setup_fse = hal_rx_flow_setup_fse_6490; 1950 hal_soc->ops->hal_rx_flow_get_tuple_info = 1951 hal_rx_flow_get_tuple_info_li; 1952 hal_soc->ops->hal_rx_flow_delete_entry = 1953 hal_rx_flow_delete_entry_li; 1954 hal_soc->ops->hal_rx_fst_get_fse_size = hal_rx_fst_get_fse_size_li; 1955 hal_soc->ops->hal_compute_reo_remap_ix2_ix3 = 1956 hal_compute_reo_remap_ix2_ix3_6490; 1957 hal_soc->ops->hal_rx_msdu_get_reo_destination_indication = 1958 hal_rx_msdu_get_reo_destination_indication_6490; 1959 hal_soc->ops->hal_setup_link_idle_list = 1960 hal_setup_link_idle_list_generic_li; 1961 #ifdef WLAN_FEATURE_MARK_FIRST_WAKEUP_PACKET 1962 hal_soc->ops->hal_get_first_wow_wakeup_packet = 1963 hal_get_first_wow_wakeup_packet_6490; 1964 #endif 1965 hal_soc->ops->hal_rx_tlv_get_pn_num = hal_rx_tlv_get_pn_num_li; 1966 hal_soc->ops->hal_rx_tlv_mic_err_get = hal_rx_tlv_mic_err_get_li; 1967 hal_soc->ops->hal_rx_tlv_decrypt_err_get = 1968 hal_rx_tlv_decrypt_err_get_li; 1969 hal_soc->ops->hal_rx_tlv_get_pkt_capture_flags = 1970 hal_rx_tlv_get_pkt_capture_flags_li; 1971 hal_soc->ops->hal_rx_mpdu_info_ampdu_flag_get = 1972 hal_rx_mpdu_info_ampdu_flag_get_li; 1973 hal_soc->ops->hal_compute_reo_remap_ix0 = 1974 hal_compute_reo_remap_ix0_6490; 1975 hal_soc->ops->hal_rx_tlv_l3_type_get = 1976 hal_rx_tlv_l3_type_get_6490; 1977 hal_soc->ops->hal_rx_tlv_msdu_len_get = 1978 hal_rx_msdu_start_get_len_6490; 1979 }; 1980 1981 struct hal_hw_srng_config hw_srng_table_6490[] = { 1982 /* TODO: max_rings can populated by querying HW capabilities */ 1983 { /* REO_DST */ 1984 .start_ring_id = HAL_SRNG_REO2SW1, 1985 .max_rings = 4, 1986 .entry_size = sizeof(struct reo_destination_ring) >> 2, 1987 .lmac_ring = FALSE, 1988 .ring_dir = HAL_SRNG_DST_RING, 1989 .reg_start = { 1990 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR( 1991 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1992 HWIO_REO_R2_REO2SW1_RING_HP_ADDR( 1993 SEQ_WCSS_UMAC_REO_REG_OFFSET) 1994 }, 1995 .reg_size = { 1996 HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(0) - 1997 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(0), 1998 HWIO_REO_R2_REO2SW2_RING_HP_ADDR(0) - 1999 HWIO_REO_R2_REO2SW1_RING_HP_ADDR(0), 2000 }, 2001 .max_size = 2002 HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_BMSK >> 2003 HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_SHFT, 2004 }, 2005 { /* REO_EXCEPTION */ 2006 /* Designating REO2TCL ring as exception ring. This ring is 2007 * similar to other REO2SW rings though it is named as REO2TCL. 2008 * Any of theREO2SW rings can be used as exception ring. 2009 */ 2010 .start_ring_id = HAL_SRNG_REO2TCL, 2011 .max_rings = 1, 2012 .entry_size = sizeof(struct reo_destination_ring) >> 2, 2013 .lmac_ring = FALSE, 2014 .ring_dir = HAL_SRNG_DST_RING, 2015 .reg_start = { 2016 HWIO_REO_R0_REO2TCL_RING_BASE_LSB_ADDR( 2017 SEQ_WCSS_UMAC_REO_REG_OFFSET), 2018 HWIO_REO_R2_REO2TCL_RING_HP_ADDR( 2019 SEQ_WCSS_UMAC_REO_REG_OFFSET) 2020 }, 2021 /* Single ring - provide ring size if multiple rings of this 2022 * type are supported 2023 */ 2024 .reg_size = {}, 2025 .max_size = 2026 HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_BMSK >> 2027 HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_SHFT, 2028 }, 2029 { /* REO_REINJECT */ 2030 .start_ring_id = HAL_SRNG_SW2REO, 2031 .max_rings = 1, 2032 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 2033 .lmac_ring = FALSE, 2034 .ring_dir = HAL_SRNG_SRC_RING, 2035 .reg_start = { 2036 HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR( 2037 SEQ_WCSS_UMAC_REO_REG_OFFSET), 2038 HWIO_REO_R2_SW2REO_RING_HP_ADDR( 2039 SEQ_WCSS_UMAC_REO_REG_OFFSET) 2040 }, 2041 /* Single ring - provide ring size if multiple rings of this 2042 * type are supported 2043 */ 2044 .reg_size = {}, 2045 .max_size = HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_BMSK >> 2046 HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_SHFT, 2047 }, 2048 { /* REO_CMD */ 2049 .start_ring_id = HAL_SRNG_REO_CMD, 2050 .max_rings = 1, 2051 .entry_size = (sizeof(struct tlv_32_hdr) + 2052 sizeof(struct reo_get_queue_stats)) >> 2, 2053 .lmac_ring = FALSE, 2054 .ring_dir = HAL_SRNG_SRC_RING, 2055 .reg_start = { 2056 HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR( 2057 SEQ_WCSS_UMAC_REO_REG_OFFSET), 2058 HWIO_REO_R2_REO_CMD_RING_HP_ADDR( 2059 SEQ_WCSS_UMAC_REO_REG_OFFSET), 2060 }, 2061 /* Single ring - provide ring size if multiple rings of this 2062 * type are supported 2063 */ 2064 .reg_size = {}, 2065 .max_size = 2066 HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_BMSK >> 2067 HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_SHFT, 2068 }, 2069 { /* REO_STATUS */ 2070 .start_ring_id = HAL_SRNG_REO_STATUS, 2071 .max_rings = 1, 2072 .entry_size = (sizeof(struct tlv_32_hdr) + 2073 sizeof(struct reo_get_queue_stats_status)) >> 2, 2074 .lmac_ring = FALSE, 2075 .ring_dir = HAL_SRNG_DST_RING, 2076 .reg_start = { 2077 HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR( 2078 SEQ_WCSS_UMAC_REO_REG_OFFSET), 2079 HWIO_REO_R2_REO_STATUS_RING_HP_ADDR( 2080 SEQ_WCSS_UMAC_REO_REG_OFFSET), 2081 }, 2082 /* Single ring - provide ring size if multiple rings of this 2083 * type are supported 2084 */ 2085 .reg_size = {}, 2086 .max_size = 2087 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> 2088 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, 2089 }, 2090 { /* TCL_DATA */ 2091 .start_ring_id = HAL_SRNG_SW2TCL1, 2092 .max_rings = 3, 2093 .entry_size = (sizeof(struct tlv_32_hdr) + 2094 sizeof(struct tcl_data_cmd)) >> 2, 2095 .lmac_ring = FALSE, 2096 .ring_dir = HAL_SRNG_SRC_RING, 2097 .reg_start = { 2098 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR( 2099 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 2100 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR( 2101 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 2102 }, 2103 .reg_size = { 2104 HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(0) - 2105 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(0), 2106 HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(0) - 2107 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(0), 2108 }, 2109 .max_size = 2110 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK >> 2111 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT, 2112 }, 2113 { /* TCL_CMD */ 2114 .start_ring_id = HAL_SRNG_SW2TCL_CMD, 2115 .max_rings = 1, 2116 .entry_size = (sizeof(struct tlv_32_hdr) + 2117 sizeof(struct tcl_gse_cmd)) >> 2, 2118 .lmac_ring = FALSE, 2119 .ring_dir = HAL_SRNG_SRC_RING, 2120 .reg_start = { 2121 HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_ADDR( 2122 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 2123 HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_ADDR( 2124 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 2125 }, 2126 /* Single ring - provide ring size if multiple rings of this 2127 * type are supported 2128 */ 2129 .reg_size = {}, 2130 .max_size = 2131 HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_SIZE_BMSK >> 2132 HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_SIZE_SHFT, 2133 }, 2134 { /* TCL_STATUS */ 2135 .start_ring_id = HAL_SRNG_TCL_STATUS, 2136 .max_rings = 1, 2137 .entry_size = (sizeof(struct tlv_32_hdr) + 2138 sizeof(struct tcl_status_ring)) >> 2, 2139 .lmac_ring = FALSE, 2140 .ring_dir = HAL_SRNG_DST_RING, 2141 .reg_start = { 2142 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR( 2143 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 2144 HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR( 2145 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 2146 }, 2147 /* Single ring - provide ring size if multiple rings of this 2148 * type are supported 2149 */ 2150 .reg_size = {}, 2151 .max_size = 2152 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_BMSK >> 2153 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_SHFT, 2154 }, 2155 { /* CE_SRC */ 2156 .start_ring_id = HAL_SRNG_CE_0_SRC, 2157 .max_rings = 12, 2158 .entry_size = sizeof(struct ce_src_desc) >> 2, 2159 .lmac_ring = FALSE, 2160 .ring_dir = HAL_SRNG_SRC_RING, 2161 .reg_start = { 2162 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR( 2163 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET), 2164 HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR( 2165 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET), 2166 }, 2167 .reg_size = { 2168 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET - 2169 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET, 2170 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET - 2171 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET, 2172 }, 2173 .max_size = 2174 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >> 2175 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT, 2176 }, 2177 { /* CE_DST */ 2178 .start_ring_id = HAL_SRNG_CE_0_DST, 2179 .max_rings = 12, 2180 .entry_size = 8 >> 2, 2181 /*TODO: entry_size above should actually be 2182 * sizeof(struct ce_dst_desc) >> 2, but couldn't find definition 2183 * of struct ce_dst_desc in HW header files 2184 */ 2185 .lmac_ring = FALSE, 2186 .ring_dir = HAL_SRNG_SRC_RING, 2187 .reg_start = { 2188 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR( 2189 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 2190 HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR( 2191 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 2192 }, 2193 .reg_size = { 2194 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 2195 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 2196 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 2197 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 2198 }, 2199 .max_size = 2200 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >> 2201 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT, 2202 }, 2203 { /* CE_DST_STATUS */ 2204 .start_ring_id = HAL_SRNG_CE_0_DST_STATUS, 2205 .max_rings = 12, 2206 .entry_size = sizeof(struct ce_stat_desc) >> 2, 2207 .lmac_ring = FALSE, 2208 .ring_dir = HAL_SRNG_DST_RING, 2209 .reg_start = { 2210 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR( 2211 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 2212 HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR( 2213 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 2214 }, 2215 /* TODO: check destination status ring registers */ 2216 .reg_size = { 2217 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 2218 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 2219 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 2220 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 2221 }, 2222 .max_size = 2223 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> 2224 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, 2225 }, 2226 { /* WBM_IDLE_LINK */ 2227 .start_ring_id = HAL_SRNG_WBM_IDLE_LINK, 2228 .max_rings = 1, 2229 .entry_size = sizeof(struct wbm_link_descriptor_ring) >> 2, 2230 .lmac_ring = FALSE, 2231 .ring_dir = HAL_SRNG_SRC_RING, 2232 .reg_start = { 2233 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2234 HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2235 }, 2236 /* Single ring - provide ring size if multiple rings of this 2237 * type are supported 2238 */ 2239 .reg_size = {}, 2240 .max_size = 2241 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_BMSK >> 2242 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_SHFT, 2243 }, 2244 { /* SW2WBM_RELEASE */ 2245 .start_ring_id = HAL_SRNG_WBM_SW_RELEASE, 2246 .max_rings = 1, 2247 .entry_size = sizeof(struct wbm_release_ring) >> 2, 2248 .lmac_ring = FALSE, 2249 .ring_dir = HAL_SRNG_SRC_RING, 2250 .reg_start = { 2251 HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2252 HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2253 }, 2254 /* Single ring - provide ring size if multiple rings of this 2255 * type are supported 2256 */ 2257 .reg_size = {}, 2258 .max_size = 2259 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> 2260 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, 2261 }, 2262 { /* WBM2SW_RELEASE */ 2263 .start_ring_id = HAL_SRNG_WBM2SW0_RELEASE, 2264 #if defined(IPA_WDI3_TX_TWO_PIPES) || defined(TX_MULTI_TCL) || \ 2265 defined(CONFIG_PLD_PCIE_FW_SIM) 2266 .max_rings = 5, 2267 #else 2268 .max_rings = 4, 2269 #endif 2270 .entry_size = sizeof(struct wbm_release_ring) >> 2, 2271 .lmac_ring = FALSE, 2272 .ring_dir = HAL_SRNG_DST_RING, 2273 .reg_start = { 2274 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2275 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2276 }, 2277 .reg_size = { 2278 HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) - 2279 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2280 HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) - 2281 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2282 }, 2283 .max_size = 2284 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> 2285 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, 2286 }, 2287 { /* RXDMA_BUF */ 2288 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA0_BUF0, 2289 #ifdef IPA_OFFLOAD 2290 .max_rings = 3, 2291 #else 2292 .max_rings = 2, 2293 #endif 2294 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 2295 .lmac_ring = TRUE, 2296 .ring_dir = HAL_SRNG_SRC_RING, 2297 /* reg_start is not set because LMAC rings are not accessed 2298 * from host 2299 */ 2300 .reg_start = {}, 2301 .reg_size = {}, 2302 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2303 }, 2304 { /* RXDMA_DST */ 2305 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW0, 2306 .max_rings = 1, 2307 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 2308 .lmac_ring = TRUE, 2309 .ring_dir = HAL_SRNG_DST_RING, 2310 /* reg_start is not set because LMAC rings are not accessed 2311 * from host 2312 */ 2313 .reg_start = {}, 2314 .reg_size = {}, 2315 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2316 }, 2317 { /* RXDMA_MONITOR_BUF */ 2318 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA2_BUF, 2319 .max_rings = 1, 2320 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 2321 .lmac_ring = TRUE, 2322 .ring_dir = HAL_SRNG_SRC_RING, 2323 /* reg_start is not set because LMAC rings are not accessed 2324 * from host 2325 */ 2326 .reg_start = {}, 2327 .reg_size = {}, 2328 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2329 }, 2330 { /* RXDMA_MONITOR_STATUS */ 2331 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_STATBUF, 2332 .max_rings = 1, 2333 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 2334 .lmac_ring = TRUE, 2335 .ring_dir = HAL_SRNG_SRC_RING, 2336 /* reg_start is not set because LMAC rings are not accessed 2337 * from host 2338 */ 2339 .reg_start = {}, 2340 .reg_size = {}, 2341 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2342 }, 2343 { /* RXDMA_MONITOR_DST */ 2344 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW1, 2345 .max_rings = 1, 2346 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 2347 .lmac_ring = TRUE, 2348 .ring_dir = HAL_SRNG_DST_RING, 2349 /* reg_start is not set because LMAC rings are not accessed 2350 * from host 2351 */ 2352 .reg_start = {}, 2353 .reg_size = {}, 2354 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2355 }, 2356 { /* RXDMA_MONITOR_DESC */ 2357 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_DESC, 2358 .max_rings = 1, 2359 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 2360 .lmac_ring = TRUE, 2361 .ring_dir = HAL_SRNG_SRC_RING, 2362 /* reg_start is not set because LMAC rings are not accessed 2363 * from host 2364 */ 2365 .reg_start = {}, 2366 .reg_size = {}, 2367 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2368 }, 2369 { /* DIR_BUF_RX_DMA_SRC */ 2370 .start_ring_id = HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING, 2371 /* 2372 * one ring is for spectral scan 2373 * the other is for cfr 2374 */ 2375 .max_rings = 2, 2376 .entry_size = 2, 2377 .lmac_ring = TRUE, 2378 .ring_dir = HAL_SRNG_SRC_RING, 2379 /* reg_start is not set because LMAC rings are not accessed 2380 * from host 2381 */ 2382 .reg_start = {}, 2383 .reg_size = {}, 2384 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2385 }, 2386 #ifdef WLAN_FEATURE_CIF_CFR 2387 { /* WIFI_POS_SRC */ 2388 .start_ring_id = HAL_SRNG_WIFI_POS_SRC_DMA_RING, 2389 .max_rings = 1, 2390 .entry_size = sizeof(wmi_oem_dma_buf_release_entry) >> 2, 2391 .lmac_ring = TRUE, 2392 .ring_dir = HAL_SRNG_SRC_RING, 2393 /* reg_start is not set because LMAC rings are not accessed 2394 * from host 2395 */ 2396 .reg_start = {}, 2397 .reg_size = {}, 2398 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2399 }, 2400 #endif 2401 { /* REO2PPE */ 0}, 2402 { /* PPE2TCL */ 0}, 2403 { /* PPE_RELEASE */ 0}, 2404 { /* TX_MONITOR_BUF */ 0}, 2405 { /* TX_MONITOR_DST */ 0}, 2406 { /* SW2RXDMA_NEW */ 0}, 2407 { /* SW2RXDMA_LINK_RELEASE */ 0}, 2408 }; 2409 2410 /** 2411 * hal_qca6490_attach() - Attach 6490 target specific hal_soc ops, 2412 * offset and srng table 2413 * @hal_soc: HAL SoC context 2414 */ 2415 void hal_qca6490_attach(struct hal_soc *hal_soc) 2416 { 2417 hal_soc->hw_srng_table = hw_srng_table_6490; 2418 2419 hal_srng_hw_reg_offset_init_generic(hal_soc); 2420 2421 hal_hw_txrx_default_ops_attach_li(hal_soc); 2422 hal_hw_txrx_ops_attach_qca6490(hal_soc); 2423 } 2424