1 /* 2 * Copyright (c) 2019 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #include "qdf_types.h" 20 #include "qdf_util.h" 21 #include "qdf_types.h" 22 #include "qdf_lock.h" 23 #include "qdf_mem.h" 24 #include "qdf_nbuf.h" 25 #include "hal_hw_headers.h" 26 #include "hal_internal.h" 27 #include "hal_api.h" 28 #include "target_type.h" 29 #include "wcss_version.h" 30 #include "qdf_module.h" 31 32 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_OFFSET \ 33 RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_OFFSET 34 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_MASK \ 35 RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_MASK 36 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_LSB \ 37 RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_LSB 38 #define UNIFIED_PHYRX_HT_SIG_0_HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS_OFFSET \ 39 PHYRX_L_SIG_B_0_PHYRX_L_SIG_B_INFO_DETAILS_RATE_OFFSET 40 #define UNIFIED_PHYRX_L_SIG_B_0_L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS_OFFSET \ 41 PHYRX_L_SIG_B_0_PHYRX_L_SIG_B_INFO_DETAILS_RATE_OFFSET 42 #define UNIFIED_PHYRX_L_SIG_A_0_L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS_OFFSET \ 43 PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_RATE_OFFSET 44 #define UNIFIED_PHYRX_VHT_SIG_A_0_VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS_OFFSET \ 45 PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_OFFSET 46 #define UNIFIED_PHYRX_HE_SIG_A_SU_0_HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS_OFFSET \ 47 PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_OFFSET 48 #define UNIFIED_PHYRX_HE_SIG_A_MU_DL_0_HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_OFFSET \ 49 PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_OFFSET 50 #define UNIFIED_PHYRX_HE_SIG_B1_MU_0_HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_OFFSET \ 51 PHYRX_HE_SIG_B1_MU_0_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_OFFSET 52 #define UNIFIED_PHYRX_HE_SIG_B2_MU_0_HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_OFFSET \ 53 PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_OFFSET 54 #define UNIFIED_PHYRX_HE_SIG_B2_OFDMA_0_HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_OFFSET \ 55 PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_OFFSET 56 57 #define UNIFIED_PHYRX_RSSI_LEGACY_3_RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS_OFFSET \ 58 PHYRX_RSSI_LEGACY_3_RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS_OFFSET 59 #define UNIFIED_PHYRX_RSSI_LEGACY_19_RECEIVE_RSSI_INFO_PREAMBLE_RSSI_INFO_DETAILS_OFFSET \ 60 PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 61 #define UNIFIED_RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET \ 62 RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 63 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 64 RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET 65 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ 66 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET 67 #define UNIFIED_RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 68 RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET 69 #define UNIFIED_REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 70 REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET 71 #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC \ 72 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER 73 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ 74 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET 75 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 76 RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET 77 #define UNIFIED_TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 78 TCL_DATA_CMD_0_BUF_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 79 #define UNIFIED_TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 80 TCL_DATA_CMD_1_BUF_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 81 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET \ 82 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET 83 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB \ 84 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB 85 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK \ 86 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK 87 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB \ 88 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB 89 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK \ 90 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK 91 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB \ 92 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB 93 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK \ 94 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK 95 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB \ 96 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB 97 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK \ 98 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK 99 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB \ 100 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB 101 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK \ 102 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK 103 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_MASK \ 104 WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MASK 105 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_OFFSET \ 106 WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_OFFSET 107 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_LSB \ 108 WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_LSB 109 110 #include "hal_6490_tx.h" 111 #include "hal_6490_rx.h" 112 #include <hal_generic_api.h> 113 #include <hal_wbm.h> 114 115 /* 116 * hal_rx_msdu_start_nss_get_6490(): API to get the NSS 117 * Interval from rx_msdu_start 118 * 119 * @buf: pointer to the start of RX PKT TLV header 120 * Return: uint32_t(nss) 121 */ 122 static uint32_t 123 hal_rx_msdu_start_nss_get_6490(uint8_t *buf) 124 { 125 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 126 struct rx_msdu_start *msdu_start = 127 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 128 uint8_t mimo_ss_bitmap; 129 130 mimo_ss_bitmap = HAL_RX_MSDU_START_MIMO_SS_BITMAP(msdu_start); 131 132 return qdf_get_hweight8(mimo_ss_bitmap); 133 } 134 135 /** 136 * hal_rx_mon_hw_desc_get_mpdu_status_6490(): Retrieve MPDU status 137 * 138 * @ hw_desc_addr: Start address of Rx HW TLVs 139 * @ rs: Status for monitor mode 140 * 141 * Return: void 142 */ 143 static void hal_rx_mon_hw_desc_get_mpdu_status_6490(void *hw_desc_addr, 144 struct mon_rx_status *rs) 145 { 146 struct rx_msdu_start *rx_msdu_start; 147 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr; 148 uint32_t reg_value; 149 const uint32_t sgi_hw_to_cdp[] = { 150 CDP_SGI_0_8_US, 151 CDP_SGI_0_4_US, 152 CDP_SGI_1_6_US, 153 CDP_SGI_3_2_US, 154 }; 155 156 rx_msdu_start = &rx_desc->msdu_start_tlv.rx_msdu_start; 157 158 HAL_RX_GET_MSDU_AGGREGATION(rx_desc, rs); 159 160 rs->ant_signal_db = HAL_RX_GET(rx_msdu_start, 161 RX_MSDU_START_5, USER_RSSI); 162 rs->is_stbc = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, STBC); 163 164 reg_value = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, SGI); 165 rs->sgi = sgi_hw_to_cdp[reg_value]; 166 167 reg_value = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, RECEPTION_TYPE); 168 rs->beamformed = (reg_value == HAL_RX_RECEPTION_TYPE_MU_MIMO) ? 1 : 0; 169 /* TODO: rs->beamformed should be set for SU beamforming also */ 170 } 171 172 #define LINK_DESC_SIZE (NUM_OF_DWORDS_RX_MSDU_LINK << 2) 173 174 static uint32_t hal_get_link_desc_size_6490(void) 175 { 176 return LINK_DESC_SIZE; 177 } 178 179 /* 180 * hal_rx_get_tlv_6490(): API to get the tlv 181 * 182 * @rx_tlv: TLV data extracted from the rx packet 183 * Return: uint8_t 184 */ 185 static uint8_t hal_rx_get_tlv_6490(void *rx_tlv) 186 { 187 return HAL_RX_GET(rx_tlv, PHYRX_RSSI_LEGACY_0, RECEIVE_BANDWIDTH); 188 } 189 190 /** 191 * hal_rx_proc_phyrx_other_receive_info_tlv_6490() 192 * - process other receive info TLV 193 * @rx_tlv_hdr: pointer to TLV header 194 * @ppdu_info: pointer to ppdu_info 195 * 196 * Return: None 197 */ 198 static 199 void hal_rx_proc_phyrx_other_receive_info_tlv_6490(void *rx_tlv_hdr, 200 void *ppdu_info_handle) 201 { 202 uint32_t tlv_tag, tlv_len; 203 uint32_t temp_len, other_tlv_len, other_tlv_tag; 204 void *rx_tlv = (uint8_t *)rx_tlv_hdr + HAL_RX_TLV32_HDR_SIZE; 205 void *other_tlv_hdr = NULL; 206 void *other_tlv = NULL; 207 208 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv_hdr); 209 tlv_len = HAL_RX_GET_USER_TLV32_LEN(rx_tlv_hdr); 210 temp_len = 0; 211 212 other_tlv_hdr = rx_tlv + HAL_RX_TLV32_HDR_SIZE; 213 214 other_tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(other_tlv_hdr); 215 other_tlv_len = HAL_RX_GET_USER_TLV32_LEN(other_tlv_hdr); 216 temp_len += other_tlv_len; 217 other_tlv = other_tlv_hdr + HAL_RX_TLV32_HDR_SIZE; 218 219 switch (other_tlv_tag) { 220 default: 221 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR, 222 "%s unhandled TLV type: %d, TLV len:%d", 223 __func__, other_tlv_tag, other_tlv_len); 224 break; 225 } 226 } 227 228 /** 229 * hal_rx_dump_msdu_start_tlv_6490() : dump RX msdu_start TLV in structured 230 * human readable format. 231 * @ msdu_start: pointer the msdu_start TLV in pkt. 232 * @ dbg_level: log level. 233 * 234 * Return: void 235 */ 236 static void hal_rx_dump_msdu_start_tlv_6490(void *msdustart, uint8_t dbg_level) 237 { 238 struct rx_msdu_start *msdu_start = (struct rx_msdu_start *)msdustart; 239 240 hal_verbose_debug( 241 "rx_msdu_start tlv (1/2) - " 242 "rxpcu_mpdu_filter_in_category: %x " 243 "sw_frame_group_id: %x " 244 "phy_ppdu_id: %x " 245 "msdu_length: %x " 246 "ipsec_esp: %x " 247 "l3_offset: %x " 248 "ipsec_ah: %x " 249 "l4_offset: %x " 250 "msdu_number: %x " 251 "decap_format: %x " 252 "ipv4_proto: %x " 253 "ipv6_proto: %x " 254 "tcp_proto: %x " 255 "udp_proto: %x " 256 "ip_frag: %x " 257 "tcp_only_ack: %x " 258 "da_is_bcast_mcast: %x " 259 "ip4_protocol_ip6_next_header: %x " 260 "toeplitz_hash_2_or_4: %x " 261 "flow_id_toeplitz: %x " 262 "user_rssi: %x " 263 "pkt_type: %x " 264 "stbc: %x " 265 "sgi: %x " 266 "rate_mcs: %x " 267 "receive_bandwidth: %x " 268 "reception_type: %x " 269 "ppdu_start_timestamp: %u ", 270 msdu_start->rxpcu_mpdu_filter_in_category, 271 msdu_start->sw_frame_group_id, 272 msdu_start->phy_ppdu_id, 273 msdu_start->msdu_length, 274 msdu_start->ipsec_esp, 275 msdu_start->l3_offset, 276 msdu_start->ipsec_ah, 277 msdu_start->l4_offset, 278 msdu_start->msdu_number, 279 msdu_start->decap_format, 280 msdu_start->ipv4_proto, 281 msdu_start->ipv6_proto, 282 msdu_start->tcp_proto, 283 msdu_start->udp_proto, 284 msdu_start->ip_frag, 285 msdu_start->tcp_only_ack, 286 msdu_start->da_is_bcast_mcast, 287 msdu_start->ip4_protocol_ip6_next_header, 288 msdu_start->toeplitz_hash_2_or_4, 289 msdu_start->flow_id_toeplitz, 290 msdu_start->user_rssi, 291 msdu_start->pkt_type, 292 msdu_start->stbc, 293 msdu_start->sgi, 294 msdu_start->rate_mcs, 295 msdu_start->receive_bandwidth, 296 msdu_start->reception_type, 297 msdu_start->ppdu_start_timestamp); 298 299 hal_verbose_debug( 300 "rx_msdu_start tlv (2/2) - " 301 "sw_phy_meta_data: %x ", 302 msdu_start->sw_phy_meta_data); 303 } 304 305 /** 306 * hal_rx_dump_msdu_end_tlv_6490: dump RX msdu_end TLV in structured 307 * human readable format. 308 * @ msdu_end: pointer the msdu_end TLV in pkt. 309 * @ dbg_level: log level. 310 * 311 * Return: void 312 */ 313 static void hal_rx_dump_msdu_end_tlv_6490(void *msduend, 314 uint8_t dbg_level) 315 { 316 struct rx_msdu_end *msdu_end = (struct rx_msdu_end *)msduend; 317 318 QDF_TRACE(QDF_MODULE_ID_DP, dbg_level, 319 "rx_msdu_end tlv (1/2) - " 320 "rxpcu_mpdu_filter_in_category: %x " 321 "sw_frame_group_id: %x " 322 "phy_ppdu_id: %x " 323 "ip_hdr_chksum: %x " 324 "tcp_udp_chksum: %x " 325 "key_id_octet: %x " 326 "cce_super_rule: %x " 327 "cce_classify_not_done_truncat: %x " 328 "cce_classify_not_done_cce_dis: %x " 329 "ext_wapi_pn_63_48: %x " 330 "ext_wapi_pn_95_64: %x " 331 "ext_wapi_pn_127_96: %x " 332 "reported_mpdu_length: %x " 333 "first_msdu: %x " 334 "last_msdu: %x " 335 "sa_idx_timeout: %x " 336 "da_idx_timeout: %x " 337 "msdu_limit_error: %x " 338 "flow_idx_timeout: %x " 339 "flow_idx_invalid: %x " 340 "wifi_parser_error: %x " 341 "amsdu_parser_error: %x", 342 msdu_end->rxpcu_mpdu_filter_in_category, 343 msdu_end->sw_frame_group_id, 344 msdu_end->phy_ppdu_id, 345 msdu_end->ip_hdr_chksum, 346 msdu_end->tcp_udp_chksum, 347 msdu_end->key_id_octet, 348 msdu_end->cce_super_rule, 349 msdu_end->cce_classify_not_done_truncate, 350 msdu_end->cce_classify_not_done_cce_dis, 351 msdu_end->ext_wapi_pn_63_48, 352 msdu_end->ext_wapi_pn_95_64, 353 msdu_end->ext_wapi_pn_127_96, 354 msdu_end->reported_mpdu_length, 355 msdu_end->first_msdu, 356 msdu_end->last_msdu, 357 msdu_end->sa_idx_timeout, 358 msdu_end->da_idx_timeout, 359 msdu_end->msdu_limit_error, 360 msdu_end->flow_idx_timeout, 361 msdu_end->flow_idx_invalid, 362 msdu_end->wifi_parser_error, 363 msdu_end->amsdu_parser_error); 364 365 QDF_TRACE(QDF_MODULE_ID_DP, dbg_level, 366 "rx_msdu_end tlv (2/2)- " 367 "sa_is_valid: %x " 368 "da_is_valid: %x " 369 "da_is_mcbc: %x " 370 "l3_header_padding: %x " 371 "ipv6_options_crc: %x " 372 "tcp_seq_number: %x " 373 "tcp_ack_number: %x " 374 "tcp_flag: %x " 375 "lro_eligible: %x " 376 "window_size: %x " 377 "da_offset: %x " 378 "sa_offset: %x " 379 "da_offset_valid: %x " 380 "sa_offset_valid: %x " 381 "rule_indication_31_0: %x " 382 "rule_indication_63_32: %x " 383 "sa_idx: %x " 384 "da_idx: %x " 385 "msdu_drop: %x " 386 "reo_destination_indication: %x " 387 "flow_idx: %x " 388 "fse_metadata: %x " 389 "cce_metadata: %x " 390 "sa_sw_peer_id: %x ", 391 msdu_end->sa_is_valid, 392 msdu_end->da_is_valid, 393 msdu_end->da_is_mcbc, 394 msdu_end->l3_header_padding, 395 msdu_end->ipv6_options_crc, 396 msdu_end->tcp_seq_number, 397 msdu_end->tcp_ack_number, 398 msdu_end->tcp_flag, 399 msdu_end->lro_eligible, 400 msdu_end->window_size, 401 msdu_end->da_offset, 402 msdu_end->sa_offset, 403 msdu_end->da_offset_valid, 404 msdu_end->sa_offset_valid, 405 msdu_end->rule_indication_31_0, 406 msdu_end->rule_indication_63_32, 407 msdu_end->sa_idx, 408 msdu_end->da_idx_or_sw_peer_id, 409 msdu_end->msdu_drop, 410 msdu_end->reo_destination_indication, 411 msdu_end->flow_idx, 412 msdu_end->fse_metadata, 413 msdu_end->cce_metadata, 414 msdu_end->sa_sw_peer_id); 415 } 416 417 /* 418 * Get tid from RX_MPDU_START 419 */ 420 #define HAL_RX_MPDU_INFO_TID_GET(_rx_mpdu_info) \ 421 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_info), \ 422 RX_MPDU_INFO_7_TID_OFFSET)), \ 423 RX_MPDU_INFO_7_TID_MASK, \ 424 RX_MPDU_INFO_7_TID_LSB)) 425 426 static uint32_t hal_rx_mpdu_start_tid_get_6490(uint8_t *buf) 427 { 428 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 429 struct rx_mpdu_start *mpdu_start = 430 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 431 uint32_t tid; 432 433 tid = HAL_RX_MPDU_INFO_TID_GET(&mpdu_start->rx_mpdu_info_details); 434 435 return tid; 436 } 437 438 #define HAL_RX_MSDU_START_RECEPTION_TYPE_GET(_rx_msdu_start) \ 439 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start), \ 440 RX_MSDU_START_5_RECEPTION_TYPE_OFFSET)), \ 441 RX_MSDU_START_5_RECEPTION_TYPE_MASK, \ 442 RX_MSDU_START_5_RECEPTION_TYPE_LSB)) 443 444 /* 445 * hal_rx_msdu_start_reception_type_get(): API to get the reception type 446 * Interval from rx_msdu_start 447 * 448 * @buf: pointer to the start of RX PKT TLV header 449 * Return: uint32_t(reception_type) 450 */ 451 static 452 uint32_t hal_rx_msdu_start_reception_type_get_6490(uint8_t *buf) 453 { 454 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 455 struct rx_msdu_start *msdu_start = 456 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 457 uint32_t reception_type; 458 459 reception_type = HAL_RX_MSDU_START_RECEPTION_TYPE_GET(msdu_start); 460 461 return reception_type; 462 } 463 464 #define HAL_RX_MSDU_END_DA_IDX_GET(_rx_msdu_end) \ 465 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 466 RX_MSDU_END_11_DA_IDX_OR_SW_PEER_ID_OFFSET)), \ 467 RX_MSDU_END_11_DA_IDX_OR_SW_PEER_ID_MASK, \ 468 RX_MSDU_END_11_DA_IDX_OR_SW_PEER_ID_LSB)) 469 470 /** 471 * hal_rx_msdu_end_da_idx_get_6490: API to get da_idx 472 * from rx_msdu_end TLV 473 * 474 * @ buf: pointer to the start of RX PKT TLV headers 475 * Return: da index 476 */ 477 static uint16_t hal_rx_msdu_end_da_idx_get_6490(uint8_t *buf) 478 { 479 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 480 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 481 uint16_t da_idx; 482 483 da_idx = HAL_RX_MSDU_END_DA_IDX_GET(msdu_end); 484 485 return da_idx; 486 } 487 /** 488 * hal_rx_get_rx_fragment_number_6490(): Function to retrieve rx fragment number 489 * 490 * @nbuf: Network buffer 491 * Returns: rx fragment number 492 */ 493 static 494 uint8_t hal_rx_get_rx_fragment_number_6490(uint8_t *buf) 495 { 496 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 497 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 498 499 /* Return first 4 bits as fragment number */ 500 return (HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info) & 501 DOT11_SEQ_FRAG_MASK); 502 } 503 504 /** 505 * hal_rx_msdu_end_da_is_mcbc_get_6490(): API to check if pkt is MCBC 506 * from rx_msdu_end TLV 507 * 508 * @ buf: pointer to the start of RX PKT TLV headers 509 * Return: da_is_mcbc 510 */ 511 static uint8_t 512 hal_rx_msdu_end_da_is_mcbc_get_6490(uint8_t *buf) 513 { 514 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 515 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 516 517 return HAL_RX_MSDU_END_DA_IS_MCBC_GET(msdu_end); 518 } 519 520 /** 521 * hal_rx_msdu_end_sa_is_valid_get_6490(): API to get_6490 the 522 * sa_is_valid bit from rx_msdu_end TLV 523 * 524 * @ buf: pointer to the start of RX PKT TLV headers 525 * Return: sa_is_valid bit 526 */ 527 static uint8_t 528 hal_rx_msdu_end_sa_is_valid_get_6490(uint8_t *buf) 529 { 530 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 531 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 532 uint8_t sa_is_valid; 533 534 sa_is_valid = HAL_RX_MSDU_END_SA_IS_VALID_GET(msdu_end); 535 536 return sa_is_valid; 537 } 538 539 /** 540 * hal_rx_msdu_end_sa_idx_get_6490(): API to get_6490 the 541 * sa_idx from rx_msdu_end TLV 542 * 543 * @ buf: pointer to the start of RX PKT TLV headers 544 * Return: sa_idx (SA AST index) 545 */ 546 static 547 uint16_t hal_rx_msdu_end_sa_idx_get_6490(uint8_t *buf) 548 { 549 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 550 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 551 uint16_t sa_idx; 552 553 sa_idx = HAL_RX_MSDU_END_SA_IDX_GET(msdu_end); 554 555 return sa_idx; 556 } 557 558 /** 559 * hal_rx_desc_is_first_msdu_6490() - Check if first msdu 560 * 561 * @hal_soc_hdl: hal_soc handle 562 * @hw_desc_addr: hardware descriptor address 563 * 564 * Return: 0 - success/ non-zero failure 565 */ 566 static uint32_t hal_rx_desc_is_first_msdu_6490(void *hw_desc_addr) 567 { 568 struct rx_pkt_tlvs *rx_tlvs = (struct rx_pkt_tlvs *)hw_desc_addr; 569 struct rx_msdu_end *msdu_end = &rx_tlvs->msdu_end_tlv.rx_msdu_end; 570 571 return HAL_RX_GET(msdu_end, RX_MSDU_END_10, FIRST_MSDU); 572 } 573 574 /** 575 * hal_rx_msdu_end_l3_hdr_padding_get_6490(): API to get_6490 the 576 * l3_header padding from rx_msdu_end TLV 577 * 578 * @ buf: pointer to the start of RX PKT TLV headers 579 * Return: number of l3 header padding bytes 580 */ 581 static uint32_t hal_rx_msdu_end_l3_hdr_padding_get_6490(uint8_t *buf) 582 { 583 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 584 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 585 uint32_t l3_header_padding; 586 587 l3_header_padding = HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(msdu_end); 588 589 return l3_header_padding; 590 } 591 592 /* 593 * @ hal_rx_encryption_info_valid_6490: Returns encryption type. 594 * 595 * @ buf: rx_tlv_hdr of the received packet 596 * @ Return: encryption type 597 */ 598 static uint32_t hal_rx_encryption_info_valid_6490(uint8_t *buf) 599 { 600 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 601 struct rx_mpdu_start *mpdu_start = 602 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 603 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 604 uint32_t encryption_info = HAL_RX_MPDU_ENCRYPTION_INFO_VALID(mpdu_info); 605 606 return encryption_info; 607 } 608 609 /* 610 * @ hal_rx_print_pn_6490: Prints the PN of rx packet. 611 * 612 * @ buf: rx_tlv_hdr of the received packet 613 * @ Return: void 614 */ 615 static void hal_rx_print_pn_6490(uint8_t *buf) 616 { 617 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 618 struct rx_mpdu_start *mpdu_start = 619 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 620 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 621 622 uint32_t pn_31_0 = HAL_RX_MPDU_PN_31_0_GET(mpdu_info); 623 uint32_t pn_63_32 = HAL_RX_MPDU_PN_63_32_GET(mpdu_info); 624 uint32_t pn_95_64 = HAL_RX_MPDU_PN_95_64_GET(mpdu_info); 625 uint32_t pn_127_96 = HAL_RX_MPDU_PN_127_96_GET(mpdu_info); 626 627 hal_debug("PN number pn_127_96 0x%x pn_95_64 0x%x pn_63_32 0x%x pn_31_0 0x%x ", 628 pn_127_96, pn_95_64, pn_63_32, pn_31_0); 629 } 630 631 /** 632 * hal_rx_msdu_end_first_msdu_get_6490: API to get first msdu status 633 * from rx_msdu_end TLV 634 * 635 * @ buf: pointer to the start of RX PKT TLV headers 636 * Return: first_msdu 637 */ 638 static uint8_t hal_rx_msdu_end_first_msdu_get_6490(uint8_t *buf) 639 { 640 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 641 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 642 uint8_t first_msdu; 643 644 first_msdu = HAL_RX_MSDU_END_FIRST_MSDU_GET(msdu_end); 645 646 return first_msdu; 647 } 648 649 /** 650 * hal_rx_msdu_end_da_is_valid_get_6490: API to check if da is valid 651 * from rx_msdu_end TLV 652 * 653 * @ buf: pointer to the start of RX PKT TLV headers 654 * Return: da_is_valid 655 */ 656 static uint8_t hal_rx_msdu_end_da_is_valid_get_6490(uint8_t *buf) 657 { 658 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 659 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 660 uint8_t da_is_valid; 661 662 da_is_valid = HAL_RX_MSDU_END_DA_IS_VALID_GET(msdu_end); 663 664 return da_is_valid; 665 } 666 667 /** 668 * hal_rx_msdu_end_last_msdu_get_6490: API to get last msdu status 669 * from rx_msdu_end TLV 670 * 671 * @ buf: pointer to the start of RX PKT TLV headers 672 * Return: last_msdu 673 */ 674 static uint8_t hal_rx_msdu_end_last_msdu_get_6490(uint8_t *buf) 675 { 676 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 677 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 678 uint8_t last_msdu; 679 680 last_msdu = HAL_RX_MSDU_END_LAST_MSDU_GET(msdu_end); 681 682 return last_msdu; 683 } 684 685 /* 686 * hal_rx_get_mpdu_mac_ad4_valid_6490(): Retrieves if mpdu 4th addr is valid 687 * 688 * @nbuf: Network buffer 689 * Returns: value of mpdu 4th address valid field 690 */ 691 static bool hal_rx_get_mpdu_mac_ad4_valid_6490(uint8_t *buf) 692 { 693 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 694 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 695 bool ad4_valid = 0; 696 697 ad4_valid = HAL_RX_MPDU_GET_MAC_AD4_VALID(rx_mpdu_info); 698 699 return ad4_valid; 700 } 701 702 /** 703 * hal_rx_mpdu_start_sw_peer_id_get_6490: Retrieve sw peer_id 704 * @buf: network buffer 705 * 706 * Return: sw peer_id 707 */ 708 static uint32_t hal_rx_mpdu_start_sw_peer_id_get_6490(uint8_t *buf) 709 { 710 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 711 struct rx_mpdu_start *mpdu_start = 712 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 713 714 return HAL_RX_MPDU_INFO_SW_PEER_ID_GET( 715 &mpdu_start->rx_mpdu_info_details); 716 } 717 718 /** 719 * hal_rx_mpdu_get_to_ds_6490(): API to get the tods info 720 * from rx_mpdu_start 721 * 722 * @buf: pointer to the start of RX PKT TLV header 723 * Return: uint32_t(to_ds) 724 */ 725 static uint32_t hal_rx_mpdu_get_to_ds_6490(uint8_t *buf) 726 { 727 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 728 struct rx_mpdu_start *mpdu_start = 729 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 730 731 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 732 733 return HAL_RX_MPDU_GET_TODS(mpdu_info); 734 } 735 736 /* 737 * hal_rx_mpdu_get_fr_ds_6490(): API to get the from ds info 738 * from rx_mpdu_start 739 * 740 * @buf: pointer to the start of RX PKT TLV header 741 * Return: uint32_t(fr_ds) 742 */ 743 static uint32_t hal_rx_mpdu_get_fr_ds_6490(uint8_t *buf) 744 { 745 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 746 struct rx_mpdu_start *mpdu_start = 747 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 748 749 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 750 751 return HAL_RX_MPDU_GET_FROMDS(mpdu_info); 752 } 753 754 /* 755 * hal_rx_get_mpdu_frame_control_valid_6490(): Retrieves mpdu 756 * frame control valid 757 * 758 * @nbuf: Network buffer 759 * Returns: value of frame control valid field 760 */ 761 static uint8_t hal_rx_get_mpdu_frame_control_valid_6490(uint8_t *buf) 762 { 763 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 764 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 765 766 return HAL_RX_MPDU_GET_FRAME_CONTROL_VALID(rx_mpdu_info); 767 } 768 769 /* 770 * hal_rx_mpdu_get_addr1_6490(): API to check get address1 of the mpdu 771 * 772 * @buf: pointer to the start of RX PKT TLV headera 773 * @mac_addr: pointer to mac address 774 * Return: success/failure 775 */ 776 static QDF_STATUS hal_rx_mpdu_get_addr1_6490(uint8_t *buf, uint8_t *mac_addr) 777 { 778 struct __attribute__((__packed__)) hal_addr1 { 779 uint32_t ad1_31_0; 780 uint16_t ad1_47_32; 781 }; 782 783 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 784 struct rx_mpdu_start *mpdu_start = 785 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 786 787 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 788 struct hal_addr1 *addr = (struct hal_addr1 *)mac_addr; 789 uint32_t mac_addr_ad1_valid; 790 791 mac_addr_ad1_valid = HAL_RX_MPDU_MAC_ADDR_AD1_VALID_GET(mpdu_info); 792 793 if (mac_addr_ad1_valid) { 794 addr->ad1_31_0 = HAL_RX_MPDU_AD1_31_0_GET(mpdu_info); 795 addr->ad1_47_32 = HAL_RX_MPDU_AD1_47_32_GET(mpdu_info); 796 return QDF_STATUS_SUCCESS; 797 } 798 799 return QDF_STATUS_E_FAILURE; 800 } 801 802 /* 803 * hal_rx_mpdu_get_addr2_6490(): API to check get address2 of the mpdu 804 * in the packet 805 * 806 * @buf: pointer to the start of RX PKT TLV header 807 * @mac_addr: pointer to mac address 808 * Return: success/failure 809 */ 810 static QDF_STATUS hal_rx_mpdu_get_addr2_6490(uint8_t *buf, 811 uint8_t *mac_addr) 812 { 813 struct __attribute__((__packed__)) hal_addr2 { 814 uint16_t ad2_15_0; 815 uint32_t ad2_47_16; 816 }; 817 818 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 819 struct rx_mpdu_start *mpdu_start = 820 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 821 822 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 823 struct hal_addr2 *addr = (struct hal_addr2 *)mac_addr; 824 uint32_t mac_addr_ad2_valid; 825 826 mac_addr_ad2_valid = HAL_RX_MPDU_MAC_ADDR_AD2_VALID_GET(mpdu_info); 827 828 if (mac_addr_ad2_valid) { 829 addr->ad2_15_0 = HAL_RX_MPDU_AD2_15_0_GET(mpdu_info); 830 addr->ad2_47_16 = HAL_RX_MPDU_AD2_47_16_GET(mpdu_info); 831 return QDF_STATUS_SUCCESS; 832 } 833 834 return QDF_STATUS_E_FAILURE; 835 } 836 837 /* 838 * hal_rx_mpdu_get_addr3_6490(): API to get address3 of the mpdu 839 * in the packet 840 * 841 * @buf: pointer to the start of RX PKT TLV header 842 * @mac_addr: pointer to mac address 843 * Return: success/failure 844 */ 845 static QDF_STATUS hal_rx_mpdu_get_addr3_6490(uint8_t *buf, uint8_t *mac_addr) 846 { 847 struct __attribute__((__packed__)) hal_addr3 { 848 uint32_t ad3_31_0; 849 uint16_t ad3_47_32; 850 }; 851 852 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 853 struct rx_mpdu_start *mpdu_start = 854 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 855 856 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 857 struct hal_addr3 *addr = (struct hal_addr3 *)mac_addr; 858 uint32_t mac_addr_ad3_valid; 859 860 mac_addr_ad3_valid = HAL_RX_MPDU_MAC_ADDR_AD3_VALID_GET(mpdu_info); 861 862 if (mac_addr_ad3_valid) { 863 addr->ad3_31_0 = HAL_RX_MPDU_AD3_31_0_GET(mpdu_info); 864 addr->ad3_47_32 = HAL_RX_MPDU_AD3_47_32_GET(mpdu_info); 865 return QDF_STATUS_SUCCESS; 866 } 867 868 return QDF_STATUS_E_FAILURE; 869 } 870 871 /* 872 * hal_rx_mpdu_get_addr4_6490(): API to get address4 of the mpdu 873 * in the packet 874 * 875 * @buf: pointer to the start of RX PKT TLV header 876 * @mac_addr: pointer to mac address 877 * Return: success/failure 878 */ 879 static QDF_STATUS hal_rx_mpdu_get_addr4_6490(uint8_t *buf, uint8_t *mac_addr) 880 { 881 struct __attribute__((__packed__)) hal_addr4 { 882 uint32_t ad4_31_0; 883 uint16_t ad4_47_32; 884 }; 885 886 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 887 struct rx_mpdu_start *mpdu_start = 888 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 889 890 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 891 struct hal_addr4 *addr = (struct hal_addr4 *)mac_addr; 892 uint32_t mac_addr_ad4_valid; 893 894 mac_addr_ad4_valid = HAL_RX_MPDU_MAC_ADDR_AD4_VALID_GET(mpdu_info); 895 896 if (mac_addr_ad4_valid) { 897 addr->ad4_31_0 = HAL_RX_MPDU_AD4_31_0_GET(mpdu_info); 898 addr->ad4_47_32 = HAL_RX_MPDU_AD4_47_32_GET(mpdu_info); 899 return QDF_STATUS_SUCCESS; 900 } 901 902 return QDF_STATUS_E_FAILURE; 903 } 904 905 /* 906 * hal_rx_get_mpdu_sequence_control_valid_6490(): Get mpdu 907 * sequence control valid 908 * 909 * @nbuf: Network buffer 910 * Returns: value of sequence control valid field 911 */ 912 static uint8_t hal_rx_get_mpdu_sequence_control_valid_6490(uint8_t *buf) 913 { 914 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 915 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 916 917 return HAL_RX_MPDU_GET_SEQUENCE_CONTROL_VALID(rx_mpdu_info); 918 } 919 920 /** 921 * hal_rx_is_unicast_6490: check packet is unicast frame or not. 922 * 923 * @ buf: pointer to rx pkt TLV. 924 * 925 * Return: true on unicast. 926 */ 927 static bool hal_rx_is_unicast_6490(uint8_t *buf) 928 { 929 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 930 struct rx_mpdu_start *mpdu_start = 931 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 932 uint32_t grp_id; 933 uint8_t *rx_mpdu_info = (uint8_t *)&mpdu_start->rx_mpdu_info_details; 934 935 grp_id = (_HAL_MS((*_OFFSET_TO_WORD_PTR((rx_mpdu_info), 936 RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_OFFSET)), 937 RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_MASK, 938 RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_LSB)); 939 940 return (HAL_MPDU_SW_FRAME_GROUP_UNICAST_DATA == grp_id) ? true : false; 941 } 942 943 /** 944 * hal_rx_tid_get_6490: get tid based on qos control valid. 945 * @hal_soc_hdl: hal_soc handle 946 * @ buf: pointer to rx pkt TLV. 947 * 948 * Return: tid 949 */ 950 static uint32_t hal_rx_tid_get_6490(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 951 { 952 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 953 struct rx_mpdu_start *mpdu_start = 954 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 955 uint8_t *rx_mpdu_info = (uint8_t *)&mpdu_start->rx_mpdu_info_details; 956 uint8_t qos_control_valid = 957 (_HAL_MS((*_OFFSET_TO_WORD_PTR((rx_mpdu_info), 958 RX_MPDU_INFO_11_MPDU_QOS_CONTROL_VALID_OFFSET)), 959 RX_MPDU_INFO_11_MPDU_QOS_CONTROL_VALID_MASK, 960 RX_MPDU_INFO_11_MPDU_QOS_CONTROL_VALID_LSB)); 961 962 if (qos_control_valid) 963 return hal_rx_mpdu_start_tid_get_6490(buf); 964 965 return HAL_RX_NON_QOS_TID; 966 } 967 968 /** 969 * hal_rx_hw_desc_get_ppduid_get_6490(): retrieve ppdu id 970 * @hw_desc_addr: hw addr 971 * 972 * Return: ppdu id 973 */ 974 static uint32_t hal_rx_hw_desc_get_ppduid_get_6490(void *hw_desc_addr) 975 { 976 struct rx_mpdu_info *rx_mpdu_info; 977 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr; 978 979 rx_mpdu_info = 980 &rx_desc->mpdu_start_tlv.rx_mpdu_start.rx_mpdu_info_details; 981 982 return HAL_RX_GET(rx_mpdu_info, RX_MPDU_INFO_9, PHY_PPDU_ID); 983 } 984 985 /** 986 * hal_reo_status_get_header_6490 - Process reo desc info 987 * @d - Pointer to reo descriptior 988 * @b - tlv type info 989 * @h1 - Pointer to hal_reo_status_header where info to be stored 990 * 991 * Return - none. 992 * 993 */ 994 static void hal_reo_status_get_header_6490(uint32_t *d, int b, void *h1) 995 { 996 uint32_t val1 = 0; 997 struct hal_reo_status_header *h = 998 (struct hal_reo_status_header *)h1; 999 1000 switch (b) { 1001 case HAL_REO_QUEUE_STATS_STATUS_TLV: 1002 val1 = d[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_0, 1003 STATUS_HEADER_REO_STATUS_NUMBER)]; 1004 break; 1005 case HAL_REO_FLUSH_QUEUE_STATUS_TLV: 1006 val1 = d[HAL_OFFSET_DW(REO_FLUSH_QUEUE_STATUS_0, 1007 STATUS_HEADER_REO_STATUS_NUMBER)]; 1008 break; 1009 case HAL_REO_FLUSH_CACHE_STATUS_TLV: 1010 val1 = d[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_0, 1011 STATUS_HEADER_REO_STATUS_NUMBER)]; 1012 break; 1013 case HAL_REO_UNBLK_CACHE_STATUS_TLV: 1014 val1 = d[HAL_OFFSET_DW(REO_UNBLOCK_CACHE_STATUS_0, 1015 STATUS_HEADER_REO_STATUS_NUMBER)]; 1016 break; 1017 case HAL_REO_TIMOUT_LIST_STATUS_TLV: 1018 val1 = d[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_0, 1019 STATUS_HEADER_REO_STATUS_NUMBER)]; 1020 break; 1021 case HAL_REO_DESC_THRES_STATUS_TLV: 1022 val1 = 1023 d[HAL_OFFSET_DW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0, 1024 STATUS_HEADER_REO_STATUS_NUMBER)]; 1025 break; 1026 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: 1027 val1 = d[HAL_OFFSET_DW(REO_UPDATE_RX_REO_QUEUE_STATUS_0, 1028 STATUS_HEADER_REO_STATUS_NUMBER)]; 1029 break; 1030 default: 1031 qdf_nofl_err("ERROR: Unknown tlv\n"); 1032 break; 1033 } 1034 h->cmd_num = 1035 HAL_GET_FIELD( 1036 UNIFORM_REO_STATUS_HEADER_0, REO_STATUS_NUMBER, 1037 val1); 1038 h->exec_time = 1039 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_0, 1040 CMD_EXECUTION_TIME, val1); 1041 h->status = 1042 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_0, 1043 REO_CMD_EXECUTION_STATUS, val1); 1044 switch (b) { 1045 case HAL_REO_QUEUE_STATS_STATUS_TLV: 1046 val1 = d[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_1, 1047 STATUS_HEADER_TIMESTAMP)]; 1048 break; 1049 case HAL_REO_FLUSH_QUEUE_STATUS_TLV: 1050 val1 = d[HAL_OFFSET_DW(REO_FLUSH_QUEUE_STATUS_1, 1051 STATUS_HEADER_TIMESTAMP)]; 1052 break; 1053 case HAL_REO_FLUSH_CACHE_STATUS_TLV: 1054 val1 = d[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_1, 1055 STATUS_HEADER_TIMESTAMP)]; 1056 break; 1057 case HAL_REO_UNBLK_CACHE_STATUS_TLV: 1058 val1 = d[HAL_OFFSET_DW(REO_UNBLOCK_CACHE_STATUS_1, 1059 STATUS_HEADER_TIMESTAMP)]; 1060 break; 1061 case HAL_REO_TIMOUT_LIST_STATUS_TLV: 1062 val1 = d[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_1, 1063 STATUS_HEADER_TIMESTAMP)]; 1064 break; 1065 case HAL_REO_DESC_THRES_STATUS_TLV: 1066 val1 = 1067 d[HAL_OFFSET_DW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_1, 1068 STATUS_HEADER_TIMESTAMP)]; 1069 break; 1070 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: 1071 val1 = d[HAL_OFFSET_DW(REO_UPDATE_RX_REO_QUEUE_STATUS_1, 1072 STATUS_HEADER_TIMESTAMP)]; 1073 break; 1074 default: 1075 qdf_nofl_err("ERROR: Unknown tlv\n"); 1076 break; 1077 } 1078 h->tstamp = 1079 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_1, TIMESTAMP, val1); 1080 } 1081 1082 /** 1083 * hal_tx_desc_set_mesh_en_6490 - Set mesh_enable flag in Tx descriptor 1084 * @desc: Handle to Tx Descriptor 1085 * @en: For raw WiFi frames, this indicates transmission to a mesh STA, 1086 * enabling the interpretation of the 'Mesh Control Present' bit 1087 * (bit 8) of QoS Control (otherwise this bit is ignored), 1088 * For native WiFi frames, this indicates that a 'Mesh Control' field 1089 * is present between the header and the LLC. 1090 * 1091 * Return: void 1092 */ 1093 static inline 1094 void hal_tx_desc_set_mesh_en_6490(void *desc, uint8_t en) 1095 { 1096 HAL_SET_FLD(desc, TCL_DATA_CMD_5, MESH_ENABLE) |= 1097 HAL_TX_SM(TCL_DATA_CMD_5, MESH_ENABLE, en); 1098 } 1099 1100 static 1101 void *hal_rx_msdu0_buffer_addr_lsb_6490(void *link_desc_va) 1102 { 1103 return (void *)HAL_RX_MSDU0_BUFFER_ADDR_LSB(link_desc_va); 1104 } 1105 1106 static 1107 void *hal_rx_msdu_desc_info_ptr_get_6490(void *msdu0) 1108 { 1109 return (void *)HAL_RX_MSDU_DESC_INFO_PTR_GET(msdu0); 1110 } 1111 1112 static 1113 void *hal_ent_mpdu_desc_info_6490(void *ent_ring_desc) 1114 { 1115 return (void *)HAL_ENT_MPDU_DESC_INFO(ent_ring_desc); 1116 } 1117 1118 static 1119 void *hal_dst_mpdu_desc_info_6490(void *dst_ring_desc) 1120 { 1121 return (void *)HAL_DST_MPDU_DESC_INFO(dst_ring_desc); 1122 } 1123 1124 static 1125 uint8_t hal_rx_get_fc_valid_6490(uint8_t *buf) 1126 { 1127 return HAL_RX_GET_FC_VALID(buf); 1128 } 1129 1130 static uint8_t hal_rx_get_to_ds_flag_6490(uint8_t *buf) 1131 { 1132 return HAL_RX_GET_TO_DS_FLAG(buf); 1133 } 1134 1135 static uint8_t hal_rx_get_mac_addr2_valid_6490(uint8_t *buf) 1136 { 1137 return HAL_RX_GET_MAC_ADDR2_VALID(buf); 1138 } 1139 1140 static uint8_t hal_rx_get_filter_category_6490(uint8_t *buf) 1141 { 1142 return HAL_RX_GET_FILTER_CATEGORY(buf); 1143 } 1144 1145 static uint32_t 1146 hal_rx_get_ppdu_id_6490(uint8_t *buf) 1147 { 1148 return HAL_RX_GET_PPDU_ID(buf); 1149 } 1150 1151 /** 1152 * hal_reo_config_6490(): Set reo config parameters 1153 * @soc: hal soc handle 1154 * @reg_val: value to be set 1155 * @reo_params: reo parameters 1156 * 1157 * Return: void 1158 */ 1159 static 1160 void hal_reo_config_6490(struct hal_soc *soc, 1161 uint32_t reg_val, 1162 struct hal_reo_params *reo_params) 1163 { 1164 HAL_REO_R0_CONFIG(soc, reg_val, reo_params); 1165 } 1166 1167 /** 1168 * hal_rx_msdu_desc_info_get_ptr_6490() - Get msdu desc info ptr 1169 * @msdu_details_ptr - Pointer to msdu_details_ptr 1170 * 1171 * Return - Pointer to rx_msdu_desc_info structure. 1172 * 1173 */ 1174 static void *hal_rx_msdu_desc_info_get_ptr_6490(void *msdu_details_ptr) 1175 { 1176 return HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr); 1177 } 1178 1179 /** 1180 * hal_rx_link_desc_msdu0_ptr_6490 - Get pointer to rx_msdu details 1181 * @link_desc - Pointer to link desc 1182 * 1183 * Return - Pointer to rx_msdu_details structure 1184 * 1185 */ 1186 static void *hal_rx_link_desc_msdu0_ptr_6490(void *link_desc) 1187 { 1188 return HAL_RX_LINK_DESC_MSDU0_PTR(link_desc); 1189 } 1190 1191 /** 1192 * hal_rx_msdu_flow_idx_get_6490: API to get flow index 1193 * from rx_msdu_end TLV 1194 * @buf: pointer to the start of RX PKT TLV headers 1195 * 1196 * Return: flow index value from MSDU END TLV 1197 */ 1198 static inline uint32_t hal_rx_msdu_flow_idx_get_6490(uint8_t *buf) 1199 { 1200 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1201 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1202 1203 return HAL_RX_MSDU_END_FLOW_IDX_GET(msdu_end); 1204 } 1205 1206 /** 1207 * hal_rx_msdu_flow_idx_invalid_6490: API to get flow index invalid 1208 * from rx_msdu_end TLV 1209 * @buf: pointer to the start of RX PKT TLV headers 1210 * 1211 * Return: flow index invalid value from MSDU END TLV 1212 */ 1213 static bool hal_rx_msdu_flow_idx_invalid_6490(uint8_t *buf) 1214 { 1215 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1216 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1217 1218 return HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(msdu_end); 1219 } 1220 1221 /** 1222 * hal_rx_msdu_flow_idx_timeout_6490: API to get flow index timeout 1223 * from rx_msdu_end TLV 1224 * @buf: pointer to the start of RX PKT TLV headers 1225 * 1226 * Return: flow index timeout value from MSDU END TLV 1227 */ 1228 static bool hal_rx_msdu_flow_idx_timeout_6490(uint8_t *buf) 1229 { 1230 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1231 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1232 1233 return HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(msdu_end); 1234 } 1235 1236 /** 1237 * hal_rx_msdu_fse_metadata_get_6490: API to get FSE metadata 1238 * from rx_msdu_end TLV 1239 * @buf: pointer to the start of RX PKT TLV headers 1240 * 1241 * Return: fse metadata value from MSDU END TLV 1242 */ 1243 static uint32_t hal_rx_msdu_fse_metadata_get_6490(uint8_t *buf) 1244 { 1245 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1246 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1247 1248 return HAL_RX_MSDU_END_FSE_METADATA_GET(msdu_end); 1249 } 1250 1251 /** 1252 * hal_rx_msdu_cce_metadata_get_6490: API to get CCE metadata 1253 * from rx_msdu_end TLV 1254 * @buf: pointer to the start of RX PKT TLV headers 1255 * 1256 * Return: cce_metadata 1257 */ 1258 static uint16_t 1259 hal_rx_msdu_cce_metadata_get_6490(uint8_t *buf) 1260 { 1261 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1262 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1263 1264 return HAL_RX_MSDU_END_CCE_METADATA_GET(msdu_end); 1265 } 1266 1267 /** 1268 * hal_rx_tlv_get_tcp_chksum_6490() - API to get tcp checksum 1269 * @buf: rx_tlv_hdr 1270 * 1271 * Return: tcp checksum 1272 */ 1273 static uint16_t 1274 hal_rx_tlv_get_tcp_chksum_6490(uint8_t *buf) 1275 { 1276 return HAL_RX_TLV_GET_TCP_CHKSUM(buf); 1277 } 1278 1279 /** 1280 * hal_rx_get_rx_sequence_6490(): Function to retrieve rx sequence number 1281 * 1282 * @nbuf: Network buffer 1283 * Returns: rx sequence number 1284 */ 1285 static 1286 uint16_t hal_rx_get_rx_sequence_6490(uint8_t *buf) 1287 { 1288 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 1289 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 1290 1291 return HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info); 1292 } 1293 1294 /** 1295 * hal_get_window_address_6490(): Function to get hp/tp address 1296 * @hal_soc: Pointer to hal_soc 1297 * @addr: address offset of register 1298 * 1299 * Return: modified address offset of register 1300 */ 1301 static inline qdf_iomem_t hal_get_window_address_6490(struct hal_soc *hal_soc, 1302 qdf_iomem_t addr) 1303 { 1304 return addr; 1305 } 1306 1307 struct hal_hw_txrx_ops qca6490_hal_hw_txrx_ops = { 1308 /* init and setup */ 1309 hal_srng_dst_hw_init_generic, 1310 hal_srng_src_hw_init_generic, 1311 hal_get_hw_hptp_generic, 1312 hal_reo_setup_generic, 1313 hal_setup_link_idle_list_generic, 1314 hal_get_window_address_6490, 1315 1316 /* tx */ 1317 hal_tx_desc_set_dscp_tid_table_id_6490, 1318 hal_tx_set_dscp_tid_map_6490, 1319 hal_tx_update_dscp_tid_6490, 1320 hal_tx_desc_set_lmac_id_6490, 1321 hal_tx_desc_set_buf_addr_generic, 1322 hal_tx_desc_set_search_type_generic, 1323 hal_tx_desc_set_search_index_generic, 1324 hal_tx_desc_set_cache_set_num_generic, 1325 hal_tx_comp_get_status_generic, 1326 hal_tx_comp_get_release_reason_generic, 1327 hal_tx_desc_set_mesh_en_6490, 1328 1329 /* rx */ 1330 hal_rx_msdu_start_nss_get_6490, 1331 hal_rx_mon_hw_desc_get_mpdu_status_6490, 1332 hal_rx_get_tlv_6490, 1333 hal_rx_proc_phyrx_other_receive_info_tlv_6490, 1334 hal_rx_dump_msdu_start_tlv_6490, 1335 hal_rx_dump_msdu_end_tlv_6490, 1336 hal_get_link_desc_size_6490, 1337 hal_rx_mpdu_start_tid_get_6490, 1338 hal_rx_msdu_start_reception_type_get_6490, 1339 hal_rx_msdu_end_da_idx_get_6490, 1340 hal_rx_msdu_desc_info_get_ptr_6490, 1341 hal_rx_link_desc_msdu0_ptr_6490, 1342 hal_reo_status_get_header_6490, 1343 hal_rx_status_get_tlv_info_generic, 1344 hal_rx_wbm_err_info_get_generic, 1345 hal_rx_dump_mpdu_start_tlv_generic, 1346 1347 hal_tx_set_pcp_tid_map_generic, 1348 hal_tx_update_pcp_tid_generic, 1349 hal_tx_update_tidmap_prty_generic, 1350 hal_rx_get_rx_fragment_number_6490, 1351 hal_rx_msdu_end_da_is_mcbc_get_6490, 1352 hal_rx_msdu_end_sa_is_valid_get_6490, 1353 hal_rx_msdu_end_sa_idx_get_6490, 1354 hal_rx_desc_is_first_msdu_6490, 1355 hal_rx_msdu_end_l3_hdr_padding_get_6490, 1356 hal_rx_encryption_info_valid_6490, 1357 hal_rx_print_pn_6490, 1358 hal_rx_msdu_end_first_msdu_get_6490, 1359 hal_rx_msdu_end_da_is_valid_get_6490, 1360 hal_rx_msdu_end_last_msdu_get_6490, 1361 hal_rx_get_mpdu_mac_ad4_valid_6490, 1362 hal_rx_mpdu_start_sw_peer_id_get_6490, 1363 hal_rx_mpdu_get_to_ds_6490, 1364 hal_rx_mpdu_get_fr_ds_6490, 1365 hal_rx_get_mpdu_frame_control_valid_6490, 1366 hal_rx_mpdu_get_addr1_6490, 1367 hal_rx_mpdu_get_addr2_6490, 1368 hal_rx_mpdu_get_addr3_6490, 1369 hal_rx_mpdu_get_addr4_6490, 1370 hal_rx_get_mpdu_sequence_control_valid_6490, 1371 hal_rx_is_unicast_6490, 1372 hal_rx_tid_get_6490, 1373 hal_rx_hw_desc_get_ppduid_get_6490, 1374 NULL, 1375 NULL, 1376 hal_rx_msdu0_buffer_addr_lsb_6490, 1377 hal_rx_msdu_desc_info_ptr_get_6490, 1378 hal_ent_mpdu_desc_info_6490, 1379 hal_dst_mpdu_desc_info_6490, 1380 hal_rx_get_fc_valid_6490, 1381 hal_rx_get_to_ds_flag_6490, 1382 hal_rx_get_mac_addr2_valid_6490, 1383 hal_rx_get_filter_category_6490, 1384 hal_rx_get_ppdu_id_6490, 1385 hal_reo_config_6490, 1386 hal_rx_msdu_flow_idx_get_6490, 1387 hal_rx_msdu_flow_idx_invalid_6490, 1388 hal_rx_msdu_flow_idx_timeout_6490, 1389 hal_rx_msdu_fse_metadata_get_6490, 1390 hal_rx_msdu_cce_metadata_get_6490, 1391 NULL, 1392 hal_rx_tlv_get_tcp_chksum_6490, 1393 hal_rx_get_rx_sequence_6490, 1394 }; 1395 1396 struct hal_hw_srng_config hw_srng_table_6490[] = { 1397 /* TODO: max_rings can populated by querying HW capabilities */ 1398 { /* REO_DST */ 1399 .start_ring_id = HAL_SRNG_REO2SW1, 1400 .max_rings = 4, 1401 .entry_size = sizeof(struct reo_destination_ring) >> 2, 1402 .lmac_ring = FALSE, 1403 .ring_dir = HAL_SRNG_DST_RING, 1404 .reg_start = { 1405 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR( 1406 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1407 HWIO_REO_R2_REO2SW1_RING_HP_ADDR( 1408 SEQ_WCSS_UMAC_REO_REG_OFFSET) 1409 }, 1410 .reg_size = { 1411 HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(0) - 1412 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(0), 1413 HWIO_REO_R2_REO2SW2_RING_HP_ADDR(0) - 1414 HWIO_REO_R2_REO2SW1_RING_HP_ADDR(0), 1415 }, 1416 .max_size = 1417 HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_BMSK >> 1418 HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_SHFT, 1419 }, 1420 { /* REO_EXCEPTION */ 1421 /* Designating REO2TCL ring as exception ring. This ring is 1422 * similar to other REO2SW rings though it is named as REO2TCL. 1423 * Any of theREO2SW rings can be used as exception ring. 1424 */ 1425 .start_ring_id = HAL_SRNG_REO2TCL, 1426 .max_rings = 1, 1427 .entry_size = sizeof(struct reo_destination_ring) >> 2, 1428 .lmac_ring = FALSE, 1429 .ring_dir = HAL_SRNG_DST_RING, 1430 .reg_start = { 1431 HWIO_REO_R0_REO2TCL_RING_BASE_LSB_ADDR( 1432 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1433 HWIO_REO_R2_REO2TCL_RING_HP_ADDR( 1434 SEQ_WCSS_UMAC_REO_REG_OFFSET) 1435 }, 1436 /* Single ring - provide ring size if multiple rings of this 1437 * type are supported 1438 */ 1439 .reg_size = {}, 1440 .max_size = 1441 HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_BMSK >> 1442 HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_SHFT, 1443 }, 1444 { /* REO_REINJECT */ 1445 .start_ring_id = HAL_SRNG_SW2REO, 1446 .max_rings = 1, 1447 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 1448 .lmac_ring = FALSE, 1449 .ring_dir = HAL_SRNG_SRC_RING, 1450 .reg_start = { 1451 HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR( 1452 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1453 HWIO_REO_R2_SW2REO_RING_HP_ADDR( 1454 SEQ_WCSS_UMAC_REO_REG_OFFSET) 1455 }, 1456 /* Single ring - provide ring size if multiple rings of this 1457 * type are supported 1458 */ 1459 .reg_size = {}, 1460 .max_size = HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_BMSK >> 1461 HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_SHFT, 1462 }, 1463 { /* REO_CMD */ 1464 .start_ring_id = HAL_SRNG_REO_CMD, 1465 .max_rings = 1, 1466 .entry_size = (sizeof(struct tlv_32_hdr) + 1467 sizeof(struct reo_get_queue_stats)) >> 2, 1468 .lmac_ring = FALSE, 1469 .ring_dir = HAL_SRNG_SRC_RING, 1470 .reg_start = { 1471 HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR( 1472 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1473 HWIO_REO_R2_REO_CMD_RING_HP_ADDR( 1474 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1475 }, 1476 /* Single ring - provide ring size if multiple rings of this 1477 * type are supported 1478 */ 1479 .reg_size = {}, 1480 .max_size = 1481 HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_BMSK >> 1482 HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_SHFT, 1483 }, 1484 { /* REO_STATUS */ 1485 .start_ring_id = HAL_SRNG_REO_STATUS, 1486 .max_rings = 1, 1487 .entry_size = (sizeof(struct tlv_32_hdr) + 1488 sizeof(struct reo_get_queue_stats_status)) >> 2, 1489 .lmac_ring = FALSE, 1490 .ring_dir = HAL_SRNG_DST_RING, 1491 .reg_start = { 1492 HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR( 1493 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1494 HWIO_REO_R2_REO_STATUS_RING_HP_ADDR( 1495 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1496 }, 1497 /* Single ring - provide ring size if multiple rings of this 1498 * type are supported 1499 */ 1500 .reg_size = {}, 1501 .max_size = 1502 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> 1503 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, 1504 }, 1505 { /* TCL_DATA */ 1506 .start_ring_id = HAL_SRNG_SW2TCL1, 1507 .max_rings = 3, 1508 .entry_size = (sizeof(struct tlv_32_hdr) + 1509 sizeof(struct tcl_data_cmd)) >> 2, 1510 .lmac_ring = FALSE, 1511 .ring_dir = HAL_SRNG_SRC_RING, 1512 .reg_start = { 1513 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR( 1514 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1515 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR( 1516 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1517 }, 1518 .reg_size = { 1519 HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(0) - 1520 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(0), 1521 HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(0) - 1522 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(0), 1523 }, 1524 .max_size = 1525 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK >> 1526 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT, 1527 }, 1528 { /* TCL_CMD */ 1529 .start_ring_id = HAL_SRNG_SW2TCL_CMD, 1530 .max_rings = 1, 1531 .entry_size = (sizeof(struct tlv_32_hdr) + 1532 sizeof(struct tcl_gse_cmd)) >> 2, 1533 .lmac_ring = FALSE, 1534 .ring_dir = HAL_SRNG_SRC_RING, 1535 .reg_start = { 1536 HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_ADDR( 1537 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1538 HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_ADDR( 1539 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1540 }, 1541 /* Single ring - provide ring size if multiple rings of this 1542 * type are supported 1543 */ 1544 .reg_size = {}, 1545 .max_size = 1546 HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_SIZE_BMSK >> 1547 HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_SIZE_SHFT, 1548 }, 1549 { /* TCL_STATUS */ 1550 .start_ring_id = HAL_SRNG_TCL_STATUS, 1551 .max_rings = 1, 1552 .entry_size = (sizeof(struct tlv_32_hdr) + 1553 sizeof(struct tcl_status_ring)) >> 2, 1554 .lmac_ring = FALSE, 1555 .ring_dir = HAL_SRNG_DST_RING, 1556 .reg_start = { 1557 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR( 1558 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1559 HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR( 1560 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1561 }, 1562 /* Single ring - provide ring size if multiple rings of this 1563 * type are supported 1564 */ 1565 .reg_size = {}, 1566 .max_size = 1567 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_BMSK >> 1568 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_SHFT, 1569 }, 1570 { /* CE_SRC */ 1571 .start_ring_id = HAL_SRNG_CE_0_SRC, 1572 .max_rings = 12, 1573 .entry_size = sizeof(struct ce_src_desc) >> 2, 1574 .lmac_ring = FALSE, 1575 .ring_dir = HAL_SRNG_SRC_RING, 1576 .reg_start = { 1577 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR( 1578 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET), 1579 HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR( 1580 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET), 1581 }, 1582 .reg_size = { 1583 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET - 1584 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET, 1585 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET - 1586 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET, 1587 }, 1588 .max_size = 1589 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >> 1590 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT, 1591 }, 1592 { /* CE_DST */ 1593 .start_ring_id = HAL_SRNG_CE_0_DST, 1594 .max_rings = 12, 1595 .entry_size = 8 >> 2, 1596 /*TODO: entry_size above should actually be 1597 * sizeof(struct ce_dst_desc) >> 2, but couldn't find definition 1598 * of struct ce_dst_desc in HW header files 1599 */ 1600 .lmac_ring = FALSE, 1601 .ring_dir = HAL_SRNG_SRC_RING, 1602 .reg_start = { 1603 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR( 1604 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 1605 HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR( 1606 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 1607 }, 1608 .reg_size = { 1609 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 1610 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 1611 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 1612 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 1613 }, 1614 .max_size = 1615 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >> 1616 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT, 1617 }, 1618 { /* CE_DST_STATUS */ 1619 .start_ring_id = HAL_SRNG_CE_0_DST_STATUS, 1620 .max_rings = 12, 1621 .entry_size = sizeof(struct ce_stat_desc) >> 2, 1622 .lmac_ring = FALSE, 1623 .ring_dir = HAL_SRNG_DST_RING, 1624 .reg_start = { 1625 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR( 1626 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 1627 HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR( 1628 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 1629 }, 1630 /* TODO: check destination status ring registers */ 1631 .reg_size = { 1632 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 1633 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 1634 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 1635 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 1636 }, 1637 .max_size = 1638 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> 1639 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, 1640 }, 1641 { /* WBM_IDLE_LINK */ 1642 .start_ring_id = HAL_SRNG_WBM_IDLE_LINK, 1643 .max_rings = 1, 1644 .entry_size = sizeof(struct wbm_link_descriptor_ring) >> 2, 1645 .lmac_ring = FALSE, 1646 .ring_dir = HAL_SRNG_SRC_RING, 1647 .reg_start = { 1648 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1649 HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1650 }, 1651 /* Single ring - provide ring size if multiple rings of this 1652 * type are supported 1653 */ 1654 .reg_size = {}, 1655 .max_size = 1656 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_BMSK >> 1657 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_SHFT, 1658 }, 1659 { /* SW2WBM_RELEASE */ 1660 .start_ring_id = HAL_SRNG_WBM_SW_RELEASE, 1661 .max_rings = 1, 1662 .entry_size = sizeof(struct wbm_release_ring) >> 2, 1663 .lmac_ring = FALSE, 1664 .ring_dir = HAL_SRNG_SRC_RING, 1665 .reg_start = { 1666 HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1667 HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1668 }, 1669 /* Single ring - provide ring size if multiple rings of this 1670 * type are supported 1671 */ 1672 .reg_size = {}, 1673 .max_size = 1674 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> 1675 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, 1676 }, 1677 { /* WBM2SW_RELEASE */ 1678 .start_ring_id = HAL_SRNG_WBM2SW0_RELEASE, 1679 .max_rings = 4, 1680 .entry_size = sizeof(struct wbm_release_ring) >> 2, 1681 .lmac_ring = FALSE, 1682 .ring_dir = HAL_SRNG_DST_RING, 1683 .reg_start = { 1684 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1685 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1686 }, 1687 .reg_size = { 1688 HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) - 1689 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1690 HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) - 1691 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1692 }, 1693 .max_size = 1694 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> 1695 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, 1696 }, 1697 { /* RXDMA_BUF */ 1698 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA0_BUF0, 1699 #ifdef IPA_OFFLOAD 1700 .max_rings = 3, 1701 #else 1702 .max_rings = 2, 1703 #endif 1704 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 1705 .lmac_ring = TRUE, 1706 .ring_dir = HAL_SRNG_SRC_RING, 1707 /* reg_start is not set because LMAC rings are not accessed 1708 * from host 1709 */ 1710 .reg_start = {}, 1711 .reg_size = {}, 1712 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1713 }, 1714 { /* RXDMA_DST */ 1715 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW0, 1716 .max_rings = 1, 1717 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 1718 .lmac_ring = TRUE, 1719 .ring_dir = HAL_SRNG_DST_RING, 1720 /* reg_start is not set because LMAC rings are not accessed 1721 * from host 1722 */ 1723 .reg_start = {}, 1724 .reg_size = {}, 1725 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1726 }, 1727 { /* RXDMA_MONITOR_BUF */ 1728 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA2_BUF, 1729 .max_rings = 1, 1730 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 1731 .lmac_ring = TRUE, 1732 .ring_dir = HAL_SRNG_SRC_RING, 1733 /* reg_start is not set because LMAC rings are not accessed 1734 * from host 1735 */ 1736 .reg_start = {}, 1737 .reg_size = {}, 1738 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1739 }, 1740 { /* RXDMA_MONITOR_STATUS */ 1741 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_STATBUF, 1742 .max_rings = 1, 1743 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 1744 .lmac_ring = TRUE, 1745 .ring_dir = HAL_SRNG_SRC_RING, 1746 /* reg_start is not set because LMAC rings are not accessed 1747 * from host 1748 */ 1749 .reg_start = {}, 1750 .reg_size = {}, 1751 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1752 }, 1753 { /* RXDMA_MONITOR_DST */ 1754 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW1, 1755 .max_rings = 1, 1756 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 1757 .lmac_ring = TRUE, 1758 .ring_dir = HAL_SRNG_DST_RING, 1759 /* reg_start is not set because LMAC rings are not accessed 1760 * from host 1761 */ 1762 .reg_start = {}, 1763 .reg_size = {}, 1764 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1765 }, 1766 { /* RXDMA_MONITOR_DESC */ 1767 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_DESC, 1768 .max_rings = 1, 1769 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 1770 .lmac_ring = TRUE, 1771 .ring_dir = HAL_SRNG_SRC_RING, 1772 /* reg_start is not set because LMAC rings are not accessed 1773 * from host 1774 */ 1775 .reg_start = {}, 1776 .reg_size = {}, 1777 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1778 }, 1779 { /* DIR_BUF_RX_DMA_SRC */ 1780 .start_ring_id = HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING, 1781 .max_rings = 1, 1782 .entry_size = 2, 1783 .lmac_ring = TRUE, 1784 .ring_dir = HAL_SRNG_SRC_RING, 1785 /* reg_start is not set because LMAC rings are not accessed 1786 * from host 1787 */ 1788 .reg_start = {}, 1789 .reg_size = {}, 1790 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1791 }, 1792 #ifdef WLAN_FEATURE_CIF_CFR 1793 { /* WIFI_POS_SRC */ 1794 .start_ring_id = HAL_SRNG_WIFI_POS_SRC_DMA_RING, 1795 .max_rings = 1, 1796 .entry_size = sizeof(wmi_oem_dma_buf_release_entry) >> 2, 1797 .lmac_ring = TRUE, 1798 .ring_dir = HAL_SRNG_SRC_RING, 1799 /* reg_start is not set because LMAC rings are not accessed 1800 * from host 1801 */ 1802 .reg_start = {}, 1803 .reg_size = {}, 1804 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1805 }, 1806 #endif 1807 }; 1808 1809 int32_t hal_hw_reg_offset_qca6490[] = { 1810 /* dst */ 1811 REG_OFFSET(DST, HP), 1812 REG_OFFSET(DST, TP), 1813 REG_OFFSET(DST, ID), 1814 REG_OFFSET(DST, MISC), 1815 REG_OFFSET(DST, HP_ADDR_LSB), 1816 REG_OFFSET(DST, HP_ADDR_MSB), 1817 REG_OFFSET(DST, MSI1_BASE_LSB), 1818 REG_OFFSET(DST, MSI1_BASE_MSB), 1819 REG_OFFSET(DST, MSI1_DATA), 1820 REG_OFFSET(DST, BASE_LSB), 1821 REG_OFFSET(DST, BASE_MSB), 1822 REG_OFFSET(DST, PRODUCER_INT_SETUP), 1823 /* src */ 1824 REG_OFFSET(SRC, HP), 1825 REG_OFFSET(SRC, TP), 1826 REG_OFFSET(SRC, ID), 1827 REG_OFFSET(SRC, MISC), 1828 REG_OFFSET(SRC, TP_ADDR_LSB), 1829 REG_OFFSET(SRC, TP_ADDR_MSB), 1830 REG_OFFSET(SRC, MSI1_BASE_LSB), 1831 REG_OFFSET(SRC, MSI1_BASE_MSB), 1832 REG_OFFSET(SRC, MSI1_DATA), 1833 REG_OFFSET(SRC, BASE_LSB), 1834 REG_OFFSET(SRC, BASE_MSB), 1835 REG_OFFSET(SRC, CONSUMER_INT_SETUP_IX0), 1836 REG_OFFSET(SRC, CONSUMER_INT_SETUP_IX1), 1837 }; 1838 1839 /** 1840 * hal_qca6490_attach() - Attach 6490 target specific hal_soc ops, 1841 * offset and srng table 1842 */ 1843 void hal_qca6490_attach(struct hal_soc *hal_soc) 1844 { 1845 hal_soc->hw_srng_table = hw_srng_table_6490; 1846 hal_soc->hal_hw_reg_offset = hal_hw_reg_offset_qca6490; 1847 hal_soc->ops = &qca6490_hal_hw_txrx_ops; 1848 } 1849