1 /* 2 * Copyright (c) 2019-2021 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #include "qdf_types.h" 20 #include "qdf_util.h" 21 #include "qdf_types.h" 22 #include "qdf_lock.h" 23 #include "qdf_mem.h" 24 #include "qdf_nbuf.h" 25 #include "hal_li_hw_headers.h" 26 #include "hal_internal.h" 27 #include "hal_api.h" 28 #include "target_type.h" 29 #include "wcss_version.h" 30 #include "qdf_module.h" 31 #include "hal_flow.h" 32 #include "rx_flow_search_entry.h" 33 #include "hal_rx_flow_info.h" 34 35 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_OFFSET \ 36 RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_OFFSET 37 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_MASK \ 38 RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_MASK 39 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_LSB \ 40 RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_LSB 41 #define UNIFIED_PHYRX_HT_SIG_0_HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS_OFFSET \ 42 PHYRX_L_SIG_B_0_PHYRX_L_SIG_B_INFO_DETAILS_RATE_OFFSET 43 #define UNIFIED_PHYRX_L_SIG_B_0_L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS_OFFSET \ 44 PHYRX_L_SIG_B_0_PHYRX_L_SIG_B_INFO_DETAILS_RATE_OFFSET 45 #define UNIFIED_PHYRX_L_SIG_A_0_L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS_OFFSET \ 46 PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_RATE_OFFSET 47 #define UNIFIED_PHYRX_VHT_SIG_A_0_VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS_OFFSET \ 48 PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_OFFSET 49 #define UNIFIED_PHYRX_HE_SIG_A_SU_0_HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS_OFFSET \ 50 PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_OFFSET 51 #define UNIFIED_PHYRX_HE_SIG_A_MU_DL_0_HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_OFFSET \ 52 PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_OFFSET 53 #define UNIFIED_PHYRX_HE_SIG_B1_MU_0_HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_OFFSET \ 54 PHYRX_HE_SIG_B1_MU_0_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_OFFSET 55 #define UNIFIED_PHYRX_HE_SIG_B2_MU_0_HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_OFFSET \ 56 PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_OFFSET 57 #define UNIFIED_PHYRX_HE_SIG_B2_OFDMA_0_HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_OFFSET \ 58 PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_OFFSET 59 60 #define UNIFIED_PHYRX_RSSI_LEGACY_3_RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS_OFFSET \ 61 PHYRX_RSSI_LEGACY_3_RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS_OFFSET 62 #define UNIFIED_PHYRX_RSSI_LEGACY_19_RECEIVE_RSSI_INFO_PREAMBLE_RSSI_INFO_DETAILS_OFFSET \ 63 PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 64 #define UNIFIED_RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET \ 65 RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 66 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 67 RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET 68 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ 69 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET 70 #define UNIFIED_RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 71 RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET 72 #define UNIFIED_REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 73 REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET 74 #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC \ 75 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER 76 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ 77 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET 78 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 79 RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET 80 #define UNIFIED_TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 81 TCL_DATA_CMD_0_BUF_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 82 #define UNIFIED_TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 83 TCL_DATA_CMD_1_BUF_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 84 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET \ 85 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET 86 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB \ 87 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB 88 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK \ 89 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK 90 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB \ 91 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB 92 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK \ 93 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK 94 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB \ 95 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB 96 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK \ 97 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK 98 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB \ 99 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB 100 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK \ 101 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK 102 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB \ 103 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB 104 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK \ 105 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK 106 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_MASK \ 107 WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MASK 108 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_OFFSET \ 109 WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_OFFSET 110 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_LSB \ 111 WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_LSB 112 113 #include "hal_6490_tx.h" 114 #include "hal_6490_rx.h" 115 #include <hal_generic_api.h> 116 #include "hal_li_rx.h" 117 #include "hal_li_api.h" 118 #include "hal_li_generic_api.h" 119 120 /* 121 * hal_rx_msdu_start_nss_get_6490(): API to get the NSS 122 * Interval from rx_msdu_start 123 * 124 * @buf: pointer to the start of RX PKT TLV header 125 * Return: uint32_t(nss) 126 */ 127 static uint32_t 128 hal_rx_msdu_start_nss_get_6490(uint8_t *buf) 129 { 130 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 131 struct rx_msdu_start *msdu_start = 132 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 133 uint8_t mimo_ss_bitmap; 134 135 mimo_ss_bitmap = HAL_RX_MSDU_START_MIMO_SS_BITMAP(msdu_start); 136 137 return qdf_get_hweight8(mimo_ss_bitmap); 138 } 139 140 /** 141 * hal_rx_mon_hw_desc_get_mpdu_status_6490(): Retrieve MPDU status 142 * 143 * @ hw_desc_addr: Start address of Rx HW TLVs 144 * @ rs: Status for monitor mode 145 * 146 * Return: void 147 */ 148 static void hal_rx_mon_hw_desc_get_mpdu_status_6490(void *hw_desc_addr, 149 struct mon_rx_status *rs) 150 { 151 struct rx_msdu_start *rx_msdu_start; 152 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr; 153 uint32_t reg_value; 154 const uint32_t sgi_hw_to_cdp[] = { 155 CDP_SGI_0_8_US, 156 CDP_SGI_0_4_US, 157 CDP_SGI_1_6_US, 158 CDP_SGI_3_2_US, 159 }; 160 161 rx_msdu_start = &rx_desc->msdu_start_tlv.rx_msdu_start; 162 163 HAL_RX_GET_MSDU_AGGREGATION(rx_desc, rs); 164 165 rs->ant_signal_db = HAL_RX_GET(rx_msdu_start, 166 RX_MSDU_START_5, USER_RSSI); 167 rs->is_stbc = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, STBC); 168 169 reg_value = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, SGI); 170 rs->sgi = sgi_hw_to_cdp[reg_value]; 171 172 reg_value = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, RECEPTION_TYPE); 173 rs->beamformed = (reg_value == HAL_RX_RECEPTION_TYPE_MU_MIMO) ? 1 : 0; 174 /* TODO: rs->beamformed should be set for SU beamforming also */ 175 } 176 177 #define LINK_DESC_SIZE (NUM_OF_DWORDS_RX_MSDU_LINK << 2) 178 179 static uint32_t hal_get_link_desc_size_6490(void) 180 { 181 return LINK_DESC_SIZE; 182 } 183 184 /* 185 * hal_rx_get_tlv_6490(): API to get the tlv 186 * 187 * @rx_tlv: TLV data extracted from the rx packet 188 * Return: uint8_t 189 */ 190 static uint8_t hal_rx_get_tlv_6490(void *rx_tlv) 191 { 192 return HAL_RX_GET(rx_tlv, PHYRX_RSSI_LEGACY_0, RECEIVE_BANDWIDTH); 193 } 194 195 /** 196 * hal_rx_proc_phyrx_other_receive_info_tlv_6490() 197 * - process other receive info TLV 198 * @rx_tlv_hdr: pointer to TLV header 199 * @ppdu_info: pointer to ppdu_info 200 * 201 * Return: None 202 */ 203 static 204 void hal_rx_proc_phyrx_other_receive_info_tlv_6490(void *rx_tlv_hdr, 205 void *ppdu_info_handle) 206 { 207 uint32_t tlv_tag, tlv_len; 208 uint32_t temp_len, other_tlv_len, other_tlv_tag; 209 void *rx_tlv = (uint8_t *)rx_tlv_hdr + HAL_RX_TLV32_HDR_SIZE; 210 void *other_tlv_hdr = NULL; 211 void *other_tlv = NULL; 212 213 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv_hdr); 214 tlv_len = HAL_RX_GET_USER_TLV32_LEN(rx_tlv_hdr); 215 temp_len = 0; 216 217 other_tlv_hdr = rx_tlv + HAL_RX_TLV32_HDR_SIZE; 218 219 other_tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(other_tlv_hdr); 220 other_tlv_len = HAL_RX_GET_USER_TLV32_LEN(other_tlv_hdr); 221 temp_len += other_tlv_len; 222 other_tlv = other_tlv_hdr + HAL_RX_TLV32_HDR_SIZE; 223 224 switch (other_tlv_tag) { 225 default: 226 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR, 227 "%s unhandled TLV type: %d, TLV len:%d", 228 __func__, other_tlv_tag, other_tlv_len); 229 break; 230 } 231 } 232 233 /** 234 * hal_rx_dump_msdu_start_tlv_6490() : dump RX msdu_start TLV in structured 235 * human readable format. 236 * @ msdu_start: pointer the msdu_start TLV in pkt. 237 * @ dbg_level: log level. 238 * 239 * Return: void 240 */ 241 static void hal_rx_dump_msdu_start_tlv_6490(void *msdustart, uint8_t dbg_level) 242 { 243 struct rx_msdu_start *msdu_start = (struct rx_msdu_start *)msdustart; 244 245 __QDF_TRACE_RL(dbg_level, QDF_MODULE_ID_DP, 246 "rx_msdu_start tlv (1/2) - " 247 "rxpcu_mpdu_filter_in_category: %x " 248 "sw_frame_group_id: %x " 249 "phy_ppdu_id: %x " 250 "msdu_length: %x " 251 "ipsec_esp: %x " 252 "l3_offset: %x " 253 "ipsec_ah: %x " 254 "l4_offset: %x " 255 "msdu_number: %x " 256 "decap_format: %x " 257 "ipv4_proto: %x " 258 "ipv6_proto: %x " 259 "tcp_proto: %x " 260 "udp_proto: %x " 261 "ip_frag: %x " 262 "tcp_only_ack: %x " 263 "da_is_bcast_mcast: %x " 264 "ip4_protocol_ip6_next_header: %x " 265 "toeplitz_hash_2_or_4: %x " 266 "flow_id_toeplitz: %x " 267 "user_rssi: %x " 268 "pkt_type: %x " 269 "stbc: %x " 270 "sgi: %x " 271 "rate_mcs: %x " 272 "receive_bandwidth: %x " 273 "reception_type: %x " 274 "ppdu_start_timestamp: %u ", 275 msdu_start->rxpcu_mpdu_filter_in_category, 276 msdu_start->sw_frame_group_id, 277 msdu_start->phy_ppdu_id, 278 msdu_start->msdu_length, 279 msdu_start->ipsec_esp, 280 msdu_start->l3_offset, 281 msdu_start->ipsec_ah, 282 msdu_start->l4_offset, 283 msdu_start->msdu_number, 284 msdu_start->decap_format, 285 msdu_start->ipv4_proto, 286 msdu_start->ipv6_proto, 287 msdu_start->tcp_proto, 288 msdu_start->udp_proto, 289 msdu_start->ip_frag, 290 msdu_start->tcp_only_ack, 291 msdu_start->da_is_bcast_mcast, 292 msdu_start->ip4_protocol_ip6_next_header, 293 msdu_start->toeplitz_hash_2_or_4, 294 msdu_start->flow_id_toeplitz, 295 msdu_start->user_rssi, 296 msdu_start->pkt_type, 297 msdu_start->stbc, 298 msdu_start->sgi, 299 msdu_start->rate_mcs, 300 msdu_start->receive_bandwidth, 301 msdu_start->reception_type, 302 msdu_start->ppdu_start_timestamp); 303 304 __QDF_TRACE_RL(dbg_level, QDF_MODULE_ID_DP, 305 "rx_msdu_start tlv (2/2) - " 306 "sw_phy_meta_data: %x ", 307 msdu_start->sw_phy_meta_data); 308 } 309 310 /** 311 * hal_rx_dump_msdu_end_tlv_6490: dump RX msdu_end TLV in structured 312 * human readable format. 313 * @ msdu_end: pointer the msdu_end TLV in pkt. 314 * @ dbg_level: log level. 315 * 316 * Return: void 317 */ 318 static void hal_rx_dump_msdu_end_tlv_6490(void *msduend, 319 uint8_t dbg_level) 320 { 321 struct rx_msdu_end *msdu_end = (struct rx_msdu_end *)msduend; 322 323 __QDF_TRACE_RL(dbg_level, QDF_MODULE_ID_DP, 324 "rx_msdu_end tlv (1/3) - " 325 "rxpcu_mpdu_filter_in_category: %x " 326 "sw_frame_group_id: %x " 327 "phy_ppdu_id: %x " 328 "ip_hdr_chksum: %x " 329 "tcp_udp_chksum: %x " 330 "key_id_octet: %x " 331 "cce_super_rule: %x " 332 "cce_classify_not_done_truncat: %x " 333 "cce_classify_not_done_cce_dis: %x " 334 "ext_wapi_pn_63_48: %x " 335 "ext_wapi_pn_95_64: %x " 336 "ext_wapi_pn_127_96: %x " 337 "reported_mpdu_length: %x " 338 "first_msdu: %x " 339 "last_msdu: %x " 340 "sa_idx_timeout: %x " 341 "da_idx_timeout: %x " 342 "msdu_limit_error: %x " 343 "flow_idx_timeout: %x " 344 "flow_idx_invalid: %x " 345 "wifi_parser_error: %x " 346 "amsdu_parser_error: %x", 347 msdu_end->rxpcu_mpdu_filter_in_category, 348 msdu_end->sw_frame_group_id, 349 msdu_end->phy_ppdu_id, 350 msdu_end->ip_hdr_chksum, 351 msdu_end->tcp_udp_chksum, 352 msdu_end->key_id_octet, 353 msdu_end->cce_super_rule, 354 msdu_end->cce_classify_not_done_truncate, 355 msdu_end->cce_classify_not_done_cce_dis, 356 msdu_end->ext_wapi_pn_63_48, 357 msdu_end->ext_wapi_pn_95_64, 358 msdu_end->ext_wapi_pn_127_96, 359 msdu_end->reported_mpdu_length, 360 msdu_end->first_msdu, 361 msdu_end->last_msdu, 362 msdu_end->sa_idx_timeout, 363 msdu_end->da_idx_timeout, 364 msdu_end->msdu_limit_error, 365 msdu_end->flow_idx_timeout, 366 msdu_end->flow_idx_invalid, 367 msdu_end->wifi_parser_error, 368 msdu_end->amsdu_parser_error); 369 370 __QDF_TRACE_RL(dbg_level, QDF_MODULE_ID_DP, 371 "rx_msdu_end tlv (2/3)- " 372 "sa_is_valid: %x " 373 "da_is_valid: %x " 374 "da_is_mcbc: %x " 375 "l3_header_padding: %x " 376 "ipv6_options_crc: %x " 377 "tcp_seq_number: %x " 378 "tcp_ack_number: %x " 379 "tcp_flag: %x " 380 "lro_eligible: %x " 381 "window_size: %x " 382 "da_offset: %x " 383 "sa_offset: %x " 384 "da_offset_valid: %x " 385 "sa_offset_valid: %x " 386 "rule_indication_31_0: %x " 387 "rule_indication_63_32: %x " 388 "sa_idx: %x " 389 "da_idx: %x " 390 "msdu_drop: %x " 391 "reo_destination_indication: %x " 392 "flow_idx: %x " 393 "fse_metadata: %x " 394 "cce_metadata: %x " 395 "sa_sw_peer_id: %x ", 396 msdu_end->sa_is_valid, 397 msdu_end->da_is_valid, 398 msdu_end->da_is_mcbc, 399 msdu_end->l3_header_padding, 400 msdu_end->ipv6_options_crc, 401 msdu_end->tcp_seq_number, 402 msdu_end->tcp_ack_number, 403 msdu_end->tcp_flag, 404 msdu_end->lro_eligible, 405 msdu_end->window_size, 406 msdu_end->da_offset, 407 msdu_end->sa_offset, 408 msdu_end->da_offset_valid, 409 msdu_end->sa_offset_valid, 410 msdu_end->rule_indication_31_0, 411 msdu_end->rule_indication_63_32, 412 msdu_end->sa_idx, 413 msdu_end->da_idx_or_sw_peer_id, 414 msdu_end->msdu_drop, 415 msdu_end->reo_destination_indication, 416 msdu_end->flow_idx, 417 msdu_end->fse_metadata, 418 msdu_end->cce_metadata, 419 msdu_end->sa_sw_peer_id); 420 __QDF_TRACE_RL(dbg_level, QDF_MODULE_ID_DP, 421 "rx_msdu_end tlv (3/3)" 422 "aggregation_count %x " 423 "flow_aggregation_continuation %x " 424 "fisa_timeout %x " 425 "cumulative_l4_checksum %x " 426 "cumulative_ip_length %x", 427 msdu_end->aggregation_count, 428 msdu_end->flow_aggregation_continuation, 429 msdu_end->fisa_timeout, 430 msdu_end->cumulative_l4_checksum, 431 msdu_end->cumulative_ip_length); 432 } 433 434 /* 435 * Get tid from RX_MPDU_START 436 */ 437 #define HAL_RX_MPDU_INFO_TID_GET(_rx_mpdu_info) \ 438 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_info), \ 439 RX_MPDU_INFO_7_TID_OFFSET)), \ 440 RX_MPDU_INFO_7_TID_MASK, \ 441 RX_MPDU_INFO_7_TID_LSB)) 442 443 static uint32_t hal_rx_mpdu_start_tid_get_6490(uint8_t *buf) 444 { 445 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 446 struct rx_mpdu_start *mpdu_start = 447 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 448 uint32_t tid; 449 450 tid = HAL_RX_MPDU_INFO_TID_GET(&mpdu_start->rx_mpdu_info_details); 451 452 return tid; 453 } 454 455 #define HAL_RX_MSDU_START_RECEPTION_TYPE_GET(_rx_msdu_start) \ 456 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start), \ 457 RX_MSDU_START_5_RECEPTION_TYPE_OFFSET)), \ 458 RX_MSDU_START_5_RECEPTION_TYPE_MASK, \ 459 RX_MSDU_START_5_RECEPTION_TYPE_LSB)) 460 461 /* 462 * hal_rx_msdu_start_reception_type_get(): API to get the reception type 463 * Interval from rx_msdu_start 464 * 465 * @buf: pointer to the start of RX PKT TLV header 466 * Return: uint32_t(reception_type) 467 */ 468 static 469 uint32_t hal_rx_msdu_start_reception_type_get_6490(uint8_t *buf) 470 { 471 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 472 struct rx_msdu_start *msdu_start = 473 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 474 uint32_t reception_type; 475 476 reception_type = HAL_RX_MSDU_START_RECEPTION_TYPE_GET(msdu_start); 477 478 return reception_type; 479 } 480 481 /** 482 * hal_rx_msdu_end_da_idx_get_6490: API to get da_idx 483 * from rx_msdu_end TLV 484 * 485 * @ buf: pointer to the start of RX PKT TLV headers 486 * Return: da index 487 */ 488 static uint16_t hal_rx_msdu_end_da_idx_get_6490(uint8_t *buf) 489 { 490 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 491 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 492 uint16_t da_idx; 493 494 da_idx = HAL_RX_MSDU_END_DA_IDX_GET(msdu_end); 495 496 return da_idx; 497 } 498 /** 499 * hal_rx_get_rx_fragment_number_6490(): Function to retrieve rx fragment number 500 * 501 * @nbuf: Network buffer 502 * Returns: rx fragment number 503 */ 504 static 505 uint8_t hal_rx_get_rx_fragment_number_6490(uint8_t *buf) 506 { 507 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 508 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 509 510 /* Return first 4 bits as fragment number */ 511 return (HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info) & 512 DOT11_SEQ_FRAG_MASK); 513 } 514 515 /** 516 * hal_rx_msdu_end_da_is_mcbc_get_6490(): API to check if pkt is MCBC 517 * from rx_msdu_end TLV 518 * 519 * @ buf: pointer to the start of RX PKT TLV headers 520 * Return: da_is_mcbc 521 */ 522 static uint8_t 523 hal_rx_msdu_end_da_is_mcbc_get_6490(uint8_t *buf) 524 { 525 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 526 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 527 528 return HAL_RX_MSDU_END_DA_IS_MCBC_GET(msdu_end); 529 } 530 531 /** 532 * hal_rx_msdu_end_sa_is_valid_get_6490(): API to get_6490 the 533 * sa_is_valid bit from rx_msdu_end TLV 534 * 535 * @ buf: pointer to the start of RX PKT TLV headers 536 * Return: sa_is_valid bit 537 */ 538 static uint8_t 539 hal_rx_msdu_end_sa_is_valid_get_6490(uint8_t *buf) 540 { 541 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 542 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 543 uint8_t sa_is_valid; 544 545 sa_is_valid = HAL_RX_MSDU_END_SA_IS_VALID_GET(msdu_end); 546 547 return sa_is_valid; 548 } 549 550 /** 551 * hal_rx_msdu_end_sa_idx_get_6490(): API to get_6490 the 552 * sa_idx from rx_msdu_end TLV 553 * 554 * @ buf: pointer to the start of RX PKT TLV headers 555 * Return: sa_idx (SA AST index) 556 */ 557 static 558 uint16_t hal_rx_msdu_end_sa_idx_get_6490(uint8_t *buf) 559 { 560 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 561 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 562 uint16_t sa_idx; 563 564 sa_idx = HAL_RX_MSDU_END_SA_IDX_GET(msdu_end); 565 566 return sa_idx; 567 } 568 569 /** 570 * hal_rx_desc_is_first_msdu_6490() - Check if first msdu 571 * 572 * @hal_soc_hdl: hal_soc handle 573 * @hw_desc_addr: hardware descriptor address 574 * 575 * Return: 0 - success/ non-zero failure 576 */ 577 static uint32_t hal_rx_desc_is_first_msdu_6490(void *hw_desc_addr) 578 { 579 struct rx_pkt_tlvs *rx_tlvs = (struct rx_pkt_tlvs *)hw_desc_addr; 580 struct rx_msdu_end *msdu_end = &rx_tlvs->msdu_end_tlv.rx_msdu_end; 581 582 return HAL_RX_GET(msdu_end, RX_MSDU_END_10, FIRST_MSDU); 583 } 584 585 /** 586 * hal_rx_msdu_end_l3_hdr_padding_get_6490(): API to get_6490 the 587 * l3_header padding from rx_msdu_end TLV 588 * 589 * @ buf: pointer to the start of RX PKT TLV headers 590 * Return: number of l3 header padding bytes 591 */ 592 static uint32_t hal_rx_msdu_end_l3_hdr_padding_get_6490(uint8_t *buf) 593 { 594 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 595 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 596 uint32_t l3_header_padding; 597 598 l3_header_padding = HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(msdu_end); 599 600 return l3_header_padding; 601 } 602 603 /* 604 * @ hal_rx_encryption_info_valid_6490: Returns encryption type. 605 * 606 * @ buf: rx_tlv_hdr of the received packet 607 * @ Return: encryption type 608 */ 609 static uint32_t hal_rx_encryption_info_valid_6490(uint8_t *buf) 610 { 611 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 612 struct rx_mpdu_start *mpdu_start = 613 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 614 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 615 uint32_t encryption_info = HAL_RX_MPDU_ENCRYPTION_INFO_VALID(mpdu_info); 616 617 return encryption_info; 618 } 619 620 /* 621 * @ hal_rx_print_pn_6490: Prints the PN of rx packet. 622 * 623 * @ buf: rx_tlv_hdr of the received packet 624 * @ Return: void 625 */ 626 static void hal_rx_print_pn_6490(uint8_t *buf) 627 { 628 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 629 struct rx_mpdu_start *mpdu_start = 630 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 631 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 632 633 uint32_t pn_31_0 = HAL_RX_MPDU_PN_31_0_GET(mpdu_info); 634 uint32_t pn_63_32 = HAL_RX_MPDU_PN_63_32_GET(mpdu_info); 635 uint32_t pn_95_64 = HAL_RX_MPDU_PN_95_64_GET(mpdu_info); 636 uint32_t pn_127_96 = HAL_RX_MPDU_PN_127_96_GET(mpdu_info); 637 638 hal_debug("PN number pn_127_96 0x%x pn_95_64 0x%x pn_63_32 0x%x pn_31_0 0x%x ", 639 pn_127_96, pn_95_64, pn_63_32, pn_31_0); 640 } 641 642 /** 643 * hal_rx_msdu_end_first_msdu_get_6490: API to get first msdu status 644 * from rx_msdu_end TLV 645 * 646 * @ buf: pointer to the start of RX PKT TLV headers 647 * Return: first_msdu 648 */ 649 static uint8_t hal_rx_msdu_end_first_msdu_get_6490(uint8_t *buf) 650 { 651 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 652 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 653 uint8_t first_msdu; 654 655 first_msdu = HAL_RX_MSDU_END_FIRST_MSDU_GET(msdu_end); 656 657 return first_msdu; 658 } 659 660 /** 661 * hal_rx_msdu_end_da_is_valid_get_6490: API to check if da is valid 662 * from rx_msdu_end TLV 663 * 664 * @ buf: pointer to the start of RX PKT TLV headers 665 * Return: da_is_valid 666 */ 667 static uint8_t hal_rx_msdu_end_da_is_valid_get_6490(uint8_t *buf) 668 { 669 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 670 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 671 uint8_t da_is_valid; 672 673 da_is_valid = HAL_RX_MSDU_END_DA_IS_VALID_GET(msdu_end); 674 675 return da_is_valid; 676 } 677 678 /** 679 * hal_rx_msdu_end_last_msdu_get_6490: API to get last msdu status 680 * from rx_msdu_end TLV 681 * 682 * @ buf: pointer to the start of RX PKT TLV headers 683 * Return: last_msdu 684 */ 685 static uint8_t hal_rx_msdu_end_last_msdu_get_6490(uint8_t *buf) 686 { 687 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 688 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 689 uint8_t last_msdu; 690 691 last_msdu = HAL_RX_MSDU_END_LAST_MSDU_GET(msdu_end); 692 693 return last_msdu; 694 } 695 696 /* 697 * hal_rx_get_mpdu_mac_ad4_valid_6490(): Retrieves if mpdu 4th addr is valid 698 * 699 * @nbuf: Network buffer 700 * Returns: value of mpdu 4th address valid field 701 */ 702 static bool hal_rx_get_mpdu_mac_ad4_valid_6490(uint8_t *buf) 703 { 704 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 705 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 706 bool ad4_valid = 0; 707 708 ad4_valid = HAL_RX_MPDU_GET_MAC_AD4_VALID(rx_mpdu_info); 709 710 return ad4_valid; 711 } 712 713 /** 714 * hal_rx_mpdu_start_sw_peer_id_get_6490: Retrieve sw peer_id 715 * @buf: network buffer 716 * 717 * Return: sw peer_id 718 */ 719 static uint32_t hal_rx_mpdu_start_sw_peer_id_get_6490(uint8_t *buf) 720 { 721 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 722 struct rx_mpdu_start *mpdu_start = 723 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 724 725 return HAL_RX_MPDU_INFO_SW_PEER_ID_GET( 726 &mpdu_start->rx_mpdu_info_details); 727 } 728 729 /** 730 * hal_rx_mpdu_get_to_ds_6490(): API to get the tods info 731 * from rx_mpdu_start 732 * 733 * @buf: pointer to the start of RX PKT TLV header 734 * Return: uint32_t(to_ds) 735 */ 736 static uint32_t hal_rx_mpdu_get_to_ds_6490(uint8_t *buf) 737 { 738 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 739 struct rx_mpdu_start *mpdu_start = 740 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 741 742 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 743 744 return HAL_RX_MPDU_GET_TODS(mpdu_info); 745 } 746 747 /* 748 * hal_rx_mpdu_get_fr_ds_6490(): API to get the from ds info 749 * from rx_mpdu_start 750 * 751 * @buf: pointer to the start of RX PKT TLV header 752 * Return: uint32_t(fr_ds) 753 */ 754 static uint32_t hal_rx_mpdu_get_fr_ds_6490(uint8_t *buf) 755 { 756 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 757 struct rx_mpdu_start *mpdu_start = 758 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 759 760 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 761 762 return HAL_RX_MPDU_GET_FROMDS(mpdu_info); 763 } 764 765 /* 766 * hal_rx_get_mpdu_frame_control_valid_6490(): Retrieves mpdu 767 * frame control valid 768 * 769 * @nbuf: Network buffer 770 * Returns: value of frame control valid field 771 */ 772 static uint8_t hal_rx_get_mpdu_frame_control_valid_6490(uint8_t *buf) 773 { 774 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 775 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 776 777 return HAL_RX_MPDU_GET_FRAME_CONTROL_VALID(rx_mpdu_info); 778 } 779 780 /* 781 * hal_rx_mpdu_get_addr1_6490(): API to check get address1 of the mpdu 782 * 783 * @buf: pointer to the start of RX PKT TLV headera 784 * @mac_addr: pointer to mac address 785 * Return: success/failure 786 */ 787 static QDF_STATUS hal_rx_mpdu_get_addr1_6490(uint8_t *buf, uint8_t *mac_addr) 788 { 789 struct __attribute__((__packed__)) hal_addr1 { 790 uint32_t ad1_31_0; 791 uint16_t ad1_47_32; 792 }; 793 794 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 795 struct rx_mpdu_start *mpdu_start = 796 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 797 798 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 799 struct hal_addr1 *addr = (struct hal_addr1 *)mac_addr; 800 uint32_t mac_addr_ad1_valid; 801 802 mac_addr_ad1_valid = HAL_RX_MPDU_MAC_ADDR_AD1_VALID_GET(mpdu_info); 803 804 if (mac_addr_ad1_valid) { 805 addr->ad1_31_0 = HAL_RX_MPDU_AD1_31_0_GET(mpdu_info); 806 addr->ad1_47_32 = HAL_RX_MPDU_AD1_47_32_GET(mpdu_info); 807 return QDF_STATUS_SUCCESS; 808 } 809 810 return QDF_STATUS_E_FAILURE; 811 } 812 813 /* 814 * hal_rx_mpdu_get_addr2_6490(): API to check get address2 of the mpdu 815 * in the packet 816 * 817 * @buf: pointer to the start of RX PKT TLV header 818 * @mac_addr: pointer to mac address 819 * Return: success/failure 820 */ 821 static QDF_STATUS hal_rx_mpdu_get_addr2_6490(uint8_t *buf, 822 uint8_t *mac_addr) 823 { 824 struct __attribute__((__packed__)) hal_addr2 { 825 uint16_t ad2_15_0; 826 uint32_t ad2_47_16; 827 }; 828 829 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 830 struct rx_mpdu_start *mpdu_start = 831 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 832 833 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 834 struct hal_addr2 *addr = (struct hal_addr2 *)mac_addr; 835 uint32_t mac_addr_ad2_valid; 836 837 mac_addr_ad2_valid = HAL_RX_MPDU_MAC_ADDR_AD2_VALID_GET(mpdu_info); 838 839 if (mac_addr_ad2_valid) { 840 addr->ad2_15_0 = HAL_RX_MPDU_AD2_15_0_GET(mpdu_info); 841 addr->ad2_47_16 = HAL_RX_MPDU_AD2_47_16_GET(mpdu_info); 842 return QDF_STATUS_SUCCESS; 843 } 844 845 return QDF_STATUS_E_FAILURE; 846 } 847 848 /* 849 * hal_rx_mpdu_get_addr3_6490(): API to get address3 of the mpdu 850 * in the packet 851 * 852 * @buf: pointer to the start of RX PKT TLV header 853 * @mac_addr: pointer to mac address 854 * Return: success/failure 855 */ 856 static QDF_STATUS hal_rx_mpdu_get_addr3_6490(uint8_t *buf, uint8_t *mac_addr) 857 { 858 struct __attribute__((__packed__)) hal_addr3 { 859 uint32_t ad3_31_0; 860 uint16_t ad3_47_32; 861 }; 862 863 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 864 struct rx_mpdu_start *mpdu_start = 865 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 866 867 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 868 struct hal_addr3 *addr = (struct hal_addr3 *)mac_addr; 869 uint32_t mac_addr_ad3_valid; 870 871 mac_addr_ad3_valid = HAL_RX_MPDU_MAC_ADDR_AD3_VALID_GET(mpdu_info); 872 873 if (mac_addr_ad3_valid) { 874 addr->ad3_31_0 = HAL_RX_MPDU_AD3_31_0_GET(mpdu_info); 875 addr->ad3_47_32 = HAL_RX_MPDU_AD3_47_32_GET(mpdu_info); 876 return QDF_STATUS_SUCCESS; 877 } 878 879 return QDF_STATUS_E_FAILURE; 880 } 881 882 /* 883 * hal_rx_mpdu_get_addr4_6490(): API to get address4 of the mpdu 884 * in the packet 885 * 886 * @buf: pointer to the start of RX PKT TLV header 887 * @mac_addr: pointer to mac address 888 * Return: success/failure 889 */ 890 static QDF_STATUS hal_rx_mpdu_get_addr4_6490(uint8_t *buf, uint8_t *mac_addr) 891 { 892 struct __attribute__((__packed__)) hal_addr4 { 893 uint32_t ad4_31_0; 894 uint16_t ad4_47_32; 895 }; 896 897 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 898 struct rx_mpdu_start *mpdu_start = 899 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 900 901 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 902 struct hal_addr4 *addr = (struct hal_addr4 *)mac_addr; 903 uint32_t mac_addr_ad4_valid; 904 905 mac_addr_ad4_valid = HAL_RX_MPDU_MAC_ADDR_AD4_VALID_GET(mpdu_info); 906 907 if (mac_addr_ad4_valid) { 908 addr->ad4_31_0 = HAL_RX_MPDU_AD4_31_0_GET(mpdu_info); 909 addr->ad4_47_32 = HAL_RX_MPDU_AD4_47_32_GET(mpdu_info); 910 return QDF_STATUS_SUCCESS; 911 } 912 913 return QDF_STATUS_E_FAILURE; 914 } 915 916 /* 917 * hal_rx_get_mpdu_sequence_control_valid_6490(): Get mpdu 918 * sequence control valid 919 * 920 * @nbuf: Network buffer 921 * Returns: value of sequence control valid field 922 */ 923 static uint8_t hal_rx_get_mpdu_sequence_control_valid_6490(uint8_t *buf) 924 { 925 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 926 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 927 928 return HAL_RX_MPDU_GET_SEQUENCE_CONTROL_VALID(rx_mpdu_info); 929 } 930 931 /** 932 * hal_rx_is_unicast_6490: check packet is unicast frame or not. 933 * 934 * @ buf: pointer to rx pkt TLV. 935 * 936 * Return: true on unicast. 937 */ 938 static bool hal_rx_is_unicast_6490(uint8_t *buf) 939 { 940 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 941 struct rx_mpdu_start *mpdu_start = 942 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 943 uint32_t grp_id; 944 uint8_t *rx_mpdu_info = (uint8_t *)&mpdu_start->rx_mpdu_info_details; 945 946 grp_id = (_HAL_MS((*_OFFSET_TO_WORD_PTR((rx_mpdu_info), 947 RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_OFFSET)), 948 RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_MASK, 949 RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_LSB)); 950 951 return (HAL_MPDU_SW_FRAME_GROUP_UNICAST_DATA == grp_id) ? true : false; 952 } 953 954 /** 955 * hal_rx_tid_get_6490: get tid based on qos control valid. 956 * @hal_soc_hdl: hal_soc handle 957 * @ buf: pointer to rx pkt TLV. 958 * 959 * Return: tid 960 */ 961 static uint32_t hal_rx_tid_get_6490(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 962 { 963 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 964 struct rx_mpdu_start *mpdu_start = 965 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 966 uint8_t *rx_mpdu_info = (uint8_t *)&mpdu_start->rx_mpdu_info_details; 967 uint8_t qos_control_valid = 968 (_HAL_MS((*_OFFSET_TO_WORD_PTR((rx_mpdu_info), 969 RX_MPDU_INFO_11_MPDU_QOS_CONTROL_VALID_OFFSET)), 970 RX_MPDU_INFO_11_MPDU_QOS_CONTROL_VALID_MASK, 971 RX_MPDU_INFO_11_MPDU_QOS_CONTROL_VALID_LSB)); 972 973 if (qos_control_valid) 974 return hal_rx_mpdu_start_tid_get_6490(buf); 975 976 return HAL_RX_NON_QOS_TID; 977 } 978 979 /** 980 * hal_rx_hw_desc_get_ppduid_get_6490(): retrieve ppdu id 981 * @rx_tlv_hdr: start address of rx_pkt_tlvs 982 * @rxdma_dst_ring_desc: Rx HW descriptor 983 * 984 * Return: ppdu id 985 */ 986 static uint32_t hal_rx_hw_desc_get_ppduid_get_6490(void *rx_tlv_hdr, 987 void *rxdma_dst_ring_desc) 988 { 989 struct rx_mpdu_info *rx_mpdu_info; 990 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)rx_tlv_hdr; 991 992 rx_mpdu_info = 993 &rx_desc->mpdu_start_tlv.rx_mpdu_start.rx_mpdu_info_details; 994 995 return HAL_RX_GET(rx_mpdu_info, RX_MPDU_INFO_9, PHY_PPDU_ID); 996 } 997 998 /** 999 * hal_reo_status_get_header_6490 - Process reo desc info 1000 * @ring_desc: REO status ring descriptor 1001 * @b - tlv type info 1002 * @h1 - Pointer to hal_reo_status_header where info to be stored 1003 * 1004 * Return - none. 1005 * 1006 */ 1007 static void hal_reo_status_get_header_6490(hal_ring_desc_t ring_desc, int b, 1008 void *h1) 1009 { 1010 uint32_t *d = (uint32_t *)ring_desc; 1011 uint32_t val1 = 0; 1012 struct hal_reo_status_header *h = 1013 (struct hal_reo_status_header *)h1; 1014 1015 /* Offsets of descriptor fields defined in HW headers start 1016 * from the field after TLV header 1017 */ 1018 d += HAL_GET_NUM_DWORDS(sizeof(struct tlv_32_hdr)); 1019 1020 switch (b) { 1021 case HAL_REO_QUEUE_STATS_STATUS_TLV: 1022 val1 = d[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_0, 1023 STATUS_HEADER_REO_STATUS_NUMBER)]; 1024 break; 1025 case HAL_REO_FLUSH_QUEUE_STATUS_TLV: 1026 val1 = d[HAL_OFFSET_DW(REO_FLUSH_QUEUE_STATUS_0, 1027 STATUS_HEADER_REO_STATUS_NUMBER)]; 1028 break; 1029 case HAL_REO_FLUSH_CACHE_STATUS_TLV: 1030 val1 = d[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_0, 1031 STATUS_HEADER_REO_STATUS_NUMBER)]; 1032 break; 1033 case HAL_REO_UNBLK_CACHE_STATUS_TLV: 1034 val1 = d[HAL_OFFSET_DW(REO_UNBLOCK_CACHE_STATUS_0, 1035 STATUS_HEADER_REO_STATUS_NUMBER)]; 1036 break; 1037 case HAL_REO_TIMOUT_LIST_STATUS_TLV: 1038 val1 = d[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_0, 1039 STATUS_HEADER_REO_STATUS_NUMBER)]; 1040 break; 1041 case HAL_REO_DESC_THRES_STATUS_TLV: 1042 val1 = 1043 d[HAL_OFFSET_DW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0, 1044 STATUS_HEADER_REO_STATUS_NUMBER)]; 1045 break; 1046 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: 1047 val1 = d[HAL_OFFSET_DW(REO_UPDATE_RX_REO_QUEUE_STATUS_0, 1048 STATUS_HEADER_REO_STATUS_NUMBER)]; 1049 break; 1050 default: 1051 qdf_nofl_err("ERROR: Unknown tlv\n"); 1052 break; 1053 } 1054 h->cmd_num = 1055 HAL_GET_FIELD( 1056 UNIFORM_REO_STATUS_HEADER_0, REO_STATUS_NUMBER, 1057 val1); 1058 h->exec_time = 1059 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_0, 1060 CMD_EXECUTION_TIME, val1); 1061 h->status = 1062 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_0, 1063 REO_CMD_EXECUTION_STATUS, val1); 1064 switch (b) { 1065 case HAL_REO_QUEUE_STATS_STATUS_TLV: 1066 val1 = d[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_1, 1067 STATUS_HEADER_TIMESTAMP)]; 1068 break; 1069 case HAL_REO_FLUSH_QUEUE_STATUS_TLV: 1070 val1 = d[HAL_OFFSET_DW(REO_FLUSH_QUEUE_STATUS_1, 1071 STATUS_HEADER_TIMESTAMP)]; 1072 break; 1073 case HAL_REO_FLUSH_CACHE_STATUS_TLV: 1074 val1 = d[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_1, 1075 STATUS_HEADER_TIMESTAMP)]; 1076 break; 1077 case HAL_REO_UNBLK_CACHE_STATUS_TLV: 1078 val1 = d[HAL_OFFSET_DW(REO_UNBLOCK_CACHE_STATUS_1, 1079 STATUS_HEADER_TIMESTAMP)]; 1080 break; 1081 case HAL_REO_TIMOUT_LIST_STATUS_TLV: 1082 val1 = d[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_1, 1083 STATUS_HEADER_TIMESTAMP)]; 1084 break; 1085 case HAL_REO_DESC_THRES_STATUS_TLV: 1086 val1 = 1087 d[HAL_OFFSET_DW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_1, 1088 STATUS_HEADER_TIMESTAMP)]; 1089 break; 1090 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: 1091 val1 = d[HAL_OFFSET_DW(REO_UPDATE_RX_REO_QUEUE_STATUS_1, 1092 STATUS_HEADER_TIMESTAMP)]; 1093 break; 1094 default: 1095 qdf_nofl_err("ERROR: Unknown tlv\n"); 1096 break; 1097 } 1098 h->tstamp = 1099 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_1, TIMESTAMP, val1); 1100 } 1101 1102 /** 1103 * hal_tx_desc_set_mesh_en_6490 - Set mesh_enable flag in Tx descriptor 1104 * @desc: Handle to Tx Descriptor 1105 * @en: For raw WiFi frames, this indicates transmission to a mesh STA, 1106 * enabling the interpretation of the 'Mesh Control Present' bit 1107 * (bit 8) of QoS Control (otherwise this bit is ignored), 1108 * For native WiFi frames, this indicates that a 'Mesh Control' field 1109 * is present between the header and the LLC. 1110 * 1111 * Return: void 1112 */ 1113 static inline 1114 void hal_tx_desc_set_mesh_en_6490(void *desc, uint8_t en) 1115 { 1116 HAL_SET_FLD(desc, TCL_DATA_CMD_5, MESH_ENABLE) |= 1117 HAL_TX_SM(TCL_DATA_CMD_5, MESH_ENABLE, en); 1118 } 1119 1120 static 1121 void *hal_rx_msdu0_buffer_addr_lsb_6490(void *link_desc_va) 1122 { 1123 return (void *)HAL_RX_MSDU0_BUFFER_ADDR_LSB(link_desc_va); 1124 } 1125 1126 static 1127 void *hal_rx_msdu_desc_info_ptr_get_6490(void *msdu0) 1128 { 1129 return (void *)HAL_RX_MSDU_DESC_INFO_PTR_GET(msdu0); 1130 } 1131 1132 static 1133 void *hal_ent_mpdu_desc_info_6490(void *ent_ring_desc) 1134 { 1135 return (void *)HAL_ENT_MPDU_DESC_INFO(ent_ring_desc); 1136 } 1137 1138 static 1139 void *hal_dst_mpdu_desc_info_6490(void *dst_ring_desc) 1140 { 1141 return (void *)HAL_DST_MPDU_DESC_INFO(dst_ring_desc); 1142 } 1143 1144 static 1145 uint8_t hal_rx_get_fc_valid_6490(uint8_t *buf) 1146 { 1147 return HAL_RX_GET_FC_VALID(buf); 1148 } 1149 1150 static uint8_t hal_rx_get_to_ds_flag_6490(uint8_t *buf) 1151 { 1152 return HAL_RX_GET_TO_DS_FLAG(buf); 1153 } 1154 1155 static uint8_t hal_rx_get_mac_addr2_valid_6490(uint8_t *buf) 1156 { 1157 return HAL_RX_GET_MAC_ADDR2_VALID(buf); 1158 } 1159 1160 static uint8_t hal_rx_get_filter_category_6490(uint8_t *buf) 1161 { 1162 return HAL_RX_GET_FILTER_CATEGORY(buf); 1163 } 1164 1165 static uint32_t 1166 hal_rx_get_ppdu_id_6490(uint8_t *buf) 1167 { 1168 return HAL_RX_GET_PPDU_ID(buf); 1169 } 1170 1171 /** 1172 * hal_reo_config_6490(): Set reo config parameters 1173 * @soc: hal soc handle 1174 * @reg_val: value to be set 1175 * @reo_params: reo parameters 1176 * 1177 * Return: void 1178 */ 1179 static 1180 void hal_reo_config_6490(struct hal_soc *soc, 1181 uint32_t reg_val, 1182 struct hal_reo_params *reo_params) 1183 { 1184 HAL_REO_R0_CONFIG(soc, reg_val, reo_params); 1185 } 1186 1187 /** 1188 * hal_rx_msdu_desc_info_get_ptr_6490() - Get msdu desc info ptr 1189 * @msdu_details_ptr - Pointer to msdu_details_ptr 1190 * 1191 * Return - Pointer to rx_msdu_desc_info structure. 1192 * 1193 */ 1194 static void *hal_rx_msdu_desc_info_get_ptr_6490(void *msdu_details_ptr) 1195 { 1196 return HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr); 1197 } 1198 1199 /** 1200 * hal_rx_link_desc_msdu0_ptr_6490 - Get pointer to rx_msdu details 1201 * @link_desc - Pointer to link desc 1202 * 1203 * Return - Pointer to rx_msdu_details structure 1204 * 1205 */ 1206 static void *hal_rx_link_desc_msdu0_ptr_6490(void *link_desc) 1207 { 1208 return HAL_RX_LINK_DESC_MSDU0_PTR(link_desc); 1209 } 1210 1211 /** 1212 * hal_rx_msdu_flow_idx_get_6490: API to get flow index 1213 * from rx_msdu_end TLV 1214 * @buf: pointer to the start of RX PKT TLV headers 1215 * 1216 * Return: flow index value from MSDU END TLV 1217 */ 1218 static inline uint32_t hal_rx_msdu_flow_idx_get_6490(uint8_t *buf) 1219 { 1220 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1221 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1222 1223 return HAL_RX_MSDU_END_FLOW_IDX_GET(msdu_end); 1224 } 1225 1226 /** 1227 * hal_rx_msdu_get_reo_destination_indication_6490: API to get 1228 * reo_destination_indication from rx_msdu_end TLV 1229 * @buf: pointer to the start of RX PKT TLV headers 1230 * @reo_destination_indication: pointer to return value of reo_destination_indication 1231 * 1232 * Return: none 1233 */ 1234 static inline void 1235 hal_rx_msdu_get_reo_destination_indication_6490(uint8_t *buf, 1236 uint32_t *reo_destination_indication) 1237 { 1238 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1239 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1240 1241 *reo_destination_indication = HAL_RX_MSDU_END_REO_DEST_IND_GET(msdu_end); 1242 } 1243 1244 /** 1245 * hal_rx_msdu_flow_idx_invalid_6490: API to get flow index invalid 1246 * from rx_msdu_end TLV 1247 * @buf: pointer to the start of RX PKT TLV headers 1248 * 1249 * Return: flow index invalid value from MSDU END TLV 1250 */ 1251 static bool hal_rx_msdu_flow_idx_invalid_6490(uint8_t *buf) 1252 { 1253 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1254 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1255 1256 return HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(msdu_end); 1257 } 1258 1259 /** 1260 * hal_rx_msdu_flow_idx_timeout_6490: API to get flow index timeout 1261 * from rx_msdu_end TLV 1262 * @buf: pointer to the start of RX PKT TLV headers 1263 * 1264 * Return: flow index timeout value from MSDU END TLV 1265 */ 1266 static bool hal_rx_msdu_flow_idx_timeout_6490(uint8_t *buf) 1267 { 1268 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1269 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1270 1271 return HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(msdu_end); 1272 } 1273 1274 /** 1275 * hal_rx_msdu_fse_metadata_get_6490: API to get FSE metadata 1276 * from rx_msdu_end TLV 1277 * @buf: pointer to the start of RX PKT TLV headers 1278 * 1279 * Return: fse metadata value from MSDU END TLV 1280 */ 1281 static uint32_t hal_rx_msdu_fse_metadata_get_6490(uint8_t *buf) 1282 { 1283 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1284 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1285 1286 return HAL_RX_MSDU_END_FSE_METADATA_GET(msdu_end); 1287 } 1288 1289 /** 1290 * hal_rx_msdu_cce_metadata_get_6490: API to get CCE metadata 1291 * from rx_msdu_end TLV 1292 * @buf: pointer to the start of RX PKT TLV headers 1293 * 1294 * Return: cce_metadata 1295 */ 1296 static uint16_t 1297 hal_rx_msdu_cce_metadata_get_6490(uint8_t *buf) 1298 { 1299 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1300 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1301 1302 return HAL_RX_MSDU_END_CCE_METADATA_GET(msdu_end); 1303 } 1304 1305 /** 1306 * hal_rx_msdu_get_flow_params_6490: API to get flow index, flow index invalid 1307 * and flow index timeout from rx_msdu_end TLV 1308 * @buf: pointer to the start of RX PKT TLV headers 1309 * @flow_invalid: pointer to return value of flow_idx_valid 1310 * @flow_timeout: pointer to return value of flow_idx_timeout 1311 * @flow_index: pointer to return value of flow_idx 1312 * 1313 * Return: none 1314 */ 1315 static inline void 1316 hal_rx_msdu_get_flow_params_6490(uint8_t *buf, 1317 bool *flow_invalid, 1318 bool *flow_timeout, 1319 uint32_t *flow_index) 1320 { 1321 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1322 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1323 1324 *flow_invalid = HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(msdu_end); 1325 *flow_timeout = HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(msdu_end); 1326 *flow_index = HAL_RX_MSDU_END_FLOW_IDX_GET(msdu_end); 1327 } 1328 1329 /** 1330 * hal_rx_tlv_get_tcp_chksum_6490() - API to get tcp checksum 1331 * @buf: rx_tlv_hdr 1332 * 1333 * Return: tcp checksum 1334 */ 1335 static uint16_t 1336 hal_rx_tlv_get_tcp_chksum_6490(uint8_t *buf) 1337 { 1338 return HAL_RX_TLV_GET_TCP_CHKSUM(buf); 1339 } 1340 1341 /** 1342 * hal_rx_get_rx_sequence_6490(): Function to retrieve rx sequence number 1343 * 1344 * @nbuf: Network buffer 1345 * Returns: rx sequence number 1346 */ 1347 static 1348 uint16_t hal_rx_get_rx_sequence_6490(uint8_t *buf) 1349 { 1350 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 1351 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 1352 1353 return HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info); 1354 } 1355 1356 /** 1357 * hal_get_window_address_6490(): Function to get hp/tp address 1358 * @hal_soc: Pointer to hal_soc 1359 * @addr: address offset of register 1360 * 1361 * Return: modified address offset of register 1362 */ 1363 static inline qdf_iomem_t hal_get_window_address_6490(struct hal_soc *hal_soc, 1364 qdf_iomem_t addr) 1365 { 1366 return addr; 1367 } 1368 1369 /** 1370 * hal_rx_get_fisa_cumulative_l4_checksum_6490() - Retrieve cumulative 1371 * checksum 1372 * @buf: buffer pointer 1373 * 1374 * Return: cumulative checksum 1375 */ 1376 static inline 1377 uint16_t hal_rx_get_fisa_cumulative_l4_checksum_6490(uint8_t *buf) 1378 { 1379 return HAL_RX_TLV_GET_FISA_CUMULATIVE_L4_CHECKSUM(buf); 1380 } 1381 1382 /** 1383 * hal_rx_get_fisa_cumulative_ip_length_6490() - Retrieve cumulative 1384 * ip length 1385 * @buf: buffer pointer 1386 * 1387 * Return: cumulative length 1388 */ 1389 static inline 1390 uint16_t hal_rx_get_fisa_cumulative_ip_length_6490(uint8_t *buf) 1391 { 1392 return HAL_RX_TLV_GET_FISA_CUMULATIVE_IP_LENGTH(buf); 1393 } 1394 1395 /** 1396 * hal_rx_get_udp_proto_6490() - Retrieve udp proto value 1397 * @buf: buffer 1398 * 1399 * Return: udp proto bit 1400 */ 1401 static inline 1402 bool hal_rx_get_udp_proto_6490(uint8_t *buf) 1403 { 1404 return HAL_RX_TLV_GET_UDP_PROTO(buf); 1405 } 1406 1407 /** 1408 * hal_rx_get_flow_agg_continuation_6490() - retrieve flow agg 1409 * continuation 1410 * @buf: buffer 1411 * 1412 * Return: flow agg 1413 */ 1414 static inline 1415 bool hal_rx_get_flow_agg_continuation_6490(uint8_t *buf) 1416 { 1417 return HAL_RX_TLV_GET_FLOW_AGGR_CONT(buf); 1418 } 1419 1420 /** 1421 * hal_rx_get_flow_agg_count_6490()- Retrieve flow agg count 1422 * @buf: buffer 1423 * 1424 * Return: flow agg count 1425 */ 1426 static inline 1427 uint8_t hal_rx_get_flow_agg_count_6490(uint8_t *buf) 1428 { 1429 return HAL_RX_TLV_GET_FLOW_AGGR_COUNT(buf); 1430 } 1431 1432 /** 1433 * hal_rx_get_fisa_timeout_6490() - Retrieve fisa timeout 1434 * @buf: buffer 1435 * 1436 * Return: fisa timeout 1437 */ 1438 static inline 1439 bool hal_rx_get_fisa_timeout_6490(uint8_t *buf) 1440 { 1441 return HAL_RX_TLV_GET_FISA_TIMEOUT(buf); 1442 } 1443 1444 /** 1445 * hal_rx_mpdu_start_tlv_tag_valid_6490 () - API to check if RX_MPDU_START 1446 * tlv tag is valid 1447 * 1448 *@rx_tlv_hdr: start address of rx_pkt_tlvs 1449 * 1450 * Return: true if RX_MPDU_START is valied, else false. 1451 */ 1452 static uint8_t hal_rx_mpdu_start_tlv_tag_valid_6490(void *rx_tlv_hdr) 1453 { 1454 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)rx_tlv_hdr; 1455 uint32_t tlv_tag; 1456 1457 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(&rx_desc->mpdu_start_tlv); 1458 1459 return tlv_tag == WIFIRX_MPDU_START_E ? true : false; 1460 } 1461 1462 /** 1463 * hal_reo_set_err_dst_remap_6490(): Function to set REO error destination 1464 * ring remap register 1465 * @hal_soc: Pointer to hal_soc 1466 * 1467 * Return: none. 1468 */ 1469 static void 1470 hal_reo_set_err_dst_remap_6490(void *hal_soc) 1471 { 1472 /* 1473 * Set REO error 2k jump (error code 5) / OOR (error code 7) 1474 * frame routed to REO2TCL ring. 1475 */ 1476 uint32_t dst_remap_ix0 = 1477 HAL_REO_ERR_REMAP_IX0(REO_REMAP_RELEASE, 0) | 1478 HAL_REO_ERR_REMAP_IX0(REO_REMAP_RELEASE, 1) | 1479 HAL_REO_ERR_REMAP_IX0(REO_REMAP_RELEASE, 2) | 1480 HAL_REO_ERR_REMAP_IX0(REO_REMAP_RELEASE, 3) | 1481 HAL_REO_ERR_REMAP_IX0(REO_REMAP_RELEASE, 4) | 1482 HAL_REO_ERR_REMAP_IX0(REO_REMAP_TCL, 5) | 1483 HAL_REO_ERR_REMAP_IX0(REO_REMAP_TCL, 6) | 1484 HAL_REO_ERR_REMAP_IX0(REO_REMAP_TCL, 7); 1485 1486 uint32_t dst_remap_ix1 = 1487 HAL_REO_ERR_REMAP_IX1(REO_REMAP_RELEASE, 14) | 1488 HAL_REO_ERR_REMAP_IX1(REO_REMAP_RELEASE, 13) | 1489 HAL_REO_ERR_REMAP_IX1(REO_REMAP_RELEASE, 12) | 1490 HAL_REO_ERR_REMAP_IX1(REO_REMAP_RELEASE, 11) | 1491 HAL_REO_ERR_REMAP_IX1(REO_REMAP_RELEASE, 10) | 1492 HAL_REO_ERR_REMAP_IX1(REO_REMAP_RELEASE, 9) | 1493 HAL_REO_ERR_REMAP_IX1(REO_REMAP_TCL, 8); 1494 1495 HAL_REG_WRITE(hal_soc, 1496 HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ADDR( 1497 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1498 dst_remap_ix0); 1499 1500 hal_info("HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0 0x%x", 1501 HAL_REG_READ( 1502 hal_soc, 1503 HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ADDR( 1504 SEQ_WCSS_UMAC_REO_REG_OFFSET))); 1505 1506 HAL_REG_WRITE(hal_soc, 1507 HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ADDR( 1508 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1509 dst_remap_ix1); 1510 1511 hal_info("HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1 0x%x", 1512 HAL_REG_READ( 1513 hal_soc, 1514 HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ADDR( 1515 SEQ_WCSS_UMAC_REO_REG_OFFSET))); 1516 } 1517 1518 /** 1519 * hal_rx_flow_setup_fse_6490() - Setup a flow search entry in HW FST 1520 * @fst: Pointer to the Rx Flow Search Table 1521 * @table_offset: offset into the table where the flow is to be setup 1522 * @flow: Flow Parameters 1523 * 1524 * Flow table entry fields are updated in host byte order, little endian order. 1525 * 1526 * Return: Success/Failure 1527 */ 1528 static void * 1529 hal_rx_flow_setup_fse_6490(uint8_t *rx_fst, uint32_t table_offset, 1530 uint8_t *rx_flow) 1531 { 1532 struct hal_rx_fst *fst = (struct hal_rx_fst *)rx_fst; 1533 struct hal_rx_flow *flow = (struct hal_rx_flow *)rx_flow; 1534 uint8_t *fse; 1535 bool fse_valid; 1536 1537 if (table_offset >= fst->max_entries) { 1538 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR, 1539 "HAL FSE table offset %u exceeds max entries %u", 1540 table_offset, fst->max_entries); 1541 return NULL; 1542 } 1543 1544 fse = (uint8_t *)fst->base_vaddr + 1545 (table_offset * HAL_RX_FST_ENTRY_SIZE); 1546 1547 fse_valid = HAL_GET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, VALID); 1548 1549 if (fse_valid) { 1550 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_DEBUG, 1551 "HAL FSE %pK already valid", fse); 1552 return NULL; 1553 } 1554 1555 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_0, SRC_IP_127_96) = 1556 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_0, SRC_IP_127_96, 1557 (flow->tuple_info.src_ip_127_96)); 1558 1559 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_1, SRC_IP_95_64) = 1560 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_1, SRC_IP_95_64, 1561 (flow->tuple_info.src_ip_95_64)); 1562 1563 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_2, SRC_IP_63_32) = 1564 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_2, SRC_IP_63_32, 1565 (flow->tuple_info.src_ip_63_32)); 1566 1567 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_3, SRC_IP_31_0) = 1568 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_3, SRC_IP_31_0, 1569 (flow->tuple_info.src_ip_31_0)); 1570 1571 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_4, DEST_IP_127_96) = 1572 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_4, DEST_IP_127_96, 1573 (flow->tuple_info.dest_ip_127_96)); 1574 1575 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_5, DEST_IP_95_64) = 1576 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_5, DEST_IP_95_64, 1577 (flow->tuple_info.dest_ip_95_64)); 1578 1579 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_6, DEST_IP_63_32) = 1580 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_6, DEST_IP_63_32, 1581 (flow->tuple_info.dest_ip_63_32)); 1582 1583 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_7, DEST_IP_31_0) = 1584 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_7, DEST_IP_31_0, 1585 (flow->tuple_info.dest_ip_31_0)); 1586 1587 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, DEST_PORT); 1588 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, DEST_PORT) |= 1589 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_8, DEST_PORT, 1590 (flow->tuple_info.dest_port)); 1591 1592 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, SRC_PORT); 1593 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, SRC_PORT) |= 1594 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_8, SRC_PORT, 1595 (flow->tuple_info.src_port)); 1596 1597 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, L4_PROTOCOL); 1598 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, L4_PROTOCOL) |= 1599 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, L4_PROTOCOL, 1600 flow->tuple_info.l4_protocol); 1601 1602 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_HANDLER); 1603 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_HANDLER) |= 1604 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_HANDLER, 1605 flow->reo_destination_handler); 1606 1607 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, VALID); 1608 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, VALID) |= 1609 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, VALID, 1); 1610 1611 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_10, METADATA); 1612 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_10, METADATA) = 1613 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_10, METADATA, 1614 (flow->fse_metadata)); 1615 1616 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_INDICATION); 1617 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_INDICATION) |= 1618 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, 1619 REO_DESTINATION_INDICATION, 1620 flow->reo_destination_indication); 1621 1622 /* Reset all the other fields in FSE */ 1623 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, RESERVED_9); 1624 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, MSDU_DROP); 1625 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_11, MSDU_COUNT); 1626 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_12, MSDU_BYTE_COUNT); 1627 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_13, TIMESTAMP); 1628 1629 return fse; 1630 } 1631 1632 static 1633 void hal_compute_reo_remap_ix2_ix3_6490(uint32_t *ring, uint32_t num_rings, 1634 uint32_t *remap1, uint32_t *remap2) 1635 { 1636 switch (num_rings) { 1637 case 3: 1638 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 1639 HAL_REO_REMAP_IX2(ring[1], 17) | 1640 HAL_REO_REMAP_IX2(ring[2], 18) | 1641 HAL_REO_REMAP_IX2(ring[0], 19) | 1642 HAL_REO_REMAP_IX2(ring[1], 20) | 1643 HAL_REO_REMAP_IX2(ring[2], 21) | 1644 HAL_REO_REMAP_IX2(ring[0], 22) | 1645 HAL_REO_REMAP_IX2(ring[1], 23); 1646 1647 *remap2 = HAL_REO_REMAP_IX3(ring[2], 24) | 1648 HAL_REO_REMAP_IX3(ring[0], 25) | 1649 HAL_REO_REMAP_IX3(ring[1], 26) | 1650 HAL_REO_REMAP_IX3(ring[2], 27) | 1651 HAL_REO_REMAP_IX3(ring[0], 28) | 1652 HAL_REO_REMAP_IX3(ring[1], 29) | 1653 HAL_REO_REMAP_IX3(ring[2], 30) | 1654 HAL_REO_REMAP_IX3(ring[0], 31); 1655 break; 1656 case 4: 1657 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 1658 HAL_REO_REMAP_IX2(ring[1], 17) | 1659 HAL_REO_REMAP_IX2(ring[2], 18) | 1660 HAL_REO_REMAP_IX2(ring[3], 19) | 1661 HAL_REO_REMAP_IX2(ring[0], 20) | 1662 HAL_REO_REMAP_IX2(ring[1], 21) | 1663 HAL_REO_REMAP_IX2(ring[2], 22) | 1664 HAL_REO_REMAP_IX2(ring[3], 23); 1665 1666 *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) | 1667 HAL_REO_REMAP_IX3(ring[1], 25) | 1668 HAL_REO_REMAP_IX3(ring[2], 26) | 1669 HAL_REO_REMAP_IX3(ring[3], 27) | 1670 HAL_REO_REMAP_IX3(ring[0], 28) | 1671 HAL_REO_REMAP_IX3(ring[1], 29) | 1672 HAL_REO_REMAP_IX3(ring[2], 30) | 1673 HAL_REO_REMAP_IX3(ring[3], 31); 1674 break; 1675 } 1676 } 1677 1678 static void hal_hw_txrx_ops_attach_qca6490(struct hal_soc *hal_soc) 1679 { 1680 /* init and setup */ 1681 hal_soc->ops->hal_srng_dst_hw_init = hal_srng_dst_hw_init_generic; 1682 hal_soc->ops->hal_srng_src_hw_init = hal_srng_src_hw_init_generic; 1683 hal_soc->ops->hal_get_hw_hptp = hal_get_hw_hptp_generic; 1684 hal_soc->ops->hal_reo_setup = hal_reo_setup_generic_li; 1685 hal_soc->ops->hal_get_window_address = hal_get_window_address_6490; 1686 hal_soc->ops->hal_reo_set_err_dst_remap = 1687 hal_reo_set_err_dst_remap_6490; 1688 1689 /* tx */ 1690 hal_soc->ops->hal_tx_desc_set_dscp_tid_table_id = 1691 hal_tx_desc_set_dscp_tid_table_id_6490; 1692 hal_soc->ops->hal_tx_set_dscp_tid_map = hal_tx_set_dscp_tid_map_6490; 1693 hal_soc->ops->hal_tx_update_dscp_tid = hal_tx_update_dscp_tid_6490; 1694 hal_soc->ops->hal_tx_desc_set_lmac_id = hal_tx_desc_set_lmac_id_6490; 1695 hal_soc->ops->hal_tx_desc_set_buf_addr = 1696 hal_tx_desc_set_buf_addr_generic_li; 1697 hal_soc->ops->hal_tx_desc_set_search_type = 1698 hal_tx_desc_set_search_type_generic_li; 1699 hal_soc->ops->hal_tx_desc_set_search_index = 1700 hal_tx_desc_set_search_index_generic_li; 1701 hal_soc->ops->hal_tx_desc_set_cache_set_num = 1702 hal_tx_desc_set_cache_set_num_generic_li; 1703 hal_soc->ops->hal_tx_comp_get_status = 1704 hal_tx_comp_get_status_generic_li; 1705 hal_soc->ops->hal_tx_comp_get_release_reason = 1706 hal_tx_comp_get_release_reason_generic_li; 1707 hal_soc->ops->hal_get_wbm_internal_error = 1708 hal_get_wbm_internal_error_generic_li; 1709 hal_soc->ops->hal_tx_desc_set_mesh_en = hal_tx_desc_set_mesh_en_6490; 1710 hal_soc->ops->hal_tx_init_cmd_credit_ring = 1711 hal_tx_init_cmd_credit_ring_6490; 1712 1713 /* rx */ 1714 hal_soc->ops->hal_rx_msdu_start_nss_get = 1715 hal_rx_msdu_start_nss_get_6490; 1716 hal_soc->ops->hal_rx_mon_hw_desc_get_mpdu_status = 1717 hal_rx_mon_hw_desc_get_mpdu_status_6490; 1718 hal_soc->ops->hal_rx_get_tlv = hal_rx_get_tlv_6490; 1719 hal_soc->ops->hal_rx_proc_phyrx_other_receive_info_tlv = 1720 hal_rx_proc_phyrx_other_receive_info_tlv_6490; 1721 hal_soc->ops->hal_rx_dump_msdu_start_tlv = 1722 hal_rx_dump_msdu_start_tlv_6490; 1723 hal_soc->ops->hal_rx_dump_msdu_end_tlv = hal_rx_dump_msdu_end_tlv_6490; 1724 hal_soc->ops->hal_get_link_desc_size = hal_get_link_desc_size_6490; 1725 hal_soc->ops->hal_rx_mpdu_start_tid_get = 1726 hal_rx_mpdu_start_tid_get_6490; 1727 hal_soc->ops->hal_rx_msdu_start_reception_type_get = 1728 hal_rx_msdu_start_reception_type_get_6490; 1729 hal_soc->ops->hal_rx_msdu_end_da_idx_get = 1730 hal_rx_msdu_end_da_idx_get_6490; 1731 hal_soc->ops->hal_rx_msdu_desc_info_get_ptr = 1732 hal_rx_msdu_desc_info_get_ptr_6490; 1733 hal_soc->ops->hal_rx_link_desc_msdu0_ptr = 1734 hal_rx_link_desc_msdu0_ptr_6490; 1735 hal_soc->ops->hal_reo_status_get_header = 1736 hal_reo_status_get_header_6490; 1737 hal_soc->ops->hal_rx_status_get_tlv_info = 1738 hal_rx_status_get_tlv_info_generic_li; 1739 hal_soc->ops->hal_rx_wbm_err_info_get = 1740 hal_rx_wbm_err_info_get_generic_li; 1741 hal_soc->ops->hal_rx_dump_mpdu_start_tlv = 1742 hal_rx_dump_mpdu_start_tlv_generic_li; 1743 1744 hal_soc->ops->hal_tx_set_pcp_tid_map = 1745 hal_tx_set_pcp_tid_map_generic_li; 1746 hal_soc->ops->hal_tx_update_pcp_tid_map = 1747 hal_tx_update_pcp_tid_generic_li; 1748 hal_soc->ops->hal_tx_set_tidmap_prty = 1749 hal_tx_update_tidmap_prty_generic_li; 1750 hal_soc->ops->hal_rx_get_rx_fragment_number = 1751 hal_rx_get_rx_fragment_number_6490; 1752 hal_soc->ops->hal_rx_msdu_end_da_is_mcbc_get = 1753 hal_rx_msdu_end_da_is_mcbc_get_6490; 1754 hal_soc->ops->hal_rx_msdu_end_sa_is_valid_get = 1755 hal_rx_msdu_end_sa_is_valid_get_6490; 1756 hal_soc->ops->hal_rx_msdu_end_sa_idx_get = 1757 hal_rx_msdu_end_sa_idx_get_6490; 1758 hal_soc->ops->hal_rx_desc_is_first_msdu = 1759 hal_rx_desc_is_first_msdu_6490; 1760 hal_soc->ops->hal_rx_msdu_end_l3_hdr_padding_get = 1761 hal_rx_msdu_end_l3_hdr_padding_get_6490; 1762 hal_soc->ops->hal_rx_encryption_info_valid = 1763 hal_rx_encryption_info_valid_6490; 1764 hal_soc->ops->hal_rx_print_pn = hal_rx_print_pn_6490; 1765 hal_soc->ops->hal_rx_msdu_end_first_msdu_get = 1766 hal_rx_msdu_end_first_msdu_get_6490; 1767 hal_soc->ops->hal_rx_msdu_end_da_is_valid_get = 1768 hal_rx_msdu_end_da_is_valid_get_6490; 1769 hal_soc->ops->hal_rx_msdu_end_last_msdu_get = 1770 hal_rx_msdu_end_last_msdu_get_6490; 1771 hal_soc->ops->hal_rx_get_mpdu_mac_ad4_valid = 1772 hal_rx_get_mpdu_mac_ad4_valid_6490; 1773 hal_soc->ops->hal_rx_mpdu_start_sw_peer_id_get = 1774 hal_rx_mpdu_start_sw_peer_id_get_6490; 1775 hal_soc->ops->hal_rx_mpdu_get_to_ds = hal_rx_mpdu_get_to_ds_6490; 1776 hal_soc->ops->hal_rx_mpdu_get_fr_ds = hal_rx_mpdu_get_fr_ds_6490; 1777 hal_soc->ops->hal_rx_get_mpdu_frame_control_valid = 1778 hal_rx_get_mpdu_frame_control_valid_6490; 1779 hal_soc->ops->hal_rx_mpdu_get_addr1 = hal_rx_mpdu_get_addr1_6490; 1780 hal_soc->ops->hal_rx_mpdu_get_addr2 = hal_rx_mpdu_get_addr2_6490; 1781 hal_soc->ops->hal_rx_mpdu_get_addr3 = hal_rx_mpdu_get_addr3_6490; 1782 hal_soc->ops->hal_rx_mpdu_get_addr4 = hal_rx_mpdu_get_addr4_6490; 1783 hal_soc->ops->hal_rx_get_mpdu_sequence_control_valid = 1784 hal_rx_get_mpdu_sequence_control_valid_6490; 1785 hal_soc->ops->hal_rx_is_unicast = hal_rx_is_unicast_6490; 1786 hal_soc->ops->hal_rx_tid_get = hal_rx_tid_get_6490; 1787 hal_soc->ops->hal_rx_hw_desc_get_ppduid_get = 1788 hal_rx_hw_desc_get_ppduid_get_6490; 1789 hal_soc->ops->hal_rx_msdu0_buffer_addr_lsb = 1790 hal_rx_msdu0_buffer_addr_lsb_6490; 1791 hal_soc->ops->hal_rx_msdu_desc_info_ptr_get = 1792 hal_rx_msdu_desc_info_ptr_get_6490; 1793 hal_soc->ops->hal_ent_mpdu_desc_info = hal_ent_mpdu_desc_info_6490; 1794 hal_soc->ops->hal_dst_mpdu_desc_info = hal_dst_mpdu_desc_info_6490; 1795 hal_soc->ops->hal_rx_get_fc_valid = hal_rx_get_fc_valid_6490; 1796 hal_soc->ops->hal_rx_get_to_ds_flag = hal_rx_get_to_ds_flag_6490; 1797 hal_soc->ops->hal_rx_get_mac_addr2_valid = 1798 hal_rx_get_mac_addr2_valid_6490; 1799 hal_soc->ops->hal_rx_get_filter_category = 1800 hal_rx_get_filter_category_6490; 1801 hal_soc->ops->hal_rx_get_ppdu_id = hal_rx_get_ppdu_id_6490; 1802 hal_soc->ops->hal_reo_config = hal_reo_config_6490; 1803 hal_soc->ops->hal_rx_msdu_flow_idx_get = hal_rx_msdu_flow_idx_get_6490; 1804 hal_soc->ops->hal_rx_msdu_flow_idx_invalid = 1805 hal_rx_msdu_flow_idx_invalid_6490; 1806 hal_soc->ops->hal_rx_msdu_flow_idx_timeout = 1807 hal_rx_msdu_flow_idx_timeout_6490; 1808 hal_soc->ops->hal_rx_msdu_fse_metadata_get = 1809 hal_rx_msdu_fse_metadata_get_6490; 1810 hal_soc->ops->hal_rx_msdu_cce_metadata_get = 1811 hal_rx_msdu_cce_metadata_get_6490; 1812 hal_soc->ops->hal_rx_msdu_get_flow_params = 1813 hal_rx_msdu_get_flow_params_6490; 1814 hal_soc->ops->hal_rx_tlv_get_tcp_chksum = 1815 hal_rx_tlv_get_tcp_chksum_6490; 1816 hal_soc->ops->hal_rx_get_rx_sequence = hal_rx_get_rx_sequence_6490; 1817 #if defined(QCA_WIFI_QCA6490) && defined(WLAN_CFR_ENABLE) && \ 1818 defined(WLAN_ENH_CFR_ENABLE) 1819 hal_soc->ops->hal_rx_get_bb_info = hal_rx_get_bb_info_6490; 1820 hal_soc->ops->hal_rx_get_rtt_info = hal_rx_get_rtt_info_6490; 1821 #endif 1822 /* rx - msdu end fast path info fields */ 1823 hal_soc->ops->hal_rx_msdu_packet_metadata_get = 1824 hal_rx_msdu_packet_metadata_get_generic_li; 1825 hal_soc->ops->hal_rx_get_fisa_cumulative_l4_checksum = 1826 hal_rx_get_fisa_cumulative_l4_checksum_6490; 1827 hal_soc->ops->hal_rx_get_fisa_cumulative_ip_length = 1828 hal_rx_get_fisa_cumulative_ip_length_6490; 1829 hal_soc->ops->hal_rx_get_udp_proto = hal_rx_get_udp_proto_6490; 1830 hal_soc->ops->hal_rx_get_fisa_flow_agg_continuation = 1831 hal_rx_get_flow_agg_continuation_6490; 1832 hal_soc->ops->hal_rx_get_fisa_flow_agg_count = 1833 hal_rx_get_flow_agg_count_6490; 1834 hal_soc->ops->hal_rx_get_fisa_timeout = hal_rx_get_fisa_timeout_6490; 1835 hal_soc->ops->hal_rx_mpdu_start_tlv_tag_valid = 1836 hal_rx_mpdu_start_tlv_tag_valid_6490; 1837 1838 /* rx - TLV struct offsets */ 1839 hal_soc->ops->hal_rx_msdu_end_offset_get = 1840 hal_rx_msdu_end_offset_get_generic; 1841 hal_soc->ops->hal_rx_attn_offset_get = hal_rx_attn_offset_get_generic; 1842 hal_soc->ops->hal_rx_msdu_start_offset_get = 1843 hal_rx_msdu_start_offset_get_generic; 1844 hal_soc->ops->hal_rx_mpdu_start_offset_get = 1845 hal_rx_mpdu_start_offset_get_generic; 1846 hal_soc->ops->hal_rx_mpdu_end_offset_get = 1847 hal_rx_mpdu_end_offset_get_generic; 1848 #ifndef NO_RX_PKT_HDR_TLV 1849 hal_soc->ops->hal_rx_pkt_tlv_offset_get = 1850 hal_rx_pkt_tlv_offset_get_generic; 1851 #endif 1852 hal_soc->ops->hal_rx_flow_setup_fse = hal_rx_flow_setup_fse_6490; 1853 hal_soc->ops->hal_compute_reo_remap_ix2_ix3 = 1854 hal_compute_reo_remap_ix2_ix3_6490; 1855 hal_soc->ops->hal_rx_msdu_get_reo_destination_indication = 1856 hal_rx_msdu_get_reo_destination_indication_6490; 1857 hal_soc->ops->hal_setup_link_idle_list = 1858 hal_setup_link_idle_list_generic_li; 1859 }; 1860 1861 struct hal_hw_srng_config hw_srng_table_6490[] = { 1862 /* TODO: max_rings can populated by querying HW capabilities */ 1863 { /* REO_DST */ 1864 .start_ring_id = HAL_SRNG_REO2SW1, 1865 .max_rings = 4, 1866 .entry_size = sizeof(struct reo_destination_ring) >> 2, 1867 .lmac_ring = FALSE, 1868 .ring_dir = HAL_SRNG_DST_RING, 1869 .reg_start = { 1870 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR( 1871 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1872 HWIO_REO_R2_REO2SW1_RING_HP_ADDR( 1873 SEQ_WCSS_UMAC_REO_REG_OFFSET) 1874 }, 1875 .reg_size = { 1876 HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(0) - 1877 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(0), 1878 HWIO_REO_R2_REO2SW2_RING_HP_ADDR(0) - 1879 HWIO_REO_R2_REO2SW1_RING_HP_ADDR(0), 1880 }, 1881 .max_size = 1882 HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_BMSK >> 1883 HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_SHFT, 1884 }, 1885 { /* REO_EXCEPTION */ 1886 /* Designating REO2TCL ring as exception ring. This ring is 1887 * similar to other REO2SW rings though it is named as REO2TCL. 1888 * Any of theREO2SW rings can be used as exception ring. 1889 */ 1890 .start_ring_id = HAL_SRNG_REO2TCL, 1891 .max_rings = 1, 1892 .entry_size = sizeof(struct reo_destination_ring) >> 2, 1893 .lmac_ring = FALSE, 1894 .ring_dir = HAL_SRNG_DST_RING, 1895 .reg_start = { 1896 HWIO_REO_R0_REO2TCL_RING_BASE_LSB_ADDR( 1897 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1898 HWIO_REO_R2_REO2TCL_RING_HP_ADDR( 1899 SEQ_WCSS_UMAC_REO_REG_OFFSET) 1900 }, 1901 /* Single ring - provide ring size if multiple rings of this 1902 * type are supported 1903 */ 1904 .reg_size = {}, 1905 .max_size = 1906 HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_BMSK >> 1907 HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_SHFT, 1908 }, 1909 { /* REO_REINJECT */ 1910 .start_ring_id = HAL_SRNG_SW2REO, 1911 .max_rings = 1, 1912 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 1913 .lmac_ring = FALSE, 1914 .ring_dir = HAL_SRNG_SRC_RING, 1915 .reg_start = { 1916 HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR( 1917 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1918 HWIO_REO_R2_SW2REO_RING_HP_ADDR( 1919 SEQ_WCSS_UMAC_REO_REG_OFFSET) 1920 }, 1921 /* Single ring - provide ring size if multiple rings of this 1922 * type are supported 1923 */ 1924 .reg_size = {}, 1925 .max_size = HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_BMSK >> 1926 HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_SHFT, 1927 }, 1928 { /* REO_CMD */ 1929 .start_ring_id = HAL_SRNG_REO_CMD, 1930 .max_rings = 1, 1931 .entry_size = (sizeof(struct tlv_32_hdr) + 1932 sizeof(struct reo_get_queue_stats)) >> 2, 1933 .lmac_ring = FALSE, 1934 .ring_dir = HAL_SRNG_SRC_RING, 1935 .reg_start = { 1936 HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR( 1937 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1938 HWIO_REO_R2_REO_CMD_RING_HP_ADDR( 1939 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1940 }, 1941 /* Single ring - provide ring size if multiple rings of this 1942 * type are supported 1943 */ 1944 .reg_size = {}, 1945 .max_size = 1946 HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_BMSK >> 1947 HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_SHFT, 1948 }, 1949 { /* REO_STATUS */ 1950 .start_ring_id = HAL_SRNG_REO_STATUS, 1951 .max_rings = 1, 1952 .entry_size = (sizeof(struct tlv_32_hdr) + 1953 sizeof(struct reo_get_queue_stats_status)) >> 2, 1954 .lmac_ring = FALSE, 1955 .ring_dir = HAL_SRNG_DST_RING, 1956 .reg_start = { 1957 HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR( 1958 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1959 HWIO_REO_R2_REO_STATUS_RING_HP_ADDR( 1960 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1961 }, 1962 /* Single ring - provide ring size if multiple rings of this 1963 * type are supported 1964 */ 1965 .reg_size = {}, 1966 .max_size = 1967 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> 1968 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, 1969 }, 1970 { /* TCL_DATA */ 1971 .start_ring_id = HAL_SRNG_SW2TCL1, 1972 .max_rings = 3, 1973 .entry_size = (sizeof(struct tlv_32_hdr) + 1974 sizeof(struct tcl_data_cmd)) >> 2, 1975 .lmac_ring = FALSE, 1976 .ring_dir = HAL_SRNG_SRC_RING, 1977 .reg_start = { 1978 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR( 1979 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1980 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR( 1981 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1982 }, 1983 .reg_size = { 1984 HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(0) - 1985 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(0), 1986 HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(0) - 1987 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(0), 1988 }, 1989 .max_size = 1990 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK >> 1991 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT, 1992 }, 1993 { /* TCL_CMD */ 1994 .start_ring_id = HAL_SRNG_SW2TCL_CMD, 1995 .max_rings = 1, 1996 .entry_size = (sizeof(struct tlv_32_hdr) + 1997 sizeof(struct tcl_gse_cmd)) >> 2, 1998 .lmac_ring = FALSE, 1999 .ring_dir = HAL_SRNG_SRC_RING, 2000 .reg_start = { 2001 HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_ADDR( 2002 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 2003 HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_ADDR( 2004 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 2005 }, 2006 /* Single ring - provide ring size if multiple rings of this 2007 * type are supported 2008 */ 2009 .reg_size = {}, 2010 .max_size = 2011 HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_SIZE_BMSK >> 2012 HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_SIZE_SHFT, 2013 }, 2014 { /* TCL_STATUS */ 2015 .start_ring_id = HAL_SRNG_TCL_STATUS, 2016 .max_rings = 1, 2017 .entry_size = (sizeof(struct tlv_32_hdr) + 2018 sizeof(struct tcl_status_ring)) >> 2, 2019 .lmac_ring = FALSE, 2020 .ring_dir = HAL_SRNG_DST_RING, 2021 .reg_start = { 2022 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR( 2023 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 2024 HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR( 2025 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 2026 }, 2027 /* Single ring - provide ring size if multiple rings of this 2028 * type are supported 2029 */ 2030 .reg_size = {}, 2031 .max_size = 2032 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_BMSK >> 2033 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_SHFT, 2034 }, 2035 { /* CE_SRC */ 2036 .start_ring_id = HAL_SRNG_CE_0_SRC, 2037 .max_rings = 12, 2038 .entry_size = sizeof(struct ce_src_desc) >> 2, 2039 .lmac_ring = FALSE, 2040 .ring_dir = HAL_SRNG_SRC_RING, 2041 .reg_start = { 2042 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR( 2043 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET), 2044 HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR( 2045 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET), 2046 }, 2047 .reg_size = { 2048 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET - 2049 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET, 2050 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET - 2051 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET, 2052 }, 2053 .max_size = 2054 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >> 2055 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT, 2056 }, 2057 { /* CE_DST */ 2058 .start_ring_id = HAL_SRNG_CE_0_DST, 2059 .max_rings = 12, 2060 .entry_size = 8 >> 2, 2061 /*TODO: entry_size above should actually be 2062 * sizeof(struct ce_dst_desc) >> 2, but couldn't find definition 2063 * of struct ce_dst_desc in HW header files 2064 */ 2065 .lmac_ring = FALSE, 2066 .ring_dir = HAL_SRNG_SRC_RING, 2067 .reg_start = { 2068 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR( 2069 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 2070 HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR( 2071 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 2072 }, 2073 .reg_size = { 2074 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 2075 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 2076 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 2077 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 2078 }, 2079 .max_size = 2080 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >> 2081 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT, 2082 }, 2083 { /* CE_DST_STATUS */ 2084 .start_ring_id = HAL_SRNG_CE_0_DST_STATUS, 2085 .max_rings = 12, 2086 .entry_size = sizeof(struct ce_stat_desc) >> 2, 2087 .lmac_ring = FALSE, 2088 .ring_dir = HAL_SRNG_DST_RING, 2089 .reg_start = { 2090 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR( 2091 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 2092 HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR( 2093 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 2094 }, 2095 /* TODO: check destination status ring registers */ 2096 .reg_size = { 2097 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 2098 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 2099 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 2100 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 2101 }, 2102 .max_size = 2103 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> 2104 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, 2105 }, 2106 { /* WBM_IDLE_LINK */ 2107 .start_ring_id = HAL_SRNG_WBM_IDLE_LINK, 2108 .max_rings = 1, 2109 .entry_size = sizeof(struct wbm_link_descriptor_ring) >> 2, 2110 .lmac_ring = FALSE, 2111 .ring_dir = HAL_SRNG_SRC_RING, 2112 .reg_start = { 2113 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2114 HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2115 }, 2116 /* Single ring - provide ring size if multiple rings of this 2117 * type are supported 2118 */ 2119 .reg_size = {}, 2120 .max_size = 2121 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_BMSK >> 2122 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_SHFT, 2123 }, 2124 { /* SW2WBM_RELEASE */ 2125 .start_ring_id = HAL_SRNG_WBM_SW_RELEASE, 2126 .max_rings = 1, 2127 .entry_size = sizeof(struct wbm_release_ring) >> 2, 2128 .lmac_ring = FALSE, 2129 .ring_dir = HAL_SRNG_SRC_RING, 2130 .reg_start = { 2131 HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2132 HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2133 }, 2134 /* Single ring - provide ring size if multiple rings of this 2135 * type are supported 2136 */ 2137 .reg_size = {}, 2138 .max_size = 2139 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> 2140 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, 2141 }, 2142 { /* WBM2SW_RELEASE */ 2143 .start_ring_id = HAL_SRNG_WBM2SW0_RELEASE, 2144 #ifdef IPA_WDI3_TX_TWO_PIPES 2145 .max_rings = 5, 2146 #else 2147 .max_rings = 4, 2148 #endif 2149 .entry_size = sizeof(struct wbm_release_ring) >> 2, 2150 .lmac_ring = FALSE, 2151 .ring_dir = HAL_SRNG_DST_RING, 2152 .reg_start = { 2153 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2154 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2155 }, 2156 .reg_size = { 2157 HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) - 2158 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2159 HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) - 2160 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2161 }, 2162 .max_size = 2163 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> 2164 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, 2165 }, 2166 { /* RXDMA_BUF */ 2167 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA0_BUF0, 2168 #ifdef IPA_OFFLOAD 2169 .max_rings = 3, 2170 #else 2171 .max_rings = 2, 2172 #endif 2173 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 2174 .lmac_ring = TRUE, 2175 .ring_dir = HAL_SRNG_SRC_RING, 2176 /* reg_start is not set because LMAC rings are not accessed 2177 * from host 2178 */ 2179 .reg_start = {}, 2180 .reg_size = {}, 2181 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2182 }, 2183 { /* RXDMA_DST */ 2184 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW0, 2185 .max_rings = 1, 2186 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 2187 .lmac_ring = TRUE, 2188 .ring_dir = HAL_SRNG_DST_RING, 2189 /* reg_start is not set because LMAC rings are not accessed 2190 * from host 2191 */ 2192 .reg_start = {}, 2193 .reg_size = {}, 2194 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2195 }, 2196 { /* RXDMA_MONITOR_BUF */ 2197 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA2_BUF, 2198 .max_rings = 1, 2199 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 2200 .lmac_ring = TRUE, 2201 .ring_dir = HAL_SRNG_SRC_RING, 2202 /* reg_start is not set because LMAC rings are not accessed 2203 * from host 2204 */ 2205 .reg_start = {}, 2206 .reg_size = {}, 2207 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2208 }, 2209 { /* RXDMA_MONITOR_STATUS */ 2210 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_STATBUF, 2211 .max_rings = 1, 2212 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 2213 .lmac_ring = TRUE, 2214 .ring_dir = HAL_SRNG_SRC_RING, 2215 /* reg_start is not set because LMAC rings are not accessed 2216 * from host 2217 */ 2218 .reg_start = {}, 2219 .reg_size = {}, 2220 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2221 }, 2222 { /* RXDMA_MONITOR_DST */ 2223 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW1, 2224 .max_rings = 1, 2225 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 2226 .lmac_ring = TRUE, 2227 .ring_dir = HAL_SRNG_DST_RING, 2228 /* reg_start is not set because LMAC rings are not accessed 2229 * from host 2230 */ 2231 .reg_start = {}, 2232 .reg_size = {}, 2233 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2234 }, 2235 { /* RXDMA_MONITOR_DESC */ 2236 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_DESC, 2237 .max_rings = 1, 2238 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 2239 .lmac_ring = TRUE, 2240 .ring_dir = HAL_SRNG_SRC_RING, 2241 /* reg_start is not set because LMAC rings are not accessed 2242 * from host 2243 */ 2244 .reg_start = {}, 2245 .reg_size = {}, 2246 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2247 }, 2248 { /* DIR_BUF_RX_DMA_SRC */ 2249 .start_ring_id = HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING, 2250 /* 2251 * one ring is for spectral scan 2252 * the other is for cfr 2253 */ 2254 .max_rings = 2, 2255 .entry_size = 2, 2256 .lmac_ring = TRUE, 2257 .ring_dir = HAL_SRNG_SRC_RING, 2258 /* reg_start is not set because LMAC rings are not accessed 2259 * from host 2260 */ 2261 .reg_start = {}, 2262 .reg_size = {}, 2263 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2264 }, 2265 #ifdef WLAN_FEATURE_CIF_CFR 2266 { /* WIFI_POS_SRC */ 2267 .start_ring_id = HAL_SRNG_WIFI_POS_SRC_DMA_RING, 2268 .max_rings = 1, 2269 .entry_size = sizeof(wmi_oem_dma_buf_release_entry) >> 2, 2270 .lmac_ring = TRUE, 2271 .ring_dir = HAL_SRNG_SRC_RING, 2272 /* reg_start is not set because LMAC rings are not accessed 2273 * from host 2274 */ 2275 .reg_start = {}, 2276 .reg_size = {}, 2277 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2278 }, 2279 #endif 2280 { /* REO2PPE */ 0}, 2281 { /* PPE2TCL */ 0}, 2282 { /* PPE_RELEASE */ 0}, 2283 { /* TX_MONITOR_BUF */ 0}, 2284 { /* TX_MONITOR_DST */ 0}, 2285 { /* SW2RXDMA_NEW */ 0}, 2286 }; 2287 2288 /** 2289 * hal_qca6490_attach() - Attach 6490 target specific hal_soc ops, 2290 * offset and srng table 2291 */ 2292 void hal_qca6490_attach(struct hal_soc *hal_soc) 2293 { 2294 hal_soc->hw_srng_table = hw_srng_table_6490; 2295 2296 hal_srng_hw_reg_offset_init_generic(hal_soc); 2297 2298 hal_hw_txrx_default_ops_attach_li(hal_soc); 2299 hal_hw_txrx_ops_attach_qca6490(hal_soc); 2300 } 2301