1 /* 2 * Copyright (c) 2016-2020 The Linux Foundation. All rights reserved. 3 * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 #include "tcl_data_cmd.h" 20 #include "mac_tcl_reg_seq_hwioreg.h" 21 #include "phyrx_rssi_legacy.h" 22 #include "hal_hw_headers.h" 23 #include "hal_internal.h" 24 #include "cdp_txrx_mon_struct.h" 25 #include "qdf_trace.h" 26 #include "hal_rx.h" 27 #include "hal_tx.h" 28 #include "dp_types.h" 29 #include "hal_api_mon.h" 30 31 /** 32 * hal_tx_desc_set_dscp_tid_table_id_6390() - Sets DSCP to TID conversion 33 * table ID 34 * @desc: Handle to Tx Descriptor 35 * @id: DSCP to tid conversion table to be used for this frame 36 * 37 * Return: void 38 */ 39 static void hal_tx_desc_set_dscp_tid_table_id_6390(void *desc, uint8_t id) 40 { 41 HAL_SET_FLD(desc, TCL_DATA_CMD_5, 42 DSCP_TID_TABLE_NUM) |= 43 HAL_TX_SM(TCL_DATA_CMD_5, 44 DSCP_TID_TABLE_NUM, id); 45 } 46 47 #define DSCP_TID_TABLE_SIZE 24 48 #define NUM_WORDS_PER_DSCP_TID_TABLE (DSCP_TID_TABLE_SIZE / 4) 49 50 /** 51 * hal_tx_set_dscp_tid_map_6390() - Configure default DSCP to TID map table 52 * @soc: HAL SoC context 53 * @map: DSCP-TID mapping table 54 * @id: mapping table ID - 0-31 55 * 56 * DSCP are mapped to 8 TID values using TID values programmed 57 * in any of the 32 DSCP_TID_MAPS (id = 0-31). 58 * 59 * Return: none 60 */ 61 static void hal_tx_set_dscp_tid_map_6390(struct hal_soc *soc, uint8_t *map, 62 uint8_t id) 63 { 64 int i; 65 uint32_t addr, cmn_reg_addr; 66 uint32_t value = 0, regval; 67 uint8_t val[DSCP_TID_TABLE_SIZE], cnt = 0; 68 69 if (id >= HAL_MAX_HW_DSCP_TID_MAPS_11AX) 70 return; 71 72 cmn_reg_addr = HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR( 73 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET); 74 75 addr = HWIO_TCL_R0_DSCP_TID_MAP_n_ADDR( 76 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET, 77 id * NUM_WORDS_PER_DSCP_TID_TABLE); 78 79 /* Enable read/write access */ 80 regval = HAL_REG_READ(soc, cmn_reg_addr); 81 regval |= 82 (1 << HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_DSCP_TID_MAP_PROGRAM_EN_SHFT); 83 84 HAL_REG_WRITE(soc, cmn_reg_addr, regval); 85 86 /* Write 8 (24 bits) DSCP-TID mappings in each iteration */ 87 for (i = 0; i < 64; i += 8) { 88 value = (map[i] | 89 (map[i + 1] << 0x3) | 90 (map[i + 2] << 0x6) | 91 (map[i + 3] << 0x9) | 92 (map[i + 4] << 0xc) | 93 (map[i + 5] << 0xf) | 94 (map[i + 6] << 0x12) | 95 (map[i + 7] << 0x15)); 96 97 qdf_mem_copy(&val[cnt], &value, 3); 98 cnt += 3; 99 } 100 101 for (i = 0; i < DSCP_TID_TABLE_SIZE; i += 4) { 102 regval = *(uint32_t *)(val + i); 103 HAL_REG_WRITE(soc, addr, 104 (regval & HWIO_TCL_R0_DSCP_TID_MAP_n_RMSK)); 105 addr += 4; 106 } 107 108 /* Diasble read/write access */ 109 regval = HAL_REG_READ(soc, cmn_reg_addr); 110 regval &= 111 ~(HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_DSCP_TID_MAP_PROGRAM_EN_BMSK); 112 113 HAL_REG_WRITE(soc, cmn_reg_addr, regval); 114 } 115 116 /** 117 * hal_tx_update_dscp_tid_6390() - Update the dscp tid map table as updated 118 * by the user 119 * @soc: HAL SoC context 120 * @map: DSCP-TID mapping table 121 * @id : MAP ID 122 * @dscp: DSCP_TID map index 123 * 124 * Return: void 125 */ 126 static void hal_tx_update_dscp_tid_6390(struct hal_soc *soc, uint8_t tid, 127 uint8_t id, uint8_t dscp) 128 { 129 int index; 130 uint32_t addr; 131 uint32_t value; 132 uint32_t regval; 133 134 addr = HWIO_TCL_R0_DSCP_TID_MAP_n_ADDR( 135 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET, id); 136 137 index = dscp % HAL_TX_NUM_DSCP_PER_REGISTER; 138 addr += 4 * (dscp / HAL_TX_NUM_DSCP_PER_REGISTER); 139 value = tid << (HAL_TX_BITS_PER_TID * index); 140 141 regval = HAL_REG_READ(soc, addr); 142 regval &= ~(HAL_TX_TID_BITS_MASK << (HAL_TX_BITS_PER_TID * index)); 143 regval |= value; 144 145 HAL_REG_WRITE(soc, addr, (regval & HWIO_TCL_R0_DSCP_TID_MAP_n_RMSK)); 146 } 147 148 /** 149 * hal_tx_desc_set_lmac_id - Set the lmac_id value 150 * @desc: Handle to Tx Descriptor 151 * @lmac_id: mac Id to ast matching 152 * b00 – mac 0 153 * b01 – mac 1 154 * b10 – mac 2 155 * b11 – all macs (legacy HK way) 156 * 157 * Return: void 158 */ 159 static void hal_tx_desc_set_lmac_id_6390(void *desc, uint8_t lmac_id) 160 { 161 HAL_SET_FLD(desc, TCL_DATA_CMD_4, LMAC_ID) |= 162 HAL_TX_SM(TCL_DATA_CMD_4, LMAC_ID, lmac_id); 163 } 164 165 /** 166 * hal_tx_init_cmd_credit_ring_6390() - Initialize command/credit SRNG 167 * @hal_soc_hdl: Handle to HAL SoC structure 168 * @hal_srng: Handle to HAL SRNG structure 169 * 170 * Return: none 171 */ 172 static inline void hal_tx_init_cmd_credit_ring_6390(hal_soc_handle_t hal_soc_hdl, 173 hal_ring_handle_t hal_ring_hdl) 174 { 175 } 176