1 /* 2 * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 #include "qdf_util.h" 19 #include "qdf_types.h" 20 #include "qdf_lock.h" 21 #include "qdf_mem.h" 22 #include "qdf_nbuf.h" 23 #include "tcl_data_cmd.h" 24 #include "mac_tcl_reg_seq_hwioreg.h" 25 #include "phyrx_rssi_legacy.h" 26 #include "rx_msdu_start.h" 27 #include "tlv_tag_def.h" 28 #include "hal_hw_headers.h" 29 #include "hal_internal.h" 30 #include "cdp_txrx_mon_struct.h" 31 #include "qdf_trace.h" 32 #include "hal_li_rx.h" 33 #include "hal_tx.h" 34 #include "dp_types.h" 35 #include "hal_api_mon.h" 36 #include "phyrx_other_receive_info_ru_details.h" 37 38 #define HAL_RX_MPDU_GET_SEQUENCE_NUMBER(_rx_mpdu_info) \ 39 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 40 RX_MPDU_INFO_2_MPDU_SEQUENCE_NUMBER_OFFSET)), \ 41 RX_MPDU_INFO_2_MPDU_SEQUENCE_NUMBER_MASK, \ 42 RX_MPDU_INFO_2_MPDU_SEQUENCE_NUMBER_LSB)) 43 44 #define HAL_RX_MSDU_END_DA_IS_MCBC_GET(_rx_msdu_end) \ 45 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 46 RX_MSDU_END_5_DA_IS_MCBC_OFFSET)), \ 47 RX_MSDU_END_5_DA_IS_MCBC_MASK, \ 48 RX_MSDU_END_5_DA_IS_MCBC_LSB)) 49 50 #define HAL_RX_MSDU_END_SA_IS_VALID_GET(_rx_msdu_end) \ 51 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 52 RX_MSDU_END_5_SA_IS_VALID_OFFSET)), \ 53 RX_MSDU_END_5_SA_IS_VALID_MASK, \ 54 RX_MSDU_END_5_SA_IS_VALID_LSB)) 55 56 #define HAL_RX_MSDU_END_SA_IDX_GET(_rx_msdu_end) \ 57 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 58 RX_MSDU_END_13_SA_IDX_OFFSET)), \ 59 RX_MSDU_END_13_SA_IDX_MASK, \ 60 RX_MSDU_END_13_SA_IDX_LSB)) 61 62 #define HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(_rx_msdu_end) \ 63 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 64 RX_MSDU_END_5_L3_HEADER_PADDING_OFFSET)), \ 65 RX_MSDU_END_5_L3_HEADER_PADDING_MASK, \ 66 RX_MSDU_END_5_L3_HEADER_PADDING_LSB)) 67 68 #define HAL_RX_MPDU_ENCRYPTION_INFO_VALID(_rx_mpdu_info) \ 69 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 70 RX_MPDU_INFO_2_FRAME_ENCRYPTION_INFO_VALID_OFFSET)), \ 71 RX_MPDU_INFO_2_FRAME_ENCRYPTION_INFO_VALID_MASK, \ 72 RX_MPDU_INFO_2_FRAME_ENCRYPTION_INFO_VALID_LSB)) 73 74 #define HAL_RX_MPDU_PN_31_0_GET(_rx_mpdu_info) \ 75 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 76 RX_MPDU_INFO_4_PN_31_0_OFFSET)), \ 77 RX_MPDU_INFO_4_PN_31_0_MASK, \ 78 RX_MPDU_INFO_4_PN_31_0_LSB)) 79 80 #define HAL_RX_MPDU_PN_63_32_GET(_rx_mpdu_info) \ 81 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 82 RX_MPDU_INFO_5_PN_63_32_OFFSET)), \ 83 RX_MPDU_INFO_5_PN_63_32_MASK, \ 84 RX_MPDU_INFO_5_PN_63_32_LSB)) 85 86 #define HAL_RX_MPDU_PN_95_64_GET(_rx_mpdu_info) \ 87 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 88 RX_MPDU_INFO_6_PN_95_64_OFFSET)), \ 89 RX_MPDU_INFO_6_PN_95_64_MASK, \ 90 RX_MPDU_INFO_6_PN_95_64_LSB)) 91 92 #define HAL_RX_MPDU_PN_127_96_GET(_rx_mpdu_info) \ 93 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 94 RX_MPDU_INFO_7_PN_127_96_OFFSET)), \ 95 RX_MPDU_INFO_7_PN_127_96_MASK, \ 96 RX_MPDU_INFO_7_PN_127_96_LSB)) 97 98 #define HAL_RX_MSDU_END_FIRST_MSDU_GET(_rx_msdu_end) \ 99 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 100 RX_MSDU_END_5_FIRST_MSDU_OFFSET)), \ 101 RX_MSDU_END_5_FIRST_MSDU_MASK, \ 102 RX_MSDU_END_5_FIRST_MSDU_LSB)) 103 104 #define HAL_RX_MSDU_END_DA_IS_VALID_GET(_rx_msdu_end) \ 105 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 106 RX_MSDU_END_5_DA_IS_VALID_OFFSET)), \ 107 RX_MSDU_END_5_DA_IS_VALID_MASK, \ 108 RX_MSDU_END_5_DA_IS_VALID_LSB)) 109 110 #define HAL_RX_MSDU_END_LAST_MSDU_GET(_rx_msdu_end) \ 111 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 112 RX_MSDU_END_5_LAST_MSDU_OFFSET)), \ 113 RX_MSDU_END_5_LAST_MSDU_MASK, \ 114 RX_MSDU_END_5_LAST_MSDU_LSB)) 115 116 #define HAL_RX_MPDU_GET_MAC_AD4_VALID(_rx_mpdu_info) \ 117 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 118 RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_OFFSET)), \ 119 RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_MASK, \ 120 RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_LSB)) 121 122 #define HAL_RX_MPDU_INFO_SW_PEER_ID_GET(_rx_mpdu_info) \ 123 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_info), \ 124 RX_MPDU_INFO_1_SW_PEER_ID_OFFSET)), \ 125 RX_MPDU_INFO_1_SW_PEER_ID_MASK, \ 126 RX_MPDU_INFO_1_SW_PEER_ID_LSB)) 127 128 #define HAL_RX_MPDU_GET_TODS(_rx_mpdu_info) \ 129 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 130 RX_MPDU_INFO_2_TO_DS_OFFSET)), \ 131 RX_MPDU_INFO_2_TO_DS_MASK, \ 132 RX_MPDU_INFO_2_TO_DS_LSB)) 133 134 #define HAL_RX_MPDU_GET_FROMDS(_rx_mpdu_info) \ 135 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 136 RX_MPDU_INFO_2_FR_DS_OFFSET)), \ 137 RX_MPDU_INFO_2_FR_DS_MASK, \ 138 RX_MPDU_INFO_2_FR_DS_LSB)) 139 140 #define HAL_RX_MPDU_GET_FRAME_CONTROL_VALID(_rx_mpdu_info) \ 141 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 142 RX_MPDU_INFO_2_MPDU_FRAME_CONTROL_VALID_OFFSET)), \ 143 RX_MPDU_INFO_2_MPDU_FRAME_CONTROL_VALID_MASK, \ 144 RX_MPDU_INFO_2_MPDU_FRAME_CONTROL_VALID_LSB)) 145 146 #define HAL_RX_MPDU_MAC_ADDR_AD1_VALID_GET(_rx_mpdu_info) \ 147 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 148 RX_MPDU_INFO_2_MAC_ADDR_AD1_VALID_OFFSET)), \ 149 RX_MPDU_INFO_2_MAC_ADDR_AD1_VALID_MASK, \ 150 RX_MPDU_INFO_2_MAC_ADDR_AD1_VALID_LSB)) 151 152 #define HAL_RX_MPDU_AD1_31_0_GET(_rx_mpdu_info) \ 153 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 154 RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_OFFSET)), \ 155 RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_MASK, \ 156 RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_LSB)) 157 158 #define HAL_RX_MPDU_AD1_47_32_GET(_rx_mpdu_info) \ 159 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 160 RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_OFFSET)), \ 161 RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_MASK, \ 162 RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_LSB)) 163 164 #define HAL_RX_MPDU_MAC_ADDR_AD2_VALID_GET(_rx_mpdu_info) \ 165 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 166 RX_MPDU_INFO_2_MAC_ADDR_AD2_VALID_OFFSET)), \ 167 RX_MPDU_INFO_2_MAC_ADDR_AD2_VALID_MASK, \ 168 RX_MPDU_INFO_2_MAC_ADDR_AD2_VALID_LSB)) 169 170 #define HAL_RX_MPDU_AD2_15_0_GET(_rx_mpdu_info) \ 171 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 172 RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_OFFSET)), \ 173 RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_MASK, \ 174 RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_LSB)) 175 176 #define HAL_RX_MPDU_AD2_47_16_GET(_rx_mpdu_info) \ 177 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 178 RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_OFFSET)), \ 179 RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_MASK, \ 180 RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_LSB)) 181 182 #define HAL_RX_MPDU_MAC_ADDR_AD3_VALID_GET(_rx_mpdu_info) \ 183 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 184 RX_MPDU_INFO_2_MAC_ADDR_AD3_VALID_OFFSET)), \ 185 RX_MPDU_INFO_2_MAC_ADDR_AD3_VALID_MASK, \ 186 RX_MPDU_INFO_2_MAC_ADDR_AD3_VALID_LSB)) 187 188 #define HAL_RX_MPDU_AD3_31_0_GET(_rx_mpdu_info) \ 189 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 190 RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_OFFSET)), \ 191 RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_MASK, \ 192 RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_LSB)) 193 194 #define HAL_RX_MPDU_AD3_47_32_GET(_rx_mpdu_info) \ 195 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 196 RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_OFFSET)), \ 197 RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_MASK, \ 198 RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_LSB)) 199 200 #define HAL_RX_MPDU_MAC_ADDR_AD4_VALID_GET(_rx_mpdu_info) \ 201 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 202 RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_OFFSET)), \ 203 RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_MASK, \ 204 RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_LSB)) 205 206 #define HAL_RX_MPDU_AD4_31_0_GET(_rx_mpdu_info) \ 207 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 208 RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_OFFSET)), \ 209 RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_MASK, \ 210 RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_LSB)) 211 212 #define HAL_RX_MPDU_AD4_47_32_GET(_rx_mpdu_info) \ 213 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 214 RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_OFFSET)), \ 215 RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_MASK, \ 216 RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_LSB)) 217 218 #define HAL_RX_MPDU_GET_SEQUENCE_CONTROL_VALID(_rx_mpdu_info) \ 219 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 220 RX_MPDU_INFO_2_MPDU_SEQUENCE_CONTROL_VALID_OFFSET)), \ 221 RX_MPDU_INFO_2_MPDU_SEQUENCE_CONTROL_VALID_MASK, \ 222 RX_MPDU_INFO_2_MPDU_SEQUENCE_CONTROL_VALID_LSB)) 223 224 #define HAL_RX_MSDU_START_MIMO_SS_BITMAP(_rx_msdu_start)\ 225 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start),\ 226 RX_MSDU_START_5_MIMO_SS_BITMAP_OFFSET)), \ 227 RX_MSDU_START_5_MIMO_SS_BITMAP_MASK, \ 228 RX_MSDU_START_5_MIMO_SS_BITMAP_LSB)) 229 230 #define HAL_RX_MPDU_INFO_QOS_CONTROL_VALID_GET(_rx_mpdu_info) \ 231 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_info), \ 232 RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_OFFSET)), \ 233 RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_MASK, \ 234 RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_LSB)) 235 236 #define HAL_RX_MSDU_END_SA_SW_PEER_ID_GET(_rx_msdu_end) \ 237 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 238 RX_MSDU_END_16_SA_SW_PEER_ID_OFFSET)), \ 239 RX_MSDU_END_16_SA_SW_PEER_ID_MASK, \ 240 RX_MSDU_END_16_SA_SW_PEER_ID_LSB)) 241 242 #define HAL_RX_MSDU0_BUFFER_ADDR_LSB(link_desc_va) \ 243 (uint8_t *)(link_desc_va) + \ 244 RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET 245 246 #define HAL_RX_MSDU_DESC_INFO_PTR_GET(msdu0) \ 247 (uint8_t *)(msdu0) + \ 248 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET 249 250 #define HAL_ENT_MPDU_DESC_INFO(ent_ring_desc) \ 251 (uint8_t *)(ent_ring_desc) + \ 252 RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET 253 254 #define HAL_DST_MPDU_DESC_INFO(dst_ring_desc) \ 255 (uint8_t *)(dst_ring_desc) + \ 256 REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET 257 258 #define HAL_RX_GET_FC_VALID(rx_mpdu_start) \ 259 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_2, MPDU_FRAME_CONTROL_VALID) 260 261 #define HAL_RX_GET_TO_DS_FLAG(rx_mpdu_start) \ 262 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_2, TO_DS) 263 264 #define HAL_RX_GET_MAC_ADDR1_VALID(rx_mpdu_start) \ 265 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_2, MAC_ADDR_AD1_VALID) 266 267 #define HAL_RX_GET_MAC_ADDR2_VALID(rx_mpdu_start) \ 268 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_2, MAC_ADDR_AD2_VALID) 269 270 #define HAL_RX_GET_FILTER_CATEGORY(rx_mpdu_start) \ 271 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_0, RXPCU_MPDU_FILTER_IN_CATEGORY) 272 273 #define HAL_RX_GET_PPDU_ID(rx_mpdu_start) \ 274 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_0, PHY_PPDU_ID) 275 276 #define HAL_RX_GET_SW_FRAME_GROUP_ID(rx_mpdu_start) \ 277 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_0, SW_FRAME_GROUP_ID) 278 279 #define HAL_RX_GET_SW_PEER_ID(rx_mpdu_start) \ 280 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_1, SW_PEER_ID) 281 282 #define HAL_REO_R0_CONFIG(soc, reg_val, reo_params) \ 283 do { \ 284 reg_val &= \ 285 ~(HWIO_REO_R0_GENERAL_ENABLE_FRAGMENT_DEST_RING_BMSK |\ 286 HWIO_REO_R0_GENERAL_ENABLE_AGING_LIST_ENABLE_BMSK | \ 287 HWIO_REO_R0_GENERAL_ENABLE_AGING_FLUSH_ENABLE_BMSK); \ 288 reg_val |= \ 289 HAL_SM(HWIO_REO_R0_GENERAL_ENABLE, \ 290 FRAGMENT_DEST_RING, \ 291 (reo_params)->frag_dst_ring) | \ 292 HAL_SM(HWIO_REO_R0_GENERAL_ENABLE, \ 293 AGING_LIST_ENABLE, 1) |\ 294 HAL_SM(HWIO_REO_R0_GENERAL_ENABLE, \ 295 AGING_FLUSH_ENABLE, 1);\ 296 HAL_REG_WRITE((soc), \ 297 HWIO_REO_R0_GENERAL_ENABLE_ADDR( \ 298 SEQ_WCSS_UMAC_REO_REG_OFFSET), \ 299 (reg_val)); \ 300 reg_val = \ 301 HAL_REG_READ((soc), \ 302 HWIO_REO_R0_GENERAL_ENABLE_ADDR( \ 303 SEQ_WCSS_UMAC_REO_REG_OFFSET)); \ 304 reg_val &= \ 305 (~HWIO_REO_R0_GENERAL_ENABLE_BAR_DEST_RING_BMSK |\ 306 (REO_REMAP_TCL << HWIO_REO_R0_GENERAL_ENABLE_BAR_DEST_RING_SHFT)); \ 307 HAL_REG_WRITE((soc), \ 308 HWIO_REO_R0_GENERAL_ENABLE_ADDR( \ 309 SEQ_WCSS_UMAC_REO_REG_OFFSET), \ 310 (reg_val)); \ 311 } while (0) 312 313 #define HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr) \ 314 ((struct rx_msdu_desc_info *) \ 315 _OFFSET_TO_BYTE_PTR(msdu_details_ptr, \ 316 UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET)) 317 318 #define HAL_RX_LINK_DESC_MSDU0_PTR(link_desc) \ 319 ((struct rx_msdu_details *) \ 320 _OFFSET_TO_BYTE_PTR((link_desc),\ 321 UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET)) 322 323 #define HAL_RX_MSDU_END_FLOW_IDX_GET(_rx_msdu_end) \ 324 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 325 RX_MSDU_END_14_FLOW_IDX_OFFSET)), \ 326 RX_MSDU_END_14_FLOW_IDX_MASK, \ 327 RX_MSDU_END_14_FLOW_IDX_LSB)) 328 329 #define HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(_rx_msdu_end) \ 330 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 331 RX_MSDU_END_5_FLOW_IDX_INVALID_OFFSET)), \ 332 RX_MSDU_END_5_FLOW_IDX_INVALID_MASK, \ 333 RX_MSDU_END_5_FLOW_IDX_INVALID_LSB)) 334 335 #define HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(_rx_msdu_end) \ 336 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 337 RX_MSDU_END_5_FLOW_IDX_TIMEOUT_OFFSET)), \ 338 RX_MSDU_END_5_FLOW_IDX_TIMEOUT_MASK, \ 339 RX_MSDU_END_5_FLOW_IDX_TIMEOUT_LSB)) 340 341 #define HAL_RX_MSDU_END_FSE_METADATA_GET(_rx_msdu_end) \ 342 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 343 RX_MSDU_END_15_FSE_METADATA_OFFSET)), \ 344 RX_MSDU_END_15_FSE_METADATA_MASK, \ 345 RX_MSDU_END_15_FSE_METADATA_LSB)) 346 347 #define HAL_RX_MSDU_END_CCE_METADATA_GET(_rx_msdu_end) \ 348 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 349 RX_MSDU_END_16_CCE_METADATA_OFFSET)), \ 350 RX_MSDU_END_16_CCE_METADATA_MASK, \ 351 RX_MSDU_END_16_CCE_METADATA_LSB)) 352 353 #define HAL_RX_TLV_GET_TCP_CHKSUM(buf) \ 354 (_HAL_MS( \ 355 (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ 356 msdu_end_tlv.rx_msdu_end), \ 357 RX_MSDU_END_1_TCP_UDP_CHKSUM_OFFSET)), \ 358 RX_MSDU_END_1_TCP_UDP_CHKSUM_MASK, \ 359 RX_MSDU_END_1_TCP_UDP_CHKSUM_LSB)) 360 /* 361 * hal_rx_msdu_start_nss_get_6390(): API to get the NSS 362 * Interval from rx_msdu_start 363 * 364 * @buf: pointer to the start of RX PKT TLV header 365 * Return: uint32_t(nss) 366 */ 367 static uint32_t 368 hal_rx_msdu_start_nss_get_6390(uint8_t *buf) 369 { 370 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 371 struct rx_msdu_start *msdu_start = 372 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 373 uint8_t mimo_ss_bitmap; 374 375 mimo_ss_bitmap = HAL_RX_MSDU_START_MIMO_SS_BITMAP(msdu_start); 376 377 return qdf_get_hweight8(mimo_ss_bitmap); 378 379 } 380 381 /** 382 * hal_rx_mon_hw_desc_get_mpdu_status_6390(): Retrieve MPDU status 383 * 384 * @ hw_desc_addr: Start address of Rx HW TLVs 385 * @ rs: Status for monitor mode 386 * 387 * Return: void 388 */ 389 static void hal_rx_mon_hw_desc_get_mpdu_status_6390(void *hw_desc_addr, 390 struct mon_rx_status *rs) 391 { 392 struct rx_msdu_start *rx_msdu_start; 393 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr; 394 uint32_t reg_value; 395 const uint32_t sgi_hw_to_cdp[] = { 396 CDP_SGI_0_8_US, 397 CDP_SGI_0_4_US, 398 CDP_SGI_1_6_US, 399 CDP_SGI_3_2_US, 400 }; 401 402 rx_msdu_start = &rx_desc->msdu_start_tlv.rx_msdu_start; 403 404 HAL_RX_GET_MSDU_AGGREGATION(rx_desc, rs); 405 406 rs->ant_signal_db = HAL_RX_GET(rx_msdu_start, 407 RX_MSDU_START_5, USER_RSSI); 408 rs->is_stbc = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, STBC); 409 410 reg_value = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, SGI); 411 rs->sgi = sgi_hw_to_cdp[reg_value]; 412 413 reg_value = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, RECEPTION_TYPE); 414 rs->beamformed = (reg_value == HAL_RX_RECEPTION_TYPE_MU_MIMO) ? 1 : 0; 415 /* TODO: rs->beamformed should be set for SU beamforming also */ 416 } 417 418 #define LINK_DESC_SIZE (NUM_OF_DWORDS_RX_MSDU_LINK << 2) 419 420 static uint32_t hal_get_link_desc_size_6390(void) 421 { 422 return LINK_DESC_SIZE; 423 } 424 425 /* 426 * hal_rx_get_tlv_6390(): API to get the tlv 427 * 428 * @rx_tlv: TLV data extracted from the rx packet 429 * Return: uint8_t 430 */ 431 static uint8_t hal_rx_get_tlv_6390(void *rx_tlv) 432 { 433 return HAL_RX_GET(rx_tlv, PHYRX_RSSI_LEGACY_0, RECEIVE_BANDWIDTH); 434 } 435 436 /** 437 * hal_rx_proc_phyrx_other_receive_info_tlv_6390() 438 * - process other receive info TLV 439 * @rx_tlv_hdr: pointer to TLV header 440 * @ppdu_info: pointer to ppdu_info 441 * 442 * Return: None 443 */ 444 static 445 void hal_rx_proc_phyrx_other_receive_info_tlv_6390(void *rx_tlv_hdr, 446 void *ppdu_info_handle) 447 { 448 uint32_t tlv_tag, tlv_len; 449 uint32_t temp_len, other_tlv_len, other_tlv_tag; 450 void *rx_tlv = (uint8_t *)rx_tlv_hdr + HAL_RX_TLV32_HDR_SIZE; 451 void *other_tlv_hdr = NULL; 452 void *other_tlv = NULL; 453 454 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv_hdr); 455 tlv_len = HAL_RX_GET_USER_TLV32_LEN(rx_tlv_hdr); 456 temp_len = 0; 457 458 other_tlv_hdr = rx_tlv + HAL_RX_TLV32_HDR_SIZE; 459 460 other_tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(other_tlv_hdr); 461 other_tlv_len = HAL_RX_GET_USER_TLV32_LEN(other_tlv_hdr); 462 temp_len += other_tlv_len; 463 other_tlv = other_tlv_hdr + HAL_RX_TLV32_HDR_SIZE; 464 465 switch (other_tlv_tag) { 466 default: 467 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR, 468 "%s unhandled TLV type: %d, TLV len:%d", 469 __func__, other_tlv_tag, other_tlv_len); 470 break; 471 } 472 } 473 474 /** 475 * hal_rx_dump_msdu_start_tlv_6390() : dump RX msdu_start TLV in structured 476 * human readable format. 477 * @ msdu_start: pointer the msdu_start TLV in pkt. 478 * @ dbg_level: log level. 479 * 480 * Return: void 481 */ 482 static void hal_rx_dump_msdu_start_tlv_6390(void *msdustart, uint8_t dbg_level) 483 { 484 struct rx_msdu_start *msdu_start = (struct rx_msdu_start *)msdustart; 485 486 hal_verbose_debug( 487 "rx_msdu_start tlv (1/2) - " 488 "rxpcu_mpdu_filter_in_category: %x " 489 "sw_frame_group_id: %x " 490 "phy_ppdu_id: %x " 491 "msdu_length: %x " 492 "ipsec_esp: %x " 493 "l3_offset: %x " 494 "ipsec_ah: %x " 495 "l4_offset: %x " 496 "msdu_number: %x " 497 "decap_format: %x " 498 "ipv4_proto: %x " 499 "ipv6_proto: %x " 500 "tcp_proto: %x " 501 "udp_proto: %x " 502 "ip_frag: %x " 503 "tcp_only_ack: %x " 504 "da_is_bcast_mcast: %x " 505 "ip4_protocol_ip6_next_header: %x " 506 "toeplitz_hash_2_or_4: %x " 507 "flow_id_toeplitz: %x " 508 "user_rssi: %x " 509 "pkt_type: %x " 510 "stbc: %x " 511 "sgi: %x " 512 "rate_mcs: %x " 513 "receive_bandwidth: %x " 514 "reception_type: %x " 515 "ppdu_start_timestamp: %u ", 516 msdu_start->rxpcu_mpdu_filter_in_category, 517 msdu_start->sw_frame_group_id, 518 msdu_start->phy_ppdu_id, 519 msdu_start->msdu_length, 520 msdu_start->ipsec_esp, 521 msdu_start->l3_offset, 522 msdu_start->ipsec_ah, 523 msdu_start->l4_offset, 524 msdu_start->msdu_number, 525 msdu_start->decap_format, 526 msdu_start->ipv4_proto, 527 msdu_start->ipv6_proto, 528 msdu_start->tcp_proto, 529 msdu_start->udp_proto, 530 msdu_start->ip_frag, 531 msdu_start->tcp_only_ack, 532 msdu_start->da_is_bcast_mcast, 533 msdu_start->ip4_protocol_ip6_next_header, 534 msdu_start->toeplitz_hash_2_or_4, 535 msdu_start->flow_id_toeplitz, 536 msdu_start->user_rssi, 537 msdu_start->pkt_type, 538 msdu_start->stbc, 539 msdu_start->sgi, 540 msdu_start->rate_mcs, 541 msdu_start->receive_bandwidth, 542 msdu_start->reception_type, 543 msdu_start->ppdu_start_timestamp); 544 545 hal_verbose_debug( 546 "rx_msdu_start tlv (2/2) - " 547 "sw_phy_meta_data: %x ", 548 msdu_start->sw_phy_meta_data); 549 } 550 551 /** 552 * hal_rx_dump_msdu_end_tlv_6390: dump RX msdu_end TLV in structured 553 * human readable format. 554 * @ msdu_end: pointer the msdu_end TLV in pkt. 555 * @ dbg_level: log level. 556 * 557 * Return: void 558 */ 559 static void hal_rx_dump_msdu_end_tlv_6390(void *msduend, 560 uint8_t dbg_level) 561 { 562 struct rx_msdu_end *msdu_end = (struct rx_msdu_end *)msduend; 563 564 __QDF_TRACE_RL(dbg_level, QDF_MODULE_ID_DP, 565 "rx_msdu_end tlv (1/2) - " 566 "rxpcu_mpdu_filter_in_category: %x " 567 "sw_frame_group_id: %x " 568 "phy_ppdu_id: %x " 569 "ip_hdr_chksum: %x " 570 "tcp_udp_chksum: %x " 571 "key_id_octet: %x " 572 "cce_super_rule: %x " 573 "cce_classify_not_done_truncat: %x " 574 "cce_classify_not_done_cce_dis: %x " 575 "ext_wapi_pn_63_48: %x " 576 "ext_wapi_pn_95_64: %x " 577 "ext_wapi_pn_127_96: %x " 578 "reported_mpdu_length: %x " 579 "first_msdu: %x " 580 "last_msdu: %x " 581 "sa_idx_timeout: %x " 582 "da_idx_timeout: %x " 583 "msdu_limit_error: %x " 584 "flow_idx_timeout: %x " 585 "flow_idx_invalid: %x " 586 "wifi_parser_error: %x " 587 "amsdu_parser_error: %x", 588 msdu_end->rxpcu_mpdu_filter_in_category, 589 msdu_end->sw_frame_group_id, 590 msdu_end->phy_ppdu_id, 591 msdu_end->ip_hdr_chksum, 592 msdu_end->tcp_udp_chksum, 593 msdu_end->key_id_octet, 594 msdu_end->cce_super_rule, 595 msdu_end->cce_classify_not_done_truncate, 596 msdu_end->cce_classify_not_done_cce_dis, 597 msdu_end->ext_wapi_pn_63_48, 598 msdu_end->ext_wapi_pn_95_64, 599 msdu_end->ext_wapi_pn_127_96, 600 msdu_end->reported_mpdu_length, 601 msdu_end->first_msdu, 602 msdu_end->last_msdu, 603 msdu_end->sa_idx_timeout, 604 msdu_end->da_idx_timeout, 605 msdu_end->msdu_limit_error, 606 msdu_end->flow_idx_timeout, 607 msdu_end->flow_idx_invalid, 608 msdu_end->wifi_parser_error, 609 msdu_end->amsdu_parser_error); 610 611 __QDF_TRACE_RL(dbg_level, QDF_MODULE_ID_DP, 612 "rx_msdu_end tlv (2/2)- " 613 "sa_is_valid: %x " 614 "da_is_valid: %x " 615 "da_is_mcbc: %x " 616 "l3_header_padding: %x " 617 "ipv6_options_crc: %x " 618 "tcp_seq_number: %x " 619 "tcp_ack_number: %x " 620 "tcp_flag: %x " 621 "lro_eligible: %x " 622 "window_size: %x " 623 "da_offset: %x " 624 "sa_offset: %x " 625 "da_offset_valid: %x " 626 "sa_offset_valid: %x " 627 "rule_indication_31_0: %x " 628 "rule_indication_63_32: %x " 629 "sa_idx: %x " 630 "da_idx: %x " 631 "msdu_drop: %x " 632 "reo_destination_indication: %x " 633 "flow_idx: %x " 634 "fse_metadata: %x " 635 "cce_metadata: %x " 636 "sa_sw_peer_id: %x ", 637 msdu_end->sa_is_valid, 638 msdu_end->da_is_valid, 639 msdu_end->da_is_mcbc, 640 msdu_end->l3_header_padding, 641 msdu_end->ipv6_options_crc, 642 msdu_end->tcp_seq_number, 643 msdu_end->tcp_ack_number, 644 msdu_end->tcp_flag, 645 msdu_end->lro_eligible, 646 msdu_end->window_size, 647 msdu_end->da_offset, 648 msdu_end->sa_offset, 649 msdu_end->da_offset_valid, 650 msdu_end->sa_offset_valid, 651 msdu_end->rule_indication_31_0, 652 msdu_end->rule_indication_63_32, 653 msdu_end->sa_idx, 654 msdu_end->da_idx_or_sw_peer_id, 655 msdu_end->msdu_drop, 656 msdu_end->reo_destination_indication, 657 msdu_end->flow_idx, 658 msdu_end->fse_metadata, 659 msdu_end->cce_metadata, 660 msdu_end->sa_sw_peer_id); 661 } 662 663 664 /* 665 * Get tid from RX_MPDU_START 666 */ 667 #define HAL_RX_MPDU_INFO_TID_GET(_rx_mpdu_info) \ 668 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_info), \ 669 RX_MPDU_INFO_3_TID_OFFSET)), \ 670 RX_MPDU_INFO_3_TID_MASK, \ 671 RX_MPDU_INFO_3_TID_LSB)) 672 673 static uint32_t hal_rx_mpdu_start_tid_get_6390(uint8_t *buf) 674 { 675 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 676 struct rx_mpdu_start *mpdu_start = 677 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 678 uint32_t tid; 679 680 tid = HAL_RX_MPDU_INFO_TID_GET(&mpdu_start->rx_mpdu_info_details); 681 682 return tid; 683 } 684 685 #define HAL_RX_MSDU_START_RECEPTION_TYPE_GET(_rx_msdu_start) \ 686 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start), \ 687 RX_MSDU_START_5_RECEPTION_TYPE_OFFSET)), \ 688 RX_MSDU_START_5_RECEPTION_TYPE_MASK, \ 689 RX_MSDU_START_5_RECEPTION_TYPE_LSB)) 690 691 /* 692 * hal_rx_msdu_start_reception_type_get(): API to get the reception type 693 * Interval from rx_msdu_start 694 * 695 * @buf: pointer to the start of RX PKT TLV header 696 * Return: uint32_t(reception_type) 697 */ 698 static 699 uint32_t hal_rx_msdu_start_reception_type_get_6390(uint8_t *buf) 700 { 701 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 702 struct rx_msdu_start *msdu_start = 703 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 704 uint32_t reception_type; 705 706 reception_type = HAL_RX_MSDU_START_RECEPTION_TYPE_GET(msdu_start); 707 708 return reception_type; 709 } 710 711 #define HAL_RX_MSDU_END_DA_IDX_GET(_rx_msdu_end) \ 712 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 713 RX_MSDU_END_13_DA_IDX_OR_SW_PEER_ID_OFFSET)), \ 714 RX_MSDU_END_13_DA_IDX_OR_SW_PEER_ID_MASK, \ 715 RX_MSDU_END_13_DA_IDX_OR_SW_PEER_ID_LSB)) 716 717 /** 718 * hal_rx_msdu_end_da_idx_get_6390: API to get da_idx 719 * from rx_msdu_end TLV 720 * 721 * @ buf: pointer to the start of RX PKT TLV headers 722 * Return: da index 723 */ 724 static uint16_t hal_rx_msdu_end_da_idx_get_6390(uint8_t *buf) 725 { 726 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 727 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 728 uint16_t da_idx; 729 730 da_idx = HAL_RX_MSDU_END_DA_IDX_GET(msdu_end); 731 732 return da_idx; 733 } 734 735