1 /* 2 * Copyright (c) 2016-2019 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 #include "qdf_types.h" 19 #include "qdf_util.h" 20 #include "qdf_types.h" 21 #include "qdf_lock.h" 22 #include "qdf_mem.h" 23 #include "qdf_nbuf.h" 24 #include "hal_hw_headers.h" 25 #include "hal_internal.h" 26 #include "hal_api.h" 27 #include "target_type.h" 28 #include "wcss_version.h" 29 #include "qdf_module.h" 30 31 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_OFFSET \ 32 RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_OFFSET 33 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_MASK \ 34 RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_MASK 35 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_LSB \ 36 RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_LSB 37 #define UNIFIED_PHYRX_HT_SIG_0_HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS_OFFSET \ 38 PHYRX_HT_SIG_0_HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS_OFFSET 39 #define UNIFIED_PHYRX_L_SIG_B_0_L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS_OFFSET \ 40 PHYRX_L_SIG_B_0_L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS_OFFSET 41 #define UNIFIED_PHYRX_L_SIG_A_0_L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS_OFFSET \ 42 PHYRX_L_SIG_A_0_L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS_OFFSET 43 #define UNIFIED_PHYRX_VHT_SIG_A_0_VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS_OFFSET \ 44 PHYRX_VHT_SIG_A_0_VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS_OFFSET 45 #define UNIFIED_PHYRX_HE_SIG_A_SU_0_HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS_OFFSET \ 46 PHYRX_HE_SIG_A_SU_0_HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS_OFFSET 47 #define UNIFIED_PHYRX_HE_SIG_A_MU_DL_0_HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_OFFSET \ 48 PHYRX_HE_SIG_A_MU_DL_0_HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_OFFSET 49 #define UNIFIED_PHYRX_HE_SIG_B1_MU_0_HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_OFFSET \ 50 PHYRX_HE_SIG_B1_MU_0_HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_OFFSET 51 #define UNIFIED_PHYRX_HE_SIG_B2_MU_0_HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_OFFSET \ 52 PHYRX_HE_SIG_B2_MU_0_HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_OFFSET 53 #define UNIFIED_PHYRX_HE_SIG_B2_OFDMA_0_HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_OFFSET \ 54 PHYRX_HE_SIG_B2_OFDMA_0_HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_OFFSET 55 #define UNIFIED_PHYRX_RSSI_LEGACY_3_RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS_OFFSET \ 56 PHYRX_RSSI_LEGACY_3_RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS_OFFSET 57 #define UNIFIED_PHYRX_RSSI_LEGACY_19_RECEIVE_RSSI_INFO_PREAMBLE_RSSI_INFO_DETAILS_OFFSET \ 58 PHYRX_RSSI_LEGACY_19_RECEIVE_RSSI_INFO_PREAMBLE_RSSI_INFO_DETAILS_OFFSET 59 #define UNIFIED_RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET \ 60 RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET 61 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 62 RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET 63 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ 64 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET 65 #define UNIFIED_RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 66 RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET 67 #define UNIFIED_REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 68 REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET 69 #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC \ 70 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER 71 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ 72 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET 73 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 74 RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET 75 #define UNIFIED_TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 76 TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET 77 #define UNIFIED_TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 78 TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET 79 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET \ 80 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET 81 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB \ 82 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB 83 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK \ 84 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK 85 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB \ 86 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB 87 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK \ 88 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK 89 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB \ 90 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB 91 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK \ 92 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK 93 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB \ 94 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB 95 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK \ 96 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK 97 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB \ 98 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB 99 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK \ 100 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK 101 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_MASK \ 102 WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_MASK 103 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_OFFSET \ 104 WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_OFFSET 105 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_LSB \ 106 WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_LSB 107 108 #include "hal_6390_tx.h" 109 #include "hal_6390_rx.h" 110 #include <hal_generic_api.h> 111 #include <hal_wbm.h> 112 113 struct hal_hw_txrx_ops qca6390_hal_hw_txrx_ops = { 114 /* init and setup */ 115 hal_srng_dst_hw_init_generic, 116 hal_srng_src_hw_init_generic, 117 hal_get_hw_hptp_generic, 118 hal_reo_setup_generic, 119 hal_setup_link_idle_list_generic, 120 121 /* tx */ 122 hal_tx_desc_set_dscp_tid_table_id_6390, 123 hal_tx_set_dscp_tid_map_6390, 124 hal_tx_update_dscp_tid_6390, 125 hal_tx_desc_set_lmac_id_6390, 126 hal_tx_desc_set_buf_addr_generic, 127 hal_tx_desc_set_search_type_generic, 128 hal_tx_desc_set_search_index_generic, 129 hal_tx_comp_get_status_generic, 130 hal_tx_comp_get_release_reason_generic, 131 132 /* rx */ 133 hal_rx_msdu_start_nss_get_6390, 134 hal_rx_mon_hw_desc_get_mpdu_status_6390, 135 hal_rx_get_tlv_6390, 136 hal_rx_proc_phyrx_other_receive_info_tlv_6390, 137 hal_rx_dump_msdu_start_tlv_6390, 138 hal_rx_dump_msdu_end_tlv_6390, 139 hal_get_link_desc_size_6390, 140 hal_rx_mpdu_start_tid_get_6390, 141 hal_rx_msdu_start_reception_type_get_6390, 142 hal_rx_msdu_end_da_idx_get_6390, 143 hal_rx_msdu_desc_info_get_ptr_generic, 144 hal_rx_link_desc_msdu0_ptr_generic, 145 hal_reo_status_get_header_generic, 146 hal_rx_status_get_tlv_info_generic, 147 hal_rx_wbm_err_info_get_generic, 148 hal_rx_dump_mpdu_start_tlv_generic, 149 150 hal_tx_set_pcp_tid_map_generic, 151 hal_tx_update_pcp_tid_generic, 152 hal_tx_update_tidmap_prty_generic, 153 }; 154 155 struct hal_hw_srng_config hw_srng_table_6390[] = { 156 /* TODO: max_rings can populated by querying HW capabilities */ 157 { /* REO_DST */ 158 .start_ring_id = HAL_SRNG_REO2SW1, 159 .max_rings = 4, 160 .entry_size = sizeof(struct reo_destination_ring) >> 2, 161 .lmac_ring = FALSE, 162 .ring_dir = HAL_SRNG_DST_RING, 163 .reg_start = { 164 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR( 165 SEQ_WCSS_UMAC_REO_REG_OFFSET), 166 HWIO_REO_R2_REO2SW1_RING_HP_ADDR( 167 SEQ_WCSS_UMAC_REO_REG_OFFSET) 168 }, 169 .reg_size = { 170 HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(0) - 171 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(0), 172 HWIO_REO_R2_REO2SW2_RING_HP_ADDR(0) - 173 HWIO_REO_R2_REO2SW1_RING_HP_ADDR(0), 174 }, 175 .max_size = 176 HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_BMSK >> 177 HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_SHFT, 178 }, 179 { /* REO_EXCEPTION */ 180 /* Designating REO2TCL ring as exception ring. This ring is 181 * similar to other REO2SW rings though it is named as REO2TCL. 182 * Any of theREO2SW rings can be used as exception ring. 183 */ 184 .start_ring_id = HAL_SRNG_REO2TCL, 185 .max_rings = 1, 186 .entry_size = sizeof(struct reo_destination_ring) >> 2, 187 .lmac_ring = FALSE, 188 .ring_dir = HAL_SRNG_DST_RING, 189 .reg_start = { 190 HWIO_REO_R0_REO2TCL_RING_BASE_LSB_ADDR( 191 SEQ_WCSS_UMAC_REO_REG_OFFSET), 192 HWIO_REO_R2_REO2TCL_RING_HP_ADDR( 193 SEQ_WCSS_UMAC_REO_REG_OFFSET) 194 }, 195 /* Single ring - provide ring size if multiple rings of this 196 * type are supported 197 */ 198 .reg_size = {}, 199 .max_size = 200 HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_BMSK >> 201 HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_SHFT, 202 }, 203 { /* REO_REINJECT */ 204 .start_ring_id = HAL_SRNG_SW2REO, 205 .max_rings = 1, 206 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 207 .lmac_ring = FALSE, 208 .ring_dir = HAL_SRNG_SRC_RING, 209 .reg_start = { 210 HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR( 211 SEQ_WCSS_UMAC_REO_REG_OFFSET), 212 HWIO_REO_R2_SW2REO_RING_HP_ADDR( 213 SEQ_WCSS_UMAC_REO_REG_OFFSET) 214 }, 215 /* Single ring - provide ring size if multiple rings of this 216 * type are supported 217 */ 218 .reg_size = {}, 219 .max_size = HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_BMSK >> 220 HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_SHFT, 221 }, 222 { /* REO_CMD */ 223 .start_ring_id = HAL_SRNG_REO_CMD, 224 .max_rings = 1, 225 .entry_size = (sizeof(struct tlv_32_hdr) + 226 sizeof(struct reo_get_queue_stats)) >> 2, 227 .lmac_ring = FALSE, 228 .ring_dir = HAL_SRNG_SRC_RING, 229 .reg_start = { 230 HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR( 231 SEQ_WCSS_UMAC_REO_REG_OFFSET), 232 HWIO_REO_R2_REO_CMD_RING_HP_ADDR( 233 SEQ_WCSS_UMAC_REO_REG_OFFSET), 234 }, 235 /* Single ring - provide ring size if multiple rings of this 236 * type are supported 237 */ 238 .reg_size = {}, 239 .max_size = 240 HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_BMSK >> 241 HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_SHFT, 242 }, 243 { /* REO_STATUS */ 244 .start_ring_id = HAL_SRNG_REO_STATUS, 245 .max_rings = 1, 246 .entry_size = (sizeof(struct tlv_32_hdr) + 247 sizeof(struct reo_get_queue_stats_status)) >> 2, 248 .lmac_ring = FALSE, 249 .ring_dir = HAL_SRNG_DST_RING, 250 .reg_start = { 251 HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR( 252 SEQ_WCSS_UMAC_REO_REG_OFFSET), 253 HWIO_REO_R2_REO_STATUS_RING_HP_ADDR( 254 SEQ_WCSS_UMAC_REO_REG_OFFSET), 255 }, 256 /* Single ring - provide ring size if multiple rings of this 257 * type are supported 258 */ 259 .reg_size = {}, 260 .max_size = 261 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> 262 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, 263 }, 264 { /* TCL_DATA */ 265 .start_ring_id = HAL_SRNG_SW2TCL1, 266 .max_rings = 3, 267 .entry_size = (sizeof(struct tlv_32_hdr) + 268 sizeof(struct tcl_data_cmd)) >> 2, 269 .lmac_ring = FALSE, 270 .ring_dir = HAL_SRNG_SRC_RING, 271 .reg_start = { 272 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR( 273 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 274 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR( 275 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 276 }, 277 .reg_size = { 278 HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(0) - 279 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(0), 280 HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(0) - 281 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(0), 282 }, 283 .max_size = 284 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK >> 285 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT, 286 }, 287 { /* TCL_CMD */ 288 .start_ring_id = HAL_SRNG_SW2TCL_CMD, 289 .max_rings = 1, 290 .entry_size = (sizeof(struct tlv_32_hdr) + 291 sizeof(struct tcl_gse_cmd)) >> 2, 292 .lmac_ring = FALSE, 293 .ring_dir = HAL_SRNG_SRC_RING, 294 .reg_start = { 295 HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_ADDR( 296 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 297 HWIO_TCL_R2_SW2TCL_CMD_RING_HP_ADDR( 298 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 299 }, 300 /* Single ring - provide ring size if multiple rings of this 301 * type are supported 302 */ 303 .reg_size = {}, 304 .max_size = 305 HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RING_SIZE_BMSK >> 306 HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RING_SIZE_SHFT, 307 }, 308 { /* TCL_STATUS */ 309 .start_ring_id = HAL_SRNG_TCL_STATUS, 310 .max_rings = 1, 311 .entry_size = (sizeof(struct tlv_32_hdr) + 312 sizeof(struct tcl_status_ring)) >> 2, 313 .lmac_ring = FALSE, 314 .ring_dir = HAL_SRNG_DST_RING, 315 .reg_start = { 316 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR( 317 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 318 HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR( 319 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 320 }, 321 /* Single ring - provide ring size if multiple rings of this 322 * type are supported 323 */ 324 .reg_size = {}, 325 .max_size = 326 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_BMSK >> 327 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_SHFT, 328 }, 329 { /* CE_SRC */ 330 .start_ring_id = HAL_SRNG_CE_0_SRC, 331 .max_rings = 12, 332 .entry_size = sizeof(struct ce_src_desc) >> 2, 333 .lmac_ring = FALSE, 334 .ring_dir = HAL_SRNG_SRC_RING, 335 .reg_start = { 336 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR( 337 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET), 338 HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR( 339 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET), 340 }, 341 .reg_size = { 342 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET - 343 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET, 344 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET - 345 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET, 346 }, 347 .max_size = 348 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >> 349 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT, 350 }, 351 { /* CE_DST */ 352 .start_ring_id = HAL_SRNG_CE_0_DST, 353 .max_rings = 12, 354 .entry_size = 8 >> 2, 355 /*TODO: entry_size above should actually be 356 * sizeof(struct ce_dst_desc) >> 2, but couldn't find definition 357 * of struct ce_dst_desc in HW header files 358 */ 359 .lmac_ring = FALSE, 360 .ring_dir = HAL_SRNG_SRC_RING, 361 .reg_start = { 362 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR( 363 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 364 HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR( 365 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 366 }, 367 .reg_size = { 368 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 369 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 370 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 371 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 372 }, 373 .max_size = 374 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >> 375 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT, 376 }, 377 { /* CE_DST_STATUS */ 378 .start_ring_id = HAL_SRNG_CE_0_DST_STATUS, 379 .max_rings = 12, 380 .entry_size = sizeof(struct ce_stat_desc) >> 2, 381 .lmac_ring = FALSE, 382 .ring_dir = HAL_SRNG_DST_RING, 383 .reg_start = { 384 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR( 385 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 386 HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR( 387 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 388 }, 389 /* TODO: check destination status ring registers */ 390 .reg_size = { 391 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 392 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 393 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 394 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 395 }, 396 .max_size = 397 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> 398 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, 399 }, 400 { /* WBM_IDLE_LINK */ 401 .start_ring_id = HAL_SRNG_WBM_IDLE_LINK, 402 .max_rings = 1, 403 .entry_size = sizeof(struct wbm_link_descriptor_ring) >> 2, 404 .lmac_ring = FALSE, 405 .ring_dir = HAL_SRNG_SRC_RING, 406 .reg_start = { 407 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 408 HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 409 }, 410 /* Single ring - provide ring size if multiple rings of this 411 * type are supported 412 */ 413 .reg_size = {}, 414 .max_size = 415 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_BMSK >> 416 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_SHFT, 417 }, 418 { /* SW2WBM_RELEASE */ 419 .start_ring_id = HAL_SRNG_WBM_SW_RELEASE, 420 .max_rings = 1, 421 .entry_size = sizeof(struct wbm_release_ring) >> 2, 422 .lmac_ring = FALSE, 423 .ring_dir = HAL_SRNG_SRC_RING, 424 .reg_start = { 425 HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 426 HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 427 }, 428 /* Single ring - provide ring size if multiple rings of this 429 * type are supported 430 */ 431 .reg_size = {}, 432 .max_size = 433 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> 434 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, 435 }, 436 { /* WBM2SW_RELEASE */ 437 .start_ring_id = HAL_SRNG_WBM2SW0_RELEASE, 438 .max_rings = 4, 439 .entry_size = sizeof(struct wbm_release_ring) >> 2, 440 .lmac_ring = FALSE, 441 .ring_dir = HAL_SRNG_DST_RING, 442 .reg_start = { 443 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 444 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 445 }, 446 .reg_size = { 447 HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) - 448 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 449 HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) - 450 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 451 }, 452 .max_size = 453 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> 454 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, 455 }, 456 { /* RXDMA_BUF */ 457 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA0_BUF0, 458 #ifdef IPA_OFFLOAD 459 .max_rings = 3, 460 #else 461 .max_rings = 2, 462 #endif 463 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 464 .lmac_ring = TRUE, 465 .ring_dir = HAL_SRNG_SRC_RING, 466 /* reg_start is not set because LMAC rings are not accessed 467 * from host 468 */ 469 .reg_start = {}, 470 .reg_size = {}, 471 .max_size = HAL_RXDMA_MAX_RING_SIZE, 472 }, 473 { /* RXDMA_DST */ 474 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW0, 475 .max_rings = 1, 476 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 477 .lmac_ring = TRUE, 478 .ring_dir = HAL_SRNG_DST_RING, 479 /* reg_start is not set because LMAC rings are not accessed 480 * from host 481 */ 482 .reg_start = {}, 483 .reg_size = {}, 484 .max_size = HAL_RXDMA_MAX_RING_SIZE, 485 }, 486 { /* RXDMA_MONITOR_BUF */ 487 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA2_BUF, 488 .max_rings = 1, 489 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 490 .lmac_ring = TRUE, 491 .ring_dir = HAL_SRNG_SRC_RING, 492 /* reg_start is not set because LMAC rings are not accessed 493 * from host 494 */ 495 .reg_start = {}, 496 .reg_size = {}, 497 .max_size = HAL_RXDMA_MAX_RING_SIZE, 498 }, 499 { /* RXDMA_MONITOR_STATUS */ 500 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_STATBUF, 501 .max_rings = 1, 502 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 503 .lmac_ring = TRUE, 504 .ring_dir = HAL_SRNG_SRC_RING, 505 /* reg_start is not set because LMAC rings are not accessed 506 * from host 507 */ 508 .reg_start = {}, 509 .reg_size = {}, 510 .max_size = HAL_RXDMA_MAX_RING_SIZE, 511 }, 512 { /* RXDMA_MONITOR_DST */ 513 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW1, 514 .max_rings = 1, 515 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 516 .lmac_ring = TRUE, 517 .ring_dir = HAL_SRNG_DST_RING, 518 /* reg_start is not set because LMAC rings are not accessed 519 * from host 520 */ 521 .reg_start = {}, 522 .reg_size = {}, 523 .max_size = HAL_RXDMA_MAX_RING_SIZE, 524 }, 525 { /* RXDMA_MONITOR_DESC */ 526 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_DESC, 527 .max_rings = 1, 528 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 529 .lmac_ring = TRUE, 530 .ring_dir = HAL_SRNG_SRC_RING, 531 /* reg_start is not set because LMAC rings are not accessed 532 * from host 533 */ 534 .reg_start = {}, 535 .reg_size = {}, 536 .max_size = HAL_RXDMA_MAX_RING_SIZE, 537 }, 538 { /* DIR_BUF_RX_DMA_SRC */ 539 .start_ring_id = HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING, 540 .max_rings = 1, 541 .entry_size = 2, 542 .lmac_ring = TRUE, 543 .ring_dir = HAL_SRNG_SRC_RING, 544 /* reg_start is not set because LMAC rings are not accessed 545 * from host 546 */ 547 .reg_start = {}, 548 .reg_size = {}, 549 .max_size = HAL_RXDMA_MAX_RING_SIZE, 550 }, 551 #ifdef WLAN_FEATURE_CIF_CFR 552 { /* WIFI_POS_SRC */ 553 .start_ring_id = HAL_SRNG_WIFI_POS_SRC_DMA_RING, 554 .max_rings = 1, 555 .entry_size = sizeof(wmi_oem_dma_buf_release_entry) >> 2, 556 .lmac_ring = TRUE, 557 .ring_dir = HAL_SRNG_SRC_RING, 558 /* reg_start is not set because LMAC rings are not accessed 559 * from host 560 */ 561 .reg_start = {}, 562 .reg_size = {}, 563 .max_size = HAL_RXDMA_MAX_RING_SIZE, 564 }, 565 #endif 566 }; 567 568 int32_t hal_hw_reg_offset_qca6390[] = { 569 /* dst */ 570 REG_OFFSET(DST, HP), 571 REG_OFFSET(DST, TP), 572 REG_OFFSET(DST, ID), 573 REG_OFFSET(DST, MISC), 574 REG_OFFSET(DST, HP_ADDR_LSB), 575 REG_OFFSET(DST, HP_ADDR_MSB), 576 REG_OFFSET(DST, MSI1_BASE_LSB), 577 REG_OFFSET(DST, MSI1_BASE_MSB), 578 REG_OFFSET(DST, MSI1_DATA), 579 REG_OFFSET(DST, BASE_LSB), 580 REG_OFFSET(DST, BASE_MSB), 581 REG_OFFSET(DST, PRODUCER_INT_SETUP), 582 /* src */ 583 REG_OFFSET(SRC, HP), 584 REG_OFFSET(SRC, TP), 585 REG_OFFSET(SRC, ID), 586 REG_OFFSET(SRC, MISC), 587 REG_OFFSET(SRC, TP_ADDR_LSB), 588 REG_OFFSET(SRC, TP_ADDR_MSB), 589 REG_OFFSET(SRC, MSI1_BASE_LSB), 590 REG_OFFSET(SRC, MSI1_BASE_MSB), 591 REG_OFFSET(SRC, MSI1_DATA), 592 REG_OFFSET(SRC, BASE_LSB), 593 REG_OFFSET(SRC, BASE_MSB), 594 REG_OFFSET(SRC, CONSUMER_INT_SETUP_IX0), 595 REG_OFFSET(SRC, CONSUMER_INT_SETUP_IX1), 596 }; 597 598 /** 599 * hal_qca6390_attach() - Attach 6390 target specific hal_soc ops, 600 * offset and srng table 601 */ 602 void hal_qca6390_attach(struct hal_soc *hal_soc) 603 { 604 hal_soc->hw_srng_table = hw_srng_table_6390; 605 hal_soc->hal_hw_reg_offset = hal_hw_reg_offset_qca6390; 606 hal_soc->ops = &qca6390_hal_hw_txrx_ops; 607 } 608