1 /* 2 * Copyright (c) 2016-2018 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 #include "qdf_types.h" 19 #include "qdf_util.h" 20 #include "qdf_types.h" 21 #include "qdf_lock.h" 22 #include "qdf_mem.h" 23 #include "qdf_nbuf.h" 24 #include "hal_hw_headers.h" 25 #include "hal_internal.h" 26 #include "hal_api.h" 27 #include "target_type.h" 28 #include "wcss_version.h" 29 #include "qdf_module.h" 30 31 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_OFFSET \ 32 RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_OFFSET 33 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_MASK \ 34 RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_MASK 35 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_LSB \ 36 RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_LSB 37 #define UNIFIED_PHYRX_HT_SIG_0_HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS_OFFSET \ 38 PHYRX_HT_SIG_0_HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS_OFFSET 39 #define UNIFIED_PHYRX_L_SIG_B_0_L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS_OFFSET \ 40 PHYRX_L_SIG_B_0_L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS_OFFSET 41 #define UNIFIED_PHYRX_L_SIG_A_0_L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS_OFFSET \ 42 PHYRX_L_SIG_A_0_L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS_OFFSET 43 #define UNIFIED_PHYRX_VHT_SIG_A_0_VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS_OFFSET \ 44 PHYRX_VHT_SIG_A_0_VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS_OFFSET 45 #define UNIFIED_PHYRX_HE_SIG_A_SU_0_HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS_OFFSET \ 46 PHYRX_HE_SIG_A_SU_0_HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS_OFFSET 47 #define UNIFIED_PHYRX_HE_SIG_A_MU_DL_0_HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_OFFSET \ 48 PHYRX_HE_SIG_A_MU_DL_0_HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_OFFSET 49 #define UNIFIED_PHYRX_HE_SIG_B1_MU_0_HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_OFFSET \ 50 PHYRX_HE_SIG_B1_MU_0_HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_OFFSET 51 #define UNIFIED_PHYRX_HE_SIG_B2_MU_0_HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_OFFSET \ 52 PHYRX_HE_SIG_B2_MU_0_HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_OFFSET 53 #define UNIFIED_PHYRX_HE_SIG_B2_OFDMA_0_HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_OFFSET \ 54 PHYRX_HE_SIG_B2_OFDMA_0_HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_OFFSET 55 #define UNIFIED_PHYRX_RSSI_LEGACY_3_RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS_OFFSET \ 56 PHYRX_RSSI_LEGACY_3_RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS_OFFSET 57 #define UNIFIED_RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET \ 58 RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET 59 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 60 RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET 61 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ 62 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET 63 #define UNIFIED_RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 64 RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET 65 #define UNIFIED_REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 66 REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET 67 #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC \ 68 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER 69 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ 70 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET 71 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 72 RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET 73 #define UNIFIED_TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 74 TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET 75 #define UNIFIED_TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 76 TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET 77 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET \ 78 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET 79 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB \ 80 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB 81 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK \ 82 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK 83 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB \ 84 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB 85 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK \ 86 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK 87 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB \ 88 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB 89 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK \ 90 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK 91 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB \ 92 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB 93 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK \ 94 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK 95 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB \ 96 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB 97 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK \ 98 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK 99 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_MASK \ 100 WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_MASK 101 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_OFFSET \ 102 WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_OFFSET 103 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_LSB \ 104 WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_LSB 105 106 #include "hal_6390_tx.h" 107 #include "hal_6390_rx.h" 108 #include <hal_generic_api.h> 109 #include <hal_wbm.h> 110 111 struct hal_hw_txrx_ops qca6390_hal_hw_txrx_ops = { 112 /* init and setup */ 113 hal_srng_dst_hw_init_generic, 114 hal_srng_src_hw_init_generic, 115 hal_reo_setup_generic, 116 hal_setup_link_idle_list_generic, 117 118 /* tx */ 119 hal_tx_desc_set_dscp_tid_table_id_6390, 120 hal_tx_set_dscp_tid_map_6390, 121 hal_tx_update_dscp_tid_6390, 122 hal_tx_desc_set_lmac_id_6390, 123 hal_tx_desc_set_buf_addr_generic, 124 hal_tx_desc_set_search_type_generic, 125 hal_tx_desc_set_search_index_generic, 126 hal_tx_comp_get_status_generic, 127 hal_tx_comp_get_release_reason_generic, 128 129 /* rx */ 130 hal_rx_msdu_start_nss_get_6390, 131 hal_rx_mon_hw_desc_get_mpdu_status_6390, 132 hal_rx_get_tlv_6390, 133 hal_rx_proc_phyrx_other_receive_info_tlv_6390, 134 hal_rx_dump_msdu_start_tlv_6390, 135 hal_rx_dump_msdu_end_tlv_6390, 136 hal_get_link_desc_size_6390, 137 hal_rx_mpdu_start_tid_get_6390, 138 hal_rx_msdu_start_reception_type_get_6390, 139 hal_rx_msdu_end_da_idx_get_6390, 140 hal_rx_msdu_desc_info_get_ptr_generic, 141 hal_rx_link_desc_msdu0_ptr_generic, 142 hal_reo_status_get_header_generic, 143 hal_rx_status_get_tlv_info_generic, 144 hal_rx_wbm_err_info_get_generic, 145 hal_rx_dump_mpdu_start_tlv_generic, 146 }; 147 148 struct hal_hw_srng_config hw_srng_table_6390[] = { 149 /* TODO: max_rings can populated by querying HW capabilities */ 150 { /* REO_DST */ 151 .start_ring_id = HAL_SRNG_REO2SW1, 152 .max_rings = 4, 153 .entry_size = sizeof(struct reo_destination_ring) >> 2, 154 .lmac_ring = FALSE, 155 .ring_dir = HAL_SRNG_DST_RING, 156 .reg_start = { 157 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR( 158 SEQ_WCSS_UMAC_REO_REG_OFFSET), 159 HWIO_REO_R2_REO2SW1_RING_HP_ADDR( 160 SEQ_WCSS_UMAC_REO_REG_OFFSET) 161 }, 162 .reg_size = { 163 HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(0) - 164 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(0), 165 HWIO_REO_R2_REO2SW2_RING_HP_ADDR(0) - 166 HWIO_REO_R2_REO2SW1_RING_HP_ADDR(0), 167 }, 168 .max_size = 169 HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_BMSK >> 170 HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_SHFT, 171 }, 172 { /* REO_EXCEPTION */ 173 /* Designating REO2TCL ring as exception ring. This ring is 174 * similar to other REO2SW rings though it is named as REO2TCL. 175 * Any of theREO2SW rings can be used as exception ring. 176 */ 177 .start_ring_id = HAL_SRNG_REO2TCL, 178 .max_rings = 1, 179 .entry_size = sizeof(struct reo_destination_ring) >> 2, 180 .lmac_ring = FALSE, 181 .ring_dir = HAL_SRNG_DST_RING, 182 .reg_start = { 183 HWIO_REO_R0_REO2TCL_RING_BASE_LSB_ADDR( 184 SEQ_WCSS_UMAC_REO_REG_OFFSET), 185 HWIO_REO_R2_REO2TCL_RING_HP_ADDR( 186 SEQ_WCSS_UMAC_REO_REG_OFFSET) 187 }, 188 /* Single ring - provide ring size if multiple rings of this 189 * type are supported 190 */ 191 .reg_size = {}, 192 .max_size = 193 HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_BMSK >> 194 HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_SHFT, 195 }, 196 { /* REO_REINJECT */ 197 .start_ring_id = HAL_SRNG_SW2REO, 198 .max_rings = 1, 199 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 200 .lmac_ring = FALSE, 201 .ring_dir = HAL_SRNG_SRC_RING, 202 .reg_start = { 203 HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR( 204 SEQ_WCSS_UMAC_REO_REG_OFFSET), 205 HWIO_REO_R2_SW2REO_RING_HP_ADDR( 206 SEQ_WCSS_UMAC_REO_REG_OFFSET) 207 }, 208 /* Single ring - provide ring size if multiple rings of this 209 * type are supported 210 */ 211 .reg_size = {}, 212 .max_size = HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_BMSK >> 213 HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_SHFT, 214 }, 215 { /* REO_CMD */ 216 .start_ring_id = HAL_SRNG_REO_CMD, 217 .max_rings = 1, 218 .entry_size = (sizeof(struct tlv_32_hdr) + 219 sizeof(struct reo_get_queue_stats)) >> 2, 220 .lmac_ring = FALSE, 221 .ring_dir = HAL_SRNG_SRC_RING, 222 .reg_start = { 223 HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR( 224 SEQ_WCSS_UMAC_REO_REG_OFFSET), 225 HWIO_REO_R2_REO_CMD_RING_HP_ADDR( 226 SEQ_WCSS_UMAC_REO_REG_OFFSET), 227 }, 228 /* Single ring - provide ring size if multiple rings of this 229 * type are supported 230 */ 231 .reg_size = {}, 232 .max_size = 233 HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_BMSK >> 234 HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_SHFT, 235 }, 236 { /* REO_STATUS */ 237 .start_ring_id = HAL_SRNG_REO_STATUS, 238 .max_rings = 1, 239 .entry_size = (sizeof(struct tlv_32_hdr) + 240 sizeof(struct reo_get_queue_stats_status)) >> 2, 241 .lmac_ring = FALSE, 242 .ring_dir = HAL_SRNG_DST_RING, 243 .reg_start = { 244 HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR( 245 SEQ_WCSS_UMAC_REO_REG_OFFSET), 246 HWIO_REO_R2_REO_STATUS_RING_HP_ADDR( 247 SEQ_WCSS_UMAC_REO_REG_OFFSET), 248 }, 249 /* Single ring - provide ring size if multiple rings of this 250 * type are supported 251 */ 252 .reg_size = {}, 253 .max_size = 254 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> 255 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, 256 }, 257 { /* TCL_DATA */ 258 .start_ring_id = HAL_SRNG_SW2TCL1, 259 .max_rings = 3, 260 .entry_size = (sizeof(struct tlv_32_hdr) + 261 sizeof(struct tcl_data_cmd)) >> 2, 262 .lmac_ring = FALSE, 263 .ring_dir = HAL_SRNG_SRC_RING, 264 .reg_start = { 265 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR( 266 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 267 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR( 268 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 269 }, 270 .reg_size = { 271 HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(0) - 272 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(0), 273 HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(0) - 274 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(0), 275 }, 276 .max_size = 277 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK >> 278 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT, 279 }, 280 { /* TCL_CMD */ 281 .start_ring_id = HAL_SRNG_SW2TCL_CMD, 282 .max_rings = 1, 283 .entry_size = (sizeof(struct tlv_32_hdr) + 284 sizeof(struct tcl_gse_cmd)) >> 2, 285 .lmac_ring = FALSE, 286 .ring_dir = HAL_SRNG_SRC_RING, 287 .reg_start = { 288 HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_ADDR( 289 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 290 HWIO_TCL_R2_SW2TCL_CMD_RING_HP_ADDR( 291 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 292 }, 293 /* Single ring - provide ring size if multiple rings of this 294 * type are supported 295 */ 296 .reg_size = {}, 297 .max_size = 298 HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RING_SIZE_BMSK >> 299 HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RING_SIZE_SHFT, 300 }, 301 { /* TCL_STATUS */ 302 .start_ring_id = HAL_SRNG_TCL_STATUS, 303 .max_rings = 1, 304 .entry_size = (sizeof(struct tlv_32_hdr) + 305 sizeof(struct tcl_status_ring)) >> 2, 306 .lmac_ring = FALSE, 307 .ring_dir = HAL_SRNG_DST_RING, 308 .reg_start = { 309 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR( 310 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 311 HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR( 312 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 313 }, 314 /* Single ring - provide ring size if multiple rings of this 315 * type are supported 316 */ 317 .reg_size = {}, 318 .max_size = 319 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_BMSK >> 320 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_SHFT, 321 }, 322 { /* CE_SRC */ 323 .start_ring_id = HAL_SRNG_CE_0_SRC, 324 .max_rings = 12, 325 .entry_size = sizeof(struct ce_src_desc) >> 2, 326 .lmac_ring = FALSE, 327 .ring_dir = HAL_SRNG_SRC_RING, 328 .reg_start = { 329 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR( 330 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET), 331 HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR( 332 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET), 333 }, 334 .reg_size = { 335 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET - 336 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET, 337 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET - 338 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET, 339 }, 340 .max_size = 341 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >> 342 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT, 343 }, 344 { /* CE_DST */ 345 .start_ring_id = HAL_SRNG_CE_0_DST, 346 .max_rings = 12, 347 .entry_size = 8 >> 2, 348 /*TODO: entry_size above should actually be 349 * sizeof(struct ce_dst_desc) >> 2, but couldn't find definition 350 * of struct ce_dst_desc in HW header files 351 */ 352 .lmac_ring = FALSE, 353 .ring_dir = HAL_SRNG_SRC_RING, 354 .reg_start = { 355 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR( 356 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 357 HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR( 358 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 359 }, 360 .reg_size = { 361 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 362 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 363 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 364 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 365 }, 366 .max_size = 367 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >> 368 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT, 369 }, 370 { /* CE_DST_STATUS */ 371 .start_ring_id = HAL_SRNG_CE_0_DST_STATUS, 372 .max_rings = 12, 373 .entry_size = sizeof(struct ce_stat_desc) >> 2, 374 .lmac_ring = FALSE, 375 .ring_dir = HAL_SRNG_DST_RING, 376 .reg_start = { 377 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR( 378 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 379 HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR( 380 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 381 }, 382 /* TODO: check destination status ring registers */ 383 .reg_size = { 384 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 385 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 386 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 387 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 388 }, 389 .max_size = 390 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> 391 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, 392 }, 393 { /* WBM_IDLE_LINK */ 394 .start_ring_id = HAL_SRNG_WBM_IDLE_LINK, 395 .max_rings = 1, 396 .entry_size = sizeof(struct wbm_link_descriptor_ring) >> 2, 397 .lmac_ring = FALSE, 398 .ring_dir = HAL_SRNG_SRC_RING, 399 .reg_start = { 400 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 401 HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 402 }, 403 /* Single ring - provide ring size if multiple rings of this 404 * type are supported 405 */ 406 .reg_size = {}, 407 .max_size = 408 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_BMSK >> 409 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_SHFT, 410 }, 411 { /* SW2WBM_RELEASE */ 412 .start_ring_id = HAL_SRNG_WBM_SW_RELEASE, 413 .max_rings = 1, 414 .entry_size = sizeof(struct wbm_release_ring) >> 2, 415 .lmac_ring = FALSE, 416 .ring_dir = HAL_SRNG_SRC_RING, 417 .reg_start = { 418 HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 419 HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 420 }, 421 /* Single ring - provide ring size if multiple rings of this 422 * type are supported 423 */ 424 .reg_size = {}, 425 .max_size = 426 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> 427 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, 428 }, 429 { /* WBM2SW_RELEASE */ 430 .start_ring_id = HAL_SRNG_WBM2SW0_RELEASE, 431 .max_rings = 4, 432 .entry_size = sizeof(struct wbm_release_ring) >> 2, 433 .lmac_ring = FALSE, 434 .ring_dir = HAL_SRNG_DST_RING, 435 .reg_start = { 436 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 437 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 438 }, 439 .reg_size = { 440 HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) - 441 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 442 HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) - 443 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 444 }, 445 .max_size = 446 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> 447 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, 448 }, 449 { /* RXDMA_BUF */ 450 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA0_BUF0, 451 #ifdef IPA_OFFLOAD 452 .max_rings = 3, 453 #else 454 .max_rings = 2, 455 #endif 456 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 457 .lmac_ring = TRUE, 458 .ring_dir = HAL_SRNG_SRC_RING, 459 /* reg_start is not set because LMAC rings are not accessed 460 * from host 461 */ 462 .reg_start = {}, 463 .reg_size = {}, 464 .max_size = HAL_RXDMA_MAX_RING_SIZE, 465 }, 466 { /* RXDMA_DST */ 467 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW0, 468 .max_rings = 1, 469 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 470 .lmac_ring = TRUE, 471 .ring_dir = HAL_SRNG_DST_RING, 472 /* reg_start is not set because LMAC rings are not accessed 473 * from host 474 */ 475 .reg_start = {}, 476 .reg_size = {}, 477 .max_size = HAL_RXDMA_MAX_RING_SIZE, 478 }, 479 { /* RXDMA_MONITOR_BUF */ 480 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA2_BUF, 481 .max_rings = 1, 482 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 483 .lmac_ring = TRUE, 484 .ring_dir = HAL_SRNG_SRC_RING, 485 /* reg_start is not set because LMAC rings are not accessed 486 * from host 487 */ 488 .reg_start = {}, 489 .reg_size = {}, 490 .max_size = HAL_RXDMA_MAX_RING_SIZE, 491 }, 492 { /* RXDMA_MONITOR_STATUS */ 493 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_STATBUF, 494 .max_rings = 1, 495 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 496 .lmac_ring = TRUE, 497 .ring_dir = HAL_SRNG_SRC_RING, 498 /* reg_start is not set because LMAC rings are not accessed 499 * from host 500 */ 501 .reg_start = {}, 502 .reg_size = {}, 503 .max_size = HAL_RXDMA_MAX_RING_SIZE, 504 }, 505 { /* RXDMA_MONITOR_DST */ 506 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW1, 507 .max_rings = 1, 508 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 509 .lmac_ring = TRUE, 510 .ring_dir = HAL_SRNG_DST_RING, 511 /* reg_start is not set because LMAC rings are not accessed 512 * from host 513 */ 514 .reg_start = {}, 515 .reg_size = {}, 516 .max_size = HAL_RXDMA_MAX_RING_SIZE, 517 }, 518 { /* RXDMA_MONITOR_DESC */ 519 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_DESC, 520 .max_rings = 1, 521 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 522 .lmac_ring = TRUE, 523 .ring_dir = HAL_SRNG_SRC_RING, 524 /* reg_start is not set because LMAC rings are not accessed 525 * from host 526 */ 527 .reg_start = {}, 528 .reg_size = {}, 529 .max_size = HAL_RXDMA_MAX_RING_SIZE, 530 }, 531 { /* DIR_BUF_RX_DMA_SRC */ 532 .start_ring_id = HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING, 533 .max_rings = 1, 534 .entry_size = 2, 535 .lmac_ring = TRUE, 536 .ring_dir = HAL_SRNG_SRC_RING, 537 /* reg_start is not set because LMAC rings are not accessed 538 * from host 539 */ 540 .reg_start = {}, 541 .reg_size = {}, 542 .max_size = HAL_RXDMA_MAX_RING_SIZE, 543 }, 544 #ifdef WLAN_FEATURE_CIF_CFR 545 { /* WIFI_POS_SRC */ 546 .start_ring_id = HAL_SRNG_WIFI_POS_SRC_DMA_RING, 547 .max_rings = 1, 548 .entry_size = sizeof(wmi_oem_dma_buf_release_entry) >> 2, 549 .lmac_ring = TRUE, 550 .ring_dir = HAL_SRNG_SRC_RING, 551 /* reg_start is not set because LMAC rings are not accessed 552 * from host 553 */ 554 .reg_start = {}, 555 .reg_size = {}, 556 .max_size = HAL_RXDMA_MAX_RING_SIZE, 557 }, 558 #endif 559 }; 560 561 int32_t hal_hw_reg_offset_qca6390[] = { 562 /* dst */ 563 REG_OFFSET(DST, HP), 564 REG_OFFSET(DST, TP), 565 REG_OFFSET(DST, ID), 566 REG_OFFSET(DST, MISC), 567 REG_OFFSET(DST, HP_ADDR_LSB), 568 REG_OFFSET(DST, HP_ADDR_MSB), 569 REG_OFFSET(DST, MSI1_BASE_LSB), 570 REG_OFFSET(DST, MSI1_BASE_MSB), 571 REG_OFFSET(DST, MSI1_DATA), 572 REG_OFFSET(DST, BASE_LSB), 573 REG_OFFSET(DST, BASE_MSB), 574 REG_OFFSET(DST, PRODUCER_INT_SETUP), 575 /* src */ 576 REG_OFFSET(SRC, HP), 577 REG_OFFSET(SRC, TP), 578 REG_OFFSET(SRC, ID), 579 REG_OFFSET(SRC, MISC), 580 REG_OFFSET(SRC, TP_ADDR_LSB), 581 REG_OFFSET(SRC, TP_ADDR_MSB), 582 REG_OFFSET(SRC, MSI1_BASE_LSB), 583 REG_OFFSET(SRC, MSI1_BASE_MSB), 584 REG_OFFSET(SRC, MSI1_DATA), 585 REG_OFFSET(SRC, BASE_LSB), 586 REG_OFFSET(SRC, BASE_MSB), 587 REG_OFFSET(SRC, CONSUMER_INT_SETUP_IX0), 588 REG_OFFSET(SRC, CONSUMER_INT_SETUP_IX1), 589 }; 590 591 /** 592 * hal_qca6390_attach() - Attach 6390 target specific hal_soc ops, 593 * offset and srng table 594 */ 595 void hal_qca6390_attach(struct hal_soc *hal_soc) 596 { 597 hal_soc->hw_srng_table = hw_srng_table_6390; 598 hal_soc->hal_hw_reg_offset = hal_hw_reg_offset_qca6390; 599 hal_soc->ops = &qca6390_hal_hw_txrx_ops; 600 } 601