1 /* 2 * Copyright (c) 2016-2020 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 #include "qdf_types.h" 19 #include "qdf_util.h" 20 #include "qdf_types.h" 21 #include "qdf_lock.h" 22 #include "qdf_mem.h" 23 #include "qdf_nbuf.h" 24 #include "hal_hw_headers.h" 25 #include "hal_internal.h" 26 #include "hal_api.h" 27 #include "target_type.h" 28 #include "wcss_version.h" 29 #include "qdf_module.h" 30 31 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_OFFSET \ 32 RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_OFFSET 33 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_MASK \ 34 RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_MASK 35 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_LSB \ 36 RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_LSB 37 #define UNIFIED_PHYRX_HT_SIG_0_HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS_OFFSET \ 38 PHYRX_HT_SIG_0_HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS_OFFSET 39 #define UNIFIED_PHYRX_L_SIG_B_0_L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS_OFFSET \ 40 PHYRX_L_SIG_B_0_L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS_OFFSET 41 #define UNIFIED_PHYRX_L_SIG_A_0_L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS_OFFSET \ 42 PHYRX_L_SIG_A_0_L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS_OFFSET 43 #define UNIFIED_PHYRX_VHT_SIG_A_0_VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS_OFFSET \ 44 PHYRX_VHT_SIG_A_0_VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS_OFFSET 45 #define UNIFIED_PHYRX_HE_SIG_A_SU_0_HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS_OFFSET \ 46 PHYRX_HE_SIG_A_SU_0_HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS_OFFSET 47 #define UNIFIED_PHYRX_HE_SIG_A_MU_DL_0_HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_OFFSET \ 48 PHYRX_HE_SIG_A_MU_DL_0_HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_OFFSET 49 #define UNIFIED_PHYRX_HE_SIG_B1_MU_0_HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_OFFSET \ 50 PHYRX_HE_SIG_B1_MU_0_HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_OFFSET 51 #define UNIFIED_PHYRX_HE_SIG_B2_MU_0_HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_OFFSET \ 52 PHYRX_HE_SIG_B2_MU_0_HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_OFFSET 53 #define UNIFIED_PHYRX_HE_SIG_B2_OFDMA_0_HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_OFFSET \ 54 PHYRX_HE_SIG_B2_OFDMA_0_HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_OFFSET 55 #define UNIFIED_PHYRX_RSSI_LEGACY_3_RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS_OFFSET \ 56 PHYRX_RSSI_LEGACY_3_RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS_OFFSET 57 #define UNIFIED_PHYRX_RSSI_LEGACY_19_RECEIVE_RSSI_INFO_PREAMBLE_RSSI_INFO_DETAILS_OFFSET \ 58 PHYRX_RSSI_LEGACY_19_RECEIVE_RSSI_INFO_PREAMBLE_RSSI_INFO_DETAILS_OFFSET 59 #define UNIFIED_RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET \ 60 RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET 61 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 62 RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET 63 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ 64 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET 65 #define UNIFIED_RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 66 RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET 67 #define UNIFIED_REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 68 REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET 69 #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC \ 70 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER 71 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ 72 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET 73 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 74 RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET 75 #define UNIFIED_TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 76 TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET 77 #define UNIFIED_TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 78 TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET 79 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET \ 80 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET 81 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB \ 82 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB 83 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK \ 84 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK 85 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB \ 86 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB 87 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK \ 88 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK 89 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB \ 90 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB 91 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK \ 92 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK 93 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB \ 94 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB 95 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK \ 96 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK 97 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB \ 98 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB 99 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK \ 100 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK 101 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_MASK \ 102 WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_MASK 103 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_OFFSET \ 104 WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_OFFSET 105 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_LSB \ 106 WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_LSB 107 108 #include "hal_6390_tx.h" 109 #include "hal_6390_rx.h" 110 #include <hal_generic_api.h> 111 #include <hal_wbm.h> 112 113 /** 114 * hal_rx_get_rx_fragment_number_6390(): Function to retrieve rx fragment number 115 * 116 * @nbuf: Network buffer 117 * Returns: rx fragment number 118 */ 119 static 120 uint8_t hal_rx_get_rx_fragment_number_6390(uint8_t *buf) 121 { 122 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 123 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 124 125 /* Return first 4 bits as fragment number */ 126 return (HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info) & 127 DOT11_SEQ_FRAG_MASK); 128 } 129 130 /** 131 * hal_rx_msdu_end_da_is_mcbc_get_6390(): API to check if pkt is MCBC 132 * from rx_msdu_end TLV 133 * 134 * @ buf: pointer to the start of RX PKT TLV headers 135 * Return: da_is_mcbc 136 */ 137 static uint8_t 138 hal_rx_msdu_end_da_is_mcbc_get_6390(uint8_t *buf) 139 { 140 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 141 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 142 143 return HAL_RX_MSDU_END_DA_IS_MCBC_GET(msdu_end); 144 } 145 146 /** 147 * hal_rx_msdu_end_sa_is_valid_get_6390(): API to get_6390 the 148 * sa_is_valid bit from rx_msdu_end TLV 149 * 150 * @ buf: pointer to the start of RX PKT TLV headers 151 * Return: sa_is_valid bit 152 */ 153 static uint8_t 154 hal_rx_msdu_end_sa_is_valid_get_6390(uint8_t *buf) 155 { 156 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 157 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 158 uint8_t sa_is_valid; 159 160 sa_is_valid = HAL_RX_MSDU_END_SA_IS_VALID_GET(msdu_end); 161 162 return sa_is_valid; 163 } 164 165 /** 166 * hal_rx_msdu_end_sa_idx_get_6390(): API to get_6390 the 167 * sa_idx from rx_msdu_end TLV 168 * 169 * @ buf: pointer to the start of RX PKT TLV headers 170 * Return: sa_idx (SA AST index) 171 */ 172 static 173 uint16_t hal_rx_msdu_end_sa_idx_get_6390(uint8_t *buf) 174 { 175 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 176 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 177 uint16_t sa_idx; 178 179 sa_idx = HAL_RX_MSDU_END_SA_IDX_GET(msdu_end); 180 181 return sa_idx; 182 } 183 184 /** 185 * hal_rx_desc_is_first_msdu_6390() - Check if first msdu 186 * 187 * @hal_soc_hdl: hal_soc handle 188 * @hw_desc_addr: hardware descriptor address 189 * 190 * Return: 0 - success/ non-zero failure 191 */ 192 static uint32_t hal_rx_desc_is_first_msdu_6390(void *hw_desc_addr) 193 { 194 struct rx_pkt_tlvs *rx_tlvs = (struct rx_pkt_tlvs *)hw_desc_addr; 195 struct rx_msdu_end *msdu_end = &rx_tlvs->msdu_end_tlv.rx_msdu_end; 196 197 return HAL_RX_GET(msdu_end, RX_MSDU_END_5, FIRST_MSDU); 198 } 199 200 /** 201 * hal_rx_msdu_end_l3_hdr_padding_get_6390(): API to get_6390 the 202 * l3_header padding from rx_msdu_end TLV 203 * 204 * @ buf: pointer to the start of RX PKT TLV headers 205 * Return: number of l3 header padding bytes 206 */ 207 static uint32_t hal_rx_msdu_end_l3_hdr_padding_get_6390(uint8_t *buf) 208 { 209 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 210 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 211 uint32_t l3_header_padding; 212 213 l3_header_padding = HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(msdu_end); 214 215 return l3_header_padding; 216 } 217 218 /* 219 * @ hal_rx_encryption_info_valid_6390: Returns encryption type. 220 * 221 * @ buf: rx_tlv_hdr of the received packet 222 * @ Return: encryption type 223 */ 224 static uint32_t hal_rx_encryption_info_valid_6390(uint8_t *buf) 225 { 226 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 227 struct rx_mpdu_start *mpdu_start = 228 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 229 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 230 uint32_t encryption_info = HAL_RX_MPDU_ENCRYPTION_INFO_VALID(mpdu_info); 231 232 return encryption_info; 233 } 234 235 /* 236 * @ hal_rx_print_pn_6390: Prints the PN of rx packet. 237 * 238 * @ buf: rx_tlv_hdr of the received packet 239 * @ Return: void 240 */ 241 static void hal_rx_print_pn_6390(uint8_t *buf) 242 { 243 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 244 struct rx_mpdu_start *mpdu_start = 245 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 246 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 247 248 uint32_t pn_31_0 = HAL_RX_MPDU_PN_31_0_GET(mpdu_info); 249 uint32_t pn_63_32 = HAL_RX_MPDU_PN_63_32_GET(mpdu_info); 250 uint32_t pn_95_64 = HAL_RX_MPDU_PN_95_64_GET(mpdu_info); 251 uint32_t pn_127_96 = HAL_RX_MPDU_PN_127_96_GET(mpdu_info); 252 253 hal_debug("PN number pn_127_96 0x%x pn_95_64 0x%x pn_63_32 0x%x pn_31_0 0x%x ", 254 pn_127_96, pn_95_64, pn_63_32, pn_31_0); 255 } 256 257 /** 258 * hal_rx_msdu_end_first_msduget_6390: API to get first msdu status 259 * from rx_msdu_end TLV 260 * 261 * @ buf: pointer to the start of RX PKT TLV headers 262 * Return: first_msdu 263 */ 264 static uint8_t hal_rx_msdu_end_first_msdu_get_6390(uint8_t *buf) 265 { 266 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 267 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 268 uint8_t first_msdu; 269 270 first_msdu = HAL_RX_MSDU_END_FIRST_MSDU_GET(msdu_end); 271 272 return first_msdu; 273 } 274 275 /** 276 * hal_rx_msdu_end_da_is_valid_get_6390: API to check if da is valid 277 * from rx_msdu_end TLV 278 * 279 * @ buf: pointer to the start of RX PKT TLV headers 280 * Return: da_is_valid 281 */ 282 static uint8_t hal_rx_msdu_end_da_is_valid_get_6390(uint8_t *buf) 283 { 284 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 285 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 286 uint8_t da_is_valid; 287 288 da_is_valid = HAL_RX_MSDU_END_DA_IS_VALID_GET(msdu_end); 289 290 return da_is_valid; 291 } 292 293 /** 294 * hal_rx_msdu_end_last_msdu_get_6390: API to get last msdu status 295 * from rx_msdu_end TLV 296 * 297 * @ buf: pointer to the start of RX PKT TLV headers 298 * Return: last_msdu 299 */ 300 static uint8_t hal_rx_msdu_end_last_msdu_get_6390(uint8_t *buf) 301 { 302 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 303 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 304 uint8_t last_msdu; 305 306 last_msdu = HAL_RX_MSDU_END_LAST_MSDU_GET(msdu_end); 307 308 return last_msdu; 309 } 310 311 /* 312 * hal_rx_get_mpdu_mac_ad4_valid_6390(): Retrieves if mpdu 4th addr is valid 313 * 314 * @nbuf: Network buffer 315 * Returns: value of mpdu 4th address valid field 316 */ 317 static bool hal_rx_get_mpdu_mac_ad4_valid_6390(uint8_t *buf) 318 { 319 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 320 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 321 bool ad4_valid = 0; 322 323 ad4_valid = HAL_RX_MPDU_GET_MAC_AD4_VALID(rx_mpdu_info); 324 325 return ad4_valid; 326 } 327 328 /** 329 * hal_rx_mpdu_start_sw_peer_id_get_6390: Retrieve sw peer_id 330 * @buf: network buffer 331 * 332 * Return: sw peer_id 333 */ 334 static uint32_t hal_rx_mpdu_start_sw_peer_id_get_6390(uint8_t *buf) 335 { 336 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 337 struct rx_mpdu_start *mpdu_start = 338 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 339 340 return HAL_RX_MPDU_INFO_SW_PEER_ID_GET( 341 &mpdu_start->rx_mpdu_info_details); 342 } 343 344 /* 345 * hal_rx_mpdu_get_to_ds_6390(): API to get the tods info 346 * from rx_mpdu_start 347 * 348 * @buf: pointer to the start of RX PKT TLV header 349 * Return: uint32_t(to_ds) 350 */ 351 static uint32_t hal_rx_mpdu_get_to_ds_6390(uint8_t *buf) 352 { 353 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 354 struct rx_mpdu_start *mpdu_start = 355 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 356 357 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 358 359 return HAL_RX_MPDU_GET_TODS(mpdu_info); 360 } 361 362 /* 363 * hal_rx_mpdu_get_fr_ds_6390(): API to get the from ds info 364 * from rx_mpdu_start 365 * 366 * @buf: pointer to the start of RX PKT TLV header 367 * Return: uint32_t(fr_ds) 368 */ 369 static uint32_t hal_rx_mpdu_get_fr_ds_6390(uint8_t *buf) 370 { 371 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 372 struct rx_mpdu_start *mpdu_start = 373 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 374 375 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 376 377 return HAL_RX_MPDU_GET_FROMDS(mpdu_info); 378 } 379 380 /* 381 * hal_rx_get_mpdu_frame_control_valid_6390(): Retrieves mpdu 382 * frame control valid 383 * 384 * @nbuf: Network buffer 385 * Returns: value of frame control valid field 386 */ 387 static uint8_t hal_rx_get_mpdu_frame_control_valid_6390(uint8_t *buf) 388 { 389 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 390 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 391 392 return HAL_RX_MPDU_GET_FRAME_CONTROL_VALID(rx_mpdu_info); 393 } 394 395 /* 396 * hal_rx_mpdu_get_addr1_6390(): API to check get address1 of the mpdu 397 * 398 * @buf: pointer to the start of RX PKT TLV headera 399 * @mac_addr: pointer to mac address 400 * Return: success/failure 401 */ 402 static QDF_STATUS hal_rx_mpdu_get_addr1_6390(uint8_t *buf, uint8_t *mac_addr) 403 { 404 struct __attribute__((__packed__)) hal_addr1 { 405 uint32_t ad1_31_0; 406 uint16_t ad1_47_32; 407 }; 408 409 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 410 struct rx_mpdu_start *mpdu_start = 411 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 412 413 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 414 struct hal_addr1 *addr = (struct hal_addr1 *)mac_addr; 415 uint32_t mac_addr_ad1_valid; 416 417 mac_addr_ad1_valid = HAL_RX_MPDU_MAC_ADDR_AD1_VALID_GET(mpdu_info); 418 419 if (mac_addr_ad1_valid) { 420 addr->ad1_31_0 = HAL_RX_MPDU_AD1_31_0_GET(mpdu_info); 421 addr->ad1_47_32 = HAL_RX_MPDU_AD1_47_32_GET(mpdu_info); 422 return QDF_STATUS_SUCCESS; 423 } 424 425 return QDF_STATUS_E_FAILURE; 426 } 427 428 /* 429 * hal_rx_mpdu_get_addr2_6390(): API to check get address2 of the mpdu 430 * in the packet 431 * 432 * @buf: pointer to the start of RX PKT TLV header 433 * @mac_addr: pointer to mac address 434 * Return: success/failure 435 */ 436 static QDF_STATUS hal_rx_mpdu_get_addr2_6390(uint8_t *buf, 437 uint8_t *mac_addr) 438 { 439 struct __attribute__((__packed__)) hal_addr2 { 440 uint16_t ad2_15_0; 441 uint32_t ad2_47_16; 442 }; 443 444 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 445 struct rx_mpdu_start *mpdu_start = 446 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 447 448 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 449 struct hal_addr2 *addr = (struct hal_addr2 *)mac_addr; 450 uint32_t mac_addr_ad2_valid; 451 452 mac_addr_ad2_valid = HAL_RX_MPDU_MAC_ADDR_AD2_VALID_GET(mpdu_info); 453 454 if (mac_addr_ad2_valid) { 455 addr->ad2_15_0 = HAL_RX_MPDU_AD2_15_0_GET(mpdu_info); 456 addr->ad2_47_16 = HAL_RX_MPDU_AD2_47_16_GET(mpdu_info); 457 return QDF_STATUS_SUCCESS; 458 } 459 460 return QDF_STATUS_E_FAILURE; 461 } 462 463 /* 464 * hal_rx_mpdu_get_addr3_6390(): API to get address3 of the mpdu 465 * in the packet 466 * 467 * @buf: pointer to the start of RX PKT TLV header 468 * @mac_addr: pointer to mac address 469 * Return: success/failure 470 */ 471 static QDF_STATUS hal_rx_mpdu_get_addr3_6390(uint8_t *buf, uint8_t *mac_addr) 472 { 473 struct __attribute__((__packed__)) hal_addr3 { 474 uint32_t ad3_31_0; 475 uint16_t ad3_47_32; 476 }; 477 478 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 479 struct rx_mpdu_start *mpdu_start = 480 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 481 482 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 483 struct hal_addr3 *addr = (struct hal_addr3 *)mac_addr; 484 uint32_t mac_addr_ad3_valid; 485 486 mac_addr_ad3_valid = HAL_RX_MPDU_MAC_ADDR_AD3_VALID_GET(mpdu_info); 487 488 if (mac_addr_ad3_valid) { 489 addr->ad3_31_0 = HAL_RX_MPDU_AD3_31_0_GET(mpdu_info); 490 addr->ad3_47_32 = HAL_RX_MPDU_AD3_47_32_GET(mpdu_info); 491 return QDF_STATUS_SUCCESS; 492 } 493 494 return QDF_STATUS_E_FAILURE; 495 } 496 497 /* 498 * hal_rx_mpdu_get_addr4_6390(): API to get address4 of the mpdu 499 * in the packet 500 * 501 * @buf: pointer to the start of RX PKT TLV header 502 * @mac_addr: pointer to mac address 503 * Return: success/failure 504 */ 505 static QDF_STATUS hal_rx_mpdu_get_addr4_6390(uint8_t *buf, uint8_t *mac_addr) 506 { 507 struct __attribute__((__packed__)) hal_addr4 { 508 uint32_t ad4_31_0; 509 uint16_t ad4_47_32; 510 }; 511 512 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 513 struct rx_mpdu_start *mpdu_start = 514 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 515 516 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 517 struct hal_addr4 *addr = (struct hal_addr4 *)mac_addr; 518 uint32_t mac_addr_ad4_valid; 519 520 mac_addr_ad4_valid = HAL_RX_MPDU_MAC_ADDR_AD4_VALID_GET(mpdu_info); 521 522 if (mac_addr_ad4_valid) { 523 addr->ad4_31_0 = HAL_RX_MPDU_AD4_31_0_GET(mpdu_info); 524 addr->ad4_47_32 = HAL_RX_MPDU_AD4_47_32_GET(mpdu_info); 525 return QDF_STATUS_SUCCESS; 526 } 527 528 return QDF_STATUS_E_FAILURE; 529 } 530 531 /* 532 * hal_rx_get_mpdu_sequence_control_valid_6390(): Get mpdu 533 * sequence control valid 534 * 535 * @nbuf: Network buffer 536 * Returns: value of sequence control valid field 537 */ 538 static uint8_t hal_rx_get_mpdu_sequence_control_valid_6390(uint8_t *buf) 539 { 540 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 541 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 542 543 return HAL_RX_MPDU_GET_SEQUENCE_CONTROL_VALID(rx_mpdu_info); 544 } 545 546 /** 547 * hal_rx_is_unicast_6390: check packet is unicast frame or not. 548 * 549 * @ buf: pointer to rx pkt TLV. 550 * 551 * Return: true on unicast. 552 */ 553 static bool hal_rx_is_unicast_6390(uint8_t *buf) 554 { 555 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 556 struct rx_mpdu_start *mpdu_start = 557 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 558 uint32_t grp_id; 559 uint8_t *rx_mpdu_info = (uint8_t *)&mpdu_start->rx_mpdu_info_details; 560 561 grp_id = (_HAL_MS((*_OFFSET_TO_WORD_PTR((rx_mpdu_info), 562 RX_MPDU_INFO_0_SW_FRAME_GROUP_ID_OFFSET)), 563 RX_MPDU_INFO_0_SW_FRAME_GROUP_ID_MASK, 564 RX_MPDU_INFO_0_SW_FRAME_GROUP_ID_LSB)); 565 566 return (HAL_MPDU_SW_FRAME_GROUP_UNICAST_DATA == grp_id) ? true : false; 567 } 568 569 /** 570 * hal_rx_tid_get_6390: get tid based on qos control valid. 571 * @hal_soc_hdl: hal soc handle 572 * @buf: pointer to rx pkt TLV. 573 * 574 * Return: tid 575 */ 576 static uint32_t hal_rx_tid_get_6390(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 577 { 578 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 579 struct rx_mpdu_start *mpdu_start = 580 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 581 uint8_t *rx_mpdu_info = (uint8_t *)&mpdu_start->rx_mpdu_info_details; 582 uint8_t qos_control_valid = 583 (_HAL_MS((*_OFFSET_TO_WORD_PTR((rx_mpdu_info), 584 RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_OFFSET)), 585 RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_MASK, 586 RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_LSB)); 587 588 if (qos_control_valid) 589 return hal_rx_mpdu_start_tid_get_6390(buf); 590 591 return HAL_RX_NON_QOS_TID; 592 } 593 594 /** 595 * hal_rx_hw_desc_get_ppduid_get_6390(): retrieve ppdu id 596 * @rx_tlv_hdr: start address of rx_pkt_tlvs 597 * @rxdma_dst_ring_desc: Rx HW descriptor 598 * 599 * Return: ppdu id 600 */ 601 static uint32_t hal_rx_hw_desc_get_ppduid_get_6390(void *rx_tlv_hdr, 602 void *rxdma_dst_ring_desc) 603 { 604 struct rx_mpdu_info *rx_mpdu_info; 605 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)rx_tlv_hdr; 606 607 rx_mpdu_info = 608 &rx_desc->mpdu_start_tlv.rx_mpdu_start.rx_mpdu_info_details; 609 610 return HAL_RX_GET(rx_mpdu_info, RX_MPDU_INFO_0, PHY_PPDU_ID); 611 } 612 613 /** 614 * hal_reo_status_get_header_6390 - Process reo desc info 615 * @d - Pointer to reo descriptior 616 * @b - tlv type info 617 * @h1 - Pointer to hal_reo_status_header where info to be stored 618 * 619 * Return - none. 620 * 621 */ 622 static void hal_reo_status_get_header_6390(uint32_t *d, int b, void *h1) 623 { 624 uint32_t val1 = 0; 625 struct hal_reo_status_header *h = 626 (struct hal_reo_status_header *)h1; 627 628 switch (b) { 629 case HAL_REO_QUEUE_STATS_STATUS_TLV: 630 val1 = d[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_0, 631 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 632 break; 633 case HAL_REO_FLUSH_QUEUE_STATUS_TLV: 634 val1 = d[HAL_OFFSET_DW(REO_FLUSH_QUEUE_STATUS_0, 635 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 636 break; 637 case HAL_REO_FLUSH_CACHE_STATUS_TLV: 638 val1 = d[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_0, 639 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 640 break; 641 case HAL_REO_UNBLK_CACHE_STATUS_TLV: 642 val1 = d[HAL_OFFSET_DW(REO_UNBLOCK_CACHE_STATUS_0, 643 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 644 break; 645 case HAL_REO_TIMOUT_LIST_STATUS_TLV: 646 val1 = d[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_0, 647 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 648 break; 649 case HAL_REO_DESC_THRES_STATUS_TLV: 650 val1 = 651 d[HAL_OFFSET_DW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0, 652 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 653 break; 654 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: 655 val1 = d[HAL_OFFSET_DW(REO_UPDATE_RX_REO_QUEUE_STATUS_0, 656 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 657 break; 658 default: 659 qdf_nofl_err("ERROR: Unknown tlv\n"); 660 break; 661 } 662 h->cmd_num = 663 HAL_GET_FIELD( 664 UNIFORM_REO_STATUS_HEADER_0, REO_STATUS_NUMBER, 665 val1); 666 h->exec_time = 667 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_0, 668 CMD_EXECUTION_TIME, val1); 669 h->status = 670 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_0, 671 REO_CMD_EXECUTION_STATUS, val1); 672 switch (b) { 673 case HAL_REO_QUEUE_STATS_STATUS_TLV: 674 val1 = d[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_1, 675 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 676 break; 677 case HAL_REO_FLUSH_QUEUE_STATUS_TLV: 678 val1 = d[HAL_OFFSET_DW(REO_FLUSH_QUEUE_STATUS_1, 679 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 680 break; 681 case HAL_REO_FLUSH_CACHE_STATUS_TLV: 682 val1 = d[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_1, 683 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 684 break; 685 case HAL_REO_UNBLK_CACHE_STATUS_TLV: 686 val1 = d[HAL_OFFSET_DW(REO_UNBLOCK_CACHE_STATUS_1, 687 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 688 break; 689 case HAL_REO_TIMOUT_LIST_STATUS_TLV: 690 val1 = d[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_1, 691 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 692 break; 693 case HAL_REO_DESC_THRES_STATUS_TLV: 694 val1 = 695 d[HAL_OFFSET_DW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_1, 696 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 697 break; 698 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: 699 val1 = d[HAL_OFFSET_DW(REO_UPDATE_RX_REO_QUEUE_STATUS_1, 700 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 701 break; 702 default: 703 qdf_nofl_err("ERROR: Unknown tlv\n"); 704 break; 705 } 706 h->tstamp = 707 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_1, TIMESTAMP, val1); 708 } 709 710 /** 711 * hal_rx_mpdu_start_mpdu_qos_control_valid_get_6390(): 712 * Retrieve qos control valid bit from the tlv. 713 * @buf: pointer to rx pkt TLV. 714 * 715 * Return: qos control value. 716 */ 717 static inline uint32_t 718 hal_rx_mpdu_start_mpdu_qos_control_valid_get_6390(uint8_t *buf) 719 { 720 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 721 struct rx_mpdu_start *mpdu_start = 722 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 723 724 return HAL_RX_MPDU_INFO_QOS_CONTROL_VALID_GET( 725 &mpdu_start->rx_mpdu_info_details); 726 } 727 728 /** 729 * hal_rx_msdu_end_sa_sw_peer_id_get_6390(): API to get the 730 * sa_sw_peer_id from rx_msdu_end TLV 731 * @buf: pointer to the start of RX PKT TLV headers 732 * 733 * Return: sa_sw_peer_id index 734 */ 735 static inline uint32_t 736 hal_rx_msdu_end_sa_sw_peer_id_get_6390(uint8_t *buf) 737 { 738 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 739 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 740 741 return HAL_RX_MSDU_END_SA_SW_PEER_ID_GET(msdu_end); 742 } 743 744 /** 745 * hal_tx_desc_set_mesh_en_6390 - Set mesh_enable flag in Tx descriptor 746 * @desc: Handle to Tx Descriptor 747 * @en: For raw WiFi frames, this indicates transmission to a mesh STA, 748 * enabling the interpretation of the 'Mesh Control Present' bit 749 * (bit 8) of QoS Control (otherwise this bit is ignored), 750 * For native WiFi frames, this indicates that a 'Mesh Control' field 751 * is present between the header and the LLC. 752 * 753 * Return: void 754 */ 755 static inline 756 void hal_tx_desc_set_mesh_en_6390(void *desc, uint8_t en) 757 { 758 HAL_SET_FLD(desc, TCL_DATA_CMD_4, MESH_ENABLE) |= 759 HAL_TX_SM(TCL_DATA_CMD_4, MESH_ENABLE, en); 760 } 761 762 static 763 void *hal_rx_msdu0_buffer_addr_lsb_6390(void *link_desc_va) 764 { 765 return (void *)HAL_RX_MSDU0_BUFFER_ADDR_LSB(link_desc_va); 766 } 767 768 static 769 void *hal_rx_msdu_desc_info_ptr_get_6390(void *msdu0) 770 { 771 return (void *)HAL_RX_MSDU_DESC_INFO_PTR_GET(msdu0); 772 } 773 774 static 775 void *hal_ent_mpdu_desc_info_6390(void *ent_ring_desc) 776 { 777 return (void *)HAL_ENT_MPDU_DESC_INFO(ent_ring_desc); 778 } 779 780 static 781 void *hal_dst_mpdu_desc_info_6390(void *dst_ring_desc) 782 { 783 return (void *)HAL_DST_MPDU_DESC_INFO(dst_ring_desc); 784 } 785 786 static 787 uint8_t hal_rx_get_fc_valid_6390(uint8_t *buf) 788 { 789 return HAL_RX_GET_FC_VALID(buf); 790 } 791 792 static uint8_t hal_rx_get_to_ds_flag_6390(uint8_t *buf) 793 { 794 return HAL_RX_GET_TO_DS_FLAG(buf); 795 } 796 797 static uint8_t hal_rx_get_mac_addr2_valid_6390(uint8_t *buf) 798 { 799 return HAL_RX_GET_MAC_ADDR2_VALID(buf); 800 } 801 802 static uint8_t hal_rx_get_filter_category_6390(uint8_t *buf) 803 { 804 return HAL_RX_GET_FILTER_CATEGORY(buf); 805 } 806 807 static uint32_t 808 hal_rx_get_ppdu_id_6390(uint8_t *buf) 809 { 810 return HAL_RX_GET_PPDU_ID(buf); 811 } 812 813 /** 814 * hal_reo_config_6390(): Set reo config parameters 815 * @soc: hal soc handle 816 * @reg_val: value to be set 817 * @reo_params: reo parameters 818 * 819 * Return: void 820 */ 821 static 822 void hal_reo_config_6390(struct hal_soc *soc, 823 uint32_t reg_val, 824 struct hal_reo_params *reo_params) 825 { 826 HAL_REO_R0_CONFIG(soc, reg_val, reo_params); 827 } 828 829 /** 830 * hal_rx_msdu_desc_info_get_ptr_6390() - Get msdu desc info ptr 831 * @msdu_details_ptr - Pointer to msdu_details_ptr 832 * Return - Pointer to rx_msdu_desc_info structure. 833 * 834 */ 835 static void *hal_rx_msdu_desc_info_get_ptr_6390(void *msdu_details_ptr) 836 { 837 return HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr); 838 } 839 840 /** 841 * hal_rx_link_desc_msdu0_ptr_6390 - Get pointer to rx_msdu details 842 * @link_desc - Pointer to link desc 843 * Return - Pointer to rx_msdu_details structure 844 * 845 */ 846 static void *hal_rx_link_desc_msdu0_ptr_6390(void *link_desc) 847 { 848 return HAL_RX_LINK_DESC_MSDU0_PTR(link_desc); 849 } 850 851 /** 852 * hal_rx_msdu_flow_idx_get_6390: API to get flow index 853 * from rx_msdu_end TLV 854 * @buf: pointer to the start of RX PKT TLV headers 855 * 856 * Return: flow index value from MSDU END TLV 857 */ 858 static inline uint32_t hal_rx_msdu_flow_idx_get_6390(uint8_t *buf) 859 { 860 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 861 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 862 863 return HAL_RX_MSDU_END_FLOW_IDX_GET(msdu_end); 864 } 865 866 /** 867 * hal_rx_msdu_flow_idx_invalid_6390: API to get flow index invalid 868 * from rx_msdu_end TLV 869 * @buf: pointer to the start of RX PKT TLV headers 870 * 871 * Return: flow index invalid value from MSDU END TLV 872 */ 873 static bool hal_rx_msdu_flow_idx_invalid_6390(uint8_t *buf) 874 { 875 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 876 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 877 878 return HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(msdu_end); 879 } 880 881 /** 882 * hal_rx_msdu_flow_idx_timeout_6390: API to get flow index timeout 883 * from rx_msdu_end TLV 884 * @buf: pointer to the start of RX PKT TLV headers 885 * 886 * Return: flow index timeout value from MSDU END TLV 887 */ 888 static bool hal_rx_msdu_flow_idx_timeout_6390(uint8_t *buf) 889 { 890 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 891 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 892 893 return HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(msdu_end); 894 } 895 896 /** 897 * hal_rx_msdu_fse_metadata_get_6390: API to get FSE metadata 898 * from rx_msdu_end TLV 899 * @buf: pointer to the start of RX PKT TLV headers 900 * 901 * Return: fse metadata value from MSDU END TLV 902 */ 903 static uint32_t hal_rx_msdu_fse_metadata_get_6390(uint8_t *buf) 904 { 905 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 906 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 907 908 return HAL_RX_MSDU_END_FSE_METADATA_GET(msdu_end); 909 } 910 911 /** 912 * hal_rx_msdu_cce_metadata_get_6390: API to get CCE metadata 913 * from rx_msdu_end TLV 914 * @buf: pointer to the start of RX PKT TLV headers 915 * 916 * Return: cce metadata 917 */ 918 static uint16_t 919 hal_rx_msdu_cce_metadata_get_6390(uint8_t *buf) 920 { 921 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 922 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 923 924 return HAL_RX_MSDU_END_CCE_METADATA_GET(msdu_end); 925 } 926 927 /** 928 * hal_rx_msdu_get_flow_params_6390: API to get flow index, flow index invalid 929 * and flow index timeout from rx_msdu_end TLV 930 * @buf: pointer to the start of RX PKT TLV headers 931 * @flow_invalid: pointer to return value of flow_idx_valid 932 * @flow_timeout: pointer to return value of flow_idx_timeout 933 * @flow_index: pointer to return value of flow_idx 934 * 935 * Return: none 936 */ 937 static inline void 938 hal_rx_msdu_get_flow_params_6390(uint8_t *buf, 939 bool *flow_invalid, 940 bool *flow_timeout, 941 uint32_t *flow_index) 942 { 943 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 944 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 945 946 *flow_invalid = HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(msdu_end); 947 *flow_timeout = HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(msdu_end); 948 *flow_index = HAL_RX_MSDU_END_FLOW_IDX_GET(msdu_end); 949 } 950 951 /** 952 * hal_rx_tlv_get_tcp_chksum_6390() - API to get tcp checksum 953 * @buf: rx_tlv_hdr 954 * 955 * Return: tcp checksum 956 */ 957 static uint16_t 958 hal_rx_tlv_get_tcp_chksum_6390(uint8_t *buf) 959 { 960 return HAL_RX_TLV_GET_TCP_CHKSUM(buf); 961 } 962 963 /** 964 * hal_rx_get_rx_sequence_6390(): Function to retrieve rx sequence number 965 * 966 * @nbuf: Network buffer 967 * Returns: rx sequence number 968 */ 969 static 970 uint16_t hal_rx_get_rx_sequence_6390(uint8_t *buf) 971 { 972 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 973 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 974 975 return HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info); 976 } 977 978 /** 979 * hal_get_window_address_6390(): Function to get hp/tp address 980 * @hal_soc: Pointer to hal_soc 981 * @addr: address offset of register 982 * 983 * Return: modified address offset of register 984 */ 985 static inline qdf_iomem_t hal_get_window_address_6390(struct hal_soc *hal_soc, 986 qdf_iomem_t addr) 987 { 988 return addr; 989 } 990 991 /** 992 * hal_reo_set_err_dst_remap_6390(): Function to set REO error destination 993 * ring remap register 994 * @hal_soc: Pointer to hal_soc 995 * 996 * Return: none. 997 */ 998 static void 999 hal_reo_set_err_dst_remap_6390(void *hal_soc) 1000 { 1001 /* 1002 * Set REO error 2k jump (error code 5) / OOR (error code 7) 1003 * frame routed to REO2TCL ring. 1004 */ 1005 uint32_t dst_remap_ix0 = 1006 HAL_REO_ERR_REMAP_IX0(REO_REMAP_RELEASE, 0) | 1007 HAL_REO_ERR_REMAP_IX0(REO_REMAP_RELEASE, 1) | 1008 HAL_REO_ERR_REMAP_IX0(REO_REMAP_RELEASE, 2) | 1009 HAL_REO_ERR_REMAP_IX0(REO_REMAP_RELEASE, 3) | 1010 HAL_REO_ERR_REMAP_IX0(REO_REMAP_RELEASE, 4) | 1011 HAL_REO_ERR_REMAP_IX0(REO_REMAP_TCL, 5) | 1012 HAL_REO_ERR_REMAP_IX0(REO_REMAP_RELEASE, 6) | 1013 HAL_REO_ERR_REMAP_IX0(REO_REMAP_TCL, 7) | 1014 HAL_REO_ERR_REMAP_IX0(REO_REMAP_RELEASE, 8) | 1015 HAL_REO_ERR_REMAP_IX0(REO_REMAP_RELEASE, 9); 1016 1017 HAL_REG_WRITE(hal_soc, 1018 HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ADDR( 1019 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1020 dst_remap_ix0); 1021 1022 hal_info("HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0 0x%x", 1023 HAL_REG_READ( 1024 hal_soc, 1025 HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ADDR( 1026 SEQ_WCSS_UMAC_REO_REG_OFFSET))); 1027 } 1028 1029 struct hal_hw_txrx_ops qca6390_hal_hw_txrx_ops = { 1030 /* init and setup */ 1031 hal_srng_dst_hw_init_generic, 1032 hal_srng_src_hw_init_generic, 1033 hal_get_hw_hptp_generic, 1034 hal_reo_setup_generic, 1035 hal_setup_link_idle_list_generic, 1036 hal_get_window_address_6390, 1037 hal_reo_set_err_dst_remap_6390, 1038 1039 /* tx */ 1040 hal_tx_desc_set_dscp_tid_table_id_6390, 1041 hal_tx_set_dscp_tid_map_6390, 1042 hal_tx_update_dscp_tid_6390, 1043 hal_tx_desc_set_lmac_id_6390, 1044 hal_tx_desc_set_buf_addr_generic, 1045 hal_tx_desc_set_search_type_generic, 1046 hal_tx_desc_set_search_index_generic, 1047 hal_tx_desc_set_cache_set_num_generic, 1048 hal_tx_comp_get_status_generic, 1049 hal_tx_comp_get_release_reason_generic, 1050 hal_get_wbm_internal_error_generic, 1051 hal_tx_desc_set_mesh_en_6390, 1052 hal_tx_init_cmd_credit_ring_6390, 1053 1054 /* rx */ 1055 hal_rx_msdu_start_nss_get_6390, 1056 hal_rx_mon_hw_desc_get_mpdu_status_6390, 1057 hal_rx_get_tlv_6390, 1058 hal_rx_proc_phyrx_other_receive_info_tlv_6390, 1059 hal_rx_dump_msdu_start_tlv_6390, 1060 hal_rx_dump_msdu_end_tlv_6390, 1061 hal_get_link_desc_size_6390, 1062 hal_rx_mpdu_start_tid_get_6390, 1063 hal_rx_msdu_start_reception_type_get_6390, 1064 hal_rx_msdu_end_da_idx_get_6390, 1065 hal_rx_msdu_desc_info_get_ptr_6390, 1066 hal_rx_link_desc_msdu0_ptr_6390, 1067 hal_reo_status_get_header_6390, 1068 hal_rx_status_get_tlv_info_generic, 1069 hal_rx_wbm_err_info_get_generic, 1070 hal_rx_dump_mpdu_start_tlv_generic, 1071 1072 hal_tx_set_pcp_tid_map_generic, 1073 hal_tx_update_pcp_tid_generic, 1074 hal_tx_update_tidmap_prty_generic, 1075 hal_rx_get_rx_fragment_number_6390, 1076 hal_rx_msdu_end_da_is_mcbc_get_6390, 1077 hal_rx_msdu_end_sa_is_valid_get_6390, 1078 hal_rx_msdu_end_sa_idx_get_6390, 1079 hal_rx_desc_is_first_msdu_6390, 1080 hal_rx_msdu_end_l3_hdr_padding_get_6390, 1081 hal_rx_encryption_info_valid_6390, 1082 hal_rx_print_pn_6390, 1083 hal_rx_msdu_end_first_msdu_get_6390, 1084 hal_rx_msdu_end_da_is_valid_get_6390, 1085 hal_rx_msdu_end_last_msdu_get_6390, 1086 hal_rx_get_mpdu_mac_ad4_valid_6390, 1087 hal_rx_mpdu_start_sw_peer_id_get_6390, 1088 hal_rx_mpdu_get_to_ds_6390, 1089 hal_rx_mpdu_get_fr_ds_6390, 1090 hal_rx_get_mpdu_frame_control_valid_6390, 1091 hal_rx_mpdu_get_addr1_6390, 1092 hal_rx_mpdu_get_addr2_6390, 1093 hal_rx_mpdu_get_addr3_6390, 1094 hal_rx_mpdu_get_addr4_6390, 1095 hal_rx_get_mpdu_sequence_control_valid_6390, 1096 hal_rx_is_unicast_6390, 1097 hal_rx_tid_get_6390, 1098 hal_rx_hw_desc_get_ppduid_get_6390, 1099 hal_rx_mpdu_start_mpdu_qos_control_valid_get_6390, 1100 hal_rx_msdu_end_sa_sw_peer_id_get_6390, 1101 hal_rx_msdu0_buffer_addr_lsb_6390, 1102 hal_rx_msdu_desc_info_ptr_get_6390, 1103 hal_ent_mpdu_desc_info_6390, 1104 hal_dst_mpdu_desc_info_6390, 1105 hal_rx_get_fc_valid_6390, 1106 hal_rx_get_to_ds_flag_6390, 1107 hal_rx_get_mac_addr2_valid_6390, 1108 hal_rx_get_filter_category_6390, 1109 hal_rx_get_ppdu_id_6390, 1110 hal_reo_config_6390, 1111 hal_rx_msdu_flow_idx_get_6390, 1112 hal_rx_msdu_flow_idx_invalid_6390, 1113 hal_rx_msdu_flow_idx_timeout_6390, 1114 hal_rx_msdu_fse_metadata_get_6390, 1115 hal_rx_msdu_cce_metadata_get_6390, 1116 hal_rx_msdu_get_flow_params_6390, 1117 hal_rx_tlv_get_tcp_chksum_6390, 1118 hal_rx_get_rx_sequence_6390, 1119 NULL, 1120 NULL, 1121 /* rx - msdu end fast path info fields */ 1122 hal_rx_msdu_packet_metadata_get_generic, 1123 NULL, 1124 NULL, 1125 NULL, 1126 NULL, 1127 NULL, 1128 NULL, 1129 NULL, 1130 NULL, 1131 NULL, 1132 1133 /* rx - TLV struct offsets */ 1134 hal_rx_msdu_end_offset_get_generic, 1135 hal_rx_attn_offset_get_generic, 1136 hal_rx_msdu_start_offset_get_generic, 1137 hal_rx_mpdu_start_offset_get_generic, 1138 hal_rx_mpdu_end_offset_get_generic 1139 }; 1140 1141 struct hal_hw_srng_config hw_srng_table_6390[] = { 1142 /* TODO: max_rings can populated by querying HW capabilities */ 1143 { /* REO_DST */ 1144 .start_ring_id = HAL_SRNG_REO2SW1, 1145 .max_rings = 4, 1146 .entry_size = sizeof(struct reo_destination_ring) >> 2, 1147 .lmac_ring = FALSE, 1148 .ring_dir = HAL_SRNG_DST_RING, 1149 .reg_start = { 1150 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR( 1151 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1152 HWIO_REO_R2_REO2SW1_RING_HP_ADDR( 1153 SEQ_WCSS_UMAC_REO_REG_OFFSET) 1154 }, 1155 .reg_size = { 1156 HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(0) - 1157 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(0), 1158 HWIO_REO_R2_REO2SW2_RING_HP_ADDR(0) - 1159 HWIO_REO_R2_REO2SW1_RING_HP_ADDR(0), 1160 }, 1161 .max_size = 1162 HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_BMSK >> 1163 HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_SHFT, 1164 }, 1165 { /* REO_EXCEPTION */ 1166 /* Designating REO2TCL ring as exception ring. This ring is 1167 * similar to other REO2SW rings though it is named as REO2TCL. 1168 * Any of theREO2SW rings can be used as exception ring. 1169 */ 1170 .start_ring_id = HAL_SRNG_REO2TCL, 1171 .max_rings = 1, 1172 .entry_size = sizeof(struct reo_destination_ring) >> 2, 1173 .lmac_ring = FALSE, 1174 .ring_dir = HAL_SRNG_DST_RING, 1175 .reg_start = { 1176 HWIO_REO_R0_REO2TCL_RING_BASE_LSB_ADDR( 1177 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1178 HWIO_REO_R2_REO2TCL_RING_HP_ADDR( 1179 SEQ_WCSS_UMAC_REO_REG_OFFSET) 1180 }, 1181 /* Single ring - provide ring size if multiple rings of this 1182 * type are supported 1183 */ 1184 .reg_size = {}, 1185 .max_size = 1186 HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_BMSK >> 1187 HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_SHFT, 1188 }, 1189 { /* REO_REINJECT */ 1190 .start_ring_id = HAL_SRNG_SW2REO, 1191 .max_rings = 1, 1192 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 1193 .lmac_ring = FALSE, 1194 .ring_dir = HAL_SRNG_SRC_RING, 1195 .reg_start = { 1196 HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR( 1197 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1198 HWIO_REO_R2_SW2REO_RING_HP_ADDR( 1199 SEQ_WCSS_UMAC_REO_REG_OFFSET) 1200 }, 1201 /* Single ring - provide ring size if multiple rings of this 1202 * type are supported 1203 */ 1204 .reg_size = {}, 1205 .max_size = HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_BMSK >> 1206 HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_SHFT, 1207 }, 1208 { /* REO_CMD */ 1209 .start_ring_id = HAL_SRNG_REO_CMD, 1210 .max_rings = 1, 1211 .entry_size = (sizeof(struct tlv_32_hdr) + 1212 sizeof(struct reo_get_queue_stats)) >> 2, 1213 .lmac_ring = FALSE, 1214 .ring_dir = HAL_SRNG_SRC_RING, 1215 .reg_start = { 1216 HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR( 1217 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1218 HWIO_REO_R2_REO_CMD_RING_HP_ADDR( 1219 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1220 }, 1221 /* Single ring - provide ring size if multiple rings of this 1222 * type are supported 1223 */ 1224 .reg_size = {}, 1225 .max_size = 1226 HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_BMSK >> 1227 HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_SHFT, 1228 }, 1229 { /* REO_STATUS */ 1230 .start_ring_id = HAL_SRNG_REO_STATUS, 1231 .max_rings = 1, 1232 .entry_size = (sizeof(struct tlv_32_hdr) + 1233 sizeof(struct reo_get_queue_stats_status)) >> 2, 1234 .lmac_ring = FALSE, 1235 .ring_dir = HAL_SRNG_DST_RING, 1236 .reg_start = { 1237 HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR( 1238 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1239 HWIO_REO_R2_REO_STATUS_RING_HP_ADDR( 1240 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1241 }, 1242 /* Single ring - provide ring size if multiple rings of this 1243 * type are supported 1244 */ 1245 .reg_size = {}, 1246 .max_size = 1247 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> 1248 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, 1249 }, 1250 { /* TCL_DATA */ 1251 .start_ring_id = HAL_SRNG_SW2TCL1, 1252 .max_rings = 3, 1253 .entry_size = (sizeof(struct tlv_32_hdr) + 1254 sizeof(struct tcl_data_cmd)) >> 2, 1255 .lmac_ring = FALSE, 1256 .ring_dir = HAL_SRNG_SRC_RING, 1257 .reg_start = { 1258 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR( 1259 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1260 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR( 1261 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1262 }, 1263 .reg_size = { 1264 HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(0) - 1265 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(0), 1266 HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(0) - 1267 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(0), 1268 }, 1269 .max_size = 1270 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK >> 1271 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT, 1272 }, 1273 { /* TCL_CMD */ 1274 .start_ring_id = HAL_SRNG_SW2TCL_CMD, 1275 .max_rings = 1, 1276 .entry_size = (sizeof(struct tlv_32_hdr) + 1277 sizeof(struct tcl_gse_cmd)) >> 2, 1278 .lmac_ring = FALSE, 1279 .ring_dir = HAL_SRNG_SRC_RING, 1280 .reg_start = { 1281 HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_ADDR( 1282 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1283 HWIO_TCL_R2_SW2TCL_CMD_RING_HP_ADDR( 1284 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1285 }, 1286 /* Single ring - provide ring size if multiple rings of this 1287 * type are supported 1288 */ 1289 .reg_size = {}, 1290 .max_size = 1291 HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RING_SIZE_BMSK >> 1292 HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RING_SIZE_SHFT, 1293 }, 1294 { /* TCL_STATUS */ 1295 .start_ring_id = HAL_SRNG_TCL_STATUS, 1296 .max_rings = 1, 1297 .entry_size = (sizeof(struct tlv_32_hdr) + 1298 sizeof(struct tcl_status_ring)) >> 2, 1299 .lmac_ring = FALSE, 1300 .ring_dir = HAL_SRNG_DST_RING, 1301 .reg_start = { 1302 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR( 1303 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1304 HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR( 1305 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1306 }, 1307 /* Single ring - provide ring size if multiple rings of this 1308 * type are supported 1309 */ 1310 .reg_size = {}, 1311 .max_size = 1312 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_BMSK >> 1313 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_SHFT, 1314 }, 1315 { /* CE_SRC */ 1316 .start_ring_id = HAL_SRNG_CE_0_SRC, 1317 .max_rings = 12, 1318 .entry_size = sizeof(struct ce_src_desc) >> 2, 1319 .lmac_ring = FALSE, 1320 .ring_dir = HAL_SRNG_SRC_RING, 1321 .reg_start = { 1322 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR( 1323 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET), 1324 HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR( 1325 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET), 1326 }, 1327 .reg_size = { 1328 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET - 1329 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET, 1330 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET - 1331 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET, 1332 }, 1333 .max_size = 1334 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >> 1335 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT, 1336 }, 1337 { /* CE_DST */ 1338 .start_ring_id = HAL_SRNG_CE_0_DST, 1339 .max_rings = 12, 1340 .entry_size = 8 >> 2, 1341 /*TODO: entry_size above should actually be 1342 * sizeof(struct ce_dst_desc) >> 2, but couldn't find definition 1343 * of struct ce_dst_desc in HW header files 1344 */ 1345 .lmac_ring = FALSE, 1346 .ring_dir = HAL_SRNG_SRC_RING, 1347 .reg_start = { 1348 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR( 1349 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 1350 HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR( 1351 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 1352 }, 1353 .reg_size = { 1354 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 1355 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 1356 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 1357 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 1358 }, 1359 .max_size = 1360 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >> 1361 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT, 1362 }, 1363 { /* CE_DST_STATUS */ 1364 .start_ring_id = HAL_SRNG_CE_0_DST_STATUS, 1365 .max_rings = 12, 1366 .entry_size = sizeof(struct ce_stat_desc) >> 2, 1367 .lmac_ring = FALSE, 1368 .ring_dir = HAL_SRNG_DST_RING, 1369 .reg_start = { 1370 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR( 1371 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 1372 HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR( 1373 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 1374 }, 1375 /* TODO: check destination status ring registers */ 1376 .reg_size = { 1377 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 1378 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 1379 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 1380 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 1381 }, 1382 .max_size = 1383 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> 1384 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, 1385 }, 1386 { /* WBM_IDLE_LINK */ 1387 .start_ring_id = HAL_SRNG_WBM_IDLE_LINK, 1388 .max_rings = 1, 1389 .entry_size = sizeof(struct wbm_link_descriptor_ring) >> 2, 1390 .lmac_ring = FALSE, 1391 .ring_dir = HAL_SRNG_SRC_RING, 1392 .reg_start = { 1393 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1394 HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1395 }, 1396 /* Single ring - provide ring size if multiple rings of this 1397 * type are supported 1398 */ 1399 .reg_size = {}, 1400 .max_size = 1401 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_BMSK >> 1402 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_SHFT, 1403 }, 1404 { /* SW2WBM_RELEASE */ 1405 .start_ring_id = HAL_SRNG_WBM_SW_RELEASE, 1406 .max_rings = 1, 1407 .entry_size = sizeof(struct wbm_release_ring) >> 2, 1408 .lmac_ring = FALSE, 1409 .ring_dir = HAL_SRNG_SRC_RING, 1410 .reg_start = { 1411 HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1412 HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1413 }, 1414 /* Single ring - provide ring size if multiple rings of this 1415 * type are supported 1416 */ 1417 .reg_size = {}, 1418 .max_size = 1419 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> 1420 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, 1421 }, 1422 { /* WBM2SW_RELEASE */ 1423 .start_ring_id = HAL_SRNG_WBM2SW0_RELEASE, 1424 .max_rings = 4, 1425 .entry_size = sizeof(struct wbm_release_ring) >> 2, 1426 .lmac_ring = FALSE, 1427 .ring_dir = HAL_SRNG_DST_RING, 1428 .reg_start = { 1429 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1430 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1431 }, 1432 .reg_size = { 1433 HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) - 1434 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1435 HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) - 1436 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1437 }, 1438 .max_size = 1439 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> 1440 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, 1441 }, 1442 { /* RXDMA_BUF */ 1443 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA0_BUF0, 1444 #ifdef IPA_OFFLOAD 1445 .max_rings = 3, 1446 #else 1447 .max_rings = 2, 1448 #endif 1449 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 1450 .lmac_ring = TRUE, 1451 .ring_dir = HAL_SRNG_SRC_RING, 1452 /* reg_start is not set because LMAC rings are not accessed 1453 * from host 1454 */ 1455 .reg_start = {}, 1456 .reg_size = {}, 1457 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1458 }, 1459 { /* RXDMA_DST */ 1460 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW0, 1461 .max_rings = 1, 1462 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 1463 .lmac_ring = TRUE, 1464 .ring_dir = HAL_SRNG_DST_RING, 1465 /* reg_start is not set because LMAC rings are not accessed 1466 * from host 1467 */ 1468 .reg_start = {}, 1469 .reg_size = {}, 1470 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1471 }, 1472 { /* RXDMA_MONITOR_BUF */ 1473 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA2_BUF, 1474 .max_rings = 1, 1475 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 1476 .lmac_ring = TRUE, 1477 .ring_dir = HAL_SRNG_SRC_RING, 1478 /* reg_start is not set because LMAC rings are not accessed 1479 * from host 1480 */ 1481 .reg_start = {}, 1482 .reg_size = {}, 1483 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1484 }, 1485 { /* RXDMA_MONITOR_STATUS */ 1486 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_STATBUF, 1487 .max_rings = 1, 1488 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 1489 .lmac_ring = TRUE, 1490 .ring_dir = HAL_SRNG_SRC_RING, 1491 /* reg_start is not set because LMAC rings are not accessed 1492 * from host 1493 */ 1494 .reg_start = {}, 1495 .reg_size = {}, 1496 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1497 }, 1498 { /* RXDMA_MONITOR_DST */ 1499 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW1, 1500 .max_rings = 1, 1501 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 1502 .lmac_ring = TRUE, 1503 .ring_dir = HAL_SRNG_DST_RING, 1504 /* reg_start is not set because LMAC rings are not accessed 1505 * from host 1506 */ 1507 .reg_start = {}, 1508 .reg_size = {}, 1509 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1510 }, 1511 { /* RXDMA_MONITOR_DESC */ 1512 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_DESC, 1513 .max_rings = 1, 1514 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 1515 .lmac_ring = TRUE, 1516 .ring_dir = HAL_SRNG_SRC_RING, 1517 /* reg_start is not set because LMAC rings are not accessed 1518 * from host 1519 */ 1520 .reg_start = {}, 1521 .reg_size = {}, 1522 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1523 }, 1524 { /* DIR_BUF_RX_DMA_SRC */ 1525 .start_ring_id = HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING, 1526 .max_rings = 1, 1527 .entry_size = 2, 1528 .lmac_ring = TRUE, 1529 .ring_dir = HAL_SRNG_SRC_RING, 1530 /* reg_start is not set because LMAC rings are not accessed 1531 * from host 1532 */ 1533 .reg_start = {}, 1534 .reg_size = {}, 1535 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1536 }, 1537 #ifdef WLAN_FEATURE_CIF_CFR 1538 { /* WIFI_POS_SRC */ 1539 .start_ring_id = HAL_SRNG_WIFI_POS_SRC_DMA_RING, 1540 .max_rings = 1, 1541 .entry_size = sizeof(wmi_oem_dma_buf_release_entry) >> 2, 1542 .lmac_ring = TRUE, 1543 .ring_dir = HAL_SRNG_SRC_RING, 1544 /* reg_start is not set because LMAC rings are not accessed 1545 * from host 1546 */ 1547 .reg_start = {}, 1548 .reg_size = {}, 1549 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1550 }, 1551 #endif 1552 }; 1553 1554 int32_t hal_hw_reg_offset_qca6390[] = { 1555 /* dst */ 1556 REG_OFFSET(DST, HP), 1557 REG_OFFSET(DST, TP), 1558 REG_OFFSET(DST, ID), 1559 REG_OFFSET(DST, MISC), 1560 REG_OFFSET(DST, HP_ADDR_LSB), 1561 REG_OFFSET(DST, HP_ADDR_MSB), 1562 REG_OFFSET(DST, MSI1_BASE_LSB), 1563 REG_OFFSET(DST, MSI1_BASE_MSB), 1564 REG_OFFSET(DST, MSI1_DATA), 1565 REG_OFFSET(DST, BASE_LSB), 1566 REG_OFFSET(DST, BASE_MSB), 1567 REG_OFFSET(DST, PRODUCER_INT_SETUP), 1568 /* src */ 1569 REG_OFFSET(SRC, HP), 1570 REG_OFFSET(SRC, TP), 1571 REG_OFFSET(SRC, ID), 1572 REG_OFFSET(SRC, MISC), 1573 REG_OFFSET(SRC, TP_ADDR_LSB), 1574 REG_OFFSET(SRC, TP_ADDR_MSB), 1575 REG_OFFSET(SRC, MSI1_BASE_LSB), 1576 REG_OFFSET(SRC, MSI1_BASE_MSB), 1577 REG_OFFSET(SRC, MSI1_DATA), 1578 REG_OFFSET(SRC, BASE_LSB), 1579 REG_OFFSET(SRC, BASE_MSB), 1580 REG_OFFSET(SRC, CONSUMER_INT_SETUP_IX0), 1581 REG_OFFSET(SRC, CONSUMER_INT_SETUP_IX1), 1582 }; 1583 1584 /** 1585 * hal_qca6390_attach() - Attach 6390 target specific hal_soc ops, 1586 * offset and srng table 1587 */ 1588 void hal_qca6390_attach(struct hal_soc *hal_soc) 1589 { 1590 hal_soc->hw_srng_table = hw_srng_table_6390; 1591 hal_soc->hal_hw_reg_offset = hal_hw_reg_offset_qca6390; 1592 hal_soc->ops = &qca6390_hal_hw_txrx_ops; 1593 } 1594