1 /* 2 * Copyright (c) 2016-2018 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 #include "qdf_types.h" 19 #include "qdf_util.h" 20 #include "qdf_types.h" 21 #include "qdf_lock.h" 22 #include "qdf_mem.h" 23 #include "qdf_nbuf.h" 24 #include "hal_hw_headers.h" 25 #include "hal_internal.h" 26 #include "hal_api.h" 27 #include "target_type.h" 28 #include "wcss_version.h" 29 #include "qdf_module.h" 30 31 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_OFFSET \ 32 RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_OFFSET 33 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_MASK \ 34 RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_MASK 35 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_LSB \ 36 RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_LSB 37 #define UNIFIED_PHYRX_HT_SIG_0_HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS_OFFSET \ 38 PHYRX_HT_SIG_0_HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS_OFFSET 39 #define UNIFIED_PHYRX_L_SIG_B_0_L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS_OFFSET \ 40 PHYRX_L_SIG_B_0_L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS_OFFSET 41 #define UNIFIED_PHYRX_L_SIG_A_0_L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS_OFFSET \ 42 PHYRX_L_SIG_A_0_L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS_OFFSET 43 #define UNIFIED_PHYRX_VHT_SIG_A_0_VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS_OFFSET \ 44 PHYRX_VHT_SIG_A_0_VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS_OFFSET 45 #define UNIFIED_PHYRX_HE_SIG_A_SU_0_HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS_OFFSET \ 46 PHYRX_HE_SIG_A_SU_0_HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS_OFFSET 47 #define UNIFIED_PHYRX_HE_SIG_A_MU_DL_0_HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_OFFSET \ 48 PHYRX_HE_SIG_A_MU_DL_0_HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_OFFSET 49 #define UNIFIED_PHYRX_HE_SIG_B1_MU_0_HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_OFFSET \ 50 PHYRX_HE_SIG_B1_MU_0_HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_OFFSET 51 #define UNIFIED_PHYRX_HE_SIG_B2_MU_0_HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_OFFSET \ 52 PHYRX_HE_SIG_B2_MU_0_HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_OFFSET 53 #define UNIFIED_PHYRX_HE_SIG_B2_OFDMA_0_HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_OFFSET \ 54 PHYRX_HE_SIG_B2_OFDMA_0_HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_OFFSET 55 #define UNIFIED_PHYRX_RSSI_LEGACY_3_RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS_OFFSET \ 56 PHYRX_RSSI_LEGACY_3_RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS_OFFSET 57 #define UNIFIED_RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET \ 58 RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET 59 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 60 RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET 61 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ 62 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET 63 #define UNIFIED_RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 64 RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET 65 #define UNIFIED_REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 66 REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET 67 #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC \ 68 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER 69 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ 70 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET 71 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 72 RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET 73 #define UNIFIED_TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 74 TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET 75 #define UNIFIED_TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 76 TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET 77 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET \ 78 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET 79 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB \ 80 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB 81 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK \ 82 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK 83 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB \ 84 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB 85 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK \ 86 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK 87 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB \ 88 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB 89 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK \ 90 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK 91 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB \ 92 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB 93 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK \ 94 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK 95 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB \ 96 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB 97 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK \ 98 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK 99 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_MASK \ 100 WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_MASK 101 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_OFFSET \ 102 WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_OFFSET 103 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_LSB \ 104 WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_LSB 105 106 #include "hal_6390_tx.h" 107 #include "hal_6390_rx.h" 108 #include <hal_generic_api.h> 109 #include <hal_wbm.h> 110 111 struct hal_hw_txrx_ops qca6390_hal_hw_txrx_ops = { 112 /* init and setup */ 113 hal_srng_dst_hw_init_generic, 114 hal_srng_src_hw_init_generic, 115 hal_reo_setup_generic, 116 hal_setup_link_idle_list_generic, 117 118 /* tx */ 119 hal_tx_desc_set_dscp_tid_table_id_6390, 120 hal_tx_set_dscp_tid_map_6390, 121 hal_tx_update_dscp_tid_6390, 122 hal_tx_desc_set_lmac_id_6390, 123 hal_tx_desc_set_buf_addr_generic, 124 hal_tx_comp_get_status_generic, 125 126 /* rx */ 127 hal_rx_msdu_start_nss_get_6390, 128 hal_rx_mon_hw_desc_get_mpdu_status_6390, 129 hal_rx_get_tlv_6390, 130 hal_rx_proc_phyrx_other_receive_info_tlv_6390, 131 hal_rx_dump_msdu_start_tlv_6390, 132 hal_rx_dump_msdu_end_tlv_6390, 133 hal_get_link_desc_size_6390, 134 hal_rx_mpdu_start_tid_get_6390, 135 hal_rx_msdu_start_reception_type_get_6390, 136 hal_rx_msdu_end_da_idx_get_6390, 137 hal_rx_msdu_desc_info_get_ptr_generic, 138 hal_rx_link_desc_msdu0_ptr_generic, 139 hal_reo_status_get_header_generic, 140 hal_rx_status_get_tlv_info_generic, 141 }; 142 143 struct hal_hw_srng_config hw_srng_table_6390[] = { 144 /* TODO: max_rings can populated by querying HW capabilities */ 145 { /* REO_DST */ 146 .start_ring_id = HAL_SRNG_REO2SW1, 147 .max_rings = 4, 148 .entry_size = sizeof(struct reo_destination_ring) >> 2, 149 .lmac_ring = FALSE, 150 .ring_dir = HAL_SRNG_DST_RING, 151 .reg_start = { 152 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR( 153 SEQ_WCSS_UMAC_REO_REG_OFFSET), 154 HWIO_REO_R2_REO2SW1_RING_HP_ADDR( 155 SEQ_WCSS_UMAC_REO_REG_OFFSET) 156 }, 157 .reg_size = { 158 HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(0) - 159 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(0), 160 HWIO_REO_R2_REO2SW2_RING_HP_ADDR(0) - 161 HWIO_REO_R2_REO2SW1_RING_HP_ADDR(0), 162 }, 163 .max_size = 164 HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_BMSK >> 165 HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_SHFT, 166 }, 167 { /* REO_EXCEPTION */ 168 /* Designating REO2TCL ring as exception ring. This ring is 169 * similar to other REO2SW rings though it is named as REO2TCL. 170 * Any of theREO2SW rings can be used as exception ring. 171 */ 172 .start_ring_id = HAL_SRNG_REO2TCL, 173 .max_rings = 1, 174 .entry_size = sizeof(struct reo_destination_ring) >> 2, 175 .lmac_ring = FALSE, 176 .ring_dir = HAL_SRNG_DST_RING, 177 .reg_start = { 178 HWIO_REO_R0_REO2TCL_RING_BASE_LSB_ADDR( 179 SEQ_WCSS_UMAC_REO_REG_OFFSET), 180 HWIO_REO_R2_REO2TCL_RING_HP_ADDR( 181 SEQ_WCSS_UMAC_REO_REG_OFFSET) 182 }, 183 /* Single ring - provide ring size if multiple rings of this 184 * type are supported 185 */ 186 .reg_size = {}, 187 .max_size = 188 HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_BMSK >> 189 HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_SHFT, 190 }, 191 { /* REO_REINJECT */ 192 .start_ring_id = HAL_SRNG_SW2REO, 193 .max_rings = 1, 194 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 195 .lmac_ring = FALSE, 196 .ring_dir = HAL_SRNG_SRC_RING, 197 .reg_start = { 198 HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR( 199 SEQ_WCSS_UMAC_REO_REG_OFFSET), 200 HWIO_REO_R2_SW2REO_RING_HP_ADDR( 201 SEQ_WCSS_UMAC_REO_REG_OFFSET) 202 }, 203 /* Single ring - provide ring size if multiple rings of this 204 * type are supported 205 */ 206 .reg_size = {}, 207 .max_size = HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_BMSK >> 208 HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_SHFT, 209 }, 210 { /* REO_CMD */ 211 .start_ring_id = HAL_SRNG_REO_CMD, 212 .max_rings = 1, 213 .entry_size = (sizeof(struct tlv_32_hdr) + 214 sizeof(struct reo_get_queue_stats)) >> 2, 215 .lmac_ring = FALSE, 216 .ring_dir = HAL_SRNG_SRC_RING, 217 .reg_start = { 218 HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR( 219 SEQ_WCSS_UMAC_REO_REG_OFFSET), 220 HWIO_REO_R2_REO_CMD_RING_HP_ADDR( 221 SEQ_WCSS_UMAC_REO_REG_OFFSET), 222 }, 223 /* Single ring - provide ring size if multiple rings of this 224 * type are supported 225 */ 226 .reg_size = {}, 227 .max_size = 228 HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_BMSK >> 229 HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_SHFT, 230 }, 231 { /* REO_STATUS */ 232 .start_ring_id = HAL_SRNG_REO_STATUS, 233 .max_rings = 1, 234 .entry_size = (sizeof(struct tlv_32_hdr) + 235 sizeof(struct reo_get_queue_stats_status)) >> 2, 236 .lmac_ring = FALSE, 237 .ring_dir = HAL_SRNG_DST_RING, 238 .reg_start = { 239 HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR( 240 SEQ_WCSS_UMAC_REO_REG_OFFSET), 241 HWIO_REO_R2_REO_STATUS_RING_HP_ADDR( 242 SEQ_WCSS_UMAC_REO_REG_OFFSET), 243 }, 244 /* Single ring - provide ring size if multiple rings of this 245 * type are supported 246 */ 247 .reg_size = {}, 248 .max_size = 249 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> 250 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, 251 }, 252 { /* TCL_DATA */ 253 .start_ring_id = HAL_SRNG_SW2TCL1, 254 .max_rings = 3, 255 .entry_size = (sizeof(struct tlv_32_hdr) + 256 sizeof(struct tcl_data_cmd)) >> 2, 257 .lmac_ring = FALSE, 258 .ring_dir = HAL_SRNG_SRC_RING, 259 .reg_start = { 260 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR( 261 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 262 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR( 263 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 264 }, 265 .reg_size = { 266 HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(0) - 267 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(0), 268 HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(0) - 269 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(0), 270 }, 271 .max_size = 272 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK >> 273 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT, 274 }, 275 { /* TCL_CMD */ 276 .start_ring_id = HAL_SRNG_SW2TCL_CMD, 277 .max_rings = 1, 278 .entry_size = (sizeof(struct tlv_32_hdr) + 279 sizeof(struct tcl_gse_cmd)) >> 2, 280 .lmac_ring = FALSE, 281 .ring_dir = HAL_SRNG_SRC_RING, 282 .reg_start = { 283 HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_ADDR( 284 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 285 HWIO_TCL_R2_SW2TCL_CMD_RING_HP_ADDR( 286 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 287 }, 288 /* Single ring - provide ring size if multiple rings of this 289 * type are supported 290 */ 291 .reg_size = {}, 292 .max_size = 293 HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RING_SIZE_BMSK >> 294 HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RING_SIZE_SHFT, 295 }, 296 { /* TCL_STATUS */ 297 .start_ring_id = HAL_SRNG_TCL_STATUS, 298 .max_rings = 1, 299 .entry_size = (sizeof(struct tlv_32_hdr) + 300 sizeof(struct tcl_status_ring)) >> 2, 301 .lmac_ring = FALSE, 302 .ring_dir = HAL_SRNG_DST_RING, 303 .reg_start = { 304 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR( 305 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 306 HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR( 307 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 308 }, 309 /* Single ring - provide ring size if multiple rings of this 310 * type are supported 311 */ 312 .reg_size = {}, 313 .max_size = 314 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_BMSK >> 315 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_SHFT, 316 }, 317 { /* CE_SRC */ 318 .start_ring_id = HAL_SRNG_CE_0_SRC, 319 .max_rings = 12, 320 .entry_size = sizeof(struct ce_src_desc) >> 2, 321 .lmac_ring = FALSE, 322 .ring_dir = HAL_SRNG_SRC_RING, 323 .reg_start = { 324 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR( 325 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET), 326 HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR( 327 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET), 328 }, 329 .reg_size = { 330 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET - 331 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET, 332 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET - 333 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET, 334 }, 335 .max_size = 336 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >> 337 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT, 338 }, 339 { /* CE_DST */ 340 .start_ring_id = HAL_SRNG_CE_0_DST, 341 .max_rings = 12, 342 .entry_size = 8 >> 2, 343 /*TODO: entry_size above should actually be 344 * sizeof(struct ce_dst_desc) >> 2, but couldn't find definition 345 * of struct ce_dst_desc in HW header files 346 */ 347 .lmac_ring = FALSE, 348 .ring_dir = HAL_SRNG_SRC_RING, 349 .reg_start = { 350 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR( 351 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 352 HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR( 353 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 354 }, 355 .reg_size = { 356 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 357 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 358 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 359 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 360 }, 361 .max_size = 362 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >> 363 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT, 364 }, 365 { /* CE_DST_STATUS */ 366 .start_ring_id = HAL_SRNG_CE_0_DST_STATUS, 367 .max_rings = 12, 368 .entry_size = sizeof(struct ce_stat_desc) >> 2, 369 .lmac_ring = FALSE, 370 .ring_dir = HAL_SRNG_DST_RING, 371 .reg_start = { 372 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR( 373 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 374 HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR( 375 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 376 }, 377 /* TODO: check destination status ring registers */ 378 .reg_size = { 379 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 380 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 381 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 382 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 383 }, 384 .max_size = 385 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> 386 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, 387 }, 388 { /* WBM_IDLE_LINK */ 389 .start_ring_id = HAL_SRNG_WBM_IDLE_LINK, 390 .max_rings = 1, 391 .entry_size = sizeof(struct wbm_link_descriptor_ring) >> 2, 392 .lmac_ring = FALSE, 393 .ring_dir = HAL_SRNG_SRC_RING, 394 .reg_start = { 395 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 396 HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 397 }, 398 /* Single ring - provide ring size if multiple rings of this 399 * type are supported 400 */ 401 .reg_size = {}, 402 .max_size = 403 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_BMSK >> 404 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_SHFT, 405 }, 406 { /* SW2WBM_RELEASE */ 407 .start_ring_id = HAL_SRNG_WBM_SW_RELEASE, 408 .max_rings = 1, 409 .entry_size = sizeof(struct wbm_release_ring) >> 2, 410 .lmac_ring = FALSE, 411 .ring_dir = HAL_SRNG_SRC_RING, 412 .reg_start = { 413 HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 414 HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 415 }, 416 /* Single ring - provide ring size if multiple rings of this 417 * type are supported 418 */ 419 .reg_size = {}, 420 .max_size = 421 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> 422 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, 423 }, 424 { /* WBM2SW_RELEASE */ 425 .start_ring_id = HAL_SRNG_WBM2SW0_RELEASE, 426 .max_rings = 4, 427 .entry_size = sizeof(struct wbm_release_ring) >> 2, 428 .lmac_ring = FALSE, 429 .ring_dir = HAL_SRNG_DST_RING, 430 .reg_start = { 431 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 432 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 433 }, 434 .reg_size = { 435 HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) - 436 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 437 HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) - 438 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 439 }, 440 .max_size = 441 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> 442 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, 443 }, 444 { /* RXDMA_BUF */ 445 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA0_BUF0, 446 #ifdef IPA_OFFLOAD 447 .max_rings = 3, 448 #else 449 .max_rings = 2, 450 #endif 451 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 452 .lmac_ring = TRUE, 453 .ring_dir = HAL_SRNG_SRC_RING, 454 /* reg_start is not set because LMAC rings are not accessed 455 * from host 456 */ 457 .reg_start = {}, 458 .reg_size = {}, 459 .max_size = HAL_RXDMA_MAX_RING_SIZE, 460 }, 461 { /* RXDMA_DST */ 462 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW0, 463 .max_rings = 1, 464 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 465 .lmac_ring = TRUE, 466 .ring_dir = HAL_SRNG_DST_RING, 467 /* reg_start is not set because LMAC rings are not accessed 468 * from host 469 */ 470 .reg_start = {}, 471 .reg_size = {}, 472 .max_size = HAL_RXDMA_MAX_RING_SIZE, 473 }, 474 { /* RXDMA_MONITOR_BUF */ 475 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA2_BUF, 476 .max_rings = 1, 477 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 478 .lmac_ring = TRUE, 479 .ring_dir = HAL_SRNG_SRC_RING, 480 /* reg_start is not set because LMAC rings are not accessed 481 * from host 482 */ 483 .reg_start = {}, 484 .reg_size = {}, 485 .max_size = HAL_RXDMA_MAX_RING_SIZE, 486 }, 487 { /* RXDMA_MONITOR_STATUS */ 488 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_STATBUF, 489 .max_rings = 1, 490 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 491 .lmac_ring = TRUE, 492 .ring_dir = HAL_SRNG_SRC_RING, 493 /* reg_start is not set because LMAC rings are not accessed 494 * from host 495 */ 496 .reg_start = {}, 497 .reg_size = {}, 498 .max_size = HAL_RXDMA_MAX_RING_SIZE, 499 }, 500 { /* RXDMA_MONITOR_DST */ 501 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW1, 502 .max_rings = 1, 503 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 504 .lmac_ring = TRUE, 505 .ring_dir = HAL_SRNG_DST_RING, 506 /* reg_start is not set because LMAC rings are not accessed 507 * from host 508 */ 509 .reg_start = {}, 510 .reg_size = {}, 511 .max_size = HAL_RXDMA_MAX_RING_SIZE, 512 }, 513 { /* RXDMA_MONITOR_DESC */ 514 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_DESC, 515 .max_rings = 1, 516 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 517 .lmac_ring = TRUE, 518 .ring_dir = HAL_SRNG_SRC_RING, 519 /* reg_start is not set because LMAC rings are not accessed 520 * from host 521 */ 522 .reg_start = {}, 523 .reg_size = {}, 524 .max_size = HAL_RXDMA_MAX_RING_SIZE, 525 }, 526 { /* DIR_BUF_RX_DMA_SRC */ 527 .start_ring_id = HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING, 528 .max_rings = 1, 529 .entry_size = 2, 530 .lmac_ring = TRUE, 531 .ring_dir = HAL_SRNG_SRC_RING, 532 /* reg_start is not set because LMAC rings are not accessed 533 * from host 534 */ 535 .reg_start = {}, 536 .reg_size = {}, 537 .max_size = HAL_RXDMA_MAX_RING_SIZE, 538 }, 539 #ifdef WLAN_FEATURE_CIF_CFR 540 { /* WIFI_POS_SRC */ 541 .start_ring_id = HAL_SRNG_WIFI_POS_SRC_DMA_RING, 542 .max_rings = 1, 543 .entry_size = sizeof(wmi_oem_dma_buf_release_entry) >> 2, 544 .lmac_ring = TRUE, 545 .ring_dir = HAL_SRNG_SRC_RING, 546 /* reg_start is not set because LMAC rings are not accessed 547 * from host 548 */ 549 .reg_start = {}, 550 .reg_size = {}, 551 .max_size = HAL_RXDMA_MAX_RING_SIZE, 552 }, 553 #endif 554 }; 555 556 int32_t hal_hw_reg_offset_qca6390[] = { 557 /* dst */ 558 REG_OFFSET(DST, HP), 559 REG_OFFSET(DST, TP), 560 REG_OFFSET(DST, ID), 561 REG_OFFSET(DST, MISC), 562 REG_OFFSET(DST, HP_ADDR_LSB), 563 REG_OFFSET(DST, HP_ADDR_MSB), 564 REG_OFFSET(DST, MSI1_BASE_LSB), 565 REG_OFFSET(DST, MSI1_BASE_MSB), 566 REG_OFFSET(DST, MSI1_DATA), 567 REG_OFFSET(DST, BASE_LSB), 568 REG_OFFSET(DST, BASE_MSB), 569 REG_OFFSET(DST, PRODUCER_INT_SETUP), 570 /* src */ 571 REG_OFFSET(SRC, HP), 572 REG_OFFSET(SRC, TP), 573 REG_OFFSET(SRC, ID), 574 REG_OFFSET(SRC, MISC), 575 REG_OFFSET(SRC, TP_ADDR_LSB), 576 REG_OFFSET(SRC, TP_ADDR_MSB), 577 REG_OFFSET(SRC, MSI1_BASE_LSB), 578 REG_OFFSET(SRC, MSI1_BASE_MSB), 579 REG_OFFSET(SRC, MSI1_DATA), 580 REG_OFFSET(SRC, BASE_LSB), 581 REG_OFFSET(SRC, BASE_MSB), 582 REG_OFFSET(SRC, CONSUMER_INT_SETUP_IX0), 583 REG_OFFSET(SRC, CONSUMER_INT_SETUP_IX1), 584 }; 585 586 /** 587 * hal_qca6390_attach() - Attach 6390 target specific hal_soc ops, 588 * offset and srng table 589 */ 590 void hal_qca6390_attach(struct hal_soc *hal_soc) 591 { 592 hal_soc->hw_srng_table = hw_srng_table_6390; 593 hal_soc->hal_hw_reg_offset = hal_hw_reg_offset_qca6390; 594 hal_soc->ops = &qca6390_hal_hw_txrx_ops; 595 } 596