1 /* 2 * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 #include "qdf_types.h" 19 #include "qdf_util.h" 20 #include "qdf_types.h" 21 #include "qdf_lock.h" 22 #include "qdf_mem.h" 23 #include "qdf_nbuf.h" 24 #include "hal_li_hw_headers.h" 25 #include "hal_internal.h" 26 #include "hal_api.h" 27 #include "target_type.h" 28 #include "wcss_version.h" 29 #include "qdf_module.h" 30 31 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_OFFSET \ 32 RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_OFFSET 33 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_MASK \ 34 RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_MASK 35 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_LSB \ 36 RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_LSB 37 #define UNIFIED_PHYRX_HT_SIG_0_HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS_OFFSET \ 38 PHYRX_HT_SIG_0_HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS_OFFSET 39 #define UNIFIED_PHYRX_L_SIG_B_0_L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS_OFFSET \ 40 PHYRX_L_SIG_B_0_L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS_OFFSET 41 #define UNIFIED_PHYRX_L_SIG_A_0_L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS_OFFSET \ 42 PHYRX_L_SIG_A_0_L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS_OFFSET 43 #define UNIFIED_PHYRX_VHT_SIG_A_0_VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS_OFFSET \ 44 PHYRX_VHT_SIG_A_0_VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS_OFFSET 45 #define UNIFIED_PHYRX_HE_SIG_A_SU_0_HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS_OFFSET \ 46 PHYRX_HE_SIG_A_SU_0_HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS_OFFSET 47 #define UNIFIED_PHYRX_HE_SIG_A_MU_DL_0_HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_OFFSET \ 48 PHYRX_HE_SIG_A_MU_DL_0_HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_OFFSET 49 #define UNIFIED_PHYRX_HE_SIG_B1_MU_0_HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_OFFSET \ 50 PHYRX_HE_SIG_B1_MU_0_HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_OFFSET 51 #define UNIFIED_PHYRX_HE_SIG_B2_MU_0_HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_OFFSET \ 52 PHYRX_HE_SIG_B2_MU_0_HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_OFFSET 53 #define UNIFIED_PHYRX_HE_SIG_B2_OFDMA_0_HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_OFFSET \ 54 PHYRX_HE_SIG_B2_OFDMA_0_HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_OFFSET 55 #define UNIFIED_PHYRX_RSSI_LEGACY_3_RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS_OFFSET \ 56 PHYRX_RSSI_LEGACY_3_RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS_OFFSET 57 #define UNIFIED_PHYRX_RSSI_LEGACY_19_RECEIVE_RSSI_INFO_PREAMBLE_RSSI_INFO_DETAILS_OFFSET \ 58 PHYRX_RSSI_LEGACY_19_RECEIVE_RSSI_INFO_PREAMBLE_RSSI_INFO_DETAILS_OFFSET 59 #define UNIFIED_RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET \ 60 RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET 61 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 62 RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET 63 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ 64 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET 65 #define UNIFIED_RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 66 RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET 67 #define UNIFIED_REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 68 REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET 69 #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC \ 70 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER 71 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ 72 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET 73 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 74 RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET 75 #define UNIFIED_TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 76 TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET 77 #define UNIFIED_TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 78 TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET 79 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET \ 80 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET 81 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB \ 82 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB 83 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK \ 84 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK 85 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB \ 86 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB 87 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK \ 88 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK 89 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB \ 90 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB 91 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK \ 92 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK 93 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB \ 94 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB 95 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK \ 96 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK 97 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB \ 98 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB 99 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK \ 100 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK 101 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_MASK \ 102 WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_MASK 103 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_OFFSET \ 104 WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_OFFSET 105 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_LSB \ 106 WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_LSB 107 108 #include "hal_6390_tx.h" 109 #include "hal_6390_rx.h" 110 #include <hal_generic_api.h> 111 #include "hal_li_rx.h" 112 #include "hal_li_api.h" 113 #include "hal_li_generic_api.h" 114 115 /** 116 * hal_rx_get_rx_fragment_number_6390(): Function to retrieve rx fragment number 117 * 118 * @nbuf: Network buffer 119 * Returns: rx fragment number 120 */ 121 static 122 uint8_t hal_rx_get_rx_fragment_number_6390(uint8_t *buf) 123 { 124 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 125 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 126 127 /* Return first 4 bits as fragment number */ 128 return (HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info) & 129 DOT11_SEQ_FRAG_MASK); 130 } 131 132 /** 133 * hal_rx_msdu_end_da_is_mcbc_get_6390(): API to check if pkt is MCBC 134 * from rx_msdu_end TLV 135 * 136 * @ buf: pointer to the start of RX PKT TLV headers 137 * Return: da_is_mcbc 138 */ 139 static uint8_t 140 hal_rx_msdu_end_da_is_mcbc_get_6390(uint8_t *buf) 141 { 142 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 143 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 144 145 return HAL_RX_MSDU_END_DA_IS_MCBC_GET(msdu_end); 146 } 147 148 /** 149 * hal_rx_msdu_end_sa_is_valid_get_6390(): API to get_6390 the 150 * sa_is_valid bit from rx_msdu_end TLV 151 * 152 * @ buf: pointer to the start of RX PKT TLV headers 153 * Return: sa_is_valid bit 154 */ 155 static uint8_t 156 hal_rx_msdu_end_sa_is_valid_get_6390(uint8_t *buf) 157 { 158 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 159 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 160 uint8_t sa_is_valid; 161 162 sa_is_valid = HAL_RX_MSDU_END_SA_IS_VALID_GET(msdu_end); 163 164 return sa_is_valid; 165 } 166 167 /** 168 * hal_rx_msdu_end_sa_idx_get_6390(): API to get_6390 the 169 * sa_idx from rx_msdu_end TLV 170 * 171 * @ buf: pointer to the start of RX PKT TLV headers 172 * Return: sa_idx (SA AST index) 173 */ 174 static 175 uint16_t hal_rx_msdu_end_sa_idx_get_6390(uint8_t *buf) 176 { 177 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 178 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 179 uint16_t sa_idx; 180 181 sa_idx = HAL_RX_MSDU_END_SA_IDX_GET(msdu_end); 182 183 return sa_idx; 184 } 185 186 /** 187 * hal_rx_desc_is_first_msdu_6390() - Check if first msdu 188 * 189 * @hal_soc_hdl: hal_soc handle 190 * @hw_desc_addr: hardware descriptor address 191 * 192 * Return: 0 - success/ non-zero failure 193 */ 194 static uint32_t hal_rx_desc_is_first_msdu_6390(void *hw_desc_addr) 195 { 196 struct rx_pkt_tlvs *rx_tlvs = (struct rx_pkt_tlvs *)hw_desc_addr; 197 struct rx_msdu_end *msdu_end = &rx_tlvs->msdu_end_tlv.rx_msdu_end; 198 199 return HAL_RX_GET(msdu_end, RX_MSDU_END_5, FIRST_MSDU); 200 } 201 202 /** 203 * hal_rx_msdu_end_l3_hdr_padding_get_6390(): API to get_6390 the 204 * l3_header padding from rx_msdu_end TLV 205 * 206 * @ buf: pointer to the start of RX PKT TLV headers 207 * Return: number of l3 header padding bytes 208 */ 209 static uint32_t hal_rx_msdu_end_l3_hdr_padding_get_6390(uint8_t *buf) 210 { 211 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 212 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 213 uint32_t l3_header_padding; 214 215 l3_header_padding = HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(msdu_end); 216 217 return l3_header_padding; 218 } 219 220 /* 221 * @ hal_rx_encryption_info_valid_6390: Returns encryption type. 222 * 223 * @ buf: rx_tlv_hdr of the received packet 224 * @ Return: encryption type 225 */ 226 static uint32_t hal_rx_encryption_info_valid_6390(uint8_t *buf) 227 { 228 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 229 struct rx_mpdu_start *mpdu_start = 230 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 231 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 232 uint32_t encryption_info = HAL_RX_MPDU_ENCRYPTION_INFO_VALID(mpdu_info); 233 234 return encryption_info; 235 } 236 237 /* 238 * @ hal_rx_print_pn_6390: Prints the PN of rx packet. 239 * 240 * @ buf: rx_tlv_hdr of the received packet 241 * @ Return: void 242 */ 243 static void hal_rx_print_pn_6390(uint8_t *buf) 244 { 245 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 246 struct rx_mpdu_start *mpdu_start = 247 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 248 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 249 250 uint32_t pn_31_0 = HAL_RX_MPDU_PN_31_0_GET(mpdu_info); 251 uint32_t pn_63_32 = HAL_RX_MPDU_PN_63_32_GET(mpdu_info); 252 uint32_t pn_95_64 = HAL_RX_MPDU_PN_95_64_GET(mpdu_info); 253 uint32_t pn_127_96 = HAL_RX_MPDU_PN_127_96_GET(mpdu_info); 254 255 hal_debug("PN number pn_127_96 0x%x pn_95_64 0x%x pn_63_32 0x%x pn_31_0 0x%x ", 256 pn_127_96, pn_95_64, pn_63_32, pn_31_0); 257 } 258 259 /** 260 * hal_rx_msdu_end_first_msduget_6390: API to get first msdu status 261 * from rx_msdu_end TLV 262 * 263 * @ buf: pointer to the start of RX PKT TLV headers 264 * Return: first_msdu 265 */ 266 static uint8_t hal_rx_msdu_end_first_msdu_get_6390(uint8_t *buf) 267 { 268 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 269 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 270 uint8_t first_msdu; 271 272 first_msdu = HAL_RX_MSDU_END_FIRST_MSDU_GET(msdu_end); 273 274 return first_msdu; 275 } 276 277 /** 278 * hal_rx_msdu_end_da_is_valid_get_6390: API to check if da is valid 279 * from rx_msdu_end TLV 280 * 281 * @ buf: pointer to the start of RX PKT TLV headers 282 * Return: da_is_valid 283 */ 284 static uint8_t hal_rx_msdu_end_da_is_valid_get_6390(uint8_t *buf) 285 { 286 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 287 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 288 uint8_t da_is_valid; 289 290 da_is_valid = HAL_RX_MSDU_END_DA_IS_VALID_GET(msdu_end); 291 292 return da_is_valid; 293 } 294 295 /** 296 * hal_rx_msdu_end_last_msdu_get_6390: API to get last msdu status 297 * from rx_msdu_end TLV 298 * 299 * @ buf: pointer to the start of RX PKT TLV headers 300 * Return: last_msdu 301 */ 302 static uint8_t hal_rx_msdu_end_last_msdu_get_6390(uint8_t *buf) 303 { 304 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 305 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 306 uint8_t last_msdu; 307 308 last_msdu = HAL_RX_MSDU_END_LAST_MSDU_GET(msdu_end); 309 310 return last_msdu; 311 } 312 313 /* 314 * hal_rx_get_mpdu_mac_ad4_valid_6390(): Retrieves if mpdu 4th addr is valid 315 * 316 * @nbuf: Network buffer 317 * Returns: value of mpdu 4th address valid field 318 */ 319 static bool hal_rx_get_mpdu_mac_ad4_valid_6390(uint8_t *buf) 320 { 321 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 322 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 323 bool ad4_valid = 0; 324 325 ad4_valid = HAL_RX_MPDU_GET_MAC_AD4_VALID(rx_mpdu_info); 326 327 return ad4_valid; 328 } 329 330 /** 331 * hal_rx_mpdu_start_sw_peer_id_get_6390: Retrieve sw peer_id 332 * @buf: network buffer 333 * 334 * Return: sw peer_id 335 */ 336 static uint32_t hal_rx_mpdu_start_sw_peer_id_get_6390(uint8_t *buf) 337 { 338 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 339 struct rx_mpdu_start *mpdu_start = 340 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 341 342 return HAL_RX_MPDU_INFO_SW_PEER_ID_GET( 343 &mpdu_start->rx_mpdu_info_details); 344 } 345 346 /* 347 * hal_rx_mpdu_get_to_ds_6390(): API to get the tods info 348 * from rx_mpdu_start 349 * 350 * @buf: pointer to the start of RX PKT TLV header 351 * Return: uint32_t(to_ds) 352 */ 353 static uint32_t hal_rx_mpdu_get_to_ds_6390(uint8_t *buf) 354 { 355 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 356 struct rx_mpdu_start *mpdu_start = 357 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 358 359 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 360 361 return HAL_RX_MPDU_GET_TODS(mpdu_info); 362 } 363 364 /* 365 * hal_rx_mpdu_get_fr_ds_6390(): API to get the from ds info 366 * from rx_mpdu_start 367 * 368 * @buf: pointer to the start of RX PKT TLV header 369 * Return: uint32_t(fr_ds) 370 */ 371 static uint32_t hal_rx_mpdu_get_fr_ds_6390(uint8_t *buf) 372 { 373 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 374 struct rx_mpdu_start *mpdu_start = 375 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 376 377 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 378 379 return HAL_RX_MPDU_GET_FROMDS(mpdu_info); 380 } 381 382 /* 383 * hal_rx_get_mpdu_frame_control_valid_6390(): Retrieves mpdu 384 * frame control valid 385 * 386 * @nbuf: Network buffer 387 * Returns: value of frame control valid field 388 */ 389 static uint8_t hal_rx_get_mpdu_frame_control_valid_6390(uint8_t *buf) 390 { 391 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 392 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 393 394 return HAL_RX_MPDU_GET_FRAME_CONTROL_VALID(rx_mpdu_info); 395 } 396 397 /* 398 * hal_rx_mpdu_get_addr1_6390(): API to check get address1 of the mpdu 399 * 400 * @buf: pointer to the start of RX PKT TLV headera 401 * @mac_addr: pointer to mac address 402 * Return: success/failure 403 */ 404 static QDF_STATUS hal_rx_mpdu_get_addr1_6390(uint8_t *buf, uint8_t *mac_addr) 405 { 406 struct __attribute__((__packed__)) hal_addr1 { 407 uint32_t ad1_31_0; 408 uint16_t ad1_47_32; 409 }; 410 411 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 412 struct rx_mpdu_start *mpdu_start = 413 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 414 415 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 416 struct hal_addr1 *addr = (struct hal_addr1 *)mac_addr; 417 uint32_t mac_addr_ad1_valid; 418 419 mac_addr_ad1_valid = HAL_RX_MPDU_MAC_ADDR_AD1_VALID_GET(mpdu_info); 420 421 if (mac_addr_ad1_valid) { 422 addr->ad1_31_0 = HAL_RX_MPDU_AD1_31_0_GET(mpdu_info); 423 addr->ad1_47_32 = HAL_RX_MPDU_AD1_47_32_GET(mpdu_info); 424 return QDF_STATUS_SUCCESS; 425 } 426 427 return QDF_STATUS_E_FAILURE; 428 } 429 430 /* 431 * hal_rx_mpdu_get_addr2_6390(): API to check get address2 of the mpdu 432 * in the packet 433 * 434 * @buf: pointer to the start of RX PKT TLV header 435 * @mac_addr: pointer to mac address 436 * Return: success/failure 437 */ 438 static QDF_STATUS hal_rx_mpdu_get_addr2_6390(uint8_t *buf, 439 uint8_t *mac_addr) 440 { 441 struct __attribute__((__packed__)) hal_addr2 { 442 uint16_t ad2_15_0; 443 uint32_t ad2_47_16; 444 }; 445 446 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 447 struct rx_mpdu_start *mpdu_start = 448 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 449 450 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 451 struct hal_addr2 *addr = (struct hal_addr2 *)mac_addr; 452 uint32_t mac_addr_ad2_valid; 453 454 mac_addr_ad2_valid = HAL_RX_MPDU_MAC_ADDR_AD2_VALID_GET(mpdu_info); 455 456 if (mac_addr_ad2_valid) { 457 addr->ad2_15_0 = HAL_RX_MPDU_AD2_15_0_GET(mpdu_info); 458 addr->ad2_47_16 = HAL_RX_MPDU_AD2_47_16_GET(mpdu_info); 459 return QDF_STATUS_SUCCESS; 460 } 461 462 return QDF_STATUS_E_FAILURE; 463 } 464 465 /* 466 * hal_rx_mpdu_get_addr3_6390(): API to get address3 of the mpdu 467 * in the packet 468 * 469 * @buf: pointer to the start of RX PKT TLV header 470 * @mac_addr: pointer to mac address 471 * Return: success/failure 472 */ 473 static QDF_STATUS hal_rx_mpdu_get_addr3_6390(uint8_t *buf, uint8_t *mac_addr) 474 { 475 struct __attribute__((__packed__)) hal_addr3 { 476 uint32_t ad3_31_0; 477 uint16_t ad3_47_32; 478 }; 479 480 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 481 struct rx_mpdu_start *mpdu_start = 482 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 483 484 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 485 struct hal_addr3 *addr = (struct hal_addr3 *)mac_addr; 486 uint32_t mac_addr_ad3_valid; 487 488 mac_addr_ad3_valid = HAL_RX_MPDU_MAC_ADDR_AD3_VALID_GET(mpdu_info); 489 490 if (mac_addr_ad3_valid) { 491 addr->ad3_31_0 = HAL_RX_MPDU_AD3_31_0_GET(mpdu_info); 492 addr->ad3_47_32 = HAL_RX_MPDU_AD3_47_32_GET(mpdu_info); 493 return QDF_STATUS_SUCCESS; 494 } 495 496 return QDF_STATUS_E_FAILURE; 497 } 498 499 /* 500 * hal_rx_mpdu_get_addr4_6390(): API to get address4 of the mpdu 501 * in the packet 502 * 503 * @buf: pointer to the start of RX PKT TLV header 504 * @mac_addr: pointer to mac address 505 * Return: success/failure 506 */ 507 static QDF_STATUS hal_rx_mpdu_get_addr4_6390(uint8_t *buf, uint8_t *mac_addr) 508 { 509 struct __attribute__((__packed__)) hal_addr4 { 510 uint32_t ad4_31_0; 511 uint16_t ad4_47_32; 512 }; 513 514 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 515 struct rx_mpdu_start *mpdu_start = 516 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 517 518 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 519 struct hal_addr4 *addr = (struct hal_addr4 *)mac_addr; 520 uint32_t mac_addr_ad4_valid; 521 522 mac_addr_ad4_valid = HAL_RX_MPDU_MAC_ADDR_AD4_VALID_GET(mpdu_info); 523 524 if (mac_addr_ad4_valid) { 525 addr->ad4_31_0 = HAL_RX_MPDU_AD4_31_0_GET(mpdu_info); 526 addr->ad4_47_32 = HAL_RX_MPDU_AD4_47_32_GET(mpdu_info); 527 return QDF_STATUS_SUCCESS; 528 } 529 530 return QDF_STATUS_E_FAILURE; 531 } 532 533 /* 534 * hal_rx_get_mpdu_sequence_control_valid_6390(): Get mpdu 535 * sequence control valid 536 * 537 * @nbuf: Network buffer 538 * Returns: value of sequence control valid field 539 */ 540 static uint8_t hal_rx_get_mpdu_sequence_control_valid_6390(uint8_t *buf) 541 { 542 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 543 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 544 545 return HAL_RX_MPDU_GET_SEQUENCE_CONTROL_VALID(rx_mpdu_info); 546 } 547 548 /** 549 * hal_rx_is_unicast_6390: check packet is unicast frame or not. 550 * 551 * @ buf: pointer to rx pkt TLV. 552 * 553 * Return: true on unicast. 554 */ 555 static bool hal_rx_is_unicast_6390(uint8_t *buf) 556 { 557 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 558 struct rx_mpdu_start *mpdu_start = 559 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 560 uint32_t grp_id; 561 uint8_t *rx_mpdu_info = (uint8_t *)&mpdu_start->rx_mpdu_info_details; 562 563 grp_id = (_HAL_MS((*_OFFSET_TO_WORD_PTR((rx_mpdu_info), 564 RX_MPDU_INFO_0_SW_FRAME_GROUP_ID_OFFSET)), 565 RX_MPDU_INFO_0_SW_FRAME_GROUP_ID_MASK, 566 RX_MPDU_INFO_0_SW_FRAME_GROUP_ID_LSB)); 567 568 return (HAL_MPDU_SW_FRAME_GROUP_UNICAST_DATA == grp_id) ? true : false; 569 } 570 571 /** 572 * hal_rx_tid_get_6390: get tid based on qos control valid. 573 * @hal_soc_hdl: hal soc handle 574 * @buf: pointer to rx pkt TLV. 575 * 576 * Return: tid 577 */ 578 static uint32_t hal_rx_tid_get_6390(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 579 { 580 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 581 struct rx_mpdu_start *mpdu_start = 582 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 583 uint8_t *rx_mpdu_info = (uint8_t *)&mpdu_start->rx_mpdu_info_details; 584 uint8_t qos_control_valid = 585 (_HAL_MS((*_OFFSET_TO_WORD_PTR((rx_mpdu_info), 586 RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_OFFSET)), 587 RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_MASK, 588 RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_LSB)); 589 590 if (qos_control_valid) 591 return hal_rx_mpdu_start_tid_get_6390(buf); 592 593 return HAL_RX_NON_QOS_TID; 594 } 595 596 /** 597 * hal_rx_hw_desc_get_ppduid_get_6390(): retrieve ppdu id 598 * @rx_tlv_hdr: start address of rx_pkt_tlvs 599 * @rxdma_dst_ring_desc: Rx HW descriptor 600 * 601 * Return: ppdu id 602 */ 603 static uint32_t hal_rx_hw_desc_get_ppduid_get_6390(void *rx_tlv_hdr, 604 void *rxdma_dst_ring_desc) 605 { 606 struct rx_mpdu_info *rx_mpdu_info; 607 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)rx_tlv_hdr; 608 609 rx_mpdu_info = 610 &rx_desc->mpdu_start_tlv.rx_mpdu_start.rx_mpdu_info_details; 611 612 return HAL_RX_GET(rx_mpdu_info, RX_MPDU_INFO_0, PHY_PPDU_ID); 613 } 614 615 /** 616 * hal_reo_status_get_header_6390 - Process reo desc info 617 * @ring_desc: REO status ring descriptor 618 * @b - tlv type info 619 * @h1 - Pointer to hal_reo_status_header where info to be stored 620 * 621 * Return - none. 622 * 623 */ 624 static void hal_reo_status_get_header_6390(hal_ring_desc_t ring_desc, int b, 625 void *h1) 626 { 627 uint32_t *d = (uint32_t *)ring_desc; 628 uint32_t val1 = 0; 629 struct hal_reo_status_header *h = 630 (struct hal_reo_status_header *)h1; 631 632 /* Offsets of descriptor fields defined in HW headers start 633 * from the field after TLV header 634 */ 635 d += HAL_GET_NUM_DWORDS(sizeof(struct tlv_32_hdr)); 636 637 switch (b) { 638 case HAL_REO_QUEUE_STATS_STATUS_TLV: 639 val1 = d[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_0, 640 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 641 break; 642 case HAL_REO_FLUSH_QUEUE_STATUS_TLV: 643 val1 = d[HAL_OFFSET_DW(REO_FLUSH_QUEUE_STATUS_0, 644 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 645 break; 646 case HAL_REO_FLUSH_CACHE_STATUS_TLV: 647 val1 = d[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_0, 648 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 649 break; 650 case HAL_REO_UNBLK_CACHE_STATUS_TLV: 651 val1 = d[HAL_OFFSET_DW(REO_UNBLOCK_CACHE_STATUS_0, 652 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 653 break; 654 case HAL_REO_TIMOUT_LIST_STATUS_TLV: 655 val1 = d[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_0, 656 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 657 break; 658 case HAL_REO_DESC_THRES_STATUS_TLV: 659 val1 = 660 d[HAL_OFFSET_DW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0, 661 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 662 break; 663 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: 664 val1 = d[HAL_OFFSET_DW(REO_UPDATE_RX_REO_QUEUE_STATUS_0, 665 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 666 break; 667 default: 668 qdf_nofl_err("ERROR: Unknown tlv\n"); 669 break; 670 } 671 h->cmd_num = 672 HAL_GET_FIELD( 673 UNIFORM_REO_STATUS_HEADER_0, REO_STATUS_NUMBER, 674 val1); 675 h->exec_time = 676 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_0, 677 CMD_EXECUTION_TIME, val1); 678 h->status = 679 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_0, 680 REO_CMD_EXECUTION_STATUS, val1); 681 switch (b) { 682 case HAL_REO_QUEUE_STATS_STATUS_TLV: 683 val1 = d[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_1, 684 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 685 break; 686 case HAL_REO_FLUSH_QUEUE_STATUS_TLV: 687 val1 = d[HAL_OFFSET_DW(REO_FLUSH_QUEUE_STATUS_1, 688 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 689 break; 690 case HAL_REO_FLUSH_CACHE_STATUS_TLV: 691 val1 = d[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_1, 692 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 693 break; 694 case HAL_REO_UNBLK_CACHE_STATUS_TLV: 695 val1 = d[HAL_OFFSET_DW(REO_UNBLOCK_CACHE_STATUS_1, 696 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 697 break; 698 case HAL_REO_TIMOUT_LIST_STATUS_TLV: 699 val1 = d[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_1, 700 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 701 break; 702 case HAL_REO_DESC_THRES_STATUS_TLV: 703 val1 = 704 d[HAL_OFFSET_DW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_1, 705 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 706 break; 707 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: 708 val1 = d[HAL_OFFSET_DW(REO_UPDATE_RX_REO_QUEUE_STATUS_1, 709 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 710 break; 711 default: 712 qdf_nofl_err("ERROR: Unknown tlv\n"); 713 break; 714 } 715 h->tstamp = 716 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_1, TIMESTAMP, val1); 717 } 718 719 /** 720 * hal_rx_mpdu_start_mpdu_qos_control_valid_get_6390(): 721 * Retrieve qos control valid bit from the tlv. 722 * @buf: pointer to rx pkt TLV. 723 * 724 * Return: qos control value. 725 */ 726 static inline uint32_t 727 hal_rx_mpdu_start_mpdu_qos_control_valid_get_6390(uint8_t *buf) 728 { 729 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 730 struct rx_mpdu_start *mpdu_start = 731 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 732 733 return HAL_RX_MPDU_INFO_QOS_CONTROL_VALID_GET( 734 &mpdu_start->rx_mpdu_info_details); 735 } 736 737 /** 738 * hal_rx_msdu_end_sa_sw_peer_id_get_6390(): API to get the 739 * sa_sw_peer_id from rx_msdu_end TLV 740 * @buf: pointer to the start of RX PKT TLV headers 741 * 742 * Return: sa_sw_peer_id index 743 */ 744 static inline uint32_t 745 hal_rx_msdu_end_sa_sw_peer_id_get_6390(uint8_t *buf) 746 { 747 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 748 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 749 750 return HAL_RX_MSDU_END_SA_SW_PEER_ID_GET(msdu_end); 751 } 752 753 /** 754 * hal_tx_desc_set_mesh_en_6390 - Set mesh_enable flag in Tx descriptor 755 * @desc: Handle to Tx Descriptor 756 * @en: For raw WiFi frames, this indicates transmission to a mesh STA, 757 * enabling the interpretation of the 'Mesh Control Present' bit 758 * (bit 8) of QoS Control (otherwise this bit is ignored), 759 * For native WiFi frames, this indicates that a 'Mesh Control' field 760 * is present between the header and the LLC. 761 * 762 * Return: void 763 */ 764 static inline 765 void hal_tx_desc_set_mesh_en_6390(void *desc, uint8_t en) 766 { 767 HAL_SET_FLD(desc, TCL_DATA_CMD_4, MESH_ENABLE) |= 768 HAL_TX_SM(TCL_DATA_CMD_4, MESH_ENABLE, en); 769 } 770 771 static 772 void *hal_rx_msdu0_buffer_addr_lsb_6390(void *link_desc_va) 773 { 774 return (void *)HAL_RX_MSDU0_BUFFER_ADDR_LSB(link_desc_va); 775 } 776 777 static 778 void *hal_rx_msdu_desc_info_ptr_get_6390(void *msdu0) 779 { 780 return (void *)HAL_RX_MSDU_DESC_INFO_PTR_GET(msdu0); 781 } 782 783 static 784 void *hal_ent_mpdu_desc_info_6390(void *ent_ring_desc) 785 { 786 return (void *)HAL_ENT_MPDU_DESC_INFO(ent_ring_desc); 787 } 788 789 static 790 void *hal_dst_mpdu_desc_info_6390(void *dst_ring_desc) 791 { 792 return (void *)HAL_DST_MPDU_DESC_INFO(dst_ring_desc); 793 } 794 795 static 796 uint8_t hal_rx_get_fc_valid_6390(uint8_t *buf) 797 { 798 return HAL_RX_GET_FC_VALID(buf); 799 } 800 801 static uint8_t hal_rx_get_to_ds_flag_6390(uint8_t *buf) 802 { 803 return HAL_RX_GET_TO_DS_FLAG(buf); 804 } 805 806 static uint8_t hal_rx_get_mac_addr2_valid_6390(uint8_t *buf) 807 { 808 return HAL_RX_GET_MAC_ADDR2_VALID(buf); 809 } 810 811 static uint8_t hal_rx_get_filter_category_6390(uint8_t *buf) 812 { 813 return HAL_RX_GET_FILTER_CATEGORY(buf); 814 } 815 816 static uint32_t 817 hal_rx_get_ppdu_id_6390(uint8_t *buf) 818 { 819 return HAL_RX_GET_PPDU_ID(buf); 820 } 821 822 /** 823 * hal_reo_config_6390(): Set reo config parameters 824 * @soc: hal soc handle 825 * @reg_val: value to be set 826 * @reo_params: reo parameters 827 * 828 * Return: void 829 */ 830 static 831 void hal_reo_config_6390(struct hal_soc *soc, 832 uint32_t reg_val, 833 struct hal_reo_params *reo_params) 834 { 835 HAL_REO_R0_CONFIG(soc, reg_val, reo_params); 836 } 837 838 /** 839 * hal_rx_msdu_desc_info_get_ptr_6390() - Get msdu desc info ptr 840 * @msdu_details_ptr - Pointer to msdu_details_ptr 841 * Return - Pointer to rx_msdu_desc_info structure. 842 * 843 */ 844 static void *hal_rx_msdu_desc_info_get_ptr_6390(void *msdu_details_ptr) 845 { 846 return HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr); 847 } 848 849 /** 850 * hal_rx_link_desc_msdu0_ptr_6390 - Get pointer to rx_msdu details 851 * @link_desc - Pointer to link desc 852 * Return - Pointer to rx_msdu_details structure 853 * 854 */ 855 static void *hal_rx_link_desc_msdu0_ptr_6390(void *link_desc) 856 { 857 return HAL_RX_LINK_DESC_MSDU0_PTR(link_desc); 858 } 859 860 /** 861 * hal_rx_msdu_flow_idx_get_6390: API to get flow index 862 * from rx_msdu_end TLV 863 * @buf: pointer to the start of RX PKT TLV headers 864 * 865 * Return: flow index value from MSDU END TLV 866 */ 867 static inline uint32_t hal_rx_msdu_flow_idx_get_6390(uint8_t *buf) 868 { 869 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 870 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 871 872 return HAL_RX_MSDU_END_FLOW_IDX_GET(msdu_end); 873 } 874 875 /** 876 * hal_rx_msdu_flow_idx_invalid_6390: API to get flow index invalid 877 * from rx_msdu_end TLV 878 * @buf: pointer to the start of RX PKT TLV headers 879 * 880 * Return: flow index invalid value from MSDU END TLV 881 */ 882 static bool hal_rx_msdu_flow_idx_invalid_6390(uint8_t *buf) 883 { 884 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 885 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 886 887 return HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(msdu_end); 888 } 889 890 /** 891 * hal_rx_msdu_flow_idx_timeout_6390: API to get flow index timeout 892 * from rx_msdu_end TLV 893 * @buf: pointer to the start of RX PKT TLV headers 894 * 895 * Return: flow index timeout value from MSDU END TLV 896 */ 897 static bool hal_rx_msdu_flow_idx_timeout_6390(uint8_t *buf) 898 { 899 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 900 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 901 902 return HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(msdu_end); 903 } 904 905 /** 906 * hal_rx_msdu_fse_metadata_get_6390: API to get FSE metadata 907 * from rx_msdu_end TLV 908 * @buf: pointer to the start of RX PKT TLV headers 909 * 910 * Return: fse metadata value from MSDU END TLV 911 */ 912 static uint32_t hal_rx_msdu_fse_metadata_get_6390(uint8_t *buf) 913 { 914 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 915 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 916 917 return HAL_RX_MSDU_END_FSE_METADATA_GET(msdu_end); 918 } 919 920 /** 921 * hal_rx_msdu_cce_metadata_get_6390: API to get CCE metadata 922 * from rx_msdu_end TLV 923 * @buf: pointer to the start of RX PKT TLV headers 924 * 925 * Return: cce metadata 926 */ 927 static uint16_t 928 hal_rx_msdu_cce_metadata_get_6390(uint8_t *buf) 929 { 930 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 931 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 932 933 return HAL_RX_MSDU_END_CCE_METADATA_GET(msdu_end); 934 } 935 936 /** 937 * hal_rx_msdu_get_flow_params_6390: API to get flow index, flow index invalid 938 * and flow index timeout from rx_msdu_end TLV 939 * @buf: pointer to the start of RX PKT TLV headers 940 * @flow_invalid: pointer to return value of flow_idx_valid 941 * @flow_timeout: pointer to return value of flow_idx_timeout 942 * @flow_index: pointer to return value of flow_idx 943 * 944 * Return: none 945 */ 946 static inline void 947 hal_rx_msdu_get_flow_params_6390(uint8_t *buf, 948 bool *flow_invalid, 949 bool *flow_timeout, 950 uint32_t *flow_index) 951 { 952 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 953 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 954 955 *flow_invalid = HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(msdu_end); 956 *flow_timeout = HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(msdu_end); 957 *flow_index = HAL_RX_MSDU_END_FLOW_IDX_GET(msdu_end); 958 } 959 960 /** 961 * hal_rx_tlv_get_tcp_chksum_6390() - API to get tcp checksum 962 * @buf: rx_tlv_hdr 963 * 964 * Return: tcp checksum 965 */ 966 static uint16_t 967 hal_rx_tlv_get_tcp_chksum_6390(uint8_t *buf) 968 { 969 return HAL_RX_TLV_GET_TCP_CHKSUM(buf); 970 } 971 972 /** 973 * hal_rx_get_rx_sequence_6390(): Function to retrieve rx sequence number 974 * 975 * @nbuf: Network buffer 976 * Returns: rx sequence number 977 */ 978 static 979 uint16_t hal_rx_get_rx_sequence_6390(uint8_t *buf) 980 { 981 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 982 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 983 984 return HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info); 985 } 986 987 /** 988 * hal_rx_mpdu_start_tlv_tag_valid_6390 () - API to check if RX_MPDU_START 989 * tlv tag is valid 990 * 991 *@rx_tlv_hdr: start address of rx_pkt_tlvs 992 * 993 * Return: true if RX_MPDU_START is valied, else false. 994 */ 995 static uint8_t hal_rx_mpdu_start_tlv_tag_valid_6390(void *rx_tlv_hdr) 996 { 997 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)rx_tlv_hdr; 998 uint32_t tlv_tag; 999 1000 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(&rx_desc->mpdu_start_tlv); 1001 1002 return tlv_tag == WIFIRX_MPDU_START_E ? true : false; 1003 } 1004 1005 /** 1006 * hal_get_window_address_6390(): Function to get hp/tp address 1007 * @hal_soc: Pointer to hal_soc 1008 * @addr: address offset of register 1009 * 1010 * Return: modified address offset of register 1011 */ 1012 static inline qdf_iomem_t hal_get_window_address_6390(struct hal_soc *hal_soc, 1013 qdf_iomem_t addr) 1014 { 1015 return addr; 1016 } 1017 1018 /** 1019 * hal_reo_set_err_dst_remap_6390(): Function to set REO error destination 1020 * ring remap register 1021 * @hal_soc: Pointer to hal_soc 1022 * 1023 * Return: none. 1024 */ 1025 static void 1026 hal_reo_set_err_dst_remap_6390(void *hal_soc) 1027 { 1028 /* 1029 * Set REO error 2k jump (error code 5) / OOR (error code 7) 1030 * frame routed to REO2TCL ring. 1031 */ 1032 uint32_t dst_remap_ix0 = 1033 HAL_REO_ERR_REMAP_IX0(REO_REMAP_RELEASE, 0) | 1034 HAL_REO_ERR_REMAP_IX0(REO_REMAP_RELEASE, 1) | 1035 HAL_REO_ERR_REMAP_IX0(REO_REMAP_RELEASE, 2) | 1036 HAL_REO_ERR_REMAP_IX0(REO_REMAP_RELEASE, 3) | 1037 HAL_REO_ERR_REMAP_IX0(REO_REMAP_RELEASE, 4) | 1038 HAL_REO_ERR_REMAP_IX0(REO_REMAP_TCL, 5) | 1039 HAL_REO_ERR_REMAP_IX0(REO_REMAP_TCL, 6) | 1040 HAL_REO_ERR_REMAP_IX0(REO_REMAP_TCL, 7) | 1041 HAL_REO_ERR_REMAP_IX0(REO_REMAP_TCL, 8) | 1042 HAL_REO_ERR_REMAP_IX0(REO_REMAP_RELEASE, 9); 1043 1044 HAL_REG_WRITE(hal_soc, 1045 HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ADDR( 1046 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1047 dst_remap_ix0); 1048 1049 hal_info("HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0 0x%x", 1050 HAL_REG_READ( 1051 hal_soc, 1052 HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ADDR( 1053 SEQ_WCSS_UMAC_REO_REG_OFFSET))); 1054 } 1055 1056 static 1057 void hal_compute_reo_remap_ix2_ix3_6390(uint32_t *ring, uint32_t num_rings, 1058 uint32_t *remap1, uint32_t *remap2) 1059 { 1060 switch (num_rings) { 1061 case 3: 1062 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 1063 HAL_REO_REMAP_IX2(ring[1], 17) | 1064 HAL_REO_REMAP_IX2(ring[2], 18) | 1065 HAL_REO_REMAP_IX2(ring[0], 19) | 1066 HAL_REO_REMAP_IX2(ring[1], 20) | 1067 HAL_REO_REMAP_IX2(ring[2], 21) | 1068 HAL_REO_REMAP_IX2(ring[0], 22) | 1069 HAL_REO_REMAP_IX2(ring[1], 23); 1070 1071 *remap2 = HAL_REO_REMAP_IX3(ring[2], 24) | 1072 HAL_REO_REMAP_IX3(ring[0], 25) | 1073 HAL_REO_REMAP_IX3(ring[1], 26) | 1074 HAL_REO_REMAP_IX3(ring[2], 27) | 1075 HAL_REO_REMAP_IX3(ring[0], 28) | 1076 HAL_REO_REMAP_IX3(ring[1], 29) | 1077 HAL_REO_REMAP_IX3(ring[2], 30) | 1078 HAL_REO_REMAP_IX3(ring[0], 31); 1079 break; 1080 case 4: 1081 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 1082 HAL_REO_REMAP_IX2(ring[1], 17) | 1083 HAL_REO_REMAP_IX2(ring[2], 18) | 1084 HAL_REO_REMAP_IX2(ring[3], 19) | 1085 HAL_REO_REMAP_IX2(ring[0], 20) | 1086 HAL_REO_REMAP_IX2(ring[1], 21) | 1087 HAL_REO_REMAP_IX2(ring[2], 22) | 1088 HAL_REO_REMAP_IX2(ring[3], 23); 1089 1090 *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) | 1091 HAL_REO_REMAP_IX3(ring[1], 25) | 1092 HAL_REO_REMAP_IX3(ring[2], 26) | 1093 HAL_REO_REMAP_IX3(ring[3], 27) | 1094 HAL_REO_REMAP_IX3(ring[0], 28) | 1095 HAL_REO_REMAP_IX3(ring[1], 29) | 1096 HAL_REO_REMAP_IX3(ring[2], 30) | 1097 HAL_REO_REMAP_IX3(ring[3], 31); 1098 break; 1099 } 1100 } 1101 1102 static void hal_hw_txrx_ops_attach_qca6390(struct hal_soc *hal_soc) 1103 { 1104 /* init and setup */ 1105 hal_soc->ops->hal_srng_dst_hw_init = hal_srng_dst_hw_init_generic; 1106 hal_soc->ops->hal_srng_src_hw_init = hal_srng_src_hw_init_generic; 1107 hal_soc->ops->hal_get_hw_hptp = hal_get_hw_hptp_generic; 1108 hal_soc->ops->hal_reo_setup = hal_reo_setup_generic_li; 1109 hal_soc->ops->hal_get_window_address = hal_get_window_address_6390; 1110 hal_soc->ops->hal_reo_set_err_dst_remap = 1111 hal_reo_set_err_dst_remap_6390; 1112 1113 /* tx */ 1114 hal_soc->ops->hal_tx_desc_set_dscp_tid_table_id = 1115 hal_tx_desc_set_dscp_tid_table_id_6390; 1116 hal_soc->ops->hal_tx_set_dscp_tid_map = hal_tx_set_dscp_tid_map_6390; 1117 hal_soc->ops->hal_tx_update_dscp_tid = hal_tx_update_dscp_tid_6390; 1118 hal_soc->ops->hal_tx_desc_set_lmac_id = hal_tx_desc_set_lmac_id_6390; 1119 hal_soc->ops->hal_tx_desc_set_buf_addr = 1120 hal_tx_desc_set_buf_addr_generic_li; 1121 hal_soc->ops->hal_tx_desc_set_search_type = 1122 hal_tx_desc_set_search_type_generic_li; 1123 hal_soc->ops->hal_tx_desc_set_search_index = 1124 hal_tx_desc_set_search_index_generic_li; 1125 hal_soc->ops->hal_tx_desc_set_cache_set_num = 1126 hal_tx_desc_set_cache_set_num_generic_li; 1127 hal_soc->ops->hal_tx_comp_get_status = 1128 hal_tx_comp_get_status_generic_li; 1129 hal_soc->ops->hal_tx_comp_get_release_reason = 1130 hal_tx_comp_get_release_reason_generic_li; 1131 hal_soc->ops->hal_get_wbm_internal_error = 1132 hal_get_wbm_internal_error_generic_li; 1133 hal_soc->ops->hal_tx_desc_set_mesh_en = hal_tx_desc_set_mesh_en_6390; 1134 hal_soc->ops->hal_tx_init_cmd_credit_ring = 1135 hal_tx_init_cmd_credit_ring_6390; 1136 1137 /* rx */ 1138 hal_soc->ops->hal_rx_msdu_start_nss_get = 1139 hal_rx_msdu_start_nss_get_6390; 1140 hal_soc->ops->hal_rx_mon_hw_desc_get_mpdu_status = 1141 hal_rx_mon_hw_desc_get_mpdu_status_6390; 1142 hal_soc->ops->hal_rx_get_tlv = hal_rx_get_tlv_6390; 1143 hal_soc->ops->hal_rx_proc_phyrx_other_receive_info_tlv = 1144 hal_rx_proc_phyrx_other_receive_info_tlv_6390; 1145 hal_soc->ops->hal_rx_dump_msdu_start_tlv = 1146 hal_rx_dump_msdu_start_tlv_6390; 1147 hal_soc->ops->hal_rx_dump_msdu_end_tlv = hal_rx_dump_msdu_end_tlv_6390; 1148 hal_soc->ops->hal_get_link_desc_size = hal_get_link_desc_size_6390; 1149 hal_soc->ops->hal_rx_mpdu_start_tid_get = 1150 hal_rx_mpdu_start_tid_get_6390; 1151 hal_soc->ops->hal_rx_msdu_start_reception_type_get = 1152 hal_rx_msdu_start_reception_type_get_6390; 1153 hal_soc->ops->hal_rx_msdu_end_da_idx_get = 1154 hal_rx_msdu_end_da_idx_get_6390; 1155 hal_soc->ops->hal_rx_msdu_desc_info_get_ptr = 1156 hal_rx_msdu_desc_info_get_ptr_6390; 1157 hal_soc->ops->hal_rx_link_desc_msdu0_ptr = 1158 hal_rx_link_desc_msdu0_ptr_6390; 1159 hal_soc->ops->hal_reo_status_get_header = 1160 hal_reo_status_get_header_6390; 1161 hal_soc->ops->hal_rx_status_get_tlv_info = 1162 hal_rx_status_get_tlv_info_generic_li; 1163 hal_soc->ops->hal_rx_wbm_err_info_get = 1164 hal_rx_wbm_err_info_get_generic_li; 1165 hal_soc->ops->hal_rx_dump_mpdu_start_tlv = 1166 hal_rx_dump_mpdu_start_tlv_generic_li; 1167 1168 hal_soc->ops->hal_tx_set_pcp_tid_map = 1169 hal_tx_set_pcp_tid_map_generic_li; 1170 hal_soc->ops->hal_tx_update_pcp_tid_map = 1171 hal_tx_update_pcp_tid_generic_li; 1172 hal_soc->ops->hal_tx_set_tidmap_prty = 1173 hal_tx_update_tidmap_prty_generic_li; 1174 hal_soc->ops->hal_rx_get_rx_fragment_number = 1175 hal_rx_get_rx_fragment_number_6390; 1176 hal_soc->ops->hal_rx_msdu_end_da_is_mcbc_get = 1177 hal_rx_msdu_end_da_is_mcbc_get_6390; 1178 hal_soc->ops->hal_rx_msdu_end_sa_is_valid_get = 1179 hal_rx_msdu_end_sa_is_valid_get_6390; 1180 hal_soc->ops->hal_rx_msdu_end_sa_idx_get = 1181 hal_rx_msdu_end_sa_idx_get_6390; 1182 hal_soc->ops->hal_rx_desc_is_first_msdu = 1183 hal_rx_desc_is_first_msdu_6390; 1184 hal_soc->ops->hal_rx_msdu_end_l3_hdr_padding_get = 1185 hal_rx_msdu_end_l3_hdr_padding_get_6390; 1186 hal_soc->ops->hal_rx_encryption_info_valid = 1187 hal_rx_encryption_info_valid_6390; 1188 hal_soc->ops->hal_rx_print_pn = hal_rx_print_pn_6390; 1189 hal_soc->ops->hal_rx_msdu_end_first_msdu_get = 1190 hal_rx_msdu_end_first_msdu_get_6390; 1191 hal_soc->ops->hal_rx_msdu_end_da_is_valid_get = 1192 hal_rx_msdu_end_da_is_valid_get_6390; 1193 hal_soc->ops->hal_rx_msdu_end_last_msdu_get = 1194 hal_rx_msdu_end_last_msdu_get_6390; 1195 hal_soc->ops->hal_rx_get_mpdu_mac_ad4_valid = 1196 hal_rx_get_mpdu_mac_ad4_valid_6390; 1197 hal_soc->ops->hal_rx_mpdu_start_sw_peer_id_get = 1198 hal_rx_mpdu_start_sw_peer_id_get_6390; 1199 hal_soc->ops->hal_rx_mpdu_get_to_ds = hal_rx_mpdu_get_to_ds_6390; 1200 hal_soc->ops->hal_rx_mpdu_get_fr_ds = hal_rx_mpdu_get_fr_ds_6390; 1201 hal_soc->ops->hal_rx_get_mpdu_frame_control_valid = 1202 hal_rx_get_mpdu_frame_control_valid_6390; 1203 hal_soc->ops->hal_rx_mpdu_get_addr1 = hal_rx_mpdu_get_addr1_6390; 1204 hal_soc->ops->hal_rx_mpdu_get_addr2 = hal_rx_mpdu_get_addr2_6390; 1205 hal_soc->ops->hal_rx_mpdu_get_addr3 = hal_rx_mpdu_get_addr3_6390; 1206 hal_soc->ops->hal_rx_mpdu_get_addr4 = hal_rx_mpdu_get_addr4_6390; 1207 hal_soc->ops->hal_rx_get_mpdu_sequence_control_valid = 1208 hal_rx_get_mpdu_sequence_control_valid_6390; 1209 hal_soc->ops->hal_rx_is_unicast = hal_rx_is_unicast_6390; 1210 hal_soc->ops->hal_rx_tid_get = hal_rx_tid_get_6390; 1211 hal_soc->ops->hal_rx_hw_desc_get_ppduid_get = 1212 hal_rx_hw_desc_get_ppduid_get_6390; 1213 hal_soc->ops->hal_rx_mpdu_start_mpdu_qos_control_valid_get = 1214 hal_rx_mpdu_start_mpdu_qos_control_valid_get_6390; 1215 hal_soc->ops->hal_rx_msdu_end_sa_sw_peer_id_get = 1216 hal_rx_msdu_end_sa_sw_peer_id_get_6390; 1217 hal_soc->ops->hal_rx_msdu0_buffer_addr_lsb = 1218 hal_rx_msdu0_buffer_addr_lsb_6390; 1219 hal_soc->ops->hal_rx_msdu_desc_info_ptr_get = 1220 hal_rx_msdu_desc_info_ptr_get_6390; 1221 hal_soc->ops->hal_ent_mpdu_desc_info = hal_ent_mpdu_desc_info_6390; 1222 hal_soc->ops->hal_dst_mpdu_desc_info = hal_dst_mpdu_desc_info_6390; 1223 hal_soc->ops->hal_rx_get_fc_valid = hal_rx_get_fc_valid_6390; 1224 hal_soc->ops->hal_rx_get_to_ds_flag = hal_rx_get_to_ds_flag_6390; 1225 hal_soc->ops->hal_rx_get_mac_addr2_valid = 1226 hal_rx_get_mac_addr2_valid_6390; 1227 hal_soc->ops->hal_rx_get_filter_category = 1228 hal_rx_get_filter_category_6390; 1229 hal_soc->ops->hal_rx_get_ppdu_id = hal_rx_get_ppdu_id_6390; 1230 hal_soc->ops->hal_reo_config = hal_reo_config_6390; 1231 hal_soc->ops->hal_rx_msdu_flow_idx_get = hal_rx_msdu_flow_idx_get_6390; 1232 hal_soc->ops->hal_rx_msdu_flow_idx_invalid = 1233 hal_rx_msdu_flow_idx_invalid_6390; 1234 hal_soc->ops->hal_rx_msdu_flow_idx_timeout = 1235 hal_rx_msdu_flow_idx_timeout_6390; 1236 hal_soc->ops->hal_rx_msdu_fse_metadata_get = 1237 hal_rx_msdu_fse_metadata_get_6390; 1238 hal_soc->ops->hal_rx_msdu_cce_metadata_get = 1239 hal_rx_msdu_cce_metadata_get_6390; 1240 hal_soc->ops->hal_rx_msdu_get_flow_params = 1241 hal_rx_msdu_get_flow_params_6390; 1242 hal_soc->ops->hal_rx_tlv_get_tcp_chksum = 1243 hal_rx_tlv_get_tcp_chksum_6390; 1244 hal_soc->ops->hal_rx_get_rx_sequence = hal_rx_get_rx_sequence_6390; 1245 /* rx - msdu end fast path info fields */ 1246 hal_soc->ops->hal_rx_msdu_packet_metadata_get = 1247 hal_rx_msdu_packet_metadata_get_generic_li; 1248 hal_soc->ops->hal_rx_mpdu_start_tlv_tag_valid = 1249 hal_rx_mpdu_start_tlv_tag_valid_6390; 1250 1251 /* rx - TLV struct offsets */ 1252 hal_soc->ops->hal_rx_msdu_end_offset_get = 1253 hal_rx_msdu_end_offset_get_generic; 1254 hal_soc->ops->hal_rx_attn_offset_get = hal_rx_attn_offset_get_generic; 1255 hal_soc->ops->hal_rx_msdu_start_offset_get = 1256 hal_rx_msdu_start_offset_get_generic; 1257 hal_soc->ops->hal_rx_mpdu_start_offset_get = 1258 hal_rx_mpdu_start_offset_get_generic; 1259 hal_soc->ops->hal_rx_mpdu_end_offset_get = 1260 hal_rx_mpdu_end_offset_get_generic; 1261 #ifndef NO_RX_PKT_HDR_TLV 1262 hal_soc->ops->hal_rx_pkt_tlv_offset_get = 1263 hal_rx_pkt_tlv_offset_get_generic; 1264 #endif 1265 hal_soc->ops->hal_compute_reo_remap_ix2_ix3 = 1266 hal_compute_reo_remap_ix2_ix3_6390; 1267 hal_soc->ops->hal_setup_link_idle_list = 1268 hal_setup_link_idle_list_generic_li; 1269 }; 1270 1271 struct hal_hw_srng_config hw_srng_table_6390[] = { 1272 /* TODO: max_rings can populated by querying HW capabilities */ 1273 { /* REO_DST */ 1274 .start_ring_id = HAL_SRNG_REO2SW1, 1275 .max_rings = 4, 1276 .entry_size = sizeof(struct reo_destination_ring) >> 2, 1277 .lmac_ring = FALSE, 1278 .ring_dir = HAL_SRNG_DST_RING, 1279 .reg_start = { 1280 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR( 1281 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1282 HWIO_REO_R2_REO2SW1_RING_HP_ADDR( 1283 SEQ_WCSS_UMAC_REO_REG_OFFSET) 1284 }, 1285 .reg_size = { 1286 HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(0) - 1287 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(0), 1288 HWIO_REO_R2_REO2SW2_RING_HP_ADDR(0) - 1289 HWIO_REO_R2_REO2SW1_RING_HP_ADDR(0), 1290 }, 1291 .max_size = 1292 HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_BMSK >> 1293 HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_SHFT, 1294 }, 1295 { /* REO_EXCEPTION */ 1296 /* Designating REO2TCL ring as exception ring. This ring is 1297 * similar to other REO2SW rings though it is named as REO2TCL. 1298 * Any of theREO2SW rings can be used as exception ring. 1299 */ 1300 .start_ring_id = HAL_SRNG_REO2TCL, 1301 .max_rings = 1, 1302 .entry_size = sizeof(struct reo_destination_ring) >> 2, 1303 .lmac_ring = FALSE, 1304 .ring_dir = HAL_SRNG_DST_RING, 1305 .reg_start = { 1306 HWIO_REO_R0_REO2TCL_RING_BASE_LSB_ADDR( 1307 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1308 HWIO_REO_R2_REO2TCL_RING_HP_ADDR( 1309 SEQ_WCSS_UMAC_REO_REG_OFFSET) 1310 }, 1311 /* Single ring - provide ring size if multiple rings of this 1312 * type are supported 1313 */ 1314 .reg_size = {}, 1315 .max_size = 1316 HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_BMSK >> 1317 HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_SHFT, 1318 }, 1319 { /* REO_REINJECT */ 1320 .start_ring_id = HAL_SRNG_SW2REO, 1321 .max_rings = 1, 1322 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 1323 .lmac_ring = FALSE, 1324 .ring_dir = HAL_SRNG_SRC_RING, 1325 .reg_start = { 1326 HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR( 1327 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1328 HWIO_REO_R2_SW2REO_RING_HP_ADDR( 1329 SEQ_WCSS_UMAC_REO_REG_OFFSET) 1330 }, 1331 /* Single ring - provide ring size if multiple rings of this 1332 * type are supported 1333 */ 1334 .reg_size = {}, 1335 .max_size = HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_BMSK >> 1336 HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_SHFT, 1337 }, 1338 { /* REO_CMD */ 1339 .start_ring_id = HAL_SRNG_REO_CMD, 1340 .max_rings = 1, 1341 .entry_size = (sizeof(struct tlv_32_hdr) + 1342 sizeof(struct reo_get_queue_stats)) >> 2, 1343 .lmac_ring = FALSE, 1344 .ring_dir = HAL_SRNG_SRC_RING, 1345 .reg_start = { 1346 HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR( 1347 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1348 HWIO_REO_R2_REO_CMD_RING_HP_ADDR( 1349 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1350 }, 1351 /* Single ring - provide ring size if multiple rings of this 1352 * type are supported 1353 */ 1354 .reg_size = {}, 1355 .max_size = 1356 HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_BMSK >> 1357 HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_SHFT, 1358 }, 1359 { /* REO_STATUS */ 1360 .start_ring_id = HAL_SRNG_REO_STATUS, 1361 .max_rings = 1, 1362 .entry_size = (sizeof(struct tlv_32_hdr) + 1363 sizeof(struct reo_get_queue_stats_status)) >> 2, 1364 .lmac_ring = FALSE, 1365 .ring_dir = HAL_SRNG_DST_RING, 1366 .reg_start = { 1367 HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR( 1368 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1369 HWIO_REO_R2_REO_STATUS_RING_HP_ADDR( 1370 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1371 }, 1372 /* Single ring - provide ring size if multiple rings of this 1373 * type are supported 1374 */ 1375 .reg_size = {}, 1376 .max_size = 1377 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> 1378 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, 1379 }, 1380 { /* TCL_DATA */ 1381 .start_ring_id = HAL_SRNG_SW2TCL1, 1382 .max_rings = 3, 1383 .entry_size = (sizeof(struct tlv_32_hdr) + 1384 sizeof(struct tcl_data_cmd)) >> 2, 1385 .lmac_ring = FALSE, 1386 .ring_dir = HAL_SRNG_SRC_RING, 1387 .reg_start = { 1388 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR( 1389 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1390 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR( 1391 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1392 }, 1393 .reg_size = { 1394 HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(0) - 1395 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(0), 1396 HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(0) - 1397 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(0), 1398 }, 1399 .max_size = 1400 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK >> 1401 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT, 1402 }, 1403 { /* TCL_CMD */ 1404 .start_ring_id = HAL_SRNG_SW2TCL_CMD, 1405 .max_rings = 1, 1406 .entry_size = (sizeof(struct tlv_32_hdr) + 1407 sizeof(struct tcl_gse_cmd)) >> 2, 1408 .lmac_ring = FALSE, 1409 .ring_dir = HAL_SRNG_SRC_RING, 1410 .reg_start = { 1411 HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_ADDR( 1412 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1413 HWIO_TCL_R2_SW2TCL_CMD_RING_HP_ADDR( 1414 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1415 }, 1416 /* Single ring - provide ring size if multiple rings of this 1417 * type are supported 1418 */ 1419 .reg_size = {}, 1420 .max_size = 1421 HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RING_SIZE_BMSK >> 1422 HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RING_SIZE_SHFT, 1423 }, 1424 { /* TCL_STATUS */ 1425 .start_ring_id = HAL_SRNG_TCL_STATUS, 1426 .max_rings = 1, 1427 .entry_size = (sizeof(struct tlv_32_hdr) + 1428 sizeof(struct tcl_status_ring)) >> 2, 1429 .lmac_ring = FALSE, 1430 .ring_dir = HAL_SRNG_DST_RING, 1431 .reg_start = { 1432 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR( 1433 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1434 HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR( 1435 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1436 }, 1437 /* Single ring - provide ring size if multiple rings of this 1438 * type are supported 1439 */ 1440 .reg_size = {}, 1441 .max_size = 1442 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_BMSK >> 1443 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_SHFT, 1444 }, 1445 { /* CE_SRC */ 1446 .start_ring_id = HAL_SRNG_CE_0_SRC, 1447 .max_rings = 12, 1448 .entry_size = sizeof(struct ce_src_desc) >> 2, 1449 .lmac_ring = FALSE, 1450 .ring_dir = HAL_SRNG_SRC_RING, 1451 .reg_start = { 1452 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR( 1453 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET), 1454 HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR( 1455 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET), 1456 }, 1457 .reg_size = { 1458 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET - 1459 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET, 1460 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET - 1461 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET, 1462 }, 1463 .max_size = 1464 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >> 1465 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT, 1466 }, 1467 { /* CE_DST */ 1468 .start_ring_id = HAL_SRNG_CE_0_DST, 1469 .max_rings = 12, 1470 .entry_size = 8 >> 2, 1471 /*TODO: entry_size above should actually be 1472 * sizeof(struct ce_dst_desc) >> 2, but couldn't find definition 1473 * of struct ce_dst_desc in HW header files 1474 */ 1475 .lmac_ring = FALSE, 1476 .ring_dir = HAL_SRNG_SRC_RING, 1477 .reg_start = { 1478 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR( 1479 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 1480 HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR( 1481 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 1482 }, 1483 .reg_size = { 1484 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 1485 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 1486 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 1487 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 1488 }, 1489 .max_size = 1490 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >> 1491 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT, 1492 }, 1493 { /* CE_DST_STATUS */ 1494 .start_ring_id = HAL_SRNG_CE_0_DST_STATUS, 1495 .max_rings = 12, 1496 .entry_size = sizeof(struct ce_stat_desc) >> 2, 1497 .lmac_ring = FALSE, 1498 .ring_dir = HAL_SRNG_DST_RING, 1499 .reg_start = { 1500 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR( 1501 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 1502 HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR( 1503 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 1504 }, 1505 /* TODO: check destination status ring registers */ 1506 .reg_size = { 1507 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 1508 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 1509 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 1510 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 1511 }, 1512 .max_size = 1513 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> 1514 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, 1515 }, 1516 { /* WBM_IDLE_LINK */ 1517 .start_ring_id = HAL_SRNG_WBM_IDLE_LINK, 1518 .max_rings = 1, 1519 .entry_size = sizeof(struct wbm_link_descriptor_ring) >> 2, 1520 .lmac_ring = FALSE, 1521 .ring_dir = HAL_SRNG_SRC_RING, 1522 .reg_start = { 1523 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1524 HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1525 }, 1526 /* Single ring - provide ring size if multiple rings of this 1527 * type are supported 1528 */ 1529 .reg_size = {}, 1530 .max_size = 1531 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_BMSK >> 1532 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_SHFT, 1533 }, 1534 { /* SW2WBM_RELEASE */ 1535 .start_ring_id = HAL_SRNG_WBM_SW_RELEASE, 1536 .max_rings = 1, 1537 .entry_size = sizeof(struct wbm_release_ring) >> 2, 1538 .lmac_ring = FALSE, 1539 .ring_dir = HAL_SRNG_SRC_RING, 1540 .reg_start = { 1541 HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1542 HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1543 }, 1544 /* Single ring - provide ring size if multiple rings of this 1545 * type are supported 1546 */ 1547 .reg_size = {}, 1548 .max_size = 1549 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> 1550 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, 1551 }, 1552 { /* WBM2SW_RELEASE */ 1553 .start_ring_id = HAL_SRNG_WBM2SW0_RELEASE, 1554 #ifdef IPA_WDI3_TX_TWO_PIPES 1555 .max_rings = 5, 1556 #else 1557 .max_rings = 4, 1558 #endif 1559 .entry_size = sizeof(struct wbm_release_ring) >> 2, 1560 .lmac_ring = FALSE, 1561 .ring_dir = HAL_SRNG_DST_RING, 1562 .reg_start = { 1563 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1564 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1565 }, 1566 .reg_size = { 1567 HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) - 1568 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1569 HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) - 1570 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1571 }, 1572 .max_size = 1573 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> 1574 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, 1575 }, 1576 { /* RXDMA_BUF */ 1577 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA0_BUF0, 1578 #ifdef IPA_OFFLOAD 1579 .max_rings = 3, 1580 #else 1581 .max_rings = 2, 1582 #endif 1583 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 1584 .lmac_ring = TRUE, 1585 .ring_dir = HAL_SRNG_SRC_RING, 1586 /* reg_start is not set because LMAC rings are not accessed 1587 * from host 1588 */ 1589 .reg_start = {}, 1590 .reg_size = {}, 1591 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1592 }, 1593 { /* RXDMA_DST */ 1594 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW0, 1595 .max_rings = 1, 1596 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 1597 .lmac_ring = TRUE, 1598 .ring_dir = HAL_SRNG_DST_RING, 1599 /* reg_start is not set because LMAC rings are not accessed 1600 * from host 1601 */ 1602 .reg_start = {}, 1603 .reg_size = {}, 1604 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1605 }, 1606 { /* RXDMA_MONITOR_BUF */ 1607 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA2_BUF, 1608 .max_rings = 1, 1609 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 1610 .lmac_ring = TRUE, 1611 .ring_dir = HAL_SRNG_SRC_RING, 1612 /* reg_start is not set because LMAC rings are not accessed 1613 * from host 1614 */ 1615 .reg_start = {}, 1616 .reg_size = {}, 1617 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1618 }, 1619 { /* RXDMA_MONITOR_STATUS */ 1620 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_STATBUF, 1621 .max_rings = 1, 1622 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 1623 .lmac_ring = TRUE, 1624 .ring_dir = HAL_SRNG_SRC_RING, 1625 /* reg_start is not set because LMAC rings are not accessed 1626 * from host 1627 */ 1628 .reg_start = {}, 1629 .reg_size = {}, 1630 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1631 }, 1632 { /* RXDMA_MONITOR_DST */ 1633 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW1, 1634 .max_rings = 1, 1635 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 1636 .lmac_ring = TRUE, 1637 .ring_dir = HAL_SRNG_DST_RING, 1638 /* reg_start is not set because LMAC rings are not accessed 1639 * from host 1640 */ 1641 .reg_start = {}, 1642 .reg_size = {}, 1643 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1644 }, 1645 { /* RXDMA_MONITOR_DESC */ 1646 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_DESC, 1647 .max_rings = 1, 1648 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 1649 .lmac_ring = TRUE, 1650 .ring_dir = HAL_SRNG_SRC_RING, 1651 /* reg_start is not set because LMAC rings are not accessed 1652 * from host 1653 */ 1654 .reg_start = {}, 1655 .reg_size = {}, 1656 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1657 }, 1658 { /* DIR_BUF_RX_DMA_SRC */ 1659 .start_ring_id = HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING, 1660 /* 1661 * one ring is for spectral scan 1662 * the other one is for cfr 1663 */ 1664 .max_rings = 2, 1665 .entry_size = 2, 1666 .lmac_ring = TRUE, 1667 .ring_dir = HAL_SRNG_SRC_RING, 1668 /* reg_start is not set because LMAC rings are not accessed 1669 * from host 1670 */ 1671 .reg_start = {}, 1672 .reg_size = {}, 1673 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1674 }, 1675 #ifdef WLAN_FEATURE_CIF_CFR 1676 { /* WIFI_POS_SRC */ 1677 .start_ring_id = HAL_SRNG_WIFI_POS_SRC_DMA_RING, 1678 .max_rings = 1, 1679 .entry_size = sizeof(wmi_oem_dma_buf_release_entry) >> 2, 1680 .lmac_ring = TRUE, 1681 .ring_dir = HAL_SRNG_SRC_RING, 1682 /* reg_start is not set because LMAC rings are not accessed 1683 * from host 1684 */ 1685 .reg_start = {}, 1686 .reg_size = {}, 1687 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1688 }, 1689 #endif 1690 { /* REO2PPE */ 0}, 1691 { /* PPE2TCL */ 0}, 1692 { /* PPE_RELEASE */ 0}, 1693 { /* TX_MONITOR_BUF */ 0}, 1694 { /* TX_MONITOR_DST */ 0}, 1695 { /* SW2RXDMA_NEW */ 0}, 1696 }; 1697 1698 /** 1699 * hal_qca6390_attach() - Attach 6390 target specific hal_soc ops, 1700 * offset and srng table 1701 */ 1702 void hal_qca6390_attach(struct hal_soc *hal_soc) 1703 { 1704 hal_soc->hw_srng_table = hw_srng_table_6390; 1705 hal_srng_hw_reg_offset_init_generic(hal_soc); 1706 hal_hw_txrx_default_ops_attach_li(hal_soc); 1707 hal_hw_txrx_ops_attach_qca6390(hal_soc); 1708 } 1709