1 /* 2 * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved. 3 * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 #include "qdf_types.h" 20 #include "qdf_util.h" 21 #include "qdf_types.h" 22 #include "qdf_lock.h" 23 #include "qdf_mem.h" 24 #include "qdf_nbuf.h" 25 #include "hal_li_hw_headers.h" 26 #include "hal_internal.h" 27 #include "hal_api.h" 28 #include "target_type.h" 29 #include "wcss_version.h" 30 #include "qdf_module.h" 31 32 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_OFFSET \ 33 RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_OFFSET 34 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_MASK \ 35 RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_MASK 36 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_LSB \ 37 RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_LSB 38 #define UNIFIED_PHYRX_HT_SIG_0_HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS_OFFSET \ 39 PHYRX_HT_SIG_0_HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS_OFFSET 40 #define UNIFIED_PHYRX_L_SIG_B_0_L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS_OFFSET \ 41 PHYRX_L_SIG_B_0_L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS_OFFSET 42 #define UNIFIED_PHYRX_L_SIG_A_0_L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS_OFFSET \ 43 PHYRX_L_SIG_A_0_L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS_OFFSET 44 #define UNIFIED_PHYRX_VHT_SIG_A_0_VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS_OFFSET \ 45 PHYRX_VHT_SIG_A_0_VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS_OFFSET 46 #define UNIFIED_PHYRX_HE_SIG_A_SU_0_HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS_OFFSET \ 47 PHYRX_HE_SIG_A_SU_0_HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS_OFFSET 48 #define UNIFIED_PHYRX_HE_SIG_A_MU_DL_0_HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_OFFSET \ 49 PHYRX_HE_SIG_A_MU_DL_0_HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_OFFSET 50 #define UNIFIED_PHYRX_HE_SIG_B1_MU_0_HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_OFFSET \ 51 PHYRX_HE_SIG_B1_MU_0_HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_OFFSET 52 #define UNIFIED_PHYRX_HE_SIG_B2_MU_0_HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_OFFSET \ 53 PHYRX_HE_SIG_B2_MU_0_HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_OFFSET 54 #define UNIFIED_PHYRX_HE_SIG_B2_OFDMA_0_HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_OFFSET \ 55 PHYRX_HE_SIG_B2_OFDMA_0_HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_OFFSET 56 #define UNIFIED_PHYRX_RSSI_LEGACY_3_RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS_OFFSET \ 57 PHYRX_RSSI_LEGACY_3_RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS_OFFSET 58 #define UNIFIED_PHYRX_RSSI_LEGACY_19_RECEIVE_RSSI_INFO_PREAMBLE_RSSI_INFO_DETAILS_OFFSET \ 59 PHYRX_RSSI_LEGACY_19_RECEIVE_RSSI_INFO_PREAMBLE_RSSI_INFO_DETAILS_OFFSET 60 #define UNIFIED_RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET \ 61 RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET 62 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 63 RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET 64 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ 65 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET 66 #define UNIFIED_RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 67 RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET 68 #define UNIFIED_REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 69 REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET 70 #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC \ 71 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER 72 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ 73 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET 74 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 75 RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET 76 #define UNIFIED_TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 77 TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET 78 #define UNIFIED_TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 79 TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET 80 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET \ 81 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET 82 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB \ 83 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB 84 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK \ 85 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK 86 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB \ 87 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB 88 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK \ 89 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK 90 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB \ 91 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB 92 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK \ 93 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK 94 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB \ 95 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB 96 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK \ 97 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK 98 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB \ 99 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB 100 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK \ 101 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK 102 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_MASK \ 103 WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_MASK 104 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_OFFSET \ 105 WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_OFFSET 106 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_LSB \ 107 WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_LSB 108 109 #include "hal_6390_tx.h" 110 #include "hal_6390_rx.h" 111 #include <hal_generic_api.h> 112 #include "hal_li_rx.h" 113 #include "hal_li_api.h" 114 #include "hal_li_generic_api.h" 115 116 /** 117 * hal_rx_get_rx_fragment_number_6390(): Function to retrieve rx fragment number 118 * 119 * @nbuf: Network buffer 120 * Returns: rx fragment number 121 */ 122 static 123 uint8_t hal_rx_get_rx_fragment_number_6390(uint8_t *buf) 124 { 125 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 126 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 127 128 /* Return first 4 bits as fragment number */ 129 return (HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info) & 130 DOT11_SEQ_FRAG_MASK); 131 } 132 133 /** 134 * hal_rx_msdu_end_da_is_mcbc_get_6390(): API to check if pkt is MCBC 135 * from rx_msdu_end TLV 136 * 137 * @ buf: pointer to the start of RX PKT TLV headers 138 * Return: da_is_mcbc 139 */ 140 static uint8_t 141 hal_rx_msdu_end_da_is_mcbc_get_6390(uint8_t *buf) 142 { 143 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 144 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 145 146 return HAL_RX_MSDU_END_DA_IS_MCBC_GET(msdu_end); 147 } 148 149 /** 150 * hal_rx_msdu_end_sa_is_valid_get_6390(): API to get_6390 the 151 * sa_is_valid bit from rx_msdu_end TLV 152 * 153 * @ buf: pointer to the start of RX PKT TLV headers 154 * Return: sa_is_valid bit 155 */ 156 static uint8_t 157 hal_rx_msdu_end_sa_is_valid_get_6390(uint8_t *buf) 158 { 159 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 160 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 161 uint8_t sa_is_valid; 162 163 sa_is_valid = HAL_RX_MSDU_END_SA_IS_VALID_GET(msdu_end); 164 165 return sa_is_valid; 166 } 167 168 /** 169 * hal_rx_msdu_end_sa_idx_get_6390(): API to get_6390 the 170 * sa_idx from rx_msdu_end TLV 171 * 172 * @ buf: pointer to the start of RX PKT TLV headers 173 * Return: sa_idx (SA AST index) 174 */ 175 static 176 uint16_t hal_rx_msdu_end_sa_idx_get_6390(uint8_t *buf) 177 { 178 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 179 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 180 uint16_t sa_idx; 181 182 sa_idx = HAL_RX_MSDU_END_SA_IDX_GET(msdu_end); 183 184 return sa_idx; 185 } 186 187 /** 188 * hal_rx_desc_is_first_msdu_6390() - Check if first msdu 189 * 190 * @hal_soc_hdl: hal_soc handle 191 * @hw_desc_addr: hardware descriptor address 192 * 193 * Return: 0 - success/ non-zero failure 194 */ 195 static uint32_t hal_rx_desc_is_first_msdu_6390(void *hw_desc_addr) 196 { 197 struct rx_pkt_tlvs *rx_tlvs = (struct rx_pkt_tlvs *)hw_desc_addr; 198 struct rx_msdu_end *msdu_end = &rx_tlvs->msdu_end_tlv.rx_msdu_end; 199 200 return HAL_RX_GET(msdu_end, RX_MSDU_END_5, FIRST_MSDU); 201 } 202 203 /** 204 * hal_rx_msdu_end_l3_hdr_padding_get_6390(): API to get_6390 the 205 * l3_header padding from rx_msdu_end TLV 206 * 207 * @ buf: pointer to the start of RX PKT TLV headers 208 * Return: number of l3 header padding bytes 209 */ 210 static uint32_t hal_rx_msdu_end_l3_hdr_padding_get_6390(uint8_t *buf) 211 { 212 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 213 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 214 uint32_t l3_header_padding; 215 216 l3_header_padding = HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(msdu_end); 217 218 return l3_header_padding; 219 } 220 221 /* 222 * @ hal_rx_encryption_info_valid_6390: Returns encryption type. 223 * 224 * @ buf: rx_tlv_hdr of the received packet 225 * @ Return: encryption type 226 */ 227 static uint32_t hal_rx_encryption_info_valid_6390(uint8_t *buf) 228 { 229 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 230 struct rx_mpdu_start *mpdu_start = 231 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 232 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 233 uint32_t encryption_info = HAL_RX_MPDU_ENCRYPTION_INFO_VALID(mpdu_info); 234 235 return encryption_info; 236 } 237 238 /* 239 * @ hal_rx_print_pn_6390: Prints the PN of rx packet. 240 * 241 * @ buf: rx_tlv_hdr of the received packet 242 * @ Return: void 243 */ 244 static void hal_rx_print_pn_6390(uint8_t *buf) 245 { 246 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 247 struct rx_mpdu_start *mpdu_start = 248 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 249 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 250 251 uint32_t pn_31_0 = HAL_RX_MPDU_PN_31_0_GET(mpdu_info); 252 uint32_t pn_63_32 = HAL_RX_MPDU_PN_63_32_GET(mpdu_info); 253 uint32_t pn_95_64 = HAL_RX_MPDU_PN_95_64_GET(mpdu_info); 254 uint32_t pn_127_96 = HAL_RX_MPDU_PN_127_96_GET(mpdu_info); 255 256 hal_debug("PN number pn_127_96 0x%x pn_95_64 0x%x pn_63_32 0x%x pn_31_0 0x%x ", 257 pn_127_96, pn_95_64, pn_63_32, pn_31_0); 258 } 259 260 /** 261 * hal_rx_msdu_end_first_msduget_6390: API to get first msdu status 262 * from rx_msdu_end TLV 263 * 264 * @ buf: pointer to the start of RX PKT TLV headers 265 * Return: first_msdu 266 */ 267 static uint8_t hal_rx_msdu_end_first_msdu_get_6390(uint8_t *buf) 268 { 269 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 270 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 271 uint8_t first_msdu; 272 273 first_msdu = HAL_RX_MSDU_END_FIRST_MSDU_GET(msdu_end); 274 275 return first_msdu; 276 } 277 278 /** 279 * hal_rx_msdu_end_da_is_valid_get_6390: API to check if da is valid 280 * from rx_msdu_end TLV 281 * 282 * @ buf: pointer to the start of RX PKT TLV headers 283 * Return: da_is_valid 284 */ 285 static uint8_t hal_rx_msdu_end_da_is_valid_get_6390(uint8_t *buf) 286 { 287 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 288 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 289 uint8_t da_is_valid; 290 291 da_is_valid = HAL_RX_MSDU_END_DA_IS_VALID_GET(msdu_end); 292 293 return da_is_valid; 294 } 295 296 /** 297 * hal_rx_msdu_end_last_msdu_get_6390: API to get last msdu status 298 * from rx_msdu_end TLV 299 * 300 * @ buf: pointer to the start of RX PKT TLV headers 301 * Return: last_msdu 302 */ 303 static uint8_t hal_rx_msdu_end_last_msdu_get_6390(uint8_t *buf) 304 { 305 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 306 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 307 uint8_t last_msdu; 308 309 last_msdu = HAL_RX_MSDU_END_LAST_MSDU_GET(msdu_end); 310 311 return last_msdu; 312 } 313 314 /* 315 * hal_rx_get_mpdu_mac_ad4_valid_6390(): Retrieves if mpdu 4th addr is valid 316 * 317 * @nbuf: Network buffer 318 * Returns: value of mpdu 4th address valid field 319 */ 320 static bool hal_rx_get_mpdu_mac_ad4_valid_6390(uint8_t *buf) 321 { 322 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 323 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 324 bool ad4_valid = 0; 325 326 ad4_valid = HAL_RX_MPDU_GET_MAC_AD4_VALID(rx_mpdu_info); 327 328 return ad4_valid; 329 } 330 331 /** 332 * hal_rx_mpdu_start_sw_peer_id_get_6390: Retrieve sw peer_id 333 * @buf: network buffer 334 * 335 * Return: sw peer_id 336 */ 337 static uint32_t hal_rx_mpdu_start_sw_peer_id_get_6390(uint8_t *buf) 338 { 339 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 340 struct rx_mpdu_start *mpdu_start = 341 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 342 343 return HAL_RX_MPDU_INFO_SW_PEER_ID_GET( 344 &mpdu_start->rx_mpdu_info_details); 345 } 346 347 /* 348 * hal_rx_mpdu_get_to_ds_6390(): API to get the tods info 349 * from rx_mpdu_start 350 * 351 * @buf: pointer to the start of RX PKT TLV header 352 * Return: uint32_t(to_ds) 353 */ 354 static uint32_t hal_rx_mpdu_get_to_ds_6390(uint8_t *buf) 355 { 356 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 357 struct rx_mpdu_start *mpdu_start = 358 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 359 360 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 361 362 return HAL_RX_MPDU_GET_TODS(mpdu_info); 363 } 364 365 /* 366 * hal_rx_mpdu_get_fr_ds_6390(): API to get the from ds info 367 * from rx_mpdu_start 368 * 369 * @buf: pointer to the start of RX PKT TLV header 370 * Return: uint32_t(fr_ds) 371 */ 372 static uint32_t hal_rx_mpdu_get_fr_ds_6390(uint8_t *buf) 373 { 374 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 375 struct rx_mpdu_start *mpdu_start = 376 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 377 378 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 379 380 return HAL_RX_MPDU_GET_FROMDS(mpdu_info); 381 } 382 383 /* 384 * hal_rx_get_mpdu_frame_control_valid_6390(): Retrieves mpdu 385 * frame control valid 386 * 387 * @nbuf: Network buffer 388 * Returns: value of frame control valid field 389 */ 390 static uint8_t hal_rx_get_mpdu_frame_control_valid_6390(uint8_t *buf) 391 { 392 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 393 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 394 395 return HAL_RX_MPDU_GET_FRAME_CONTROL_VALID(rx_mpdu_info); 396 } 397 398 /* 399 * hal_rx_mpdu_get_addr1_6390(): API to check get address1 of the mpdu 400 * 401 * @buf: pointer to the start of RX PKT TLV headera 402 * @mac_addr: pointer to mac address 403 * Return: success/failure 404 */ 405 static QDF_STATUS hal_rx_mpdu_get_addr1_6390(uint8_t *buf, uint8_t *mac_addr) 406 { 407 struct __attribute__((__packed__)) hal_addr1 { 408 uint32_t ad1_31_0; 409 uint16_t ad1_47_32; 410 }; 411 412 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 413 struct rx_mpdu_start *mpdu_start = 414 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 415 416 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 417 struct hal_addr1 *addr = (struct hal_addr1 *)mac_addr; 418 uint32_t mac_addr_ad1_valid; 419 420 mac_addr_ad1_valid = HAL_RX_MPDU_MAC_ADDR_AD1_VALID_GET(mpdu_info); 421 422 if (mac_addr_ad1_valid) { 423 addr->ad1_31_0 = HAL_RX_MPDU_AD1_31_0_GET(mpdu_info); 424 addr->ad1_47_32 = HAL_RX_MPDU_AD1_47_32_GET(mpdu_info); 425 return QDF_STATUS_SUCCESS; 426 } 427 428 return QDF_STATUS_E_FAILURE; 429 } 430 431 /* 432 * hal_rx_mpdu_get_addr2_6390(): API to check get address2 of the mpdu 433 * in the packet 434 * 435 * @buf: pointer to the start of RX PKT TLV header 436 * @mac_addr: pointer to mac address 437 * Return: success/failure 438 */ 439 static QDF_STATUS hal_rx_mpdu_get_addr2_6390(uint8_t *buf, 440 uint8_t *mac_addr) 441 { 442 struct __attribute__((__packed__)) hal_addr2 { 443 uint16_t ad2_15_0; 444 uint32_t ad2_47_16; 445 }; 446 447 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 448 struct rx_mpdu_start *mpdu_start = 449 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 450 451 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 452 struct hal_addr2 *addr = (struct hal_addr2 *)mac_addr; 453 uint32_t mac_addr_ad2_valid; 454 455 mac_addr_ad2_valid = HAL_RX_MPDU_MAC_ADDR_AD2_VALID_GET(mpdu_info); 456 457 if (mac_addr_ad2_valid) { 458 addr->ad2_15_0 = HAL_RX_MPDU_AD2_15_0_GET(mpdu_info); 459 addr->ad2_47_16 = HAL_RX_MPDU_AD2_47_16_GET(mpdu_info); 460 return QDF_STATUS_SUCCESS; 461 } 462 463 return QDF_STATUS_E_FAILURE; 464 } 465 466 /* 467 * hal_rx_mpdu_get_addr3_6390(): API to get address3 of the mpdu 468 * in the packet 469 * 470 * @buf: pointer to the start of RX PKT TLV header 471 * @mac_addr: pointer to mac address 472 * Return: success/failure 473 */ 474 static QDF_STATUS hal_rx_mpdu_get_addr3_6390(uint8_t *buf, uint8_t *mac_addr) 475 { 476 struct __attribute__((__packed__)) hal_addr3 { 477 uint32_t ad3_31_0; 478 uint16_t ad3_47_32; 479 }; 480 481 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 482 struct rx_mpdu_start *mpdu_start = 483 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 484 485 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 486 struct hal_addr3 *addr = (struct hal_addr3 *)mac_addr; 487 uint32_t mac_addr_ad3_valid; 488 489 mac_addr_ad3_valid = HAL_RX_MPDU_MAC_ADDR_AD3_VALID_GET(mpdu_info); 490 491 if (mac_addr_ad3_valid) { 492 addr->ad3_31_0 = HAL_RX_MPDU_AD3_31_0_GET(mpdu_info); 493 addr->ad3_47_32 = HAL_RX_MPDU_AD3_47_32_GET(mpdu_info); 494 return QDF_STATUS_SUCCESS; 495 } 496 497 return QDF_STATUS_E_FAILURE; 498 } 499 500 /* 501 * hal_rx_mpdu_get_addr4_6390(): API to get address4 of the mpdu 502 * in the packet 503 * 504 * @buf: pointer to the start of RX PKT TLV header 505 * @mac_addr: pointer to mac address 506 * Return: success/failure 507 */ 508 static QDF_STATUS hal_rx_mpdu_get_addr4_6390(uint8_t *buf, uint8_t *mac_addr) 509 { 510 struct __attribute__((__packed__)) hal_addr4 { 511 uint32_t ad4_31_0; 512 uint16_t ad4_47_32; 513 }; 514 515 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 516 struct rx_mpdu_start *mpdu_start = 517 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 518 519 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 520 struct hal_addr4 *addr = (struct hal_addr4 *)mac_addr; 521 uint32_t mac_addr_ad4_valid; 522 523 mac_addr_ad4_valid = HAL_RX_MPDU_MAC_ADDR_AD4_VALID_GET(mpdu_info); 524 525 if (mac_addr_ad4_valid) { 526 addr->ad4_31_0 = HAL_RX_MPDU_AD4_31_0_GET(mpdu_info); 527 addr->ad4_47_32 = HAL_RX_MPDU_AD4_47_32_GET(mpdu_info); 528 return QDF_STATUS_SUCCESS; 529 } 530 531 return QDF_STATUS_E_FAILURE; 532 } 533 534 /* 535 * hal_rx_get_mpdu_sequence_control_valid_6390(): Get mpdu 536 * sequence control valid 537 * 538 * @nbuf: Network buffer 539 * Returns: value of sequence control valid field 540 */ 541 static uint8_t hal_rx_get_mpdu_sequence_control_valid_6390(uint8_t *buf) 542 { 543 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 544 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 545 546 return HAL_RX_MPDU_GET_SEQUENCE_CONTROL_VALID(rx_mpdu_info); 547 } 548 549 /** 550 * hal_rx_is_unicast_6390: check packet is unicast frame or not. 551 * 552 * @ buf: pointer to rx pkt TLV. 553 * 554 * Return: true on unicast. 555 */ 556 static bool hal_rx_is_unicast_6390(uint8_t *buf) 557 { 558 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 559 struct rx_mpdu_start *mpdu_start = 560 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 561 uint32_t grp_id; 562 uint8_t *rx_mpdu_info = (uint8_t *)&mpdu_start->rx_mpdu_info_details; 563 564 grp_id = (_HAL_MS((*_OFFSET_TO_WORD_PTR((rx_mpdu_info), 565 RX_MPDU_INFO_0_SW_FRAME_GROUP_ID_OFFSET)), 566 RX_MPDU_INFO_0_SW_FRAME_GROUP_ID_MASK, 567 RX_MPDU_INFO_0_SW_FRAME_GROUP_ID_LSB)); 568 569 return (HAL_MPDU_SW_FRAME_GROUP_UNICAST_DATA == grp_id) ? true : false; 570 } 571 572 /** 573 * hal_rx_tid_get_6390: get tid based on qos control valid. 574 * @hal_soc_hdl: hal soc handle 575 * @buf: pointer to rx pkt TLV. 576 * 577 * Return: tid 578 */ 579 static uint32_t hal_rx_tid_get_6390(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 580 { 581 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 582 struct rx_mpdu_start *mpdu_start = 583 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 584 uint8_t *rx_mpdu_info = (uint8_t *)&mpdu_start->rx_mpdu_info_details; 585 uint8_t qos_control_valid = 586 (_HAL_MS((*_OFFSET_TO_WORD_PTR((rx_mpdu_info), 587 RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_OFFSET)), 588 RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_MASK, 589 RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_LSB)); 590 591 if (qos_control_valid) 592 return hal_rx_mpdu_start_tid_get_6390(buf); 593 594 return HAL_RX_NON_QOS_TID; 595 } 596 597 /** 598 * hal_rx_hw_desc_get_ppduid_get_6390(): retrieve ppdu id 599 * @rx_tlv_hdr: start address of rx_pkt_tlvs 600 * @rxdma_dst_ring_desc: Rx HW descriptor 601 * 602 * Return: ppdu id 603 */ 604 static uint32_t hal_rx_hw_desc_get_ppduid_get_6390(void *rx_tlv_hdr, 605 void *rxdma_dst_ring_desc) 606 { 607 struct rx_mpdu_info *rx_mpdu_info; 608 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)rx_tlv_hdr; 609 610 rx_mpdu_info = 611 &rx_desc->mpdu_start_tlv.rx_mpdu_start.rx_mpdu_info_details; 612 613 return HAL_RX_GET(rx_mpdu_info, RX_MPDU_INFO_0, PHY_PPDU_ID); 614 } 615 616 /** 617 * hal_reo_status_get_header_6390 - Process reo desc info 618 * @ring_desc: REO status ring descriptor 619 * @b - tlv type info 620 * @h1 - Pointer to hal_reo_status_header where info to be stored 621 * 622 * Return - none. 623 * 624 */ 625 static void hal_reo_status_get_header_6390(hal_ring_desc_t ring_desc, int b, 626 void *h1) 627 { 628 uint32_t *d = (uint32_t *)ring_desc; 629 uint32_t val1 = 0; 630 struct hal_reo_status_header *h = 631 (struct hal_reo_status_header *)h1; 632 633 /* Offsets of descriptor fields defined in HW headers start 634 * from the field after TLV header 635 */ 636 d += HAL_GET_NUM_DWORDS(sizeof(struct tlv_32_hdr)); 637 638 switch (b) { 639 case HAL_REO_QUEUE_STATS_STATUS_TLV: 640 val1 = d[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_0, 641 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 642 break; 643 case HAL_REO_FLUSH_QUEUE_STATUS_TLV: 644 val1 = d[HAL_OFFSET_DW(REO_FLUSH_QUEUE_STATUS_0, 645 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 646 break; 647 case HAL_REO_FLUSH_CACHE_STATUS_TLV: 648 val1 = d[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_0, 649 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 650 break; 651 case HAL_REO_UNBLK_CACHE_STATUS_TLV: 652 val1 = d[HAL_OFFSET_DW(REO_UNBLOCK_CACHE_STATUS_0, 653 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 654 break; 655 case HAL_REO_TIMOUT_LIST_STATUS_TLV: 656 val1 = d[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_0, 657 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 658 break; 659 case HAL_REO_DESC_THRES_STATUS_TLV: 660 val1 = 661 d[HAL_OFFSET_DW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0, 662 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 663 break; 664 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: 665 val1 = d[HAL_OFFSET_DW(REO_UPDATE_RX_REO_QUEUE_STATUS_0, 666 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 667 break; 668 default: 669 qdf_nofl_err("ERROR: Unknown tlv\n"); 670 break; 671 } 672 h->cmd_num = 673 HAL_GET_FIELD( 674 UNIFORM_REO_STATUS_HEADER_0, REO_STATUS_NUMBER, 675 val1); 676 h->exec_time = 677 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_0, 678 CMD_EXECUTION_TIME, val1); 679 h->status = 680 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_0, 681 REO_CMD_EXECUTION_STATUS, val1); 682 switch (b) { 683 case HAL_REO_QUEUE_STATS_STATUS_TLV: 684 val1 = d[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_1, 685 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 686 break; 687 case HAL_REO_FLUSH_QUEUE_STATUS_TLV: 688 val1 = d[HAL_OFFSET_DW(REO_FLUSH_QUEUE_STATUS_1, 689 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 690 break; 691 case HAL_REO_FLUSH_CACHE_STATUS_TLV: 692 val1 = d[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_1, 693 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 694 break; 695 case HAL_REO_UNBLK_CACHE_STATUS_TLV: 696 val1 = d[HAL_OFFSET_DW(REO_UNBLOCK_CACHE_STATUS_1, 697 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 698 break; 699 case HAL_REO_TIMOUT_LIST_STATUS_TLV: 700 val1 = d[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_1, 701 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 702 break; 703 case HAL_REO_DESC_THRES_STATUS_TLV: 704 val1 = 705 d[HAL_OFFSET_DW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_1, 706 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 707 break; 708 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: 709 val1 = d[HAL_OFFSET_DW(REO_UPDATE_RX_REO_QUEUE_STATUS_1, 710 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 711 break; 712 default: 713 qdf_nofl_err("ERROR: Unknown tlv\n"); 714 break; 715 } 716 h->tstamp = 717 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_1, TIMESTAMP, val1); 718 } 719 720 /** 721 * hal_rx_mpdu_start_mpdu_qos_control_valid_get_6390(): 722 * Retrieve qos control valid bit from the tlv. 723 * @buf: pointer to rx pkt TLV. 724 * 725 * Return: qos control value. 726 */ 727 static inline uint32_t 728 hal_rx_mpdu_start_mpdu_qos_control_valid_get_6390(uint8_t *buf) 729 { 730 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 731 struct rx_mpdu_start *mpdu_start = 732 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 733 734 return HAL_RX_MPDU_INFO_QOS_CONTROL_VALID_GET( 735 &mpdu_start->rx_mpdu_info_details); 736 } 737 738 /** 739 * hal_rx_msdu_end_sa_sw_peer_id_get_6390(): API to get the 740 * sa_sw_peer_id from rx_msdu_end TLV 741 * @buf: pointer to the start of RX PKT TLV headers 742 * 743 * Return: sa_sw_peer_id index 744 */ 745 static inline uint32_t 746 hal_rx_msdu_end_sa_sw_peer_id_get_6390(uint8_t *buf) 747 { 748 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 749 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 750 751 return HAL_RX_MSDU_END_SA_SW_PEER_ID_GET(msdu_end); 752 } 753 754 /** 755 * hal_tx_desc_set_mesh_en_6390 - Set mesh_enable flag in Tx descriptor 756 * @desc: Handle to Tx Descriptor 757 * @en: For raw WiFi frames, this indicates transmission to a mesh STA, 758 * enabling the interpretation of the 'Mesh Control Present' bit 759 * (bit 8) of QoS Control (otherwise this bit is ignored), 760 * For native WiFi frames, this indicates that a 'Mesh Control' field 761 * is present between the header and the LLC. 762 * 763 * Return: void 764 */ 765 static inline 766 void hal_tx_desc_set_mesh_en_6390(void *desc, uint8_t en) 767 { 768 HAL_SET_FLD(desc, TCL_DATA_CMD_4, MESH_ENABLE) |= 769 HAL_TX_SM(TCL_DATA_CMD_4, MESH_ENABLE, en); 770 } 771 772 static 773 void *hal_rx_msdu0_buffer_addr_lsb_6390(void *link_desc_va) 774 { 775 return (void *)HAL_RX_MSDU0_BUFFER_ADDR_LSB(link_desc_va); 776 } 777 778 static 779 void *hal_rx_msdu_desc_info_ptr_get_6390(void *msdu0) 780 { 781 return (void *)HAL_RX_MSDU_DESC_INFO_PTR_GET(msdu0); 782 } 783 784 static 785 void *hal_ent_mpdu_desc_info_6390(void *ent_ring_desc) 786 { 787 return (void *)HAL_ENT_MPDU_DESC_INFO(ent_ring_desc); 788 } 789 790 static 791 void *hal_dst_mpdu_desc_info_6390(void *dst_ring_desc) 792 { 793 return (void *)HAL_DST_MPDU_DESC_INFO(dst_ring_desc); 794 } 795 796 static 797 uint8_t hal_rx_get_fc_valid_6390(uint8_t *buf) 798 { 799 return HAL_RX_GET_FC_VALID(buf); 800 } 801 802 static uint8_t hal_rx_get_to_ds_flag_6390(uint8_t *buf) 803 { 804 return HAL_RX_GET_TO_DS_FLAG(buf); 805 } 806 807 static uint8_t hal_rx_get_mac_addr2_valid_6390(uint8_t *buf) 808 { 809 return HAL_RX_GET_MAC_ADDR2_VALID(buf); 810 } 811 812 static uint8_t hal_rx_get_filter_category_6390(uint8_t *buf) 813 { 814 return HAL_RX_GET_FILTER_CATEGORY(buf); 815 } 816 817 static uint32_t 818 hal_rx_get_ppdu_id_6390(uint8_t *buf) 819 { 820 return HAL_RX_GET_PPDU_ID(buf); 821 } 822 823 /** 824 * hal_reo_config_6390(): Set reo config parameters 825 * @soc: hal soc handle 826 * @reg_val: value to be set 827 * @reo_params: reo parameters 828 * 829 * Return: void 830 */ 831 static 832 void hal_reo_config_6390(struct hal_soc *soc, 833 uint32_t reg_val, 834 struct hal_reo_params *reo_params) 835 { 836 HAL_REO_R0_CONFIG(soc, reg_val, reo_params); 837 } 838 839 /** 840 * hal_rx_msdu_desc_info_get_ptr_6390() - Get msdu desc info ptr 841 * @msdu_details_ptr - Pointer to msdu_details_ptr 842 * Return - Pointer to rx_msdu_desc_info structure. 843 * 844 */ 845 static void *hal_rx_msdu_desc_info_get_ptr_6390(void *msdu_details_ptr) 846 { 847 return HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr); 848 } 849 850 /** 851 * hal_rx_link_desc_msdu0_ptr_6390 - Get pointer to rx_msdu details 852 * @link_desc - Pointer to link desc 853 * Return - Pointer to rx_msdu_details structure 854 * 855 */ 856 static void *hal_rx_link_desc_msdu0_ptr_6390(void *link_desc) 857 { 858 return HAL_RX_LINK_DESC_MSDU0_PTR(link_desc); 859 } 860 861 /** 862 * hal_rx_msdu_flow_idx_get_6390: API to get flow index 863 * from rx_msdu_end TLV 864 * @buf: pointer to the start of RX PKT TLV headers 865 * 866 * Return: flow index value from MSDU END TLV 867 */ 868 static inline uint32_t hal_rx_msdu_flow_idx_get_6390(uint8_t *buf) 869 { 870 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 871 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 872 873 return HAL_RX_MSDU_END_FLOW_IDX_GET(msdu_end); 874 } 875 876 /** 877 * hal_rx_msdu_flow_idx_invalid_6390: API to get flow index invalid 878 * from rx_msdu_end TLV 879 * @buf: pointer to the start of RX PKT TLV headers 880 * 881 * Return: flow index invalid value from MSDU END TLV 882 */ 883 static bool hal_rx_msdu_flow_idx_invalid_6390(uint8_t *buf) 884 { 885 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 886 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 887 888 return HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(msdu_end); 889 } 890 891 /** 892 * hal_rx_msdu_flow_idx_timeout_6390: API to get flow index timeout 893 * from rx_msdu_end TLV 894 * @buf: pointer to the start of RX PKT TLV headers 895 * 896 * Return: flow index timeout value from MSDU END TLV 897 */ 898 static bool hal_rx_msdu_flow_idx_timeout_6390(uint8_t *buf) 899 { 900 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 901 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 902 903 return HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(msdu_end); 904 } 905 906 /** 907 * hal_rx_msdu_fse_metadata_get_6390: API to get FSE metadata 908 * from rx_msdu_end TLV 909 * @buf: pointer to the start of RX PKT TLV headers 910 * 911 * Return: fse metadata value from MSDU END TLV 912 */ 913 static uint32_t hal_rx_msdu_fse_metadata_get_6390(uint8_t *buf) 914 { 915 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 916 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 917 918 return HAL_RX_MSDU_END_FSE_METADATA_GET(msdu_end); 919 } 920 921 /** 922 * hal_rx_msdu_cce_metadata_get_6390: API to get CCE metadata 923 * from rx_msdu_end TLV 924 * @buf: pointer to the start of RX PKT TLV headers 925 * 926 * Return: cce metadata 927 */ 928 static uint16_t 929 hal_rx_msdu_cce_metadata_get_6390(uint8_t *buf) 930 { 931 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 932 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 933 934 return HAL_RX_MSDU_END_CCE_METADATA_GET(msdu_end); 935 } 936 937 /** 938 * hal_rx_msdu_get_flow_params_6390: API to get flow index, flow index invalid 939 * and flow index timeout from rx_msdu_end TLV 940 * @buf: pointer to the start of RX PKT TLV headers 941 * @flow_invalid: pointer to return value of flow_idx_valid 942 * @flow_timeout: pointer to return value of flow_idx_timeout 943 * @flow_index: pointer to return value of flow_idx 944 * 945 * Return: none 946 */ 947 static inline void 948 hal_rx_msdu_get_flow_params_6390(uint8_t *buf, 949 bool *flow_invalid, 950 bool *flow_timeout, 951 uint32_t *flow_index) 952 { 953 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 954 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 955 956 *flow_invalid = HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(msdu_end); 957 *flow_timeout = HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(msdu_end); 958 *flow_index = HAL_RX_MSDU_END_FLOW_IDX_GET(msdu_end); 959 } 960 961 /** 962 * hal_rx_tlv_get_tcp_chksum_6390() - API to get tcp checksum 963 * @buf: rx_tlv_hdr 964 * 965 * Return: tcp checksum 966 */ 967 static uint16_t 968 hal_rx_tlv_get_tcp_chksum_6390(uint8_t *buf) 969 { 970 return HAL_RX_TLV_GET_TCP_CHKSUM(buf); 971 } 972 973 /** 974 * hal_rx_get_rx_sequence_6390(): Function to retrieve rx sequence number 975 * 976 * @nbuf: Network buffer 977 * Returns: rx sequence number 978 */ 979 static 980 uint16_t hal_rx_get_rx_sequence_6390(uint8_t *buf) 981 { 982 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 983 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 984 985 return HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info); 986 } 987 988 /** 989 * hal_rx_mpdu_start_tlv_tag_valid_6390 () - API to check if RX_MPDU_START 990 * tlv tag is valid 991 * 992 *@rx_tlv_hdr: start address of rx_pkt_tlvs 993 * 994 * Return: true if RX_MPDU_START is valied, else false. 995 */ 996 static uint8_t hal_rx_mpdu_start_tlv_tag_valid_6390(void *rx_tlv_hdr) 997 { 998 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)rx_tlv_hdr; 999 uint32_t tlv_tag; 1000 1001 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(&rx_desc->mpdu_start_tlv); 1002 1003 return tlv_tag == WIFIRX_MPDU_START_E ? true : false; 1004 } 1005 1006 /** 1007 * hal_get_window_address_6390(): Function to get hp/tp address 1008 * @hal_soc: Pointer to hal_soc 1009 * @addr: address offset of register 1010 * 1011 * Return: modified address offset of register 1012 */ 1013 static inline qdf_iomem_t hal_get_window_address_6390(struct hal_soc *hal_soc, 1014 qdf_iomem_t addr) 1015 { 1016 return addr; 1017 } 1018 1019 /** 1020 * hal_reo_set_err_dst_remap_6390(): Function to set REO error destination 1021 * ring remap register 1022 * @hal_soc: Pointer to hal_soc 1023 * 1024 * Return: none. 1025 */ 1026 static void 1027 hal_reo_set_err_dst_remap_6390(void *hal_soc) 1028 { 1029 /* 1030 * Set REO error 2k jump (error code 5) / OOR (error code 7) 1031 * frame routed to REO2TCL ring. 1032 */ 1033 uint32_t dst_remap_ix0 = 1034 HAL_REO_ERR_REMAP_IX0(REO_REMAP_RELEASE, 0) | 1035 HAL_REO_ERR_REMAP_IX0(REO_REMAP_RELEASE, 1) | 1036 HAL_REO_ERR_REMAP_IX0(REO_REMAP_RELEASE, 2) | 1037 HAL_REO_ERR_REMAP_IX0(REO_REMAP_RELEASE, 3) | 1038 HAL_REO_ERR_REMAP_IX0(REO_REMAP_RELEASE, 4) | 1039 HAL_REO_ERR_REMAP_IX0(REO_REMAP_TCL, 5) | 1040 HAL_REO_ERR_REMAP_IX0(REO_REMAP_TCL, 6) | 1041 HAL_REO_ERR_REMAP_IX0(REO_REMAP_TCL, 7) | 1042 HAL_REO_ERR_REMAP_IX0(REO_REMAP_TCL, 8) | 1043 HAL_REO_ERR_REMAP_IX0(REO_REMAP_RELEASE, 9); 1044 1045 HAL_REG_WRITE(hal_soc, 1046 HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ADDR( 1047 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1048 dst_remap_ix0); 1049 1050 hal_info("HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0 0x%x", 1051 HAL_REG_READ( 1052 hal_soc, 1053 HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ADDR( 1054 SEQ_WCSS_UMAC_REO_REG_OFFSET))); 1055 } 1056 1057 static 1058 void hal_compute_reo_remap_ix2_ix3_6390(uint32_t *ring, uint32_t num_rings, 1059 uint32_t *remap1, uint32_t *remap2) 1060 { 1061 switch (num_rings) { 1062 case 3: 1063 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 1064 HAL_REO_REMAP_IX2(ring[1], 17) | 1065 HAL_REO_REMAP_IX2(ring[2], 18) | 1066 HAL_REO_REMAP_IX2(ring[0], 19) | 1067 HAL_REO_REMAP_IX2(ring[1], 20) | 1068 HAL_REO_REMAP_IX2(ring[2], 21) | 1069 HAL_REO_REMAP_IX2(ring[0], 22) | 1070 HAL_REO_REMAP_IX2(ring[1], 23); 1071 1072 *remap2 = HAL_REO_REMAP_IX3(ring[2], 24) | 1073 HAL_REO_REMAP_IX3(ring[0], 25) | 1074 HAL_REO_REMAP_IX3(ring[1], 26) | 1075 HAL_REO_REMAP_IX3(ring[2], 27) | 1076 HAL_REO_REMAP_IX3(ring[0], 28) | 1077 HAL_REO_REMAP_IX3(ring[1], 29) | 1078 HAL_REO_REMAP_IX3(ring[2], 30) | 1079 HAL_REO_REMAP_IX3(ring[0], 31); 1080 break; 1081 case 4: 1082 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 1083 HAL_REO_REMAP_IX2(ring[1], 17) | 1084 HAL_REO_REMAP_IX2(ring[2], 18) | 1085 HAL_REO_REMAP_IX2(ring[3], 19) | 1086 HAL_REO_REMAP_IX2(ring[0], 20) | 1087 HAL_REO_REMAP_IX2(ring[1], 21) | 1088 HAL_REO_REMAP_IX2(ring[2], 22) | 1089 HAL_REO_REMAP_IX2(ring[3], 23); 1090 1091 *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) | 1092 HAL_REO_REMAP_IX3(ring[1], 25) | 1093 HAL_REO_REMAP_IX3(ring[2], 26) | 1094 HAL_REO_REMAP_IX3(ring[3], 27) | 1095 HAL_REO_REMAP_IX3(ring[0], 28) | 1096 HAL_REO_REMAP_IX3(ring[1], 29) | 1097 HAL_REO_REMAP_IX3(ring[2], 30) | 1098 HAL_REO_REMAP_IX3(ring[3], 31); 1099 break; 1100 } 1101 } 1102 1103 static 1104 void hal_compute_reo_remap_ix0_6390(uint32_t *remap0) 1105 { 1106 *remap0 = HAL_REO_REMAP_IX0(REO_REMAP_SW1, 0) | 1107 HAL_REO_REMAP_IX0(REO_REMAP_SW1, 1) | 1108 HAL_REO_REMAP_IX0(REO_REMAP_SW2, 2) | 1109 HAL_REO_REMAP_IX0(REO_REMAP_SW3, 3) | 1110 HAL_REO_REMAP_IX0(REO_REMAP_SW2, 4) | 1111 HAL_REO_REMAP_IX0(REO_REMAP_RELEASE, 5) | 1112 HAL_REO_REMAP_IX0(REO_REMAP_FW, 6) | 1113 HAL_REO_REMAP_IX0(REO_REMAP_FW, 7); 1114 } 1115 1116 #ifdef WLAN_FEATURE_MARK_FIRST_WAKEUP_PACKET 1117 /** 1118 * hal_get_first_wow_wakeup_packet_6390(): Function to get if the buffer 1119 * is the first one that wakes up host from WoW. 1120 * 1121 * @buf: network buffer 1122 * 1123 * Dummy function for QCA6390 1124 * 1125 * Returns: 1 to indicate it is first packet received that wakes up host from 1126 * WoW. Otherwise 0 1127 */ 1128 static inline uint8_t hal_get_first_wow_wakeup_packet_6390(uint8_t *buf) 1129 { 1130 return 0; 1131 } 1132 #endif 1133 1134 static void hal_hw_txrx_ops_attach_qca6390(struct hal_soc *hal_soc) 1135 { 1136 /* init and setup */ 1137 hal_soc->ops->hal_srng_dst_hw_init = hal_srng_dst_hw_init_generic; 1138 hal_soc->ops->hal_srng_src_hw_init = hal_srng_src_hw_init_generic; 1139 hal_soc->ops->hal_get_hw_hptp = hal_get_hw_hptp_generic; 1140 hal_soc->ops->hal_reo_setup = hal_reo_setup_generic_li; 1141 hal_soc->ops->hal_get_window_address = hal_get_window_address_6390; 1142 hal_soc->ops->hal_reo_set_err_dst_remap = 1143 hal_reo_set_err_dst_remap_6390; 1144 1145 /* tx */ 1146 hal_soc->ops->hal_tx_desc_set_dscp_tid_table_id = 1147 hal_tx_desc_set_dscp_tid_table_id_6390; 1148 hal_soc->ops->hal_tx_set_dscp_tid_map = hal_tx_set_dscp_tid_map_6390; 1149 hal_soc->ops->hal_tx_update_dscp_tid = hal_tx_update_dscp_tid_6390; 1150 hal_soc->ops->hal_tx_desc_set_lmac_id = hal_tx_desc_set_lmac_id_6390; 1151 hal_soc->ops->hal_tx_desc_set_buf_addr = 1152 hal_tx_desc_set_buf_addr_generic_li; 1153 hal_soc->ops->hal_tx_desc_set_search_type = 1154 hal_tx_desc_set_search_type_generic_li; 1155 hal_soc->ops->hal_tx_desc_set_search_index = 1156 hal_tx_desc_set_search_index_generic_li; 1157 hal_soc->ops->hal_tx_desc_set_cache_set_num = 1158 hal_tx_desc_set_cache_set_num_generic_li; 1159 hal_soc->ops->hal_tx_comp_get_status = 1160 hal_tx_comp_get_status_generic_li; 1161 hal_soc->ops->hal_tx_comp_get_release_reason = 1162 hal_tx_comp_get_release_reason_generic_li; 1163 hal_soc->ops->hal_get_wbm_internal_error = 1164 hal_get_wbm_internal_error_generic_li; 1165 hal_soc->ops->hal_tx_desc_set_mesh_en = hal_tx_desc_set_mesh_en_6390; 1166 hal_soc->ops->hal_tx_init_cmd_credit_ring = 1167 hal_tx_init_cmd_credit_ring_6390; 1168 1169 /* rx */ 1170 hal_soc->ops->hal_rx_msdu_start_nss_get = 1171 hal_rx_msdu_start_nss_get_6390; 1172 hal_soc->ops->hal_rx_mon_hw_desc_get_mpdu_status = 1173 hal_rx_mon_hw_desc_get_mpdu_status_6390; 1174 hal_soc->ops->hal_rx_get_tlv = hal_rx_get_tlv_6390; 1175 hal_soc->ops->hal_rx_proc_phyrx_other_receive_info_tlv = 1176 hal_rx_proc_phyrx_other_receive_info_tlv_6390; 1177 hal_soc->ops->hal_rx_dump_msdu_start_tlv = 1178 hal_rx_dump_msdu_start_tlv_6390; 1179 hal_soc->ops->hal_rx_dump_msdu_end_tlv = hal_rx_dump_msdu_end_tlv_6390; 1180 hal_soc->ops->hal_get_link_desc_size = hal_get_link_desc_size_6390; 1181 hal_soc->ops->hal_rx_mpdu_start_tid_get = 1182 hal_rx_mpdu_start_tid_get_6390; 1183 hal_soc->ops->hal_rx_msdu_start_reception_type_get = 1184 hal_rx_msdu_start_reception_type_get_6390; 1185 hal_soc->ops->hal_rx_msdu_end_da_idx_get = 1186 hal_rx_msdu_end_da_idx_get_6390; 1187 hal_soc->ops->hal_rx_msdu_desc_info_get_ptr = 1188 hal_rx_msdu_desc_info_get_ptr_6390; 1189 hal_soc->ops->hal_rx_link_desc_msdu0_ptr = 1190 hal_rx_link_desc_msdu0_ptr_6390; 1191 hal_soc->ops->hal_reo_status_get_header = 1192 hal_reo_status_get_header_6390; 1193 hal_soc->ops->hal_rx_status_get_tlv_info = 1194 hal_rx_status_get_tlv_info_generic_li; 1195 hal_soc->ops->hal_rx_wbm_err_info_get = 1196 hal_rx_wbm_err_info_get_generic_li; 1197 hal_soc->ops->hal_rx_dump_mpdu_start_tlv = 1198 hal_rx_dump_mpdu_start_tlv_generic_li; 1199 1200 hal_soc->ops->hal_tx_set_pcp_tid_map = 1201 hal_tx_set_pcp_tid_map_generic_li; 1202 hal_soc->ops->hal_tx_update_pcp_tid_map = 1203 hal_tx_update_pcp_tid_generic_li; 1204 hal_soc->ops->hal_tx_set_tidmap_prty = 1205 hal_tx_update_tidmap_prty_generic_li; 1206 hal_soc->ops->hal_rx_get_rx_fragment_number = 1207 hal_rx_get_rx_fragment_number_6390; 1208 hal_soc->ops->hal_rx_msdu_end_da_is_mcbc_get = 1209 hal_rx_msdu_end_da_is_mcbc_get_6390; 1210 hal_soc->ops->hal_rx_msdu_end_sa_is_valid_get = 1211 hal_rx_msdu_end_sa_is_valid_get_6390; 1212 hal_soc->ops->hal_rx_msdu_end_sa_idx_get = 1213 hal_rx_msdu_end_sa_idx_get_6390; 1214 hal_soc->ops->hal_rx_desc_is_first_msdu = 1215 hal_rx_desc_is_first_msdu_6390; 1216 hal_soc->ops->hal_rx_msdu_end_l3_hdr_padding_get = 1217 hal_rx_msdu_end_l3_hdr_padding_get_6390; 1218 hal_soc->ops->hal_rx_encryption_info_valid = 1219 hal_rx_encryption_info_valid_6390; 1220 hal_soc->ops->hal_rx_print_pn = hal_rx_print_pn_6390; 1221 hal_soc->ops->hal_rx_msdu_end_first_msdu_get = 1222 hal_rx_msdu_end_first_msdu_get_6390; 1223 hal_soc->ops->hal_rx_msdu_end_da_is_valid_get = 1224 hal_rx_msdu_end_da_is_valid_get_6390; 1225 hal_soc->ops->hal_rx_msdu_end_last_msdu_get = 1226 hal_rx_msdu_end_last_msdu_get_6390; 1227 hal_soc->ops->hal_rx_get_mpdu_mac_ad4_valid = 1228 hal_rx_get_mpdu_mac_ad4_valid_6390; 1229 hal_soc->ops->hal_rx_mpdu_start_sw_peer_id_get = 1230 hal_rx_mpdu_start_sw_peer_id_get_6390; 1231 hal_soc->ops->hal_rx_tlv_peer_meta_data_get = 1232 hal_rx_mpdu_peer_meta_data_get_li; 1233 hal_soc->ops->hal_rx_mpdu_get_to_ds = hal_rx_mpdu_get_to_ds_6390; 1234 hal_soc->ops->hal_rx_mpdu_get_fr_ds = hal_rx_mpdu_get_fr_ds_6390; 1235 hal_soc->ops->hal_rx_get_mpdu_frame_control_valid = 1236 hal_rx_get_mpdu_frame_control_valid_6390; 1237 hal_soc->ops->hal_rx_mpdu_get_addr1 = hal_rx_mpdu_get_addr1_6390; 1238 hal_soc->ops->hal_rx_mpdu_get_addr2 = hal_rx_mpdu_get_addr2_6390; 1239 hal_soc->ops->hal_rx_mpdu_get_addr3 = hal_rx_mpdu_get_addr3_6390; 1240 hal_soc->ops->hal_rx_mpdu_get_addr4 = hal_rx_mpdu_get_addr4_6390; 1241 hal_soc->ops->hal_rx_get_mpdu_sequence_control_valid = 1242 hal_rx_get_mpdu_sequence_control_valid_6390; 1243 hal_soc->ops->hal_rx_is_unicast = hal_rx_is_unicast_6390; 1244 hal_soc->ops->hal_rx_tid_get = hal_rx_tid_get_6390; 1245 hal_soc->ops->hal_rx_hw_desc_get_ppduid_get = 1246 hal_rx_hw_desc_get_ppduid_get_6390; 1247 hal_soc->ops->hal_rx_mpdu_start_mpdu_qos_control_valid_get = 1248 hal_rx_mpdu_start_mpdu_qos_control_valid_get_6390; 1249 hal_soc->ops->hal_rx_msdu_end_sa_sw_peer_id_get = 1250 hal_rx_msdu_end_sa_sw_peer_id_get_6390; 1251 hal_soc->ops->hal_rx_msdu0_buffer_addr_lsb = 1252 hal_rx_msdu0_buffer_addr_lsb_6390; 1253 hal_soc->ops->hal_rx_msdu_desc_info_ptr_get = 1254 hal_rx_msdu_desc_info_ptr_get_6390; 1255 hal_soc->ops->hal_ent_mpdu_desc_info = hal_ent_mpdu_desc_info_6390; 1256 hal_soc->ops->hal_dst_mpdu_desc_info = hal_dst_mpdu_desc_info_6390; 1257 hal_soc->ops->hal_rx_get_fc_valid = hal_rx_get_fc_valid_6390; 1258 hal_soc->ops->hal_rx_get_to_ds_flag = hal_rx_get_to_ds_flag_6390; 1259 hal_soc->ops->hal_rx_get_mac_addr2_valid = 1260 hal_rx_get_mac_addr2_valid_6390; 1261 hal_soc->ops->hal_rx_get_filter_category = 1262 hal_rx_get_filter_category_6390; 1263 hal_soc->ops->hal_rx_get_ppdu_id = hal_rx_get_ppdu_id_6390; 1264 hal_soc->ops->hal_reo_config = hal_reo_config_6390; 1265 hal_soc->ops->hal_rx_msdu_flow_idx_get = hal_rx_msdu_flow_idx_get_6390; 1266 hal_soc->ops->hal_rx_msdu_flow_idx_invalid = 1267 hal_rx_msdu_flow_idx_invalid_6390; 1268 hal_soc->ops->hal_rx_msdu_flow_idx_timeout = 1269 hal_rx_msdu_flow_idx_timeout_6390; 1270 hal_soc->ops->hal_rx_msdu_fse_metadata_get = 1271 hal_rx_msdu_fse_metadata_get_6390; 1272 hal_soc->ops->hal_rx_msdu_cce_match_get = 1273 hal_rx_msdu_cce_match_get_li; 1274 hal_soc->ops->hal_rx_msdu_cce_metadata_get = 1275 hal_rx_msdu_cce_metadata_get_6390; 1276 hal_soc->ops->hal_rx_msdu_get_flow_params = 1277 hal_rx_msdu_get_flow_params_6390; 1278 hal_soc->ops->hal_rx_tlv_get_tcp_chksum = 1279 hal_rx_tlv_get_tcp_chksum_6390; 1280 hal_soc->ops->hal_rx_get_rx_sequence = hal_rx_get_rx_sequence_6390; 1281 /* rx - msdu end fast path info fields */ 1282 hal_soc->ops->hal_rx_msdu_packet_metadata_get = 1283 hal_rx_msdu_packet_metadata_get_generic_li; 1284 hal_soc->ops->hal_rx_mpdu_start_tlv_tag_valid = 1285 hal_rx_mpdu_start_tlv_tag_valid_6390; 1286 1287 /* rx - TLV struct offsets */ 1288 hal_soc->ops->hal_rx_msdu_end_offset_get = 1289 hal_rx_msdu_end_offset_get_generic; 1290 hal_soc->ops->hal_rx_attn_offset_get = hal_rx_attn_offset_get_generic; 1291 hal_soc->ops->hal_rx_msdu_start_offset_get = 1292 hal_rx_msdu_start_offset_get_generic; 1293 hal_soc->ops->hal_rx_mpdu_start_offset_get = 1294 hal_rx_mpdu_start_offset_get_generic; 1295 hal_soc->ops->hal_rx_mpdu_end_offset_get = 1296 hal_rx_mpdu_end_offset_get_generic; 1297 #ifndef NO_RX_PKT_HDR_TLV 1298 hal_soc->ops->hal_rx_pkt_tlv_offset_get = 1299 hal_rx_pkt_tlv_offset_get_generic; 1300 #endif 1301 hal_soc->ops->hal_compute_reo_remap_ix2_ix3 = 1302 hal_compute_reo_remap_ix2_ix3_6390; 1303 hal_soc->ops->hal_setup_link_idle_list = 1304 hal_setup_link_idle_list_generic_li; 1305 #ifdef WLAN_FEATURE_MARK_FIRST_WAKEUP_PACKET 1306 hal_soc->ops->hal_get_first_wow_wakeup_packet = 1307 hal_get_first_wow_wakeup_packet_6390; 1308 #endif 1309 hal_soc->ops->hal_compute_reo_remap_ix0 = 1310 hal_compute_reo_remap_ix0_6390; 1311 }; 1312 1313 struct hal_hw_srng_config hw_srng_table_6390[] = { 1314 /* TODO: max_rings can populated by querying HW capabilities */ 1315 { /* REO_DST */ 1316 .start_ring_id = HAL_SRNG_REO2SW1, 1317 .max_rings = 4, 1318 .entry_size = sizeof(struct reo_destination_ring) >> 2, 1319 .lmac_ring = FALSE, 1320 .ring_dir = HAL_SRNG_DST_RING, 1321 .reg_start = { 1322 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR( 1323 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1324 HWIO_REO_R2_REO2SW1_RING_HP_ADDR( 1325 SEQ_WCSS_UMAC_REO_REG_OFFSET) 1326 }, 1327 .reg_size = { 1328 HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(0) - 1329 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(0), 1330 HWIO_REO_R2_REO2SW2_RING_HP_ADDR(0) - 1331 HWIO_REO_R2_REO2SW1_RING_HP_ADDR(0), 1332 }, 1333 .max_size = 1334 HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_BMSK >> 1335 HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_SHFT, 1336 }, 1337 { /* REO_EXCEPTION */ 1338 /* Designating REO2TCL ring as exception ring. This ring is 1339 * similar to other REO2SW rings though it is named as REO2TCL. 1340 * Any of theREO2SW rings can be used as exception ring. 1341 */ 1342 .start_ring_id = HAL_SRNG_REO2TCL, 1343 .max_rings = 1, 1344 .entry_size = sizeof(struct reo_destination_ring) >> 2, 1345 .lmac_ring = FALSE, 1346 .ring_dir = HAL_SRNG_DST_RING, 1347 .reg_start = { 1348 HWIO_REO_R0_REO2TCL_RING_BASE_LSB_ADDR( 1349 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1350 HWIO_REO_R2_REO2TCL_RING_HP_ADDR( 1351 SEQ_WCSS_UMAC_REO_REG_OFFSET) 1352 }, 1353 /* Single ring - provide ring size if multiple rings of this 1354 * type are supported 1355 */ 1356 .reg_size = {}, 1357 .max_size = 1358 HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_BMSK >> 1359 HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_SHFT, 1360 }, 1361 { /* REO_REINJECT */ 1362 .start_ring_id = HAL_SRNG_SW2REO, 1363 .max_rings = 1, 1364 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 1365 .lmac_ring = FALSE, 1366 .ring_dir = HAL_SRNG_SRC_RING, 1367 .reg_start = { 1368 HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR( 1369 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1370 HWIO_REO_R2_SW2REO_RING_HP_ADDR( 1371 SEQ_WCSS_UMAC_REO_REG_OFFSET) 1372 }, 1373 /* Single ring - provide ring size if multiple rings of this 1374 * type are supported 1375 */ 1376 .reg_size = {}, 1377 .max_size = HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_BMSK >> 1378 HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_SHFT, 1379 }, 1380 { /* REO_CMD */ 1381 .start_ring_id = HAL_SRNG_REO_CMD, 1382 .max_rings = 1, 1383 .entry_size = (sizeof(struct tlv_32_hdr) + 1384 sizeof(struct reo_get_queue_stats)) >> 2, 1385 .lmac_ring = FALSE, 1386 .ring_dir = HAL_SRNG_SRC_RING, 1387 .reg_start = { 1388 HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR( 1389 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1390 HWIO_REO_R2_REO_CMD_RING_HP_ADDR( 1391 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1392 }, 1393 /* Single ring - provide ring size if multiple rings of this 1394 * type are supported 1395 */ 1396 .reg_size = {}, 1397 .max_size = 1398 HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_BMSK >> 1399 HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_SHFT, 1400 }, 1401 { /* REO_STATUS */ 1402 .start_ring_id = HAL_SRNG_REO_STATUS, 1403 .max_rings = 1, 1404 .entry_size = (sizeof(struct tlv_32_hdr) + 1405 sizeof(struct reo_get_queue_stats_status)) >> 2, 1406 .lmac_ring = FALSE, 1407 .ring_dir = HAL_SRNG_DST_RING, 1408 .reg_start = { 1409 HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR( 1410 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1411 HWIO_REO_R2_REO_STATUS_RING_HP_ADDR( 1412 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1413 }, 1414 /* Single ring - provide ring size if multiple rings of this 1415 * type are supported 1416 */ 1417 .reg_size = {}, 1418 .max_size = 1419 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> 1420 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, 1421 }, 1422 { /* TCL_DATA */ 1423 .start_ring_id = HAL_SRNG_SW2TCL1, 1424 .max_rings = 3, 1425 .entry_size = (sizeof(struct tlv_32_hdr) + 1426 sizeof(struct tcl_data_cmd)) >> 2, 1427 .lmac_ring = FALSE, 1428 .ring_dir = HAL_SRNG_SRC_RING, 1429 .reg_start = { 1430 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR( 1431 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1432 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR( 1433 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1434 }, 1435 .reg_size = { 1436 HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(0) - 1437 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(0), 1438 HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(0) - 1439 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(0), 1440 }, 1441 .max_size = 1442 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK >> 1443 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT, 1444 }, 1445 { /* TCL_CMD */ 1446 .start_ring_id = HAL_SRNG_SW2TCL_CMD, 1447 .max_rings = 1, 1448 .entry_size = (sizeof(struct tlv_32_hdr) + 1449 sizeof(struct tcl_gse_cmd)) >> 2, 1450 .lmac_ring = FALSE, 1451 .ring_dir = HAL_SRNG_SRC_RING, 1452 .reg_start = { 1453 HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_ADDR( 1454 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1455 HWIO_TCL_R2_SW2TCL_CMD_RING_HP_ADDR( 1456 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1457 }, 1458 /* Single ring - provide ring size if multiple rings of this 1459 * type are supported 1460 */ 1461 .reg_size = {}, 1462 .max_size = 1463 HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RING_SIZE_BMSK >> 1464 HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RING_SIZE_SHFT, 1465 }, 1466 { /* TCL_STATUS */ 1467 .start_ring_id = HAL_SRNG_TCL_STATUS, 1468 .max_rings = 1, 1469 .entry_size = (sizeof(struct tlv_32_hdr) + 1470 sizeof(struct tcl_status_ring)) >> 2, 1471 .lmac_ring = FALSE, 1472 .ring_dir = HAL_SRNG_DST_RING, 1473 .reg_start = { 1474 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR( 1475 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1476 HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR( 1477 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1478 }, 1479 /* Single ring - provide ring size if multiple rings of this 1480 * type are supported 1481 */ 1482 .reg_size = {}, 1483 .max_size = 1484 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_BMSK >> 1485 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_SHFT, 1486 }, 1487 { /* CE_SRC */ 1488 .start_ring_id = HAL_SRNG_CE_0_SRC, 1489 .max_rings = 12, 1490 .entry_size = sizeof(struct ce_src_desc) >> 2, 1491 .lmac_ring = FALSE, 1492 .ring_dir = HAL_SRNG_SRC_RING, 1493 .reg_start = { 1494 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR( 1495 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET), 1496 HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR( 1497 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET), 1498 }, 1499 .reg_size = { 1500 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET - 1501 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET, 1502 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET - 1503 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET, 1504 }, 1505 .max_size = 1506 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >> 1507 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT, 1508 }, 1509 { /* CE_DST */ 1510 .start_ring_id = HAL_SRNG_CE_0_DST, 1511 .max_rings = 12, 1512 .entry_size = 8 >> 2, 1513 /*TODO: entry_size above should actually be 1514 * sizeof(struct ce_dst_desc) >> 2, but couldn't find definition 1515 * of struct ce_dst_desc in HW header files 1516 */ 1517 .lmac_ring = FALSE, 1518 .ring_dir = HAL_SRNG_SRC_RING, 1519 .reg_start = { 1520 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR( 1521 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 1522 HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR( 1523 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 1524 }, 1525 .reg_size = { 1526 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 1527 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 1528 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 1529 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 1530 }, 1531 .max_size = 1532 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >> 1533 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT, 1534 }, 1535 { /* CE_DST_STATUS */ 1536 .start_ring_id = HAL_SRNG_CE_0_DST_STATUS, 1537 .max_rings = 12, 1538 .entry_size = sizeof(struct ce_stat_desc) >> 2, 1539 .lmac_ring = FALSE, 1540 .ring_dir = HAL_SRNG_DST_RING, 1541 .reg_start = { 1542 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR( 1543 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 1544 HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR( 1545 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 1546 }, 1547 /* TODO: check destination status ring registers */ 1548 .reg_size = { 1549 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 1550 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 1551 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 1552 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 1553 }, 1554 .max_size = 1555 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> 1556 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, 1557 }, 1558 { /* WBM_IDLE_LINK */ 1559 .start_ring_id = HAL_SRNG_WBM_IDLE_LINK, 1560 .max_rings = 1, 1561 .entry_size = sizeof(struct wbm_link_descriptor_ring) >> 2, 1562 .lmac_ring = FALSE, 1563 .ring_dir = HAL_SRNG_SRC_RING, 1564 .reg_start = { 1565 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1566 HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1567 }, 1568 /* Single ring - provide ring size if multiple rings of this 1569 * type are supported 1570 */ 1571 .reg_size = {}, 1572 .max_size = 1573 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_BMSK >> 1574 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_SHFT, 1575 }, 1576 { /* SW2WBM_RELEASE */ 1577 .start_ring_id = HAL_SRNG_WBM_SW_RELEASE, 1578 .max_rings = 1, 1579 .entry_size = sizeof(struct wbm_release_ring) >> 2, 1580 .lmac_ring = FALSE, 1581 .ring_dir = HAL_SRNG_SRC_RING, 1582 .reg_start = { 1583 HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1584 HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1585 }, 1586 /* Single ring - provide ring size if multiple rings of this 1587 * type are supported 1588 */ 1589 .reg_size = {}, 1590 .max_size = 1591 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> 1592 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, 1593 }, 1594 { /* WBM2SW_RELEASE */ 1595 .start_ring_id = HAL_SRNG_WBM2SW0_RELEASE, 1596 #ifdef IPA_WDI3_TX_TWO_PIPES 1597 .max_rings = 5, 1598 #else 1599 .max_rings = 4, 1600 #endif 1601 .entry_size = sizeof(struct wbm_release_ring) >> 2, 1602 .lmac_ring = FALSE, 1603 .ring_dir = HAL_SRNG_DST_RING, 1604 .reg_start = { 1605 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1606 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1607 }, 1608 .reg_size = { 1609 HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) - 1610 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1611 HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) - 1612 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1613 }, 1614 .max_size = 1615 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> 1616 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, 1617 }, 1618 { /* RXDMA_BUF */ 1619 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA0_BUF0, 1620 #ifdef IPA_OFFLOAD 1621 .max_rings = 3, 1622 #else 1623 .max_rings = 2, 1624 #endif 1625 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 1626 .lmac_ring = TRUE, 1627 .ring_dir = HAL_SRNG_SRC_RING, 1628 /* reg_start is not set because LMAC rings are not accessed 1629 * from host 1630 */ 1631 .reg_start = {}, 1632 .reg_size = {}, 1633 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1634 }, 1635 { /* RXDMA_DST */ 1636 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW0, 1637 .max_rings = 1, 1638 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 1639 .lmac_ring = TRUE, 1640 .ring_dir = HAL_SRNG_DST_RING, 1641 /* reg_start is not set because LMAC rings are not accessed 1642 * from host 1643 */ 1644 .reg_start = {}, 1645 .reg_size = {}, 1646 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1647 }, 1648 { /* RXDMA_MONITOR_BUF */ 1649 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA2_BUF, 1650 .max_rings = 1, 1651 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 1652 .lmac_ring = TRUE, 1653 .ring_dir = HAL_SRNG_SRC_RING, 1654 /* reg_start is not set because LMAC rings are not accessed 1655 * from host 1656 */ 1657 .reg_start = {}, 1658 .reg_size = {}, 1659 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1660 }, 1661 { /* RXDMA_MONITOR_STATUS */ 1662 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_STATBUF, 1663 .max_rings = 1, 1664 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 1665 .lmac_ring = TRUE, 1666 .ring_dir = HAL_SRNG_SRC_RING, 1667 /* reg_start is not set because LMAC rings are not accessed 1668 * from host 1669 */ 1670 .reg_start = {}, 1671 .reg_size = {}, 1672 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1673 }, 1674 { /* RXDMA_MONITOR_DST */ 1675 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW1, 1676 .max_rings = 1, 1677 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 1678 .lmac_ring = TRUE, 1679 .ring_dir = HAL_SRNG_DST_RING, 1680 /* reg_start is not set because LMAC rings are not accessed 1681 * from host 1682 */ 1683 .reg_start = {}, 1684 .reg_size = {}, 1685 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1686 }, 1687 { /* RXDMA_MONITOR_DESC */ 1688 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_DESC, 1689 .max_rings = 1, 1690 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 1691 .lmac_ring = TRUE, 1692 .ring_dir = HAL_SRNG_SRC_RING, 1693 /* reg_start is not set because LMAC rings are not accessed 1694 * from host 1695 */ 1696 .reg_start = {}, 1697 .reg_size = {}, 1698 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1699 }, 1700 { /* DIR_BUF_RX_DMA_SRC */ 1701 .start_ring_id = HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING, 1702 /* 1703 * one ring is for spectral scan 1704 * the other one is for cfr 1705 */ 1706 .max_rings = 2, 1707 .entry_size = 2, 1708 .lmac_ring = TRUE, 1709 .ring_dir = HAL_SRNG_SRC_RING, 1710 /* reg_start is not set because LMAC rings are not accessed 1711 * from host 1712 */ 1713 .reg_start = {}, 1714 .reg_size = {}, 1715 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1716 }, 1717 #ifdef WLAN_FEATURE_CIF_CFR 1718 { /* WIFI_POS_SRC */ 1719 .start_ring_id = HAL_SRNG_WIFI_POS_SRC_DMA_RING, 1720 .max_rings = 1, 1721 .entry_size = sizeof(wmi_oem_dma_buf_release_entry) >> 2, 1722 .lmac_ring = TRUE, 1723 .ring_dir = HAL_SRNG_SRC_RING, 1724 /* reg_start is not set because LMAC rings are not accessed 1725 * from host 1726 */ 1727 .reg_start = {}, 1728 .reg_size = {}, 1729 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1730 }, 1731 #endif 1732 { /* REO2PPE */ 0}, 1733 { /* PPE2TCL */ 0}, 1734 { /* PPE_RELEASE */ 0}, 1735 { /* TX_MONITOR_BUF */ 0}, 1736 { /* TX_MONITOR_DST */ 0}, 1737 { /* SW2RXDMA_NEW */ 0}, 1738 }; 1739 1740 /** 1741 * hal_qca6390_attach() - Attach 6390 target specific hal_soc ops, 1742 * offset and srng table 1743 */ 1744 void hal_qca6390_attach(struct hal_soc *hal_soc) 1745 { 1746 hal_soc->hw_srng_table = hw_srng_table_6390; 1747 hal_srng_hw_reg_offset_init_generic(hal_soc); 1748 hal_hw_txrx_default_ops_attach_li(hal_soc); 1749 hal_hw_txrx_ops_attach_qca6390(hal_soc); 1750 } 1751