1 /* 2 * Copyright (c) 2016-2018 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 #include "qdf_types.h" 19 #include "qdf_util.h" 20 #include "qdf_types.h" 21 #include "qdf_lock.h" 22 #include "qdf_mem.h" 23 #include "qdf_nbuf.h" 24 #include "hal_hw_headers.h" 25 #include "hal_internal.h" 26 #include "hal_api.h" 27 #include "target_type.h" 28 #include "wcss_version.h" 29 #include "qdf_module.h" 30 31 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_OFFSET \ 32 RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_OFFSET 33 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_MASK \ 34 RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_MASK 35 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_LSB \ 36 RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_LSB 37 #define UNIFIED_PHYRX_HT_SIG_0_HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS_OFFSET \ 38 PHYRX_HT_SIG_0_HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS_OFFSET 39 #define UNIFIED_PHYRX_L_SIG_B_0_L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS_OFFSET \ 40 PHYRX_L_SIG_B_0_L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS_OFFSET 41 #define UNIFIED_PHYRX_L_SIG_A_0_L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS_OFFSET \ 42 PHYRX_L_SIG_A_0_L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS_OFFSET 43 #define UNIFIED_PHYRX_VHT_SIG_A_0_VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS_OFFSET \ 44 PHYRX_VHT_SIG_A_0_VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS_OFFSET 45 #define UNIFIED_PHYRX_HE_SIG_A_SU_0_HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS_OFFSET \ 46 PHYRX_HE_SIG_A_SU_0_HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS_OFFSET 47 #define UNIFIED_PHYRX_HE_SIG_A_MU_DL_0_HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_OFFSET \ 48 PHYRX_HE_SIG_A_MU_DL_0_HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_OFFSET 49 #define UNIFIED_PHYRX_HE_SIG_B1_MU_0_HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_OFFSET \ 50 PHYRX_HE_SIG_B1_MU_0_HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_OFFSET 51 #define UNIFIED_PHYRX_HE_SIG_B2_MU_0_HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_OFFSET \ 52 PHYRX_HE_SIG_B2_MU_0_HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_OFFSET 53 #define UNIFIED_PHYRX_HE_SIG_B2_OFDMA_0_HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_OFFSET \ 54 PHYRX_HE_SIG_B2_OFDMA_0_HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_OFFSET 55 #define UNIFIED_PHYRX_RSSI_LEGACY_3_RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS_OFFSET \ 56 PHYRX_RSSI_LEGACY_3_RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS_OFFSET 57 #define UNIFIED_RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET \ 58 RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET 59 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 60 RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET 61 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ 62 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET 63 #define UNIFIED_RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 64 RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET 65 #define UNIFIED_REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 66 REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET 67 #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC \ 68 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER 69 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ 70 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET 71 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 72 RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET 73 #define UNIFIED_TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 74 TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET 75 #define UNIFIED_TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 76 TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET 77 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET \ 78 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET 79 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB \ 80 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB 81 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK \ 82 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK 83 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB \ 84 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB 85 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK \ 86 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK 87 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB \ 88 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB 89 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK \ 90 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK 91 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB \ 92 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB 93 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK \ 94 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK 95 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB \ 96 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB 97 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK \ 98 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK 99 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_MASK \ 100 WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_MASK 101 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_OFFSET \ 102 WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_OFFSET 103 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_LSB \ 104 WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_LSB 105 106 #include "hal_6390_tx.h" 107 #include "hal_6390_rx.h" 108 #include <hal_generic_api.h> 109 #include <hal_wbm.h> 110 111 struct hal_hw_txrx_ops qca6390_hal_hw_txrx_ops = { 112 /* init and setup */ 113 hal_srng_dst_hw_init_generic, 114 hal_srng_src_hw_init_generic, 115 hal_get_hw_hptp_generic, 116 hal_reo_setup_generic, 117 hal_setup_link_idle_list_generic, 118 119 /* tx */ 120 hal_tx_desc_set_dscp_tid_table_id_6390, 121 hal_tx_set_dscp_tid_map_6390, 122 hal_tx_update_dscp_tid_6390, 123 hal_tx_desc_set_lmac_id_6390, 124 hal_tx_desc_set_buf_addr_generic, 125 hal_tx_desc_set_search_type_generic, 126 hal_tx_desc_set_search_index_generic, 127 hal_tx_comp_get_status_generic, 128 hal_tx_comp_get_release_reason_generic, 129 130 /* rx */ 131 hal_rx_msdu_start_nss_get_6390, 132 hal_rx_mon_hw_desc_get_mpdu_status_6390, 133 hal_rx_get_tlv_6390, 134 hal_rx_proc_phyrx_other_receive_info_tlv_6390, 135 hal_rx_dump_msdu_start_tlv_6390, 136 hal_rx_dump_msdu_end_tlv_6390, 137 hal_get_link_desc_size_6390, 138 hal_rx_mpdu_start_tid_get_6390, 139 hal_rx_msdu_start_reception_type_get_6390, 140 hal_rx_msdu_end_da_idx_get_6390, 141 hal_rx_msdu_desc_info_get_ptr_generic, 142 hal_rx_link_desc_msdu0_ptr_generic, 143 hal_reo_status_get_header_generic, 144 hal_rx_status_get_tlv_info_generic, 145 hal_rx_wbm_err_info_get_generic, 146 hal_rx_dump_mpdu_start_tlv_generic, 147 }; 148 149 struct hal_hw_srng_config hw_srng_table_6390[] = { 150 /* TODO: max_rings can populated by querying HW capabilities */ 151 { /* REO_DST */ 152 .start_ring_id = HAL_SRNG_REO2SW1, 153 .max_rings = 4, 154 .entry_size = sizeof(struct reo_destination_ring) >> 2, 155 .lmac_ring = FALSE, 156 .ring_dir = HAL_SRNG_DST_RING, 157 .reg_start = { 158 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR( 159 SEQ_WCSS_UMAC_REO_REG_OFFSET), 160 HWIO_REO_R2_REO2SW1_RING_HP_ADDR( 161 SEQ_WCSS_UMAC_REO_REG_OFFSET) 162 }, 163 .reg_size = { 164 HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(0) - 165 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(0), 166 HWIO_REO_R2_REO2SW2_RING_HP_ADDR(0) - 167 HWIO_REO_R2_REO2SW1_RING_HP_ADDR(0), 168 }, 169 .max_size = 170 HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_BMSK >> 171 HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_SHFT, 172 }, 173 { /* REO_EXCEPTION */ 174 /* Designating REO2TCL ring as exception ring. This ring is 175 * similar to other REO2SW rings though it is named as REO2TCL. 176 * Any of theREO2SW rings can be used as exception ring. 177 */ 178 .start_ring_id = HAL_SRNG_REO2TCL, 179 .max_rings = 1, 180 .entry_size = sizeof(struct reo_destination_ring) >> 2, 181 .lmac_ring = FALSE, 182 .ring_dir = HAL_SRNG_DST_RING, 183 .reg_start = { 184 HWIO_REO_R0_REO2TCL_RING_BASE_LSB_ADDR( 185 SEQ_WCSS_UMAC_REO_REG_OFFSET), 186 HWIO_REO_R2_REO2TCL_RING_HP_ADDR( 187 SEQ_WCSS_UMAC_REO_REG_OFFSET) 188 }, 189 /* Single ring - provide ring size if multiple rings of this 190 * type are supported 191 */ 192 .reg_size = {}, 193 .max_size = 194 HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_BMSK >> 195 HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_SHFT, 196 }, 197 { /* REO_REINJECT */ 198 .start_ring_id = HAL_SRNG_SW2REO, 199 .max_rings = 1, 200 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 201 .lmac_ring = FALSE, 202 .ring_dir = HAL_SRNG_SRC_RING, 203 .reg_start = { 204 HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR( 205 SEQ_WCSS_UMAC_REO_REG_OFFSET), 206 HWIO_REO_R2_SW2REO_RING_HP_ADDR( 207 SEQ_WCSS_UMAC_REO_REG_OFFSET) 208 }, 209 /* Single ring - provide ring size if multiple rings of this 210 * type are supported 211 */ 212 .reg_size = {}, 213 .max_size = HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_BMSK >> 214 HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_SHFT, 215 }, 216 { /* REO_CMD */ 217 .start_ring_id = HAL_SRNG_REO_CMD, 218 .max_rings = 1, 219 .entry_size = (sizeof(struct tlv_32_hdr) + 220 sizeof(struct reo_get_queue_stats)) >> 2, 221 .lmac_ring = FALSE, 222 .ring_dir = HAL_SRNG_SRC_RING, 223 .reg_start = { 224 HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR( 225 SEQ_WCSS_UMAC_REO_REG_OFFSET), 226 HWIO_REO_R2_REO_CMD_RING_HP_ADDR( 227 SEQ_WCSS_UMAC_REO_REG_OFFSET), 228 }, 229 /* Single ring - provide ring size if multiple rings of this 230 * type are supported 231 */ 232 .reg_size = {}, 233 .max_size = 234 HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_BMSK >> 235 HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_SHFT, 236 }, 237 { /* REO_STATUS */ 238 .start_ring_id = HAL_SRNG_REO_STATUS, 239 .max_rings = 1, 240 .entry_size = (sizeof(struct tlv_32_hdr) + 241 sizeof(struct reo_get_queue_stats_status)) >> 2, 242 .lmac_ring = FALSE, 243 .ring_dir = HAL_SRNG_DST_RING, 244 .reg_start = { 245 HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR( 246 SEQ_WCSS_UMAC_REO_REG_OFFSET), 247 HWIO_REO_R2_REO_STATUS_RING_HP_ADDR( 248 SEQ_WCSS_UMAC_REO_REG_OFFSET), 249 }, 250 /* Single ring - provide ring size if multiple rings of this 251 * type are supported 252 */ 253 .reg_size = {}, 254 .max_size = 255 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> 256 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, 257 }, 258 { /* TCL_DATA */ 259 .start_ring_id = HAL_SRNG_SW2TCL1, 260 .max_rings = 3, 261 .entry_size = (sizeof(struct tlv_32_hdr) + 262 sizeof(struct tcl_data_cmd)) >> 2, 263 .lmac_ring = FALSE, 264 .ring_dir = HAL_SRNG_SRC_RING, 265 .reg_start = { 266 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR( 267 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 268 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR( 269 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 270 }, 271 .reg_size = { 272 HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(0) - 273 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(0), 274 HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(0) - 275 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(0), 276 }, 277 .max_size = 278 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK >> 279 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT, 280 }, 281 { /* TCL_CMD */ 282 .start_ring_id = HAL_SRNG_SW2TCL_CMD, 283 .max_rings = 1, 284 .entry_size = (sizeof(struct tlv_32_hdr) + 285 sizeof(struct tcl_gse_cmd)) >> 2, 286 .lmac_ring = FALSE, 287 .ring_dir = HAL_SRNG_SRC_RING, 288 .reg_start = { 289 HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_ADDR( 290 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 291 HWIO_TCL_R2_SW2TCL_CMD_RING_HP_ADDR( 292 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 293 }, 294 /* Single ring - provide ring size if multiple rings of this 295 * type are supported 296 */ 297 .reg_size = {}, 298 .max_size = 299 HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RING_SIZE_BMSK >> 300 HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RING_SIZE_SHFT, 301 }, 302 { /* TCL_STATUS */ 303 .start_ring_id = HAL_SRNG_TCL_STATUS, 304 .max_rings = 1, 305 .entry_size = (sizeof(struct tlv_32_hdr) + 306 sizeof(struct tcl_status_ring)) >> 2, 307 .lmac_ring = FALSE, 308 .ring_dir = HAL_SRNG_DST_RING, 309 .reg_start = { 310 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR( 311 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 312 HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR( 313 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 314 }, 315 /* Single ring - provide ring size if multiple rings of this 316 * type are supported 317 */ 318 .reg_size = {}, 319 .max_size = 320 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_BMSK >> 321 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_SHFT, 322 }, 323 { /* CE_SRC */ 324 .start_ring_id = HAL_SRNG_CE_0_SRC, 325 .max_rings = 12, 326 .entry_size = sizeof(struct ce_src_desc) >> 2, 327 .lmac_ring = FALSE, 328 .ring_dir = HAL_SRNG_SRC_RING, 329 .reg_start = { 330 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR( 331 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET), 332 HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR( 333 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET), 334 }, 335 .reg_size = { 336 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET - 337 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET, 338 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET - 339 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET, 340 }, 341 .max_size = 342 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >> 343 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT, 344 }, 345 { /* CE_DST */ 346 .start_ring_id = HAL_SRNG_CE_0_DST, 347 .max_rings = 12, 348 .entry_size = 8 >> 2, 349 /*TODO: entry_size above should actually be 350 * sizeof(struct ce_dst_desc) >> 2, but couldn't find definition 351 * of struct ce_dst_desc in HW header files 352 */ 353 .lmac_ring = FALSE, 354 .ring_dir = HAL_SRNG_SRC_RING, 355 .reg_start = { 356 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR( 357 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 358 HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR( 359 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 360 }, 361 .reg_size = { 362 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 363 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 364 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 365 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 366 }, 367 .max_size = 368 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >> 369 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT, 370 }, 371 { /* CE_DST_STATUS */ 372 .start_ring_id = HAL_SRNG_CE_0_DST_STATUS, 373 .max_rings = 12, 374 .entry_size = sizeof(struct ce_stat_desc) >> 2, 375 .lmac_ring = FALSE, 376 .ring_dir = HAL_SRNG_DST_RING, 377 .reg_start = { 378 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR( 379 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 380 HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR( 381 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 382 }, 383 /* TODO: check destination status ring registers */ 384 .reg_size = { 385 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 386 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 387 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 388 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 389 }, 390 .max_size = 391 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> 392 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, 393 }, 394 { /* WBM_IDLE_LINK */ 395 .start_ring_id = HAL_SRNG_WBM_IDLE_LINK, 396 .max_rings = 1, 397 .entry_size = sizeof(struct wbm_link_descriptor_ring) >> 2, 398 .lmac_ring = FALSE, 399 .ring_dir = HAL_SRNG_SRC_RING, 400 .reg_start = { 401 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 402 HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 403 }, 404 /* Single ring - provide ring size if multiple rings of this 405 * type are supported 406 */ 407 .reg_size = {}, 408 .max_size = 409 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_BMSK >> 410 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_SHFT, 411 }, 412 { /* SW2WBM_RELEASE */ 413 .start_ring_id = HAL_SRNG_WBM_SW_RELEASE, 414 .max_rings = 1, 415 .entry_size = sizeof(struct wbm_release_ring) >> 2, 416 .lmac_ring = FALSE, 417 .ring_dir = HAL_SRNG_SRC_RING, 418 .reg_start = { 419 HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 420 HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 421 }, 422 /* Single ring - provide ring size if multiple rings of this 423 * type are supported 424 */ 425 .reg_size = {}, 426 .max_size = 427 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> 428 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, 429 }, 430 { /* WBM2SW_RELEASE */ 431 .start_ring_id = HAL_SRNG_WBM2SW0_RELEASE, 432 .max_rings = 4, 433 .entry_size = sizeof(struct wbm_release_ring) >> 2, 434 .lmac_ring = FALSE, 435 .ring_dir = HAL_SRNG_DST_RING, 436 .reg_start = { 437 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 438 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 439 }, 440 .reg_size = { 441 HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) - 442 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 443 HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) - 444 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 445 }, 446 .max_size = 447 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> 448 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, 449 }, 450 { /* RXDMA_BUF */ 451 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA0_BUF0, 452 #ifdef IPA_OFFLOAD 453 .max_rings = 3, 454 #else 455 .max_rings = 2, 456 #endif 457 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 458 .lmac_ring = TRUE, 459 .ring_dir = HAL_SRNG_SRC_RING, 460 /* reg_start is not set because LMAC rings are not accessed 461 * from host 462 */ 463 .reg_start = {}, 464 .reg_size = {}, 465 .max_size = HAL_RXDMA_MAX_RING_SIZE, 466 }, 467 { /* RXDMA_DST */ 468 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW0, 469 .max_rings = 1, 470 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 471 .lmac_ring = TRUE, 472 .ring_dir = HAL_SRNG_DST_RING, 473 /* reg_start is not set because LMAC rings are not accessed 474 * from host 475 */ 476 .reg_start = {}, 477 .reg_size = {}, 478 .max_size = HAL_RXDMA_MAX_RING_SIZE, 479 }, 480 { /* RXDMA_MONITOR_BUF */ 481 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA2_BUF, 482 .max_rings = 1, 483 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 484 .lmac_ring = TRUE, 485 .ring_dir = HAL_SRNG_SRC_RING, 486 /* reg_start is not set because LMAC rings are not accessed 487 * from host 488 */ 489 .reg_start = {}, 490 .reg_size = {}, 491 .max_size = HAL_RXDMA_MAX_RING_SIZE, 492 }, 493 { /* RXDMA_MONITOR_STATUS */ 494 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_STATBUF, 495 .max_rings = 1, 496 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 497 .lmac_ring = TRUE, 498 .ring_dir = HAL_SRNG_SRC_RING, 499 /* reg_start is not set because LMAC rings are not accessed 500 * from host 501 */ 502 .reg_start = {}, 503 .reg_size = {}, 504 .max_size = HAL_RXDMA_MAX_RING_SIZE, 505 }, 506 { /* RXDMA_MONITOR_DST */ 507 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW1, 508 .max_rings = 1, 509 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 510 .lmac_ring = TRUE, 511 .ring_dir = HAL_SRNG_DST_RING, 512 /* reg_start is not set because LMAC rings are not accessed 513 * from host 514 */ 515 .reg_start = {}, 516 .reg_size = {}, 517 .max_size = HAL_RXDMA_MAX_RING_SIZE, 518 }, 519 { /* RXDMA_MONITOR_DESC */ 520 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_DESC, 521 .max_rings = 1, 522 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 523 .lmac_ring = TRUE, 524 .ring_dir = HAL_SRNG_SRC_RING, 525 /* reg_start is not set because LMAC rings are not accessed 526 * from host 527 */ 528 .reg_start = {}, 529 .reg_size = {}, 530 .max_size = HAL_RXDMA_MAX_RING_SIZE, 531 }, 532 { /* DIR_BUF_RX_DMA_SRC */ 533 .start_ring_id = HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING, 534 .max_rings = 1, 535 .entry_size = 2, 536 .lmac_ring = TRUE, 537 .ring_dir = HAL_SRNG_SRC_RING, 538 /* reg_start is not set because LMAC rings are not accessed 539 * from host 540 */ 541 .reg_start = {}, 542 .reg_size = {}, 543 .max_size = HAL_RXDMA_MAX_RING_SIZE, 544 }, 545 #ifdef WLAN_FEATURE_CIF_CFR 546 { /* WIFI_POS_SRC */ 547 .start_ring_id = HAL_SRNG_WIFI_POS_SRC_DMA_RING, 548 .max_rings = 1, 549 .entry_size = sizeof(wmi_oem_dma_buf_release_entry) >> 2, 550 .lmac_ring = TRUE, 551 .ring_dir = HAL_SRNG_SRC_RING, 552 /* reg_start is not set because LMAC rings are not accessed 553 * from host 554 */ 555 .reg_start = {}, 556 .reg_size = {}, 557 .max_size = HAL_RXDMA_MAX_RING_SIZE, 558 }, 559 #endif 560 }; 561 562 int32_t hal_hw_reg_offset_qca6390[] = { 563 /* dst */ 564 REG_OFFSET(DST, HP), 565 REG_OFFSET(DST, TP), 566 REG_OFFSET(DST, ID), 567 REG_OFFSET(DST, MISC), 568 REG_OFFSET(DST, HP_ADDR_LSB), 569 REG_OFFSET(DST, HP_ADDR_MSB), 570 REG_OFFSET(DST, MSI1_BASE_LSB), 571 REG_OFFSET(DST, MSI1_BASE_MSB), 572 REG_OFFSET(DST, MSI1_DATA), 573 REG_OFFSET(DST, BASE_LSB), 574 REG_OFFSET(DST, BASE_MSB), 575 REG_OFFSET(DST, PRODUCER_INT_SETUP), 576 /* src */ 577 REG_OFFSET(SRC, HP), 578 REG_OFFSET(SRC, TP), 579 REG_OFFSET(SRC, ID), 580 REG_OFFSET(SRC, MISC), 581 REG_OFFSET(SRC, TP_ADDR_LSB), 582 REG_OFFSET(SRC, TP_ADDR_MSB), 583 REG_OFFSET(SRC, MSI1_BASE_LSB), 584 REG_OFFSET(SRC, MSI1_BASE_MSB), 585 REG_OFFSET(SRC, MSI1_DATA), 586 REG_OFFSET(SRC, BASE_LSB), 587 REG_OFFSET(SRC, BASE_MSB), 588 REG_OFFSET(SRC, CONSUMER_INT_SETUP_IX0), 589 REG_OFFSET(SRC, CONSUMER_INT_SETUP_IX1), 590 }; 591 592 /** 593 * hal_qca6390_attach() - Attach 6390 target specific hal_soc ops, 594 * offset and srng table 595 */ 596 void hal_qca6390_attach(struct hal_soc *hal_soc) 597 { 598 hal_soc->hw_srng_table = hw_srng_table_6390; 599 hal_soc->hal_hw_reg_offset = hal_hw_reg_offset_qca6390; 600 hal_soc->ops = &qca6390_hal_hw_txrx_ops; 601 } 602