1 /* 2 * Copyright (c) 2016-2019 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 #include "qdf_types.h" 19 #include "qdf_util.h" 20 #include "qdf_types.h" 21 #include "qdf_lock.h" 22 #include "qdf_mem.h" 23 #include "qdf_nbuf.h" 24 #include "hal_hw_headers.h" 25 #include "hal_internal.h" 26 #include "hal_api.h" 27 #include "target_type.h" 28 #include "wcss_version.h" 29 #include "qdf_module.h" 30 31 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_OFFSET \ 32 RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_OFFSET 33 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_MASK \ 34 RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_MASK 35 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_LSB \ 36 RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_LSB 37 #define UNIFIED_PHYRX_HT_SIG_0_HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS_OFFSET \ 38 PHYRX_HT_SIG_0_HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS_OFFSET 39 #define UNIFIED_PHYRX_L_SIG_B_0_L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS_OFFSET \ 40 PHYRX_L_SIG_B_0_L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS_OFFSET 41 #define UNIFIED_PHYRX_L_SIG_A_0_L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS_OFFSET \ 42 PHYRX_L_SIG_A_0_L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS_OFFSET 43 #define UNIFIED_PHYRX_VHT_SIG_A_0_VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS_OFFSET \ 44 PHYRX_VHT_SIG_A_0_VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS_OFFSET 45 #define UNIFIED_PHYRX_HE_SIG_A_SU_0_HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS_OFFSET \ 46 PHYRX_HE_SIG_A_SU_0_HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS_OFFSET 47 #define UNIFIED_PHYRX_HE_SIG_A_MU_DL_0_HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_OFFSET \ 48 PHYRX_HE_SIG_A_MU_DL_0_HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_OFFSET 49 #define UNIFIED_PHYRX_HE_SIG_B1_MU_0_HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_OFFSET \ 50 PHYRX_HE_SIG_B1_MU_0_HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_OFFSET 51 #define UNIFIED_PHYRX_HE_SIG_B2_MU_0_HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_OFFSET \ 52 PHYRX_HE_SIG_B2_MU_0_HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_OFFSET 53 #define UNIFIED_PHYRX_HE_SIG_B2_OFDMA_0_HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_OFFSET \ 54 PHYRX_HE_SIG_B2_OFDMA_0_HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_OFFSET 55 #define UNIFIED_PHYRX_RSSI_LEGACY_3_RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS_OFFSET \ 56 PHYRX_RSSI_LEGACY_3_RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS_OFFSET 57 #define UNIFIED_PHYRX_RSSI_LEGACY_19_RECEIVE_RSSI_INFO_PREAMBLE_RSSI_INFO_DETAILS_OFFSET \ 58 PHYRX_RSSI_LEGACY_19_RECEIVE_RSSI_INFO_PREAMBLE_RSSI_INFO_DETAILS_OFFSET 59 #define UNIFIED_RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET \ 60 RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET 61 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 62 RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET 63 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ 64 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET 65 #define UNIFIED_RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 66 RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET 67 #define UNIFIED_REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 68 REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET 69 #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC \ 70 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER 71 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ 72 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET 73 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 74 RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET 75 #define UNIFIED_TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 76 TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET 77 #define UNIFIED_TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 78 TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET 79 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET \ 80 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET 81 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB \ 82 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB 83 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK \ 84 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK 85 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB \ 86 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB 87 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK \ 88 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK 89 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB \ 90 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB 91 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK \ 92 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK 93 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB \ 94 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB 95 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK \ 96 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK 97 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB \ 98 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB 99 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK \ 100 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK 101 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_MASK \ 102 WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_MASK 103 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_OFFSET \ 104 WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_OFFSET 105 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_LSB \ 106 WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_LSB 107 108 #include "hal_6390_tx.h" 109 #include "hal_6390_rx.h" 110 #include <hal_generic_api.h> 111 #include <hal_wbm.h> 112 113 /** 114 * hal_rx_get_rx_fragment_number_6390(): Function to retrieve rx fragment number 115 * 116 * @nbuf: Network buffer 117 * Returns: rx fragment number 118 */ 119 static 120 uint8_t hal_rx_get_rx_fragment_number_6390(uint8_t *buf) 121 { 122 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 123 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 124 125 /* Return first 4 bits as fragment number */ 126 return (HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info) & 127 DOT11_SEQ_FRAG_MASK); 128 } 129 130 /** 131 * hal_rx_msdu_end_da_is_mcbc_get_6390(): API to check if pkt is MCBC 132 * from rx_msdu_end TLV 133 * 134 * @ buf: pointer to the start of RX PKT TLV headers 135 * Return: da_is_mcbc 136 */ 137 static uint8_t 138 hal_rx_msdu_end_da_is_mcbc_get_6390(uint8_t *buf) 139 { 140 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 141 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 142 143 return HAL_RX_MSDU_END_DA_IS_MCBC_GET(msdu_end); 144 } 145 146 /** 147 * hal_rx_msdu_end_sa_is_valid_get_6390(): API to get_6390 the 148 * sa_is_valid bit from rx_msdu_end TLV 149 * 150 * @ buf: pointer to the start of RX PKT TLV headers 151 * Return: sa_is_valid bit 152 */ 153 static uint8_t 154 hal_rx_msdu_end_sa_is_valid_get_6390(uint8_t *buf) 155 { 156 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 157 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 158 uint8_t sa_is_valid; 159 160 sa_is_valid = HAL_RX_MSDU_END_SA_IS_VALID_GET(msdu_end); 161 162 return sa_is_valid; 163 } 164 165 /** 166 * hal_rx_msdu_end_sa_idx_get_6390(): API to get_6390 the 167 * sa_idx from rx_msdu_end TLV 168 * 169 * @ buf: pointer to the start of RX PKT TLV headers 170 * Return: sa_idx (SA AST index) 171 */ 172 static 173 uint16_t hal_rx_msdu_end_sa_idx_get_6390(uint8_t *buf) 174 { 175 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 176 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 177 uint16_t sa_idx; 178 179 sa_idx = HAL_RX_MSDU_END_SA_IDX_GET(msdu_end); 180 181 return sa_idx; 182 } 183 184 /** 185 * hal_rx_desc_is_first_msdu_6390() - Check if first msdu 186 * 187 * @hal_soc_hdl: hal_soc handle 188 * @hw_desc_addr: hardware descriptor address 189 * 190 * Return: 0 - success/ non-zero failure 191 */ 192 static uint32_t hal_rx_desc_is_first_msdu_6390(void *hw_desc_addr) 193 { 194 struct rx_pkt_tlvs *rx_tlvs = (struct rx_pkt_tlvs *)hw_desc_addr; 195 struct rx_msdu_end *msdu_end = &rx_tlvs->msdu_end_tlv.rx_msdu_end; 196 197 return HAL_RX_GET(msdu_end, RX_MSDU_END_5, FIRST_MSDU); 198 } 199 200 /** 201 * hal_rx_msdu_end_l3_hdr_padding_get_6390(): API to get_6390 the 202 * l3_header padding from rx_msdu_end TLV 203 * 204 * @ buf: pointer to the start of RX PKT TLV headers 205 * Return: number of l3 header padding bytes 206 */ 207 static uint32_t hal_rx_msdu_end_l3_hdr_padding_get_6390(uint8_t *buf) 208 { 209 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 210 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 211 uint32_t l3_header_padding; 212 213 l3_header_padding = HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(msdu_end); 214 215 return l3_header_padding; 216 } 217 218 /* 219 * @ hal_rx_encryption_info_valid_6390: Returns encryption type. 220 * 221 * @ buf: rx_tlv_hdr of the received packet 222 * @ Return: encryption type 223 */ 224 static uint32_t hal_rx_encryption_info_valid_6390(uint8_t *buf) 225 { 226 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 227 struct rx_mpdu_start *mpdu_start = 228 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 229 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 230 uint32_t encryption_info = HAL_RX_MPDU_ENCRYPTION_INFO_VALID(mpdu_info); 231 232 return encryption_info; 233 } 234 235 /* 236 * @ hal_rx_print_pn_6390: Prints the PN of rx packet. 237 * 238 * @ buf: rx_tlv_hdr of the received packet 239 * @ Return: void 240 */ 241 static void hal_rx_print_pn_6390(uint8_t *buf) 242 { 243 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 244 struct rx_mpdu_start *mpdu_start = 245 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 246 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 247 248 uint32_t pn_31_0 = HAL_RX_MPDU_PN_31_0_GET(mpdu_info); 249 uint32_t pn_63_32 = HAL_RX_MPDU_PN_63_32_GET(mpdu_info); 250 uint32_t pn_95_64 = HAL_RX_MPDU_PN_95_64_GET(mpdu_info); 251 uint32_t pn_127_96 = HAL_RX_MPDU_PN_127_96_GET(mpdu_info); 252 253 hal_debug("PN number pn_127_96 0x%x pn_95_64 0x%x pn_63_32 0x%x pn_31_0 0x%x ", 254 pn_127_96, pn_95_64, pn_63_32, pn_31_0); 255 } 256 257 /** 258 * hal_rx_msdu_end_first_msduget_6390: API to get first msdu status 259 * from rx_msdu_end TLV 260 * 261 * @ buf: pointer to the start of RX PKT TLV headers 262 * Return: first_msdu 263 */ 264 static uint8_t hal_rx_msdu_end_first_msdu_get_6390(uint8_t *buf) 265 { 266 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 267 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 268 uint8_t first_msdu; 269 270 first_msdu = HAL_RX_MSDU_END_FIRST_MSDU_GET(msdu_end); 271 272 return first_msdu; 273 } 274 275 /** 276 * hal_rx_msdu_end_da_is_valid_get_6390: API to check if da is valid 277 * from rx_msdu_end TLV 278 * 279 * @ buf: pointer to the start of RX PKT TLV headers 280 * Return: da_is_valid 281 */ 282 static uint8_t hal_rx_msdu_end_da_is_valid_get_6390(uint8_t *buf) 283 { 284 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 285 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 286 uint8_t da_is_valid; 287 288 da_is_valid = HAL_RX_MSDU_END_DA_IS_VALID_GET(msdu_end); 289 290 return da_is_valid; 291 } 292 293 /** 294 * hal_rx_msdu_end_last_msdu_get_6390: API to get last msdu status 295 * from rx_msdu_end TLV 296 * 297 * @ buf: pointer to the start of RX PKT TLV headers 298 * Return: last_msdu 299 */ 300 static uint8_t hal_rx_msdu_end_last_msdu_get_6390(uint8_t *buf) 301 { 302 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 303 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 304 uint8_t last_msdu; 305 306 last_msdu = HAL_RX_MSDU_END_LAST_MSDU_GET(msdu_end); 307 308 return last_msdu; 309 } 310 311 /* 312 * hal_rx_get_mpdu_mac_ad4_valid_6390(): Retrieves if mpdu 4th addr is valid 313 * 314 * @nbuf: Network buffer 315 * Returns: value of mpdu 4th address valid field 316 */ 317 static bool hal_rx_get_mpdu_mac_ad4_valid_6390(uint8_t *buf) 318 { 319 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 320 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 321 bool ad4_valid = 0; 322 323 ad4_valid = HAL_RX_MPDU_GET_MAC_AD4_VALID(rx_mpdu_info); 324 325 return ad4_valid; 326 } 327 328 /** 329 * hal_rx_mpdu_start_sw_peer_id_get_6390: Retrieve sw peer_id 330 * @buf: network buffer 331 * 332 * Return: sw peer_id 333 */ 334 static uint32_t hal_rx_mpdu_start_sw_peer_id_get_6390(uint8_t *buf) 335 { 336 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 337 struct rx_mpdu_start *mpdu_start = 338 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 339 340 return HAL_RX_MPDU_INFO_SW_PEER_ID_GET( 341 &mpdu_start->rx_mpdu_info_details); 342 } 343 344 /* 345 * hal_rx_mpdu_get_to_ds_6390(): API to get the tods info 346 * from rx_mpdu_start 347 * 348 * @buf: pointer to the start of RX PKT TLV header 349 * Return: uint32_t(to_ds) 350 */ 351 static uint32_t hal_rx_mpdu_get_to_ds_6390(uint8_t *buf) 352 { 353 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 354 struct rx_mpdu_start *mpdu_start = 355 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 356 357 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 358 359 return HAL_RX_MPDU_GET_TODS(mpdu_info); 360 } 361 362 /* 363 * hal_rx_mpdu_get_fr_ds_6390(): API to get the from ds info 364 * from rx_mpdu_start 365 * 366 * @buf: pointer to the start of RX PKT TLV header 367 * Return: uint32_t(fr_ds) 368 */ 369 static uint32_t hal_rx_mpdu_get_fr_ds_6390(uint8_t *buf) 370 { 371 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 372 struct rx_mpdu_start *mpdu_start = 373 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 374 375 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 376 377 return HAL_RX_MPDU_GET_FROMDS(mpdu_info); 378 } 379 380 /* 381 * hal_rx_get_mpdu_frame_control_valid_6390(): Retrieves mpdu 382 * frame control valid 383 * 384 * @nbuf: Network buffer 385 * Returns: value of frame control valid field 386 */ 387 static uint8_t hal_rx_get_mpdu_frame_control_valid_6390(uint8_t *buf) 388 { 389 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 390 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 391 392 return HAL_RX_MPDU_GET_FRAME_CONTROL_VALID(rx_mpdu_info); 393 } 394 395 /* 396 * hal_rx_mpdu_get_addr1_6390(): API to check get address1 of the mpdu 397 * 398 * @buf: pointer to the start of RX PKT TLV headera 399 * @mac_addr: pointer to mac address 400 * Return: success/failure 401 */ 402 static QDF_STATUS hal_rx_mpdu_get_addr1_6390(uint8_t *buf, uint8_t *mac_addr) 403 { 404 struct __attribute__((__packed__)) hal_addr1 { 405 uint32_t ad1_31_0; 406 uint16_t ad1_47_32; 407 }; 408 409 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 410 struct rx_mpdu_start *mpdu_start = 411 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 412 413 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 414 struct hal_addr1 *addr = (struct hal_addr1 *)mac_addr; 415 uint32_t mac_addr_ad1_valid; 416 417 mac_addr_ad1_valid = HAL_RX_MPDU_MAC_ADDR_AD1_VALID_GET(mpdu_info); 418 419 if (mac_addr_ad1_valid) { 420 addr->ad1_31_0 = HAL_RX_MPDU_AD1_31_0_GET(mpdu_info); 421 addr->ad1_47_32 = HAL_RX_MPDU_AD1_47_32_GET(mpdu_info); 422 return QDF_STATUS_SUCCESS; 423 } 424 425 return QDF_STATUS_E_FAILURE; 426 } 427 428 /* 429 * hal_rx_mpdu_get_addr2_6390(): API to check get address2 of the mpdu 430 * in the packet 431 * 432 * @buf: pointer to the start of RX PKT TLV header 433 * @mac_addr: pointer to mac address 434 * Return: success/failure 435 */ 436 static QDF_STATUS hal_rx_mpdu_get_addr2_6390(uint8_t *buf, 437 uint8_t *mac_addr) 438 { 439 struct __attribute__((__packed__)) hal_addr2 { 440 uint16_t ad2_15_0; 441 uint32_t ad2_47_16; 442 }; 443 444 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 445 struct rx_mpdu_start *mpdu_start = 446 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 447 448 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 449 struct hal_addr2 *addr = (struct hal_addr2 *)mac_addr; 450 uint32_t mac_addr_ad2_valid; 451 452 mac_addr_ad2_valid = HAL_RX_MPDU_MAC_ADDR_AD2_VALID_GET(mpdu_info); 453 454 if (mac_addr_ad2_valid) { 455 addr->ad2_15_0 = HAL_RX_MPDU_AD2_15_0_GET(mpdu_info); 456 addr->ad2_47_16 = HAL_RX_MPDU_AD2_47_16_GET(mpdu_info); 457 return QDF_STATUS_SUCCESS; 458 } 459 460 return QDF_STATUS_E_FAILURE; 461 } 462 463 /* 464 * hal_rx_mpdu_get_addr3_6390(): API to get address3 of the mpdu 465 * in the packet 466 * 467 * @buf: pointer to the start of RX PKT TLV header 468 * @mac_addr: pointer to mac address 469 * Return: success/failure 470 */ 471 static QDF_STATUS hal_rx_mpdu_get_addr3_6390(uint8_t *buf, uint8_t *mac_addr) 472 { 473 struct __attribute__((__packed__)) hal_addr3 { 474 uint32_t ad3_31_0; 475 uint16_t ad3_47_32; 476 }; 477 478 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 479 struct rx_mpdu_start *mpdu_start = 480 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 481 482 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 483 struct hal_addr3 *addr = (struct hal_addr3 *)mac_addr; 484 uint32_t mac_addr_ad3_valid; 485 486 mac_addr_ad3_valid = HAL_RX_MPDU_MAC_ADDR_AD3_VALID_GET(mpdu_info); 487 488 if (mac_addr_ad3_valid) { 489 addr->ad3_31_0 = HAL_RX_MPDU_AD3_31_0_GET(mpdu_info); 490 addr->ad3_47_32 = HAL_RX_MPDU_AD3_47_32_GET(mpdu_info); 491 return QDF_STATUS_SUCCESS; 492 } 493 494 return QDF_STATUS_E_FAILURE; 495 } 496 497 /* 498 * hal_rx_mpdu_get_addr4_6390(): API to get address4 of the mpdu 499 * in the packet 500 * 501 * @buf: pointer to the start of RX PKT TLV header 502 * @mac_addr: pointer to mac address 503 * Return: success/failure 504 */ 505 static QDF_STATUS hal_rx_mpdu_get_addr4_6390(uint8_t *buf, uint8_t *mac_addr) 506 { 507 struct __attribute__((__packed__)) hal_addr4 { 508 uint32_t ad4_31_0; 509 uint16_t ad4_47_32; 510 }; 511 512 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 513 struct rx_mpdu_start *mpdu_start = 514 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 515 516 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 517 struct hal_addr4 *addr = (struct hal_addr4 *)mac_addr; 518 uint32_t mac_addr_ad4_valid; 519 520 mac_addr_ad4_valid = HAL_RX_MPDU_MAC_ADDR_AD4_VALID_GET(mpdu_info); 521 522 if (mac_addr_ad4_valid) { 523 addr->ad4_31_0 = HAL_RX_MPDU_AD4_31_0_GET(mpdu_info); 524 addr->ad4_47_32 = HAL_RX_MPDU_AD4_47_32_GET(mpdu_info); 525 return QDF_STATUS_SUCCESS; 526 } 527 528 return QDF_STATUS_E_FAILURE; 529 } 530 531 /* 532 * hal_rx_get_mpdu_sequence_control_valid_6390(): Get mpdu 533 * sequence control valid 534 * 535 * @nbuf: Network buffer 536 * Returns: value of sequence control valid field 537 */ 538 static uint8_t hal_rx_get_mpdu_sequence_control_valid_6390(uint8_t *buf) 539 { 540 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 541 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 542 543 return HAL_RX_MPDU_GET_SEQUENCE_CONTROL_VALID(rx_mpdu_info); 544 } 545 546 /** 547 * hal_rx_is_unicast_6390: check packet is unicast frame or not. 548 * 549 * @ buf: pointer to rx pkt TLV. 550 * 551 * Return: true on unicast. 552 */ 553 static bool hal_rx_is_unicast_6390(uint8_t *buf) 554 { 555 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 556 struct rx_mpdu_start *mpdu_start = 557 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 558 uint32_t grp_id; 559 uint8_t *rx_mpdu_info = (uint8_t *)&mpdu_start->rx_mpdu_info_details; 560 561 grp_id = (_HAL_MS((*_OFFSET_TO_WORD_PTR((rx_mpdu_info), 562 RX_MPDU_INFO_0_SW_FRAME_GROUP_ID_OFFSET)), 563 RX_MPDU_INFO_0_SW_FRAME_GROUP_ID_MASK, 564 RX_MPDU_INFO_0_SW_FRAME_GROUP_ID_LSB)); 565 566 return (HAL_MPDU_SW_FRAME_GROUP_UNICAST_DATA == grp_id) ? true : false; 567 } 568 569 /** 570 * hal_rx_tid_get_6390: get tid based on qos control valid. 571 * @hal_soc_hdl: hal soc handle 572 * @buf: pointer to rx pkt TLV. 573 * 574 * Return: tid 575 */ 576 static uint32_t hal_rx_tid_get_6390(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 577 { 578 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 579 struct rx_mpdu_start *mpdu_start = 580 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 581 uint8_t *rx_mpdu_info = (uint8_t *)&mpdu_start->rx_mpdu_info_details; 582 uint8_t qos_control_valid = 583 (_HAL_MS((*_OFFSET_TO_WORD_PTR((rx_mpdu_info), 584 RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_OFFSET)), 585 RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_MASK, 586 RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_LSB)); 587 588 if (qos_control_valid) 589 return hal_rx_mpdu_start_tid_get_6390(buf); 590 591 return HAL_RX_NON_QOS_TID; 592 } 593 594 /** 595 * hal_rx_hw_desc_get_ppduid_get_6390(): retrieve ppdu id 596 * @hw_desc_addr: hw addr 597 * 598 * Return: ppdu id 599 */ 600 static uint32_t hal_rx_hw_desc_get_ppduid_get_6390(void *hw_desc_addr) 601 { 602 struct rx_mpdu_info *rx_mpdu_info; 603 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr; 604 605 rx_mpdu_info = 606 &rx_desc->mpdu_start_tlv.rx_mpdu_start.rx_mpdu_info_details; 607 608 return HAL_RX_GET(rx_mpdu_info, RX_MPDU_INFO_0, PHY_PPDU_ID); 609 } 610 611 /** 612 * hal_reo_status_get_header_6390 - Process reo desc info 613 * @d - Pointer to reo descriptior 614 * @b - tlv type info 615 * @h1 - Pointer to hal_reo_status_header where info to be stored 616 * 617 * Return - none. 618 * 619 */ 620 static void hal_reo_status_get_header_6390(uint32_t *d, int b, void *h1) 621 { 622 uint32_t val1 = 0; 623 struct hal_reo_status_header *h = 624 (struct hal_reo_status_header *)h1; 625 626 switch (b) { 627 case HAL_REO_QUEUE_STATS_STATUS_TLV: 628 val1 = d[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_0, 629 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 630 break; 631 case HAL_REO_FLUSH_QUEUE_STATUS_TLV: 632 val1 = d[HAL_OFFSET_DW(REO_FLUSH_QUEUE_STATUS_0, 633 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 634 break; 635 case HAL_REO_FLUSH_CACHE_STATUS_TLV: 636 val1 = d[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_0, 637 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 638 break; 639 case HAL_REO_UNBLK_CACHE_STATUS_TLV: 640 val1 = d[HAL_OFFSET_DW(REO_UNBLOCK_CACHE_STATUS_0, 641 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 642 break; 643 case HAL_REO_TIMOUT_LIST_STATUS_TLV: 644 val1 = d[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_0, 645 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 646 break; 647 case HAL_REO_DESC_THRES_STATUS_TLV: 648 val1 = 649 d[HAL_OFFSET_DW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0, 650 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 651 break; 652 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: 653 val1 = d[HAL_OFFSET_DW(REO_UPDATE_RX_REO_QUEUE_STATUS_0, 654 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 655 break; 656 default: 657 qdf_nofl_err("ERROR: Unknown tlv\n"); 658 break; 659 } 660 h->cmd_num = 661 HAL_GET_FIELD( 662 UNIFORM_REO_STATUS_HEADER_0, REO_STATUS_NUMBER, 663 val1); 664 h->exec_time = 665 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_0, 666 CMD_EXECUTION_TIME, val1); 667 h->status = 668 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_0, 669 REO_CMD_EXECUTION_STATUS, val1); 670 switch (b) { 671 case HAL_REO_QUEUE_STATS_STATUS_TLV: 672 val1 = d[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_1, 673 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 674 break; 675 case HAL_REO_FLUSH_QUEUE_STATUS_TLV: 676 val1 = d[HAL_OFFSET_DW(REO_FLUSH_QUEUE_STATUS_1, 677 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 678 break; 679 case HAL_REO_FLUSH_CACHE_STATUS_TLV: 680 val1 = d[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_1, 681 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 682 break; 683 case HAL_REO_UNBLK_CACHE_STATUS_TLV: 684 val1 = d[HAL_OFFSET_DW(REO_UNBLOCK_CACHE_STATUS_1, 685 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 686 break; 687 case HAL_REO_TIMOUT_LIST_STATUS_TLV: 688 val1 = d[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_1, 689 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 690 break; 691 case HAL_REO_DESC_THRES_STATUS_TLV: 692 val1 = 693 d[HAL_OFFSET_DW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_1, 694 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 695 break; 696 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: 697 val1 = d[HAL_OFFSET_DW(REO_UPDATE_RX_REO_QUEUE_STATUS_1, 698 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 699 break; 700 default: 701 qdf_nofl_err("ERROR: Unknown tlv\n"); 702 break; 703 } 704 h->tstamp = 705 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_1, TIMESTAMP, val1); 706 } 707 708 /** 709 * hal_rx_mpdu_start_mpdu_qos_control_valid_get_6390(): 710 * Retrieve qos control valid bit from the tlv. 711 * @buf: pointer to rx pkt TLV. 712 * 713 * Return: qos control value. 714 */ 715 static inline uint32_t 716 hal_rx_mpdu_start_mpdu_qos_control_valid_get_6390(uint8_t *buf) 717 { 718 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 719 struct rx_mpdu_start *mpdu_start = 720 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 721 722 return HAL_RX_MPDU_INFO_QOS_CONTROL_VALID_GET( 723 &mpdu_start->rx_mpdu_info_details); 724 } 725 726 /** 727 * hal_rx_msdu_end_sa_sw_peer_id_get_6390(): API to get the 728 * sa_sw_peer_id from rx_msdu_end TLV 729 * @buf: pointer to the start of RX PKT TLV headers 730 * 731 * Return: sa_sw_peer_id index 732 */ 733 static inline uint32_t 734 hal_rx_msdu_end_sa_sw_peer_id_get_6390(uint8_t *buf) 735 { 736 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 737 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 738 739 return HAL_RX_MSDU_END_SA_SW_PEER_ID_GET(msdu_end); 740 } 741 742 /** 743 * hal_tx_desc_set_mesh_en_6390 - Set mesh_enable flag in Tx descriptor 744 * @desc: Handle to Tx Descriptor 745 * @en: For raw WiFi frames, this indicates transmission to a mesh STA, 746 * enabling the interpretation of the 'Mesh Control Present' bit 747 * (bit 8) of QoS Control (otherwise this bit is ignored), 748 * For native WiFi frames, this indicates that a 'Mesh Control' field 749 * is present between the header and the LLC. 750 * 751 * Return: void 752 */ 753 static inline 754 void hal_tx_desc_set_mesh_en_6390(void *desc, uint8_t en) 755 { 756 HAL_SET_FLD(desc, TCL_DATA_CMD_4, MESH_ENABLE) |= 757 HAL_TX_SM(TCL_DATA_CMD_4, MESH_ENABLE, en); 758 } 759 760 static 761 void *hal_rx_msdu0_buffer_addr_lsb_6390(void *link_desc_va) 762 { 763 return (void *)HAL_RX_MSDU0_BUFFER_ADDR_LSB(link_desc_va); 764 } 765 766 static 767 void *hal_rx_msdu_desc_info_ptr_get_6390(void *msdu0) 768 { 769 return (void *)HAL_RX_MSDU_DESC_INFO_PTR_GET(msdu0); 770 } 771 772 static 773 void *hal_ent_mpdu_desc_info_6390(void *ent_ring_desc) 774 { 775 return (void *)HAL_ENT_MPDU_DESC_INFO(ent_ring_desc); 776 } 777 778 static 779 void *hal_dst_mpdu_desc_info_6390(void *dst_ring_desc) 780 { 781 return (void *)HAL_DST_MPDU_DESC_INFO(dst_ring_desc); 782 } 783 784 static 785 uint8_t hal_rx_get_fc_valid_6390(uint8_t *buf) 786 { 787 return HAL_RX_GET_FC_VALID(buf); 788 } 789 790 static uint8_t hal_rx_get_to_ds_flag_6390(uint8_t *buf) 791 { 792 return HAL_RX_GET_TO_DS_FLAG(buf); 793 } 794 795 static uint8_t hal_rx_get_mac_addr2_valid_6390(uint8_t *buf) 796 { 797 return HAL_RX_GET_MAC_ADDR2_VALID(buf); 798 } 799 800 static uint8_t hal_rx_get_filter_category_6390(uint8_t *buf) 801 { 802 return HAL_RX_GET_FILTER_CATEGORY(buf); 803 } 804 805 static uint32_t 806 hal_rx_get_ppdu_id_6390(uint8_t *buf) 807 { 808 return HAL_RX_GET_PPDU_ID(buf); 809 } 810 811 /** 812 * hal_reo_config_6390(): Set reo config parameters 813 * @soc: hal soc handle 814 * @reg_val: value to be set 815 * @reo_params: reo parameters 816 * 817 * Return: void 818 */ 819 static 820 void hal_reo_config_6390(struct hal_soc *soc, 821 uint32_t reg_val, 822 struct hal_reo_params *reo_params) 823 { 824 HAL_REO_R0_CONFIG(soc, reg_val, reo_params); 825 } 826 827 /** 828 * hal_rx_msdu_desc_info_get_ptr_6390() - Get msdu desc info ptr 829 * @msdu_details_ptr - Pointer to msdu_details_ptr 830 * Return - Pointer to rx_msdu_desc_info structure. 831 * 832 */ 833 static void *hal_rx_msdu_desc_info_get_ptr_6390(void *msdu_details_ptr) 834 { 835 return HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr); 836 } 837 838 /** 839 * hal_rx_link_desc_msdu0_ptr_6390 - Get pointer to rx_msdu details 840 * @link_desc - Pointer to link desc 841 * Return - Pointer to rx_msdu_details structure 842 * 843 */ 844 static void *hal_rx_link_desc_msdu0_ptr_6390(void *link_desc) 845 { 846 return HAL_RX_LINK_DESC_MSDU0_PTR(link_desc); 847 } 848 849 /** 850 * hal_rx_msdu_flow_idx_get_6390: API to get flow index 851 * from rx_msdu_end TLV 852 * @buf: pointer to the start of RX PKT TLV headers 853 * 854 * Return: flow index value from MSDU END TLV 855 */ 856 static inline uint32_t hal_rx_msdu_flow_idx_get_6390(uint8_t *buf) 857 { 858 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 859 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 860 861 return HAL_RX_MSDU_END_FLOW_IDX_GET(msdu_end); 862 } 863 864 /** 865 * hal_rx_msdu_flow_idx_invalid_6390: API to get flow index invalid 866 * from rx_msdu_end TLV 867 * @buf: pointer to the start of RX PKT TLV headers 868 * 869 * Return: flow index invalid value from MSDU END TLV 870 */ 871 static bool hal_rx_msdu_flow_idx_invalid_6390(uint8_t *buf) 872 { 873 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 874 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 875 876 return HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(msdu_end); 877 } 878 879 /** 880 * hal_rx_msdu_flow_idx_timeout_6390: API to get flow index timeout 881 * from rx_msdu_end TLV 882 * @buf: pointer to the start of RX PKT TLV headers 883 * 884 * Return: flow index timeout value from MSDU END TLV 885 */ 886 static bool hal_rx_msdu_flow_idx_timeout_6390(uint8_t *buf) 887 { 888 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 889 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 890 891 return HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(msdu_end); 892 } 893 894 /** 895 * hal_rx_msdu_fse_metadata_get_6390: API to get FSE metadata 896 * from rx_msdu_end TLV 897 * @buf: pointer to the start of RX PKT TLV headers 898 * 899 * Return: fse metadata value from MSDU END TLV 900 */ 901 static uint32_t hal_rx_msdu_fse_metadata_get_6390(uint8_t *buf) 902 { 903 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 904 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 905 906 return HAL_RX_MSDU_END_FSE_METADATA_GET(msdu_end); 907 } 908 909 /** 910 * hal_rx_msdu_cce_metadata_get_6390: API to get CCE metadata 911 * from rx_msdu_end TLV 912 * @buf: pointer to the start of RX PKT TLV headers 913 * 914 * Return: cce metadata 915 */ 916 static uint16_t 917 hal_rx_msdu_cce_metadata_get_6390(uint8_t *buf) 918 { 919 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 920 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 921 922 return HAL_RX_MSDU_END_CCE_METADATA_GET(msdu_end); 923 } 924 925 /** 926 * hal_rx_msdu_get_flow_params_6390: API to get flow index, flow index invalid 927 * and flow index timeout from rx_msdu_end TLV 928 * @buf: pointer to the start of RX PKT TLV headers 929 * @flow_invalid: pointer to return value of flow_idx_valid 930 * @flow_timeout: pointer to return value of flow_idx_timeout 931 * @flow_index: pointer to return value of flow_idx 932 * 933 * Return: none 934 */ 935 static inline void 936 hal_rx_msdu_get_flow_params_6390(uint8_t *buf, 937 bool *flow_invalid, 938 bool *flow_timeout, 939 uint32_t *flow_index) 940 { 941 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 942 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 943 944 *flow_invalid = HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(msdu_end); 945 *flow_timeout = HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(msdu_end); 946 *flow_index = HAL_RX_MSDU_END_FLOW_IDX_GET(msdu_end); 947 } 948 949 /** 950 * hal_rx_tlv_get_tcp_chksum_6390() - API to get tcp checksum 951 * @buf: rx_tlv_hdr 952 * 953 * Return: tcp checksum 954 */ 955 static uint16_t 956 hal_rx_tlv_get_tcp_chksum_6390(uint8_t *buf) 957 { 958 return HAL_RX_TLV_GET_TCP_CHKSUM(buf); 959 } 960 961 /** 962 * hal_rx_get_rx_sequence_6390(): Function to retrieve rx sequence number 963 * 964 * @nbuf: Network buffer 965 * Returns: rx sequence number 966 */ 967 static 968 uint16_t hal_rx_get_rx_sequence_6390(uint8_t *buf) 969 { 970 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 971 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 972 973 return HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info); 974 } 975 976 struct hal_hw_txrx_ops qca6390_hal_hw_txrx_ops = { 977 /* init and setup */ 978 hal_srng_dst_hw_init_generic, 979 hal_srng_src_hw_init_generic, 980 hal_get_hw_hptp_generic, 981 hal_reo_setup_generic, 982 hal_setup_link_idle_list_generic, 983 984 /* tx */ 985 hal_tx_desc_set_dscp_tid_table_id_6390, 986 hal_tx_set_dscp_tid_map_6390, 987 hal_tx_update_dscp_tid_6390, 988 hal_tx_desc_set_lmac_id_6390, 989 hal_tx_desc_set_buf_addr_generic, 990 hal_tx_desc_set_search_type_generic, 991 hal_tx_desc_set_search_index_generic, 992 hal_tx_desc_set_cache_set_num_generic, 993 hal_tx_comp_get_status_generic, 994 hal_tx_comp_get_release_reason_generic, 995 hal_tx_desc_set_mesh_en_6390, 996 /* rx */ 997 hal_rx_msdu_start_nss_get_6390, 998 hal_rx_mon_hw_desc_get_mpdu_status_6390, 999 hal_rx_get_tlv_6390, 1000 hal_rx_proc_phyrx_other_receive_info_tlv_6390, 1001 hal_rx_dump_msdu_start_tlv_6390, 1002 hal_rx_dump_msdu_end_tlv_6390, 1003 hal_get_link_desc_size_6390, 1004 hal_rx_mpdu_start_tid_get_6390, 1005 hal_rx_msdu_start_reception_type_get_6390, 1006 hal_rx_msdu_end_da_idx_get_6390, 1007 hal_rx_msdu_desc_info_get_ptr_6390, 1008 hal_rx_link_desc_msdu0_ptr_6390, 1009 hal_reo_status_get_header_6390, 1010 hal_rx_status_get_tlv_info_generic, 1011 hal_rx_wbm_err_info_get_generic, 1012 hal_rx_dump_mpdu_start_tlv_generic, 1013 1014 hal_tx_set_pcp_tid_map_generic, 1015 hal_tx_update_pcp_tid_generic, 1016 hal_tx_update_tidmap_prty_generic, 1017 hal_rx_get_rx_fragment_number_6390, 1018 hal_rx_msdu_end_da_is_mcbc_get_6390, 1019 hal_rx_msdu_end_sa_is_valid_get_6390, 1020 hal_rx_msdu_end_sa_idx_get_6390, 1021 hal_rx_desc_is_first_msdu_6390, 1022 hal_rx_msdu_end_l3_hdr_padding_get_6390, 1023 hal_rx_encryption_info_valid_6390, 1024 hal_rx_print_pn_6390, 1025 hal_rx_msdu_end_first_msdu_get_6390, 1026 hal_rx_msdu_end_da_is_valid_get_6390, 1027 hal_rx_msdu_end_last_msdu_get_6390, 1028 hal_rx_get_mpdu_mac_ad4_valid_6390, 1029 hal_rx_mpdu_start_sw_peer_id_get_6390, 1030 hal_rx_mpdu_get_to_ds_6390, 1031 hal_rx_mpdu_get_fr_ds_6390, 1032 hal_rx_get_mpdu_frame_control_valid_6390, 1033 hal_rx_mpdu_get_addr1_6390, 1034 hal_rx_mpdu_get_addr2_6390, 1035 hal_rx_mpdu_get_addr3_6390, 1036 hal_rx_mpdu_get_addr4_6390, 1037 hal_rx_get_mpdu_sequence_control_valid_6390, 1038 hal_rx_is_unicast_6390, 1039 hal_rx_tid_get_6390, 1040 hal_rx_hw_desc_get_ppduid_get_6390, 1041 hal_rx_mpdu_start_mpdu_qos_control_valid_get_6390, 1042 hal_rx_msdu_end_sa_sw_peer_id_get_6390, 1043 hal_rx_msdu0_buffer_addr_lsb_6390, 1044 hal_rx_msdu_desc_info_ptr_get_6390, 1045 hal_ent_mpdu_desc_info_6390, 1046 hal_dst_mpdu_desc_info_6390, 1047 hal_rx_get_fc_valid_6390, 1048 hal_rx_get_to_ds_flag_6390, 1049 hal_rx_get_mac_addr2_valid_6390, 1050 hal_rx_get_filter_category_6390, 1051 hal_rx_get_ppdu_id_6390, 1052 hal_reo_config_6390, 1053 hal_rx_msdu_flow_idx_get_6390, 1054 hal_rx_msdu_flow_idx_invalid_6390, 1055 hal_rx_msdu_flow_idx_timeout_6390, 1056 hal_rx_msdu_fse_metadata_get_6390, 1057 hal_rx_msdu_cce_metadata_get_6390, 1058 hal_rx_msdu_get_flow_params_6390, 1059 hal_rx_tlv_get_tcp_chksum_6390, 1060 hal_rx_get_rx_sequence_6390, 1061 }; 1062 1063 struct hal_hw_srng_config hw_srng_table_6390[] = { 1064 /* TODO: max_rings can populated by querying HW capabilities */ 1065 { /* REO_DST */ 1066 .start_ring_id = HAL_SRNG_REO2SW1, 1067 .max_rings = 4, 1068 .entry_size = sizeof(struct reo_destination_ring) >> 2, 1069 .lmac_ring = FALSE, 1070 .ring_dir = HAL_SRNG_DST_RING, 1071 .reg_start = { 1072 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR( 1073 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1074 HWIO_REO_R2_REO2SW1_RING_HP_ADDR( 1075 SEQ_WCSS_UMAC_REO_REG_OFFSET) 1076 }, 1077 .reg_size = { 1078 HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(0) - 1079 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(0), 1080 HWIO_REO_R2_REO2SW2_RING_HP_ADDR(0) - 1081 HWIO_REO_R2_REO2SW1_RING_HP_ADDR(0), 1082 }, 1083 .max_size = 1084 HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_BMSK >> 1085 HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_SHFT, 1086 }, 1087 { /* REO_EXCEPTION */ 1088 /* Designating REO2TCL ring as exception ring. This ring is 1089 * similar to other REO2SW rings though it is named as REO2TCL. 1090 * Any of theREO2SW rings can be used as exception ring. 1091 */ 1092 .start_ring_id = HAL_SRNG_REO2TCL, 1093 .max_rings = 1, 1094 .entry_size = sizeof(struct reo_destination_ring) >> 2, 1095 .lmac_ring = FALSE, 1096 .ring_dir = HAL_SRNG_DST_RING, 1097 .reg_start = { 1098 HWIO_REO_R0_REO2TCL_RING_BASE_LSB_ADDR( 1099 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1100 HWIO_REO_R2_REO2TCL_RING_HP_ADDR( 1101 SEQ_WCSS_UMAC_REO_REG_OFFSET) 1102 }, 1103 /* Single ring - provide ring size if multiple rings of this 1104 * type are supported 1105 */ 1106 .reg_size = {}, 1107 .max_size = 1108 HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_BMSK >> 1109 HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_SHFT, 1110 }, 1111 { /* REO_REINJECT */ 1112 .start_ring_id = HAL_SRNG_SW2REO, 1113 .max_rings = 1, 1114 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 1115 .lmac_ring = FALSE, 1116 .ring_dir = HAL_SRNG_SRC_RING, 1117 .reg_start = { 1118 HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR( 1119 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1120 HWIO_REO_R2_SW2REO_RING_HP_ADDR( 1121 SEQ_WCSS_UMAC_REO_REG_OFFSET) 1122 }, 1123 /* Single ring - provide ring size if multiple rings of this 1124 * type are supported 1125 */ 1126 .reg_size = {}, 1127 .max_size = HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_BMSK >> 1128 HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_SHFT, 1129 }, 1130 { /* REO_CMD */ 1131 .start_ring_id = HAL_SRNG_REO_CMD, 1132 .max_rings = 1, 1133 .entry_size = (sizeof(struct tlv_32_hdr) + 1134 sizeof(struct reo_get_queue_stats)) >> 2, 1135 .lmac_ring = FALSE, 1136 .ring_dir = HAL_SRNG_SRC_RING, 1137 .reg_start = { 1138 HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR( 1139 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1140 HWIO_REO_R2_REO_CMD_RING_HP_ADDR( 1141 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1142 }, 1143 /* Single ring - provide ring size if multiple rings of this 1144 * type are supported 1145 */ 1146 .reg_size = {}, 1147 .max_size = 1148 HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_BMSK >> 1149 HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_SHFT, 1150 }, 1151 { /* REO_STATUS */ 1152 .start_ring_id = HAL_SRNG_REO_STATUS, 1153 .max_rings = 1, 1154 .entry_size = (sizeof(struct tlv_32_hdr) + 1155 sizeof(struct reo_get_queue_stats_status)) >> 2, 1156 .lmac_ring = FALSE, 1157 .ring_dir = HAL_SRNG_DST_RING, 1158 .reg_start = { 1159 HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR( 1160 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1161 HWIO_REO_R2_REO_STATUS_RING_HP_ADDR( 1162 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1163 }, 1164 /* Single ring - provide ring size if multiple rings of this 1165 * type are supported 1166 */ 1167 .reg_size = {}, 1168 .max_size = 1169 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> 1170 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, 1171 }, 1172 { /* TCL_DATA */ 1173 .start_ring_id = HAL_SRNG_SW2TCL1, 1174 .max_rings = 3, 1175 .entry_size = (sizeof(struct tlv_32_hdr) + 1176 sizeof(struct tcl_data_cmd)) >> 2, 1177 .lmac_ring = FALSE, 1178 .ring_dir = HAL_SRNG_SRC_RING, 1179 .reg_start = { 1180 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR( 1181 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1182 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR( 1183 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1184 }, 1185 .reg_size = { 1186 HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(0) - 1187 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(0), 1188 HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(0) - 1189 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(0), 1190 }, 1191 .max_size = 1192 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK >> 1193 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT, 1194 }, 1195 { /* TCL_CMD */ 1196 .start_ring_id = HAL_SRNG_SW2TCL_CMD, 1197 .max_rings = 1, 1198 .entry_size = (sizeof(struct tlv_32_hdr) + 1199 sizeof(struct tcl_gse_cmd)) >> 2, 1200 .lmac_ring = FALSE, 1201 .ring_dir = HAL_SRNG_SRC_RING, 1202 .reg_start = { 1203 HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_ADDR( 1204 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1205 HWIO_TCL_R2_SW2TCL_CMD_RING_HP_ADDR( 1206 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1207 }, 1208 /* Single ring - provide ring size if multiple rings of this 1209 * type are supported 1210 */ 1211 .reg_size = {}, 1212 .max_size = 1213 HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RING_SIZE_BMSK >> 1214 HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RING_SIZE_SHFT, 1215 }, 1216 { /* TCL_STATUS */ 1217 .start_ring_id = HAL_SRNG_TCL_STATUS, 1218 .max_rings = 1, 1219 .entry_size = (sizeof(struct tlv_32_hdr) + 1220 sizeof(struct tcl_status_ring)) >> 2, 1221 .lmac_ring = FALSE, 1222 .ring_dir = HAL_SRNG_DST_RING, 1223 .reg_start = { 1224 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR( 1225 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1226 HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR( 1227 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1228 }, 1229 /* Single ring - provide ring size if multiple rings of this 1230 * type are supported 1231 */ 1232 .reg_size = {}, 1233 .max_size = 1234 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_BMSK >> 1235 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_SHFT, 1236 }, 1237 { /* CE_SRC */ 1238 .start_ring_id = HAL_SRNG_CE_0_SRC, 1239 .max_rings = 12, 1240 .entry_size = sizeof(struct ce_src_desc) >> 2, 1241 .lmac_ring = FALSE, 1242 .ring_dir = HAL_SRNG_SRC_RING, 1243 .reg_start = { 1244 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR( 1245 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET), 1246 HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR( 1247 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET), 1248 }, 1249 .reg_size = { 1250 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET - 1251 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET, 1252 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET - 1253 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET, 1254 }, 1255 .max_size = 1256 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >> 1257 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT, 1258 }, 1259 { /* CE_DST */ 1260 .start_ring_id = HAL_SRNG_CE_0_DST, 1261 .max_rings = 12, 1262 .entry_size = 8 >> 2, 1263 /*TODO: entry_size above should actually be 1264 * sizeof(struct ce_dst_desc) >> 2, but couldn't find definition 1265 * of struct ce_dst_desc in HW header files 1266 */ 1267 .lmac_ring = FALSE, 1268 .ring_dir = HAL_SRNG_SRC_RING, 1269 .reg_start = { 1270 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR( 1271 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 1272 HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR( 1273 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 1274 }, 1275 .reg_size = { 1276 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 1277 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 1278 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 1279 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 1280 }, 1281 .max_size = 1282 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >> 1283 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT, 1284 }, 1285 { /* CE_DST_STATUS */ 1286 .start_ring_id = HAL_SRNG_CE_0_DST_STATUS, 1287 .max_rings = 12, 1288 .entry_size = sizeof(struct ce_stat_desc) >> 2, 1289 .lmac_ring = FALSE, 1290 .ring_dir = HAL_SRNG_DST_RING, 1291 .reg_start = { 1292 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR( 1293 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 1294 HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR( 1295 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 1296 }, 1297 /* TODO: check destination status ring registers */ 1298 .reg_size = { 1299 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 1300 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 1301 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 1302 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 1303 }, 1304 .max_size = 1305 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> 1306 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, 1307 }, 1308 { /* WBM_IDLE_LINK */ 1309 .start_ring_id = HAL_SRNG_WBM_IDLE_LINK, 1310 .max_rings = 1, 1311 .entry_size = sizeof(struct wbm_link_descriptor_ring) >> 2, 1312 .lmac_ring = FALSE, 1313 .ring_dir = HAL_SRNG_SRC_RING, 1314 .reg_start = { 1315 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1316 HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1317 }, 1318 /* Single ring - provide ring size if multiple rings of this 1319 * type are supported 1320 */ 1321 .reg_size = {}, 1322 .max_size = 1323 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_BMSK >> 1324 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_SHFT, 1325 }, 1326 { /* SW2WBM_RELEASE */ 1327 .start_ring_id = HAL_SRNG_WBM_SW_RELEASE, 1328 .max_rings = 1, 1329 .entry_size = sizeof(struct wbm_release_ring) >> 2, 1330 .lmac_ring = FALSE, 1331 .ring_dir = HAL_SRNG_SRC_RING, 1332 .reg_start = { 1333 HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1334 HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1335 }, 1336 /* Single ring - provide ring size if multiple rings of this 1337 * type are supported 1338 */ 1339 .reg_size = {}, 1340 .max_size = 1341 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> 1342 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, 1343 }, 1344 { /* WBM2SW_RELEASE */ 1345 .start_ring_id = HAL_SRNG_WBM2SW0_RELEASE, 1346 .max_rings = 4, 1347 .entry_size = sizeof(struct wbm_release_ring) >> 2, 1348 .lmac_ring = FALSE, 1349 .ring_dir = HAL_SRNG_DST_RING, 1350 .reg_start = { 1351 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1352 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1353 }, 1354 .reg_size = { 1355 HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) - 1356 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1357 HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) - 1358 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1359 }, 1360 .max_size = 1361 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> 1362 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, 1363 }, 1364 { /* RXDMA_BUF */ 1365 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA0_BUF0, 1366 #ifdef IPA_OFFLOAD 1367 .max_rings = 3, 1368 #else 1369 .max_rings = 2, 1370 #endif 1371 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 1372 .lmac_ring = TRUE, 1373 .ring_dir = HAL_SRNG_SRC_RING, 1374 /* reg_start is not set because LMAC rings are not accessed 1375 * from host 1376 */ 1377 .reg_start = {}, 1378 .reg_size = {}, 1379 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1380 }, 1381 { /* RXDMA_DST */ 1382 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW0, 1383 .max_rings = 1, 1384 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 1385 .lmac_ring = TRUE, 1386 .ring_dir = HAL_SRNG_DST_RING, 1387 /* reg_start is not set because LMAC rings are not accessed 1388 * from host 1389 */ 1390 .reg_start = {}, 1391 .reg_size = {}, 1392 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1393 }, 1394 { /* RXDMA_MONITOR_BUF */ 1395 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA2_BUF, 1396 .max_rings = 1, 1397 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 1398 .lmac_ring = TRUE, 1399 .ring_dir = HAL_SRNG_SRC_RING, 1400 /* reg_start is not set because LMAC rings are not accessed 1401 * from host 1402 */ 1403 .reg_start = {}, 1404 .reg_size = {}, 1405 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1406 }, 1407 { /* RXDMA_MONITOR_STATUS */ 1408 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_STATBUF, 1409 .max_rings = 1, 1410 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 1411 .lmac_ring = TRUE, 1412 .ring_dir = HAL_SRNG_SRC_RING, 1413 /* reg_start is not set because LMAC rings are not accessed 1414 * from host 1415 */ 1416 .reg_start = {}, 1417 .reg_size = {}, 1418 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1419 }, 1420 { /* RXDMA_MONITOR_DST */ 1421 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW1, 1422 .max_rings = 1, 1423 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 1424 .lmac_ring = TRUE, 1425 .ring_dir = HAL_SRNG_DST_RING, 1426 /* reg_start is not set because LMAC rings are not accessed 1427 * from host 1428 */ 1429 .reg_start = {}, 1430 .reg_size = {}, 1431 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1432 }, 1433 { /* RXDMA_MONITOR_DESC */ 1434 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_DESC, 1435 .max_rings = 1, 1436 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 1437 .lmac_ring = TRUE, 1438 .ring_dir = HAL_SRNG_SRC_RING, 1439 /* reg_start is not set because LMAC rings are not accessed 1440 * from host 1441 */ 1442 .reg_start = {}, 1443 .reg_size = {}, 1444 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1445 }, 1446 { /* DIR_BUF_RX_DMA_SRC */ 1447 .start_ring_id = HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING, 1448 .max_rings = 1, 1449 .entry_size = 2, 1450 .lmac_ring = TRUE, 1451 .ring_dir = HAL_SRNG_SRC_RING, 1452 /* reg_start is not set because LMAC rings are not accessed 1453 * from host 1454 */ 1455 .reg_start = {}, 1456 .reg_size = {}, 1457 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1458 }, 1459 #ifdef WLAN_FEATURE_CIF_CFR 1460 { /* WIFI_POS_SRC */ 1461 .start_ring_id = HAL_SRNG_WIFI_POS_SRC_DMA_RING, 1462 .max_rings = 1, 1463 .entry_size = sizeof(wmi_oem_dma_buf_release_entry) >> 2, 1464 .lmac_ring = TRUE, 1465 .ring_dir = HAL_SRNG_SRC_RING, 1466 /* reg_start is not set because LMAC rings are not accessed 1467 * from host 1468 */ 1469 .reg_start = {}, 1470 .reg_size = {}, 1471 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1472 }, 1473 #endif 1474 }; 1475 1476 int32_t hal_hw_reg_offset_qca6390[] = { 1477 /* dst */ 1478 REG_OFFSET(DST, HP), 1479 REG_OFFSET(DST, TP), 1480 REG_OFFSET(DST, ID), 1481 REG_OFFSET(DST, MISC), 1482 REG_OFFSET(DST, HP_ADDR_LSB), 1483 REG_OFFSET(DST, HP_ADDR_MSB), 1484 REG_OFFSET(DST, MSI1_BASE_LSB), 1485 REG_OFFSET(DST, MSI1_BASE_MSB), 1486 REG_OFFSET(DST, MSI1_DATA), 1487 REG_OFFSET(DST, BASE_LSB), 1488 REG_OFFSET(DST, BASE_MSB), 1489 REG_OFFSET(DST, PRODUCER_INT_SETUP), 1490 /* src */ 1491 REG_OFFSET(SRC, HP), 1492 REG_OFFSET(SRC, TP), 1493 REG_OFFSET(SRC, ID), 1494 REG_OFFSET(SRC, MISC), 1495 REG_OFFSET(SRC, TP_ADDR_LSB), 1496 REG_OFFSET(SRC, TP_ADDR_MSB), 1497 REG_OFFSET(SRC, MSI1_BASE_LSB), 1498 REG_OFFSET(SRC, MSI1_BASE_MSB), 1499 REG_OFFSET(SRC, MSI1_DATA), 1500 REG_OFFSET(SRC, BASE_LSB), 1501 REG_OFFSET(SRC, BASE_MSB), 1502 REG_OFFSET(SRC, CONSUMER_INT_SETUP_IX0), 1503 REG_OFFSET(SRC, CONSUMER_INT_SETUP_IX1), 1504 }; 1505 1506 /** 1507 * hal_qca6390_attach() - Attach 6390 target specific hal_soc ops, 1508 * offset and srng table 1509 */ 1510 void hal_qca6390_attach(struct hal_soc *hal_soc) 1511 { 1512 hal_soc->hw_srng_table = hw_srng_table_6390; 1513 hal_soc->hal_hw_reg_offset = hal_hw_reg_offset_qca6390; 1514 hal_soc->ops = &qca6390_hal_hw_txrx_ops; 1515 } 1516