xref: /wlan-dirver/qca-wifi-host-cmn/hal/wifi3.0/qca6290/hal_6290_tx.h (revision 1b9674e21e24478fba4530f5ae7396b9555e9c6a)
1 /*
2  * Copyright (c) 2018 The Linux Foundation. All rights reserved.
3  *
4  * Redistribution and use in source and binary forms, with or without
5  * modification, are permitted provided that the following conditions are
6  * met:
7  *     * Redistributions of source code must retain the above copyright
8  *       notice, this list of conditions and the following disclaimer.
9  *     * Redistributions in binary form must reproduce the above
10  *       copyright notice, this list of conditions and the following
11  *       disclaimer in the documentation and/or other materials provided
12  *       with the distribution.
13  *     * Neither the name of The Linux Foundation nor the names of its
14  *       contributors may be used to endorse or promote products derived
15  *       from this software without specific prior written permission.
16  *
17  * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
18  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
19  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
20  * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
21  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
22  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
24  * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
25  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
26  * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
27  * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28  */
29 
30 #include "tcl_data_cmd.h"
31 #include "mac_tcl_reg_seq_hwioreg.h"
32 #include "phyrx_rssi_legacy.h"
33 #include "hal_hw_headers.h"
34 #include "hal_internal.h"
35 #include "cdp_txrx_mon_struct.h"
36 #include "qdf_trace.h"
37 #include "hal_rx.h"
38 #include "hal_tx.h"
39 #include "dp_types.h"
40 #include "hal_api_mon.h"
41 
42 /**
43  * hal_tx_desc_set_dscp_tid_table_id_6290() - Sets DSCP to TID conversion
44  *						table ID
45  * @desc: Handle to Tx Descriptor
46  * @id: DSCP to tid conversion table to be used for this frame
47  *
48  * Return: void
49  */
50 #if defined(QCA_WIFI_QCA6290_11AX)
51 static void hal_tx_desc_set_dscp_tid_table_id_6290(void *desc,
52 						   uint8_t id)
53 {
54 	HAL_SET_FLD(desc, TCL_DATA_CMD_5,
55 		    DSCP_TID_TABLE_NUM) |=
56 	HAL_TX_SM(TCL_DATA_CMD_5,
57 		  DSCP_TID_TABLE_NUM, id);
58 }
59 #else
60 #ifdef CONFIG_MCL
61 static void hal_tx_desc_set_dscp_tid_table_id_6290(void *desc,
62 						   uint8_t id)
63 {
64 	HAL_SET_FLD(desc, TCL_DATA_CMD_3,
65 		    DSCP_TO_TID_PRIORITY_TABLE_ID) |=
66 			HAL_TX_SM(TCL_DATA_CMD_3,
67 				  DSCP_TO_TID_PRIORITY_TABLE_ID, id);
68 }
69 #endif
70 #endif
71 
72 
73 #define DSCP_TID_TABLE_SIZE 24
74 #define NUM_WORDS_PER_DSCP_TID_TABLE (DSCP_TID_TABLE_SIZE / 4)
75 
76 #if defined(QCA_WIFI_QCA6290_11AX)
77 /**
78  * hal_tx_set_dscp_tid_map_6290() - Configure default DSCP to TID map table
79  * @soc: HAL SoC context
80  * @map: DSCP-TID mapping table
81  * @id: mapping table ID - 0-31
82  *
83  * DSCP are mapped to 8 TID values using TID values programmed
84  * in any of the 32 DSCP_TID_MAPS (id = 0-31).
85  *
86  * Return: none
87  */
88 static void hal_tx_set_dscp_tid_map_6290(void *hal_soc, uint8_t *map,
89 					 uint8_t id)
90 {
91 	int i;
92 	uint32_t addr, cmn_reg_addr;
93 	uint32_t value = 0, regval;
94 	uint8_t val[DSCP_TID_TABLE_SIZE], cnt = 0;
95 
96 	struct hal_soc *soc = (struct hal_soc *)hal_soc;
97 
98 	if (id >= HAL_MAX_HW_DSCP_TID_MAPS_11AX)
99 		return;
100 
101 	cmn_reg_addr = HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(
102 					SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET);
103 
104 	addr = HWIO_TCL_R0_DSCP_TID_MAP_n_ADDR(
105 				SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET,
106 				id * NUM_WORDS_PER_DSCP_TID_TABLE);
107 
108 	/* Enable read/write access */
109 	regval = HAL_REG_READ(soc, cmn_reg_addr);
110 	regval |=
111 	(1 << HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_DSCP_TID_MAP_PROGRAM_EN_SHFT);
112 
113 	HAL_REG_WRITE(soc, cmn_reg_addr, regval);
114 
115 	/* Write 8 (24 bits) DSCP-TID mappings in each interation */
116 	for (i = 0; i < 64; i += 8) {
117 		value = (map[i] |
118 			(map[i + 1] << 0x3) |
119 			(map[i + 2] << 0x6) |
120 			(map[i + 3] << 0x9) |
121 			(map[i + 4] << 0xc) |
122 			(map[i + 5] << 0xf) |
123 			(map[i + 6] << 0x12) |
124 			(map[i + 7] << 0x15));
125 
126 		qdf_mem_copy(&val[cnt], (void *)&value, 3);
127 		cnt += 3;
128 	}
129 
130 	for (i = 0; i < DSCP_TID_TABLE_SIZE; i += 4) {
131 		regval = *(uint32_t *)(val + i);
132 		HAL_REG_WRITE(soc, addr,
133 			      (regval & HWIO_TCL_R0_DSCP_TID_MAP_n_RMSK));
134 		addr += 4;
135 	}
136 
137 	/* Diasble read/write access */
138 	regval = HAL_REG_READ(soc, cmn_reg_addr);
139 	regval &=
140 	~(HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_DSCP_TID_MAP_PROGRAM_EN_BMSK);
141 
142 	HAL_REG_WRITE(soc, cmn_reg_addr, regval);
143 }
144 #else
145 static void hal_tx_set_dscp_tid_map_6290(void *hal_soc, uint8_t *map,
146 					 uint8_t id)
147 {
148 	int i;
149 	uint32_t addr;
150 	uint32_t value;
151 
152 	struct hal_soc *soc = (struct hal_soc *)hal_soc;
153 
154 	if (id == HAL_TX_DSCP_TID_MAP_TABLE_DEFAULT) {
155 		addr =
156 			HWIO_TCL_R0_DSCP_TID1_MAP_0_ADDR(
157 					SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET);
158 	} else {
159 		addr =
160 			HWIO_TCL_R0_DSCP_TID2_MAP_0_ADDR(
161 					SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET);
162 	}
163 
164 	for (i = 0; i < 64; i += 10) {
165 		value = (map[i] |
166 			(map[i+1] << HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_1_SHFT) |
167 			(map[i+2] << HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_2_SHFT) |
168 			(map[i+3] << HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_3_SHFT) |
169 			(map[i+4] << HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_4_SHFT) |
170 			(map[i+5] << HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_5_SHFT) |
171 			(map[i+6] << HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_6_SHFT) |
172 			(map[i+7] << HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_7_SHFT) |
173 			(map[i+8] << HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_8_SHFT) |
174 			(map[i+9] << HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_9_SHFT));
175 
176 		HAL_REG_WRITE(soc, addr,
177 				(value & HWIO_TCL_R0_DSCP_TID1_MAP_1_RMSK));
178 
179 		addr += 4;
180 	}
181 }
182 #endif
183 
184 #ifdef QCA_WIFI_QCA6290_11AX
185 /**
186  * hal_tx_update_dscp_tid_6290() - Update the dscp tid map table as updated
187  *					by the user
188  * @soc: HAL SoC context
189  * @map: DSCP-TID mapping table
190  * @id : MAP ID
191  * @dscp: DSCP_TID map index
192  *
193  * Return: void
194  */
195 static void hal_tx_update_dscp_tid_6290(void *hal_soc, uint8_t tid,
196 					uint8_t id, uint8_t dscp)
197 {
198 	int index;
199 	uint32_t addr;
200 	uint32_t value;
201 	uint32_t regval;
202 	struct hal_soc *soc = (struct hal_soc *)hal_soc;
203 
204 	addr = HWIO_TCL_R0_DSCP_TID_MAP_n_ADDR(
205 			SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET, id);
206 
207 	index = dscp % HAL_TX_NUM_DSCP_PER_REGISTER;
208 	addr += 4 * (dscp / HAL_TX_NUM_DSCP_PER_REGISTER);
209 	value = tid << (HAL_TX_BITS_PER_TID * index);
210 
211 	regval = HAL_REG_READ(soc, addr);
212 	regval &= ~(HAL_TX_TID_BITS_MASK << (HAL_TX_BITS_PER_TID * index));
213 	regval |= value;
214 
215 	HAL_REG_WRITE(soc, addr, (regval & HWIO_TCL_R0_DSCP_TID_MAP_n_RMSK));
216 }
217 #else
218 static void hal_tx_update_dscp_tid_6290(void *hal_soc, uint8_t tid,
219 					uint8_t id, uint8_t dscp)
220 {
221 	int index;
222 	uint32_t addr;
223 	uint32_t value;
224 	uint32_t regval;
225 
226 	struct hal_soc *soc = (struct hal_soc *)hal_soc;
227 
228 	if (id == HAL_TX_DSCP_TID_MAP_TABLE_DEFAULT)
229 		addr =
230 			HWIO_TCL_R0_DSCP_TID1_MAP_0_ADDR(
231 					SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET);
232 	else
233 		addr =
234 			HWIO_TCL_R0_DSCP_TID2_MAP_0_ADDR(
235 					SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET);
236 
237 	index = dscp % HAL_TX_NUM_DSCP_PER_REGISTER;
238 	addr += 4 * (dscp/HAL_TX_NUM_DSCP_PER_REGISTER);
239 	value = tid << (HAL_TX_BITS_PER_TID * index);
240 
241 	/* Read back previous DSCP TID config and update
242 	 * with new config.
243 	 */
244 	regval = HAL_REG_READ(soc, addr);
245 	regval &= ~(HAL_TX_TID_BITS_MASK << (HAL_TX_BITS_PER_TID * index));
246 	regval |= value;
247 
248 	HAL_REG_WRITE(soc, addr,
249 			(regval & HWIO_TCL_R0_DSCP_TID1_MAP_1_RMSK));
250 }
251 #endif
252 
253 #ifdef QCA_WIFI_QCA6290_11AX
254 /**
255  * hal_tx_desc_set_lmac_id - Set the lmac_id value
256  * @desc: Handle to Tx Descriptor
257  * @lmac_id: mac Id to ast matching
258  *		     b00 – mac 0
259  *		     b01 – mac 1
260  *		     b10 – mac 2
261  *		     b11 – all macs (legacy HK way)
262  *
263  * Return: void
264  */
265 static void hal_tx_desc_set_lmac_id_6290(void *desc, uint8_t lmac_id)
266 {
267 	HAL_SET_FLD(desc, TCL_DATA_CMD_4, LMAC_ID) |=
268 		HAL_TX_SM(TCL_DATA_CMD_4, LMAC_ID, lmac_id);
269 }
270 #else
271 static void hal_tx_desc_set_lmac_id_6290(void *desc, uint8_t lmac_id)
272 {
273 }
274 #endif
275