1 /* 2 * Copyright (c) 2016-2020 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 #include "qdf_util.h" 19 #include "qdf_types.h" 20 #include "qdf_lock.h" 21 #include "qdf_mem.h" 22 #include "qdf_nbuf.h" 23 #include "tcl_data_cmd.h" 24 #include "mac_tcl_reg_seq_hwioreg.h" 25 #include "phyrx_rssi_legacy.h" 26 #include "rx_msdu_start.h" 27 #include "tlv_tag_def.h" 28 #include "hal_hw_headers.h" 29 #include "hal_internal.h" 30 #include "cdp_txrx_mon_struct.h" 31 #include "qdf_trace.h" 32 #include "hal_rx.h" 33 #include "hal_tx.h" 34 #include "dp_types.h" 35 #include "hal_api_mon.h" 36 #include "phyrx_other_receive_info_ru_details.h" 37 38 #define HAL_RX_MPDU_GET_SEQUENCE_NUMBER(_rx_mpdu_info) \ 39 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 40 RX_MPDU_INFO_2_MPDU_SEQUENCE_NUMBER_OFFSET)), \ 41 RX_MPDU_INFO_2_MPDU_SEQUENCE_NUMBER_MASK, \ 42 RX_MPDU_INFO_2_MPDU_SEQUENCE_NUMBER_LSB)) 43 44 #define HAL_RX_MSDU_END_DA_IS_MCBC_GET(_rx_msdu_end) \ 45 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 46 RX_MSDU_END_5_DA_IS_MCBC_OFFSET)), \ 47 RX_MSDU_END_5_DA_IS_MCBC_MASK, \ 48 RX_MSDU_END_5_DA_IS_MCBC_LSB)) 49 50 #define HAL_RX_MSDU_END_SA_IS_VALID_GET(_rx_msdu_end) \ 51 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 52 RX_MSDU_END_5_SA_IS_VALID_OFFSET)), \ 53 RX_MSDU_END_5_SA_IS_VALID_MASK, \ 54 RX_MSDU_END_5_SA_IS_VALID_LSB)) 55 56 #define HAL_RX_MSDU_END_SA_IDX_GET(_rx_msdu_end) \ 57 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 58 RX_MSDU_END_13_SA_IDX_OFFSET)), \ 59 RX_MSDU_END_13_SA_IDX_MASK, \ 60 RX_MSDU_END_13_SA_IDX_LSB)) 61 62 #define HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(_rx_msdu_end) \ 63 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 64 RX_MSDU_END_5_L3_HEADER_PADDING_OFFSET)), \ 65 RX_MSDU_END_5_L3_HEADER_PADDING_MASK, \ 66 RX_MSDU_END_5_L3_HEADER_PADDING_LSB)) 67 68 #define HAL_RX_MPDU_ENCRYPTION_INFO_VALID(_rx_mpdu_info) \ 69 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 70 RX_MPDU_INFO_2_FRAME_ENCRYPTION_INFO_VALID_OFFSET)), \ 71 RX_MPDU_INFO_2_FRAME_ENCRYPTION_INFO_VALID_MASK, \ 72 RX_MPDU_INFO_2_FRAME_ENCRYPTION_INFO_VALID_LSB)) 73 74 #define HAL_RX_MPDU_PN_31_0_GET(_rx_mpdu_info) \ 75 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 76 RX_MPDU_INFO_4_PN_31_0_OFFSET)), \ 77 RX_MPDU_INFO_4_PN_31_0_MASK, \ 78 RX_MPDU_INFO_4_PN_31_0_LSB)) 79 80 #define HAL_RX_MPDU_PN_63_32_GET(_rx_mpdu_info) \ 81 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 82 RX_MPDU_INFO_5_PN_63_32_OFFSET)), \ 83 RX_MPDU_INFO_5_PN_63_32_MASK, \ 84 RX_MPDU_INFO_5_PN_63_32_LSB)) 85 86 #define HAL_RX_MPDU_PN_95_64_GET(_rx_mpdu_info) \ 87 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 88 RX_MPDU_INFO_6_PN_95_64_OFFSET)), \ 89 RX_MPDU_INFO_6_PN_95_64_MASK, \ 90 RX_MPDU_INFO_6_PN_95_64_LSB)) 91 92 #define HAL_RX_MPDU_PN_127_96_GET(_rx_mpdu_info) \ 93 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 94 RX_MPDU_INFO_7_PN_127_96_OFFSET)), \ 95 RX_MPDU_INFO_7_PN_127_96_MASK, \ 96 RX_MPDU_INFO_7_PN_127_96_LSB)) 97 98 #define HAL_RX_MSDU_END_FIRST_MSDU_GET(_rx_msdu_end) \ 99 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 100 RX_MSDU_END_5_FIRST_MSDU_OFFSET)), \ 101 RX_MSDU_END_5_FIRST_MSDU_MASK, \ 102 RX_MSDU_END_5_FIRST_MSDU_LSB)) 103 104 #define HAL_RX_MSDU_END_DA_IS_VALID_GET(_rx_msdu_end) \ 105 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 106 RX_MSDU_END_5_DA_IS_VALID_OFFSET)), \ 107 RX_MSDU_END_5_DA_IS_VALID_MASK, \ 108 RX_MSDU_END_5_DA_IS_VALID_LSB)) 109 110 #define HAL_RX_MSDU_END_LAST_MSDU_GET(_rx_msdu_end) \ 111 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 112 RX_MSDU_END_5_LAST_MSDU_OFFSET)), \ 113 RX_MSDU_END_5_LAST_MSDU_MASK, \ 114 RX_MSDU_END_5_LAST_MSDU_LSB)) 115 116 #define HAL_RX_MPDU_GET_MAC_AD4_VALID(_rx_mpdu_info) \ 117 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 118 RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_OFFSET)), \ 119 RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_MASK, \ 120 RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_LSB)) 121 122 #define HAL_RX_MPDU_INFO_SW_PEER_ID_GET(_rx_mpdu_info) \ 123 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_info), \ 124 RX_MPDU_INFO_1_SW_PEER_ID_OFFSET)), \ 125 RX_MPDU_INFO_1_SW_PEER_ID_MASK, \ 126 RX_MPDU_INFO_1_SW_PEER_ID_LSB)) 127 128 #define HAL_RX_MPDU_GET_TODS(_rx_mpdu_info) \ 129 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 130 RX_MPDU_INFO_2_TO_DS_OFFSET)), \ 131 RX_MPDU_INFO_2_TO_DS_MASK, \ 132 RX_MPDU_INFO_2_TO_DS_LSB)) 133 134 #define HAL_RX_MPDU_GET_FROMDS(_rx_mpdu_info) \ 135 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 136 RX_MPDU_INFO_2_FR_DS_OFFSET)), \ 137 RX_MPDU_INFO_2_FR_DS_MASK, \ 138 RX_MPDU_INFO_2_FR_DS_LSB)) 139 140 #define HAL_RX_MPDU_GET_FRAME_CONTROL_VALID(_rx_mpdu_info) \ 141 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 142 RX_MPDU_INFO_2_MPDU_FRAME_CONTROL_VALID_OFFSET)), \ 143 RX_MPDU_INFO_2_MPDU_FRAME_CONTROL_VALID_MASK, \ 144 RX_MPDU_INFO_2_MPDU_FRAME_CONTROL_VALID_LSB)) 145 146 #define HAL_RX_MPDU_MAC_ADDR_AD1_VALID_GET(_rx_mpdu_info) \ 147 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 148 RX_MPDU_INFO_2_MAC_ADDR_AD1_VALID_OFFSET)), \ 149 RX_MPDU_INFO_2_MAC_ADDR_AD1_VALID_MASK, \ 150 RX_MPDU_INFO_2_MAC_ADDR_AD1_VALID_LSB)) 151 152 #define HAL_RX_MPDU_AD1_31_0_GET(_rx_mpdu_info) \ 153 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 154 RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_OFFSET)), \ 155 RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_MASK, \ 156 RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_LSB)) 157 158 #define HAL_RX_MPDU_AD1_47_32_GET(_rx_mpdu_info) \ 159 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 160 RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_OFFSET)), \ 161 RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_MASK, \ 162 RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_LSB)) 163 164 #define HAL_RX_MPDU_MAC_ADDR_AD2_VALID_GET(_rx_mpdu_info) \ 165 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 166 RX_MPDU_INFO_2_MAC_ADDR_AD2_VALID_OFFSET)), \ 167 RX_MPDU_INFO_2_MAC_ADDR_AD2_VALID_MASK, \ 168 RX_MPDU_INFO_2_MAC_ADDR_AD2_VALID_LSB)) 169 170 #define HAL_RX_MPDU_AD2_15_0_GET(_rx_mpdu_info) \ 171 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 172 RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_OFFSET)), \ 173 RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_MASK, \ 174 RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_LSB)) 175 176 #define HAL_RX_MPDU_AD2_47_16_GET(_rx_mpdu_info) \ 177 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 178 RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_OFFSET)), \ 179 RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_MASK, \ 180 RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_LSB)) 181 182 #define HAL_RX_MPDU_MAC_ADDR_AD3_VALID_GET(_rx_mpdu_info) \ 183 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 184 RX_MPDU_INFO_2_MAC_ADDR_AD3_VALID_OFFSET)), \ 185 RX_MPDU_INFO_2_MAC_ADDR_AD3_VALID_MASK, \ 186 RX_MPDU_INFO_2_MAC_ADDR_AD3_VALID_LSB)) 187 188 #define HAL_RX_MPDU_AD3_31_0_GET(_rx_mpdu_info) \ 189 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 190 RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_OFFSET)), \ 191 RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_MASK, \ 192 RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_LSB)) 193 194 #define HAL_RX_MPDU_AD3_47_32_GET(_rx_mpdu_info) \ 195 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 196 RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_OFFSET)), \ 197 RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_MASK, \ 198 RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_LSB)) 199 200 #define HAL_RX_MPDU_MAC_ADDR_AD4_VALID_GET(_rx_mpdu_info) \ 201 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 202 RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_OFFSET)), \ 203 RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_MASK, \ 204 RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_LSB)) 205 206 #define HAL_RX_MPDU_AD4_31_0_GET(_rx_mpdu_info) \ 207 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 208 RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_OFFSET)), \ 209 RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_MASK, \ 210 RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_LSB)) 211 212 #define HAL_RX_MPDU_AD4_47_32_GET(_rx_mpdu_info) \ 213 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 214 RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_OFFSET)), \ 215 RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_MASK, \ 216 RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_LSB)) 217 218 #define HAL_RX_MPDU_GET_SEQUENCE_CONTROL_VALID(_rx_mpdu_info) \ 219 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 220 RX_MPDU_INFO_2_MPDU_SEQUENCE_CONTROL_VALID_OFFSET)), \ 221 RX_MPDU_INFO_2_MPDU_SEQUENCE_CONTROL_VALID_MASK, \ 222 RX_MPDU_INFO_2_MPDU_SEQUENCE_CONTROL_VALID_LSB)) 223 224 #define HAL_RX_MPDU_INFO_QOS_CONTROL_VALID_GET(_rx_mpdu_info) \ 225 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_info), \ 226 RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_OFFSET)), \ 227 RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_MASK, \ 228 RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_LSB)) 229 230 #define HAL_RX_MSDU_END_SA_SW_PEER_ID_GET(_rx_msdu_end) \ 231 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 232 RX_MSDU_END_16_SA_SW_PEER_ID_OFFSET)), \ 233 RX_MSDU_END_16_SA_SW_PEER_ID_MASK, \ 234 RX_MSDU_END_16_SA_SW_PEER_ID_LSB)) 235 236 #define HAL_RX_MSDU0_BUFFER_ADDR_LSB(link_desc_va) \ 237 (uint8_t *)(link_desc_va) + \ 238 RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET 239 240 #define HAL_RX_MSDU_DESC_INFO_PTR_GET(msdu0) \ 241 (uint8_t *)(msdu0) + \ 242 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET 243 244 #define HAL_ENT_MPDU_DESC_INFO(ent_ring_desc) \ 245 (uint8_t *)(ent_ring_desc) + \ 246 RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET 247 248 #define HAL_DST_MPDU_DESC_INFO(dst_ring_desc) \ 249 (uint8_t *)(dst_ring_desc) + \ 250 REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET 251 252 #define HAL_RX_GET_FC_VALID(rx_mpdu_start) \ 253 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_2, MPDU_FRAME_CONTROL_VALID) 254 255 #define HAL_RX_GET_TO_DS_FLAG(rx_mpdu_start) \ 256 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_2, TO_DS) 257 258 #define HAL_RX_GET_MAC_ADDR1_VALID(rx_mpdu_start) \ 259 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_2, MAC_ADDR_AD1_VALID) 260 261 #define HAL_RX_GET_MAC_ADDR2_VALID(rx_mpdu_start) \ 262 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_2, MAC_ADDR_AD2_VALID) 263 264 #define HAL_RX_GET_FILTER_CATEGORY(rx_mpdu_start) \ 265 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_0, RXPCU_MPDU_FILTER_IN_CATEGORY) 266 267 #define HAL_RX_GET_PPDU_ID(rx_mpdu_start) \ 268 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_0, PHY_PPDU_ID) 269 270 #define HAL_RX_GET_SW_FRAME_GROUP_ID(rx_mpdu_start) \ 271 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_0, SW_FRAME_GROUP_ID) 272 273 #define HAL_REO_R0_CONFIG(soc, reg_val, reo_params) \ 274 do { \ 275 (reg_val) &= \ 276 ~(HWIO_REO_R0_GENERAL_ENABLE_FRAGMENT_DEST_RING_BMSK |\ 277 HWIO_REO_R0_GENERAL_ENABLE_AGING_LIST_ENABLE_BMSK |\ 278 HWIO_REO_R0_GENERAL_ENABLE_AGING_FLUSH_ENABLE_BMSK);\ 279 (reg_val) |= \ 280 HAL_SM(HWIO_REO_R0_GENERAL_ENABLE, \ 281 FRAGMENT_DEST_RING, \ 282 (reo_params)->frag_dst_ring) | \ 283 HAL_SM(HWIO_REO_R0_GENERAL_ENABLE, \ 284 AGING_LIST_ENABLE, 1) |\ 285 HAL_SM(HWIO_REO_R0_GENERAL_ENABLE, \ 286 AGING_FLUSH_ENABLE, 1);\ 287 HAL_REG_WRITE((soc), \ 288 HWIO_REO_R0_GENERAL_ENABLE_ADDR( \ 289 SEQ_WCSS_UMAC_REO_REG_OFFSET), \ 290 (reg_val)); \ 291 } while (0) 292 293 #define HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr) \ 294 ((struct rx_msdu_desc_info *) \ 295 _OFFSET_TO_BYTE_PTR(msdu_details_ptr, \ 296 UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET)) 297 298 #define HAL_RX_LINK_DESC_MSDU0_PTR(link_desc) \ 299 ((struct rx_msdu_details *) \ 300 _OFFSET_TO_BYTE_PTR((link_desc),\ 301 UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET)) 302 303 #define HAL_RX_MSDU_END_FLOW_IDX_GET(_rx_msdu_end) \ 304 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 305 RX_MSDU_END_14_FLOW_IDX_OFFSET)), \ 306 RX_MSDU_END_14_FLOW_IDX_MASK, \ 307 RX_MSDU_END_14_FLOW_IDX_LSB)) 308 309 #define HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(_rx_msdu_end) \ 310 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 311 RX_MSDU_END_5_FLOW_IDX_INVALID_OFFSET)), \ 312 RX_MSDU_END_5_FLOW_IDX_INVALID_MASK, \ 313 RX_MSDU_END_5_FLOW_IDX_INVALID_LSB)) 314 315 #define HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(_rx_msdu_end) \ 316 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 317 RX_MSDU_END_5_FLOW_IDX_TIMEOUT_OFFSET)), \ 318 RX_MSDU_END_5_FLOW_IDX_TIMEOUT_MASK, \ 319 RX_MSDU_END_5_FLOW_IDX_TIMEOUT_LSB)) 320 321 #define HAL_RX_MSDU_END_FSE_METADATA_GET(_rx_msdu_end) \ 322 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 323 RX_MSDU_END_15_FSE_METADATA_OFFSET)), \ 324 RX_MSDU_END_15_FSE_METADATA_MASK, \ 325 RX_MSDU_END_15_FSE_METADATA_LSB)) 326 327 #define HAL_RX_MSDU_END_CCE_METADATA_GET(_rx_msdu_end) \ 328 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 329 RX_MSDU_END_16_CCE_METADATA_OFFSET)), \ 330 RX_MSDU_END_16_CCE_METADATA_MASK, \ 331 RX_MSDU_END_16_CCE_METADATA_LSB)) 332 333 #define HAL_RX_TLV_GET_TCP_CHKSUM(buf) \ 334 (_HAL_MS( \ 335 (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ 336 msdu_end_tlv.rx_msdu_end), \ 337 RX_MSDU_END_1_TCP_UDP_CHKSUM_OFFSET)), \ 338 RX_MSDU_END_1_TCP_UDP_CHKSUM_MASK, \ 339 RX_MSDU_END_1_TCP_UDP_CHKSUM_LSB)) 340 341 #if defined(QCA_WIFI_QCA6290_11AX) 342 #define HAL_RX_MSDU_START_MIMO_SS_BITMAP(_rx_msdu_start)\ 343 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start),\ 344 RX_MSDU_START_5_MIMO_SS_BITMAP_OFFSET)), \ 345 RX_MSDU_START_5_MIMO_SS_BITMAP_MASK, \ 346 RX_MSDU_START_5_MIMO_SS_BITMAP_LSB)) 347 348 /* 349 * hal_rx_msdu_start_nss_get_6290(): API to get the NSS 350 * Interval from rx_msdu_start 351 * 352 * @buf: pointer to the start of RX PKT TLV header 353 * Return: uint32_t(nss) 354 */ 355 static uint32_t 356 hal_rx_msdu_start_nss_get_6290(uint8_t *buf) 357 { 358 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 359 struct rx_msdu_start *msdu_start = 360 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 361 uint8_t mimo_ss_bitmap; 362 363 mimo_ss_bitmap = HAL_RX_MSDU_START_MIMO_SS_BITMAP(msdu_start); 364 365 return qdf_get_hweight8(mimo_ss_bitmap); 366 } 367 #else 368 static uint32_t 369 hal_rx_msdu_start_nss_get_6290(uint8_t *buf) 370 { 371 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 372 struct rx_msdu_start *msdu_start = 373 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 374 uint32_t nss; 375 376 nss = HAL_RX_MSDU_START_NSS_GET(msdu_start); 377 return nss; 378 } 379 #endif 380 381 /** 382 * hal_rx_mon_hw_desc_get_mpdu_status_6290(): Retrieve MPDU status 383 * 384 * @ hw_desc_addr: Start address of Rx HW TLVs 385 * @ rs: Status for monitor mode 386 * 387 * Return: void 388 */ 389 static void hal_rx_mon_hw_desc_get_mpdu_status_6290(void *hw_desc_addr, 390 struct mon_rx_status *rs) 391 { 392 struct rx_msdu_start *rx_msdu_start; 393 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr; 394 uint32_t reg_value; 395 const uint32_t sgi_hw_to_cdp[] = { 396 CDP_SGI_0_8_US, 397 CDP_SGI_0_4_US, 398 CDP_SGI_1_6_US, 399 CDP_SGI_3_2_US, 400 }; 401 402 rx_msdu_start = &rx_desc->msdu_start_tlv.rx_msdu_start; 403 404 HAL_RX_GET_MSDU_AGGREGATION(rx_desc, rs); 405 406 rs->ant_signal_db = HAL_RX_GET(rx_msdu_start, 407 RX_MSDU_START_5, USER_RSSI); 408 rs->is_stbc = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, STBC); 409 410 reg_value = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, SGI); 411 rs->sgi = sgi_hw_to_cdp[reg_value]; 412 #if !defined(QCA_WIFI_QCA6290_11AX) 413 rs->nr_ant = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, NSS); 414 #endif 415 reg_value = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, RECEPTION_TYPE); 416 rs->beamformed = (reg_value == HAL_RX_RECEPTION_TYPE_MU_MIMO) ? 1 : 0; 417 /* TODO: rs->beamformed should be set for SU beamforming also */ 418 } 419 420 #define LINK_DESC_SIZE (NUM_OF_DWORDS_RX_MSDU_LINK << 2) 421 422 static uint32_t hal_get_link_desc_size_6290(void) 423 { 424 return LINK_DESC_SIZE; 425 } 426 427 428 #ifdef QCA_WIFI_QCA6290_11AX 429 /* 430 * hal_rx_get_tlv_6290(): API to get the tlv 431 * 432 * @rx_tlv: TLV data extracted from the rx packet 433 * Return: uint8_t 434 */ 435 static uint8_t hal_rx_get_tlv_6290(void *rx_tlv) 436 { 437 return HAL_RX_GET(rx_tlv, PHYRX_RSSI_LEGACY_0, RECEIVE_BANDWIDTH); 438 } 439 #else 440 static uint8_t hal_rx_get_tlv_6290(void *rx_tlv) 441 { 442 return HAL_RX_GET(rx_tlv, PHYRX_RSSI_LEGACY_35, RECEIVE_BANDWIDTH); 443 } 444 #endif 445 446 #ifdef QCA_WIFI_QCA6290_11AX 447 /** 448 * hal_rx_proc_phyrx_other_receive_info_tlv_6290() 449 * - process other receive info TLV 450 * @rx_tlv_hdr: pointer to TLV header 451 * @ppdu_info: pointer to ppdu_info 452 * 453 * Return: None 454 */ 455 static 456 void hal_rx_proc_phyrx_other_receive_info_tlv_6290(void *rx_tlv_hdr, 457 void *ppdu_info_handle) 458 { 459 uint32_t tlv_tag, tlv_len; 460 uint32_t temp_len, other_tlv_len, other_tlv_tag; 461 void *rx_tlv = (uint8_t *)rx_tlv_hdr + HAL_RX_TLV32_HDR_SIZE; 462 void *other_tlv_hdr = NULL; 463 void *other_tlv = NULL; 464 uint32_t ru_details_channel_0; 465 struct hal_rx_ppdu_info *ppdu_info = 466 (struct hal_rx_ppdu_info *)ppdu_info_handle; 467 468 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv_hdr); 469 tlv_len = HAL_RX_GET_USER_TLV32_LEN(rx_tlv_hdr); 470 temp_len = 0; 471 472 other_tlv_hdr = rx_tlv + HAL_RX_TLV32_HDR_SIZE; 473 474 other_tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(other_tlv_hdr); 475 other_tlv_len = HAL_RX_GET_USER_TLV32_LEN(other_tlv_hdr); 476 temp_len += other_tlv_len; 477 other_tlv = other_tlv_hdr + HAL_RX_TLV32_HDR_SIZE; 478 479 switch (other_tlv_tag) { 480 case WIFIPHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_E: 481 ru_details_channel_0 = 482 HAL_RX_GET(other_tlv, 483 PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_0, 484 RU_DETAILS_CHANNEL_0); 485 486 qdf_mem_copy(ppdu_info->rx_status.he_RU, 487 &ru_details_channel_0, 488 sizeof(ppdu_info->rx_status.he_RU)); 489 490 if (ppdu_info->rx_status.bw >= HAL_FULL_RX_BW_20) { 491 ppdu_info->rx_status.he_sig_b_common_known |= 492 QDF_MON_STATUS_HE_SIG_B_COMMON_KNOWN_RU0; 493 } 494 if (ppdu_info->rx_status.bw >= HAL_FULL_RX_BW_40) { 495 ppdu_info->rx_status.he_sig_b_common_known |= 496 QDF_MON_STATUS_HE_SIG_B_COMMON_KNOWN_RU1; 497 } 498 if (ppdu_info->rx_status.bw >= HAL_FULL_RX_BW_80) { 499 ppdu_info->rx_status.he_sig_b_common_known |= 500 QDF_MON_STATUS_HE_SIG_B_COMMON_KNOWN_RU2; 501 } 502 if (ppdu_info->rx_status.bw >= HAL_FULL_RX_BW_160) { 503 ppdu_info->rx_status.he_sig_b_common_known |= 504 QDF_MON_STATUS_HE_SIG_B_COMMON_KNOWN_RU3; 505 } 506 break; 507 default: 508 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR, 509 "%s unhandled TLV type: %d, TLV len:%d", 510 __func__, other_tlv_tag, other_tlv_len); 511 break; 512 } 513 } 514 #else 515 static 516 void hal_rx_proc_phyrx_other_receive_info_tlv_6290(void *rx_tlv_hdr, 517 void *ppdu_info_handle) 518 { 519 } 520 #endif /* QCA_WIFI_QCA6290_11AX */ 521 522 /** 523 * hal_rx_dump_msdu_start_tlv_6290() : dump RX msdu_start TLV in structured 524 * human readable format. 525 * @ msdu_start: pointer the msdu_start TLV in pkt. 526 * @ dbg_level: log level. 527 * 528 * Return: void 529 */ 530 static void hal_rx_dump_msdu_start_tlv_6290(void *msdustart, 531 uint8_t dbg_level) 532 { 533 struct rx_msdu_start *msdu_start = (struct rx_msdu_start *)msdustart; 534 535 QDF_TRACE(QDF_MODULE_ID_DP, dbg_level, 536 "rx_msdu_start tlv - " 537 "rxpcu_mpdu_filter_in_category: %d " 538 "sw_frame_group_id: %d " 539 "phy_ppdu_id: %d " 540 "msdu_length: %d " 541 "ipsec_esp: %d " 542 "l3_offset: %d " 543 "ipsec_ah: %d " 544 "l4_offset: %d " 545 "msdu_number: %d " 546 "decap_format: %d " 547 "ipv4_proto: %d " 548 "ipv6_proto: %d " 549 "tcp_proto: %d " 550 "udp_proto: %d " 551 "ip_frag: %d " 552 "tcp_only_ack: %d " 553 "da_is_bcast_mcast: %d " 554 "ip4_protocol_ip6_next_header: %d " 555 "toeplitz_hash_2_or_4: %d " 556 "flow_id_toeplitz: %d " 557 "user_rssi: %d " 558 "pkt_type: %d " 559 "stbc: %d " 560 "sgi: %d " 561 "rate_mcs: %d " 562 "receive_bandwidth: %d " 563 "reception_type: %d " 564 #if !defined(QCA_WIFI_QCA6290_11AX) 565 "toeplitz_hash: %d " 566 "nss: %d " 567 #endif 568 "ppdu_start_timestamp: %d " 569 "sw_phy_meta_data: %d ", 570 msdu_start->rxpcu_mpdu_filter_in_category, 571 msdu_start->sw_frame_group_id, 572 msdu_start->phy_ppdu_id, 573 msdu_start->msdu_length, 574 msdu_start->ipsec_esp, 575 msdu_start->l3_offset, 576 msdu_start->ipsec_ah, 577 msdu_start->l4_offset, 578 msdu_start->msdu_number, 579 msdu_start->decap_format, 580 msdu_start->ipv4_proto, 581 msdu_start->ipv6_proto, 582 msdu_start->tcp_proto, 583 msdu_start->udp_proto, 584 msdu_start->ip_frag, 585 msdu_start->tcp_only_ack, 586 msdu_start->da_is_bcast_mcast, 587 msdu_start->ip4_protocol_ip6_next_header, 588 msdu_start->toeplitz_hash_2_or_4, 589 msdu_start->flow_id_toeplitz, 590 msdu_start->user_rssi, 591 msdu_start->pkt_type, 592 msdu_start->stbc, 593 msdu_start->sgi, 594 msdu_start->rate_mcs, 595 msdu_start->receive_bandwidth, 596 msdu_start->reception_type, 597 #if !defined(QCA_WIFI_QCA6290_11AX) 598 msdu_start->toeplitz_hash, 599 msdu_start->nss, 600 #endif 601 msdu_start->ppdu_start_timestamp, 602 msdu_start->sw_phy_meta_data); 603 } 604 605 /** 606 * hal_rx_dump_msdu_end_tlv_6290: dump RX msdu_end TLV in structured 607 * human readable format. 608 * @ msdu_end: pointer the msdu_end TLV in pkt. 609 * @ dbg_level: log level. 610 * 611 * Return: void 612 */ 613 static void hal_rx_dump_msdu_end_tlv_6290(void *msduend, 614 uint8_t dbg_level) 615 { 616 struct rx_msdu_end *msdu_end = (struct rx_msdu_end *)msduend; 617 618 QDF_TRACE(QDF_MODULE_ID_DP, dbg_level, 619 "rx_msdu_end tlv - " 620 "rxpcu_mpdu_filter_in_category: %d " 621 "sw_frame_group_id: %d " 622 "phy_ppdu_id: %d " 623 "ip_hdr_chksum: %d " 624 "tcp_udp_chksum: %d " 625 "key_id_octet: %d " 626 "cce_super_rule: %d " 627 "cce_classify_not_done_truncat: %d " 628 "cce_classify_not_done_cce_dis: %d " 629 "ext_wapi_pn_63_48: %d " 630 "ext_wapi_pn_95_64: %d " 631 "ext_wapi_pn_127_96: %d " 632 "reported_mpdu_length: %d " 633 "first_msdu: %d " 634 "last_msdu: %d " 635 "sa_idx_timeout: %d " 636 "da_idx_timeout: %d " 637 "msdu_limit_error: %d " 638 "flow_idx_timeout: %d " 639 "flow_idx_invalid: %d " 640 "wifi_parser_error: %d " 641 "amsdu_parser_error: %d " 642 "sa_is_valid: %d " 643 "da_is_valid: %d " 644 "da_is_mcbc: %d " 645 "l3_header_padding: %d " 646 "ipv6_options_crc: %d " 647 "tcp_seq_number: %d " 648 "tcp_ack_number: %d " 649 "tcp_flag: %d " 650 "lro_eligible: %d " 651 "window_size: %d " 652 "da_offset: %d " 653 "sa_offset: %d " 654 "da_offset_valid: %d " 655 "sa_offset_valid: %d " 656 "rule_indication_31_0: %d " 657 "rule_indication_63_32: %d " 658 "sa_idx: %d " 659 "da_idx: %d " 660 "msdu_drop: %d " 661 "reo_destination_indication: %d " 662 "flow_idx: %d " 663 "fse_metadata: %d " 664 "cce_metadata: %d " 665 "sa_sw_peer_id: %d ", 666 msdu_end->rxpcu_mpdu_filter_in_category, 667 msdu_end->sw_frame_group_id, 668 msdu_end->phy_ppdu_id, 669 msdu_end->ip_hdr_chksum, 670 msdu_end->tcp_udp_chksum, 671 msdu_end->key_id_octet, 672 msdu_end->cce_super_rule, 673 msdu_end->cce_classify_not_done_truncate, 674 msdu_end->cce_classify_not_done_cce_dis, 675 msdu_end->ext_wapi_pn_63_48, 676 msdu_end->ext_wapi_pn_95_64, 677 msdu_end->ext_wapi_pn_127_96, 678 msdu_end->reported_mpdu_length, 679 msdu_end->first_msdu, 680 msdu_end->last_msdu, 681 msdu_end->sa_idx_timeout, 682 msdu_end->da_idx_timeout, 683 msdu_end->msdu_limit_error, 684 msdu_end->flow_idx_timeout, 685 msdu_end->flow_idx_invalid, 686 msdu_end->wifi_parser_error, 687 msdu_end->amsdu_parser_error, 688 msdu_end->sa_is_valid, 689 msdu_end->da_is_valid, 690 msdu_end->da_is_mcbc, 691 msdu_end->l3_header_padding, 692 msdu_end->ipv6_options_crc, 693 msdu_end->tcp_seq_number, 694 msdu_end->tcp_ack_number, 695 msdu_end->tcp_flag, 696 msdu_end->lro_eligible, 697 msdu_end->window_size, 698 msdu_end->da_offset, 699 msdu_end->sa_offset, 700 msdu_end->da_offset_valid, 701 msdu_end->sa_offset_valid, 702 msdu_end->rule_indication_31_0, 703 msdu_end->rule_indication_63_32, 704 msdu_end->sa_idx, 705 msdu_end->da_idx, 706 msdu_end->msdu_drop, 707 msdu_end->reo_destination_indication, 708 msdu_end->flow_idx, 709 msdu_end->fse_metadata, 710 msdu_end->cce_metadata, 711 msdu_end->sa_sw_peer_id); 712 } 713 714 715 /* 716 * Get tid from RX_MPDU_START 717 */ 718 #define HAL_RX_MPDU_INFO_TID_GET(_rx_mpdu_info) \ 719 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_info), \ 720 RX_MPDU_INFO_3_TID_OFFSET)), \ 721 RX_MPDU_INFO_3_TID_MASK, \ 722 RX_MPDU_INFO_3_TID_LSB)) 723 724 static uint32_t hal_rx_mpdu_start_tid_get_6290(uint8_t *buf) 725 { 726 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 727 struct rx_mpdu_start *mpdu_start = 728 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 729 uint32_t tid; 730 731 tid = HAL_RX_MPDU_INFO_TID_GET(&mpdu_start->rx_mpdu_info_details); 732 733 return tid; 734 } 735 736 #define HAL_RX_MSDU_START_RECEPTION_TYPE_GET(_rx_msdu_start) \ 737 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start), \ 738 RX_MSDU_START_5_RECEPTION_TYPE_OFFSET)), \ 739 RX_MSDU_START_5_RECEPTION_TYPE_MASK, \ 740 RX_MSDU_START_5_RECEPTION_TYPE_LSB)) 741 742 /* 743 * hal_rx_msdu_start_reception_type_get(): API to get the reception type 744 * Interval from rx_msdu_start 745 * 746 * @buf: pointer to the start of RX PKT TLV header 747 * Return: uint32_t(reception_type) 748 */ 749 static uint32_t hal_rx_msdu_start_reception_type_get_6290(uint8_t *buf) 750 { 751 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 752 struct rx_msdu_start *msdu_start = 753 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 754 uint32_t reception_type; 755 756 reception_type = HAL_RX_MSDU_START_RECEPTION_TYPE_GET(msdu_start); 757 758 return reception_type; 759 } 760 761 #define HAL_RX_MSDU_END_DA_IDX_GET(_rx_msdu_end) \ 762 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 763 RX_MSDU_END_13_DA_IDX_OFFSET)), \ 764 RX_MSDU_END_13_DA_IDX_MASK, \ 765 RX_MSDU_END_13_DA_IDX_LSB)) 766 767 /** 768 * hal_rx_msdu_end_da_idx_get_6290: API to get da_idx 769 * from rx_msdu_end TLV 770 * 771 * @ buf: pointer to the start of RX PKT TLV headers 772 * Return: da index 773 */ 774 static uint16_t hal_rx_msdu_end_da_idx_get_6290(uint8_t *buf) 775 { 776 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 777 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 778 uint16_t da_idx; 779 780 da_idx = HAL_RX_MSDU_END_DA_IDX_GET(msdu_end); 781 782 return da_idx; 783 } 784 785