1 /* 2 * Copyright (c) 2016-2019 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 #include "qdf_util.h" 19 #include "qdf_types.h" 20 #include "qdf_lock.h" 21 #include "qdf_mem.h" 22 #include "qdf_nbuf.h" 23 #include "tcl_data_cmd.h" 24 #include "mac_tcl_reg_seq_hwioreg.h" 25 #include "phyrx_rssi_legacy.h" 26 #include "rx_msdu_start.h" 27 #include "tlv_tag_def.h" 28 #include "hal_hw_headers.h" 29 #include "hal_internal.h" 30 #include "cdp_txrx_mon_struct.h" 31 #include "qdf_trace.h" 32 #include "hal_rx.h" 33 #include "hal_tx.h" 34 #include "dp_types.h" 35 #include "hal_api_mon.h" 36 #include "phyrx_other_receive_info_ru_details.h" 37 38 #define HAL_RX_MPDU_GET_SEQUENCE_NUMBER(_rx_mpdu_info) \ 39 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 40 RX_MPDU_INFO_2_MPDU_SEQUENCE_NUMBER_OFFSET)), \ 41 RX_MPDU_INFO_2_MPDU_SEQUENCE_NUMBER_MASK, \ 42 RX_MPDU_INFO_2_MPDU_SEQUENCE_NUMBER_LSB)) 43 44 #define HAL_RX_MSDU_END_DA_IS_MCBC_GET(_rx_msdu_end) \ 45 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 46 RX_MSDU_END_5_DA_IS_MCBC_OFFSET)), \ 47 RX_MSDU_END_5_DA_IS_MCBC_MASK, \ 48 RX_MSDU_END_5_DA_IS_MCBC_LSB)) 49 50 #define HAL_RX_MSDU_END_SA_IS_VALID_GET(_rx_msdu_end) \ 51 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 52 RX_MSDU_END_5_SA_IS_VALID_OFFSET)), \ 53 RX_MSDU_END_5_SA_IS_VALID_MASK, \ 54 RX_MSDU_END_5_SA_IS_VALID_LSB)) 55 56 #define HAL_RX_MSDU_END_SA_IDX_GET(_rx_msdu_end) \ 57 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 58 RX_MSDU_END_13_SA_IDX_OFFSET)), \ 59 RX_MSDU_END_13_SA_IDX_MASK, \ 60 RX_MSDU_END_13_SA_IDX_LSB)) 61 62 #define HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(_rx_msdu_end) \ 63 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 64 RX_MSDU_END_5_L3_HEADER_PADDING_OFFSET)), \ 65 RX_MSDU_END_5_L3_HEADER_PADDING_MASK, \ 66 RX_MSDU_END_5_L3_HEADER_PADDING_LSB)) 67 68 #define HAL_RX_MPDU_ENCRYPTION_INFO_VALID(_rx_mpdu_info) \ 69 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 70 RX_MPDU_INFO_2_FRAME_ENCRYPTION_INFO_VALID_OFFSET)), \ 71 RX_MPDU_INFO_2_FRAME_ENCRYPTION_INFO_VALID_MASK, \ 72 RX_MPDU_INFO_2_FRAME_ENCRYPTION_INFO_VALID_LSB)) 73 74 #define HAL_RX_MPDU_PN_31_0_GET(_rx_mpdu_info) \ 75 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 76 RX_MPDU_INFO_4_PN_31_0_OFFSET)), \ 77 RX_MPDU_INFO_4_PN_31_0_MASK, \ 78 RX_MPDU_INFO_4_PN_31_0_LSB)) 79 80 #define HAL_RX_MPDU_PN_63_32_GET(_rx_mpdu_info) \ 81 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 82 RX_MPDU_INFO_5_PN_63_32_OFFSET)), \ 83 RX_MPDU_INFO_5_PN_63_32_MASK, \ 84 RX_MPDU_INFO_5_PN_63_32_LSB)) 85 86 #define HAL_RX_MPDU_PN_95_64_GET(_rx_mpdu_info) \ 87 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 88 RX_MPDU_INFO_6_PN_95_64_OFFSET)), \ 89 RX_MPDU_INFO_6_PN_95_64_MASK, \ 90 RX_MPDU_INFO_6_PN_95_64_LSB)) 91 92 #define HAL_RX_MPDU_PN_127_96_GET(_rx_mpdu_info) \ 93 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 94 RX_MPDU_INFO_7_PN_127_96_OFFSET)), \ 95 RX_MPDU_INFO_7_PN_127_96_MASK, \ 96 RX_MPDU_INFO_7_PN_127_96_LSB)) 97 98 #define HAL_RX_MSDU_END_FIRST_MSDU_GET(_rx_msdu_end) \ 99 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 100 RX_MSDU_END_5_FIRST_MSDU_OFFSET)), \ 101 RX_MSDU_END_5_FIRST_MSDU_MASK, \ 102 RX_MSDU_END_5_FIRST_MSDU_LSB)) 103 104 #define HAL_RX_MSDU_END_DA_IS_VALID_GET(_rx_msdu_end) \ 105 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 106 RX_MSDU_END_5_DA_IS_VALID_OFFSET)), \ 107 RX_MSDU_END_5_DA_IS_VALID_MASK, \ 108 RX_MSDU_END_5_DA_IS_VALID_LSB)) 109 110 #define HAL_RX_MSDU_END_LAST_MSDU_GET(_rx_msdu_end) \ 111 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 112 RX_MSDU_END_5_LAST_MSDU_OFFSET)), \ 113 RX_MSDU_END_5_LAST_MSDU_MASK, \ 114 RX_MSDU_END_5_LAST_MSDU_LSB)) 115 116 #define HAL_RX_MPDU_GET_MAC_AD4_VALID(_rx_mpdu_info) \ 117 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 118 RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_OFFSET)), \ 119 RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_MASK, \ 120 RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_LSB)) 121 122 #define HAL_RX_MPDU_INFO_SW_PEER_ID_GET(_rx_mpdu_info) \ 123 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_info), \ 124 RX_MPDU_INFO_1_SW_PEER_ID_OFFSET)), \ 125 RX_MPDU_INFO_1_SW_PEER_ID_MASK, \ 126 RX_MPDU_INFO_1_SW_PEER_ID_LSB)) 127 128 #define HAL_RX_MPDU_GET_TODS(_rx_mpdu_info) \ 129 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 130 RX_MPDU_INFO_2_TO_DS_OFFSET)), \ 131 RX_MPDU_INFO_2_TO_DS_MASK, \ 132 RX_MPDU_INFO_2_TO_DS_LSB)) 133 134 #define HAL_RX_MPDU_GET_FROMDS(_rx_mpdu_info) \ 135 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 136 RX_MPDU_INFO_2_FR_DS_OFFSET)), \ 137 RX_MPDU_INFO_2_FR_DS_MASK, \ 138 RX_MPDU_INFO_2_FR_DS_LSB)) 139 140 #define HAL_RX_MPDU_GET_FRAME_CONTROL_VALID(_rx_mpdu_info) \ 141 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 142 RX_MPDU_INFO_2_MPDU_FRAME_CONTROL_VALID_OFFSET)), \ 143 RX_MPDU_INFO_2_MPDU_FRAME_CONTROL_VALID_MASK, \ 144 RX_MPDU_INFO_2_MPDU_FRAME_CONTROL_VALID_LSB)) 145 146 #define HAL_RX_MPDU_MAC_ADDR_AD1_VALID_GET(_rx_mpdu_info) \ 147 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 148 RX_MPDU_INFO_2_MAC_ADDR_AD1_VALID_OFFSET)), \ 149 RX_MPDU_INFO_2_MAC_ADDR_AD1_VALID_MASK, \ 150 RX_MPDU_INFO_2_MAC_ADDR_AD1_VALID_LSB)) 151 152 #define HAL_RX_MPDU_AD1_31_0_GET(_rx_mpdu_info) \ 153 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 154 RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_OFFSET)), \ 155 RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_MASK, \ 156 RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_LSB)) 157 158 #define HAL_RX_MPDU_AD1_47_32_GET(_rx_mpdu_info) \ 159 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 160 RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_OFFSET)), \ 161 RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_MASK, \ 162 RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_LSB)) 163 164 #define HAL_RX_MPDU_MAC_ADDR_AD2_VALID_GET(_rx_mpdu_info) \ 165 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 166 RX_MPDU_INFO_2_MAC_ADDR_AD2_VALID_OFFSET)), \ 167 RX_MPDU_INFO_2_MAC_ADDR_AD2_VALID_MASK, \ 168 RX_MPDU_INFO_2_MAC_ADDR_AD2_VALID_LSB)) 169 170 #define HAL_RX_MPDU_AD2_15_0_GET(_rx_mpdu_info) \ 171 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 172 RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_OFFSET)), \ 173 RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_MASK, \ 174 RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_LSB)) 175 176 #define HAL_RX_MPDU_AD2_47_16_GET(_rx_mpdu_info) \ 177 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 178 RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_OFFSET)), \ 179 RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_MASK, \ 180 RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_LSB)) 181 182 #define HAL_RX_MPDU_MAC_ADDR_AD3_VALID_GET(_rx_mpdu_info) \ 183 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 184 RX_MPDU_INFO_2_MAC_ADDR_AD3_VALID_OFFSET)), \ 185 RX_MPDU_INFO_2_MAC_ADDR_AD3_VALID_MASK, \ 186 RX_MPDU_INFO_2_MAC_ADDR_AD3_VALID_LSB)) 187 188 #define HAL_RX_MPDU_AD3_31_0_GET(_rx_mpdu_info) \ 189 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 190 RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_OFFSET)), \ 191 RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_MASK, \ 192 RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_LSB)) 193 194 #define HAL_RX_MPDU_AD3_47_32_GET(_rx_mpdu_info) \ 195 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 196 RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_OFFSET)), \ 197 RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_MASK, \ 198 RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_LSB)) 199 200 #define HAL_RX_MPDU_MAC_ADDR_AD4_VALID_GET(_rx_mpdu_info) \ 201 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 202 RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_OFFSET)), \ 203 RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_MASK, \ 204 RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_LSB)) 205 206 #define HAL_RX_MPDU_AD4_31_0_GET(_rx_mpdu_info) \ 207 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 208 RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_OFFSET)), \ 209 RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_MASK, \ 210 RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_LSB)) 211 212 #define HAL_RX_MPDU_AD4_47_32_GET(_rx_mpdu_info) \ 213 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 214 RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_OFFSET)), \ 215 RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_MASK, \ 216 RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_LSB)) 217 218 #define HAL_RX_MPDU_GET_SEQUENCE_CONTROL_VALID(_rx_mpdu_info) \ 219 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 220 RX_MPDU_INFO_2_MPDU_SEQUENCE_CONTROL_VALID_OFFSET)), \ 221 RX_MPDU_INFO_2_MPDU_SEQUENCE_CONTROL_VALID_MASK, \ 222 RX_MPDU_INFO_2_MPDU_SEQUENCE_CONTROL_VALID_LSB)) 223 224 #define HAL_RX_MPDU_INFO_QOS_CONTROL_VALID_GET(_rx_mpdu_info) \ 225 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_info), \ 226 RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_OFFSET)), \ 227 RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_MASK, \ 228 RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_LSB)) 229 230 #define HAL_RX_MSDU_END_SA_SW_PEER_ID_GET(_rx_msdu_end) \ 231 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 232 RX_MSDU_END_16_SA_SW_PEER_ID_OFFSET)), \ 233 RX_MSDU_END_16_SA_SW_PEER_ID_MASK, \ 234 RX_MSDU_END_16_SA_SW_PEER_ID_LSB)) 235 236 #define HAL_RX_MSDU0_BUFFER_ADDR_LSB(link_desc_va) \ 237 (uint8_t *)(link_desc_va) + \ 238 RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET 239 240 #define HAL_RX_MSDU_DESC_INFO_PTR_GET(msdu0) \ 241 (uint8_t *)(msdu0) + \ 242 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET 243 244 #define HAL_ENT_MPDU_DESC_INFO(ent_ring_desc) \ 245 (uint8_t *)(ent_ring_desc) + \ 246 RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET 247 248 #define HAL_DST_MPDU_DESC_INFO(dst_ring_desc) \ 249 (uint8_t *)(dst_ring_desc) + \ 250 REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET 251 252 #define HAL_RX_GET_FC_VALID(rx_mpdu_start) \ 253 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_2, MPDU_FRAME_CONTROL_VALID) 254 255 #define HAL_RX_GET_TO_DS_FLAG(rx_mpdu_start) \ 256 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_2, TO_DS) 257 258 #define HAL_RX_GET_MAC_ADDR2_VALID(rx_mpdu_start) \ 259 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_2, MAC_ADDR_AD2_VALID) 260 261 #define HAL_RX_GET_FILTER_CATEGORY(rx_mpdu_start) \ 262 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_0, RXPCU_MPDU_FILTER_IN_CATEGORY) 263 264 #define HAL_RX_GET_PPDU_ID(rx_mpdu_start) \ 265 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_0, PHY_PPDU_ID) 266 267 #define HAL_RX_GET_SW_FRAME_GROUP_ID(rx_mpdu_start) \ 268 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_0, SW_FRAME_GROUP_ID) 269 270 #define HAL_REO_R0_CONFIG(soc, reg_val, reo_params) \ 271 do { \ 272 (reg_val) &= \ 273 ~(HWIO_REO_R0_GENERAL_ENABLE_FRAGMENT_DEST_RING_BMSK |\ 274 HWIO_REO_R0_GENERAL_ENABLE_AGING_LIST_ENABLE_BMSK |\ 275 HWIO_REO_R0_GENERAL_ENABLE_AGING_FLUSH_ENABLE_BMSK);\ 276 (reg_val) |= \ 277 HAL_SM(HWIO_REO_R0_GENERAL_ENABLE, \ 278 FRAGMENT_DEST_RING, \ 279 (reo_params)->frag_dst_ring) | \ 280 HAL_SM(HWIO_REO_R0_GENERAL_ENABLE, \ 281 AGING_LIST_ENABLE, 1) |\ 282 HAL_SM(HWIO_REO_R0_GENERAL_ENABLE, \ 283 AGING_FLUSH_ENABLE, 1);\ 284 HAL_REG_WRITE((soc), \ 285 HWIO_REO_R0_GENERAL_ENABLE_ADDR( \ 286 SEQ_WCSS_UMAC_REO_REG_OFFSET), \ 287 (reg_val)); \ 288 } while (0) 289 290 #define HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr) \ 291 ((struct rx_msdu_desc_info *) \ 292 _OFFSET_TO_BYTE_PTR(msdu_details_ptr, \ 293 UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET)) 294 295 #define HAL_RX_LINK_DESC_MSDU0_PTR(link_desc) \ 296 ((struct rx_msdu_details *) \ 297 _OFFSET_TO_BYTE_PTR((link_desc),\ 298 UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET)) 299 300 #define HAL_RX_MSDU_END_FLOW_IDX_GET(_rx_msdu_end) \ 301 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 302 RX_MSDU_END_14_FLOW_IDX_OFFSET)), \ 303 RX_MSDU_END_14_FLOW_IDX_MASK, \ 304 RX_MSDU_END_14_FLOW_IDX_LSB)) 305 306 #define HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(_rx_msdu_end) \ 307 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 308 RX_MSDU_END_5_FLOW_IDX_INVALID_OFFSET)), \ 309 RX_MSDU_END_5_FLOW_IDX_INVALID_MASK, \ 310 RX_MSDU_END_5_FLOW_IDX_INVALID_LSB)) 311 312 #define HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(_rx_msdu_end) \ 313 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 314 RX_MSDU_END_5_FLOW_IDX_TIMEOUT_OFFSET)), \ 315 RX_MSDU_END_5_FLOW_IDX_TIMEOUT_MASK, \ 316 RX_MSDU_END_5_FLOW_IDX_TIMEOUT_LSB)) 317 318 #define HAL_RX_MSDU_END_FSE_METADATA_GET(_rx_msdu_end) \ 319 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 320 RX_MSDU_END_15_FSE_METADATA_OFFSET)), \ 321 RX_MSDU_END_15_FSE_METADATA_MASK, \ 322 RX_MSDU_END_15_FSE_METADATA_LSB)) 323 324 #define HAL_RX_MSDU_END_CCE_METADATA_GET(_rx_msdu_end) \ 325 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 326 RX_MSDU_END_16_CCE_METADATA_OFFSET)), \ 327 RX_MSDU_END_16_CCE_METADATA_MASK, \ 328 RX_MSDU_END_16_CCE_METADATA_LSB)) 329 330 #define HAL_RX_TLV_GET_TCP_CHKSUM(buf) \ 331 (_HAL_MS( \ 332 (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ 333 msdu_end_tlv.rx_msdu_end), \ 334 RX_MSDU_END_1_TCP_UDP_CHKSUM_OFFSET)), \ 335 RX_MSDU_END_1_TCP_UDP_CHKSUM_MASK, \ 336 RX_MSDU_END_1_TCP_UDP_CHKSUM_LSB)) 337 338 #if defined(QCA_WIFI_QCA6290_11AX) 339 #define HAL_RX_MSDU_START_MIMO_SS_BITMAP(_rx_msdu_start)\ 340 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start),\ 341 RX_MSDU_START_5_MIMO_SS_BITMAP_OFFSET)), \ 342 RX_MSDU_START_5_MIMO_SS_BITMAP_MASK, \ 343 RX_MSDU_START_5_MIMO_SS_BITMAP_LSB)) 344 345 /* 346 * hal_rx_msdu_start_nss_get_6290(): API to get the NSS 347 * Interval from rx_msdu_start 348 * 349 * @buf: pointer to the start of RX PKT TLV header 350 * Return: uint32_t(nss) 351 */ 352 static uint32_t 353 hal_rx_msdu_start_nss_get_6290(uint8_t *buf) 354 { 355 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 356 struct rx_msdu_start *msdu_start = 357 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 358 uint8_t mimo_ss_bitmap; 359 360 mimo_ss_bitmap = HAL_RX_MSDU_START_MIMO_SS_BITMAP(msdu_start); 361 362 return qdf_get_hweight8(mimo_ss_bitmap); 363 } 364 #else 365 static uint32_t 366 hal_rx_msdu_start_nss_get_6290(uint8_t *buf) 367 { 368 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 369 struct rx_msdu_start *msdu_start = 370 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 371 uint32_t nss; 372 373 nss = HAL_RX_MSDU_START_NSS_GET(msdu_start); 374 return nss; 375 } 376 #endif 377 378 /** 379 * hal_rx_mon_hw_desc_get_mpdu_status_6290(): Retrieve MPDU status 380 * 381 * @ hw_desc_addr: Start address of Rx HW TLVs 382 * @ rs: Status for monitor mode 383 * 384 * Return: void 385 */ 386 static void hal_rx_mon_hw_desc_get_mpdu_status_6290(void *hw_desc_addr, 387 struct mon_rx_status *rs) 388 { 389 struct rx_msdu_start *rx_msdu_start; 390 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr; 391 uint32_t reg_value; 392 const uint32_t sgi_hw_to_cdp[] = { 393 CDP_SGI_0_8_US, 394 CDP_SGI_0_4_US, 395 CDP_SGI_1_6_US, 396 CDP_SGI_3_2_US, 397 }; 398 399 rx_msdu_start = &rx_desc->msdu_start_tlv.rx_msdu_start; 400 401 HAL_RX_GET_MSDU_AGGREGATION(rx_desc, rs); 402 403 rs->ant_signal_db = HAL_RX_GET(rx_msdu_start, 404 RX_MSDU_START_5, USER_RSSI); 405 rs->is_stbc = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, STBC); 406 407 reg_value = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, SGI); 408 rs->sgi = sgi_hw_to_cdp[reg_value]; 409 #if !defined(QCA_WIFI_QCA6290_11AX) 410 rs->nr_ant = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, NSS); 411 #endif 412 reg_value = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, RECEPTION_TYPE); 413 rs->beamformed = (reg_value == HAL_RX_RECEPTION_TYPE_MU_MIMO) ? 1 : 0; 414 /* TODO: rs->beamformed should be set for SU beamforming also */ 415 } 416 417 #define LINK_DESC_SIZE (NUM_OF_DWORDS_RX_MSDU_LINK << 2) 418 419 static uint32_t hal_get_link_desc_size_6290(void) 420 { 421 return LINK_DESC_SIZE; 422 } 423 424 425 #ifdef QCA_WIFI_QCA6290_11AX 426 /* 427 * hal_rx_get_tlv_6290(): API to get the tlv 428 * 429 * @rx_tlv: TLV data extracted from the rx packet 430 * Return: uint8_t 431 */ 432 static uint8_t hal_rx_get_tlv_6290(void *rx_tlv) 433 { 434 return HAL_RX_GET(rx_tlv, PHYRX_RSSI_LEGACY_0, RECEIVE_BANDWIDTH); 435 } 436 #else 437 static uint8_t hal_rx_get_tlv_6290(void *rx_tlv) 438 { 439 return HAL_RX_GET(rx_tlv, PHYRX_RSSI_LEGACY_35, RECEIVE_BANDWIDTH); 440 } 441 #endif 442 443 #ifdef QCA_WIFI_QCA6290_11AX 444 /** 445 * hal_rx_proc_phyrx_other_receive_info_tlv_6290() 446 * - process other receive info TLV 447 * @rx_tlv_hdr: pointer to TLV header 448 * @ppdu_info: pointer to ppdu_info 449 * 450 * Return: None 451 */ 452 static 453 void hal_rx_proc_phyrx_other_receive_info_tlv_6290(void *rx_tlv_hdr, 454 void *ppdu_info_handle) 455 { 456 uint32_t tlv_tag, tlv_len; 457 uint32_t temp_len, other_tlv_len, other_tlv_tag; 458 void *rx_tlv = (uint8_t *)rx_tlv_hdr + HAL_RX_TLV32_HDR_SIZE; 459 void *other_tlv_hdr = NULL; 460 void *other_tlv = NULL; 461 uint32_t ru_details_channel_0; 462 struct hal_rx_ppdu_info *ppdu_info = 463 (struct hal_rx_ppdu_info *)ppdu_info_handle; 464 465 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv_hdr); 466 tlv_len = HAL_RX_GET_USER_TLV32_LEN(rx_tlv_hdr); 467 temp_len = 0; 468 469 other_tlv_hdr = rx_tlv + HAL_RX_TLV32_HDR_SIZE; 470 471 other_tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(other_tlv_hdr); 472 other_tlv_len = HAL_RX_GET_USER_TLV32_LEN(other_tlv_hdr); 473 temp_len += other_tlv_len; 474 other_tlv = other_tlv_hdr + HAL_RX_TLV32_HDR_SIZE; 475 476 switch (other_tlv_tag) { 477 case WIFIPHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_E: 478 ru_details_channel_0 = 479 HAL_RX_GET(other_tlv, 480 PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_0, 481 RU_DETAILS_CHANNEL_0); 482 483 qdf_mem_copy(ppdu_info->rx_status.he_RU, 484 &ru_details_channel_0, 485 sizeof(ppdu_info->rx_status.he_RU)); 486 487 if (ppdu_info->rx_status.bw >= HAL_FULL_RX_BW_20) { 488 ppdu_info->rx_status.he_sig_b_common_known |= 489 QDF_MON_STATUS_HE_SIG_B_COMMON_KNOWN_RU0; 490 } 491 if (ppdu_info->rx_status.bw >= HAL_FULL_RX_BW_40) { 492 ppdu_info->rx_status.he_sig_b_common_known |= 493 QDF_MON_STATUS_HE_SIG_B_COMMON_KNOWN_RU1; 494 } 495 if (ppdu_info->rx_status.bw >= HAL_FULL_RX_BW_80) { 496 ppdu_info->rx_status.he_sig_b_common_known |= 497 QDF_MON_STATUS_HE_SIG_B_COMMON_KNOWN_RU2; 498 } 499 if (ppdu_info->rx_status.bw >= HAL_FULL_RX_BW_160) { 500 ppdu_info->rx_status.he_sig_b_common_known |= 501 QDF_MON_STATUS_HE_SIG_B_COMMON_KNOWN_RU3; 502 } 503 break; 504 default: 505 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR, 506 "%s unhandled TLV type: %d, TLV len:%d", 507 __func__, other_tlv_tag, other_tlv_len); 508 break; 509 } 510 } 511 #else 512 static 513 void hal_rx_proc_phyrx_other_receive_info_tlv_6290(void *rx_tlv_hdr, 514 void *ppdu_info_handle) 515 { 516 } 517 #endif /* QCA_WIFI_QCA6290_11AX */ 518 519 /** 520 * hal_rx_dump_msdu_start_tlv_6290() : dump RX msdu_start TLV in structured 521 * human readable format. 522 * @ msdu_start: pointer the msdu_start TLV in pkt. 523 * @ dbg_level: log level. 524 * 525 * Return: void 526 */ 527 static void hal_rx_dump_msdu_start_tlv_6290(void *msdustart, 528 uint8_t dbg_level) 529 { 530 struct rx_msdu_start *msdu_start = (struct rx_msdu_start *)msdustart; 531 532 QDF_TRACE(QDF_MODULE_ID_DP, dbg_level, 533 "rx_msdu_start tlv - " 534 "rxpcu_mpdu_filter_in_category: %d " 535 "sw_frame_group_id: %d " 536 "phy_ppdu_id: %d " 537 "msdu_length: %d " 538 "ipsec_esp: %d " 539 "l3_offset: %d " 540 "ipsec_ah: %d " 541 "l4_offset: %d " 542 "msdu_number: %d " 543 "decap_format: %d " 544 "ipv4_proto: %d " 545 "ipv6_proto: %d " 546 "tcp_proto: %d " 547 "udp_proto: %d " 548 "ip_frag: %d " 549 "tcp_only_ack: %d " 550 "da_is_bcast_mcast: %d " 551 "ip4_protocol_ip6_next_header: %d " 552 "toeplitz_hash_2_or_4: %d " 553 "flow_id_toeplitz: %d " 554 "user_rssi: %d " 555 "pkt_type: %d " 556 "stbc: %d " 557 "sgi: %d " 558 "rate_mcs: %d " 559 "receive_bandwidth: %d " 560 "reception_type: %d " 561 #if !defined(QCA_WIFI_QCA6290_11AX) 562 "toeplitz_hash: %d " 563 "nss: %d " 564 #endif 565 "ppdu_start_timestamp: %d " 566 "sw_phy_meta_data: %d ", 567 msdu_start->rxpcu_mpdu_filter_in_category, 568 msdu_start->sw_frame_group_id, 569 msdu_start->phy_ppdu_id, 570 msdu_start->msdu_length, 571 msdu_start->ipsec_esp, 572 msdu_start->l3_offset, 573 msdu_start->ipsec_ah, 574 msdu_start->l4_offset, 575 msdu_start->msdu_number, 576 msdu_start->decap_format, 577 msdu_start->ipv4_proto, 578 msdu_start->ipv6_proto, 579 msdu_start->tcp_proto, 580 msdu_start->udp_proto, 581 msdu_start->ip_frag, 582 msdu_start->tcp_only_ack, 583 msdu_start->da_is_bcast_mcast, 584 msdu_start->ip4_protocol_ip6_next_header, 585 msdu_start->toeplitz_hash_2_or_4, 586 msdu_start->flow_id_toeplitz, 587 msdu_start->user_rssi, 588 msdu_start->pkt_type, 589 msdu_start->stbc, 590 msdu_start->sgi, 591 msdu_start->rate_mcs, 592 msdu_start->receive_bandwidth, 593 msdu_start->reception_type, 594 #if !defined(QCA_WIFI_QCA6290_11AX) 595 msdu_start->toeplitz_hash, 596 msdu_start->nss, 597 #endif 598 msdu_start->ppdu_start_timestamp, 599 msdu_start->sw_phy_meta_data); 600 } 601 602 /** 603 * hal_rx_dump_msdu_end_tlv_6290: dump RX msdu_end TLV in structured 604 * human readable format. 605 * @ msdu_end: pointer the msdu_end TLV in pkt. 606 * @ dbg_level: log level. 607 * 608 * Return: void 609 */ 610 static void hal_rx_dump_msdu_end_tlv_6290(void *msduend, 611 uint8_t dbg_level) 612 { 613 struct rx_msdu_end *msdu_end = (struct rx_msdu_end *)msduend; 614 615 QDF_TRACE(QDF_MODULE_ID_DP, dbg_level, 616 "rx_msdu_end tlv - " 617 "rxpcu_mpdu_filter_in_category: %d " 618 "sw_frame_group_id: %d " 619 "phy_ppdu_id: %d " 620 "ip_hdr_chksum: %d " 621 "tcp_udp_chksum: %d " 622 "key_id_octet: %d " 623 "cce_super_rule: %d " 624 "cce_classify_not_done_truncat: %d " 625 "cce_classify_not_done_cce_dis: %d " 626 "ext_wapi_pn_63_48: %d " 627 "ext_wapi_pn_95_64: %d " 628 "ext_wapi_pn_127_96: %d " 629 "reported_mpdu_length: %d " 630 "first_msdu: %d " 631 "last_msdu: %d " 632 "sa_idx_timeout: %d " 633 "da_idx_timeout: %d " 634 "msdu_limit_error: %d " 635 "flow_idx_timeout: %d " 636 "flow_idx_invalid: %d " 637 "wifi_parser_error: %d " 638 "amsdu_parser_error: %d " 639 "sa_is_valid: %d " 640 "da_is_valid: %d " 641 "da_is_mcbc: %d " 642 "l3_header_padding: %d " 643 "ipv6_options_crc: %d " 644 "tcp_seq_number: %d " 645 "tcp_ack_number: %d " 646 "tcp_flag: %d " 647 "lro_eligible: %d " 648 "window_size: %d " 649 "da_offset: %d " 650 "sa_offset: %d " 651 "da_offset_valid: %d " 652 "sa_offset_valid: %d " 653 "rule_indication_31_0: %d " 654 "rule_indication_63_32: %d " 655 "sa_idx: %d " 656 "da_idx: %d " 657 "msdu_drop: %d " 658 "reo_destination_indication: %d " 659 "flow_idx: %d " 660 "fse_metadata: %d " 661 "cce_metadata: %d " 662 "sa_sw_peer_id: %d ", 663 msdu_end->rxpcu_mpdu_filter_in_category, 664 msdu_end->sw_frame_group_id, 665 msdu_end->phy_ppdu_id, 666 msdu_end->ip_hdr_chksum, 667 msdu_end->tcp_udp_chksum, 668 msdu_end->key_id_octet, 669 msdu_end->cce_super_rule, 670 msdu_end->cce_classify_not_done_truncate, 671 msdu_end->cce_classify_not_done_cce_dis, 672 msdu_end->ext_wapi_pn_63_48, 673 msdu_end->ext_wapi_pn_95_64, 674 msdu_end->ext_wapi_pn_127_96, 675 msdu_end->reported_mpdu_length, 676 msdu_end->first_msdu, 677 msdu_end->last_msdu, 678 msdu_end->sa_idx_timeout, 679 msdu_end->da_idx_timeout, 680 msdu_end->msdu_limit_error, 681 msdu_end->flow_idx_timeout, 682 msdu_end->flow_idx_invalid, 683 msdu_end->wifi_parser_error, 684 msdu_end->amsdu_parser_error, 685 msdu_end->sa_is_valid, 686 msdu_end->da_is_valid, 687 msdu_end->da_is_mcbc, 688 msdu_end->l3_header_padding, 689 msdu_end->ipv6_options_crc, 690 msdu_end->tcp_seq_number, 691 msdu_end->tcp_ack_number, 692 msdu_end->tcp_flag, 693 msdu_end->lro_eligible, 694 msdu_end->window_size, 695 msdu_end->da_offset, 696 msdu_end->sa_offset, 697 msdu_end->da_offset_valid, 698 msdu_end->sa_offset_valid, 699 msdu_end->rule_indication_31_0, 700 msdu_end->rule_indication_63_32, 701 msdu_end->sa_idx, 702 msdu_end->da_idx, 703 msdu_end->msdu_drop, 704 msdu_end->reo_destination_indication, 705 msdu_end->flow_idx, 706 msdu_end->fse_metadata, 707 msdu_end->cce_metadata, 708 msdu_end->sa_sw_peer_id); 709 } 710 711 712 /* 713 * Get tid from RX_MPDU_START 714 */ 715 #define HAL_RX_MPDU_INFO_TID_GET(_rx_mpdu_info) \ 716 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_info), \ 717 RX_MPDU_INFO_3_TID_OFFSET)), \ 718 RX_MPDU_INFO_3_TID_MASK, \ 719 RX_MPDU_INFO_3_TID_LSB)) 720 721 static uint32_t hal_rx_mpdu_start_tid_get_6290(uint8_t *buf) 722 { 723 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 724 struct rx_mpdu_start *mpdu_start = 725 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 726 uint32_t tid; 727 728 tid = HAL_RX_MPDU_INFO_TID_GET(&mpdu_start->rx_mpdu_info_details); 729 730 return tid; 731 } 732 733 #define HAL_RX_MSDU_START_RECEPTION_TYPE_GET(_rx_msdu_start) \ 734 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start), \ 735 RX_MSDU_START_5_RECEPTION_TYPE_OFFSET)), \ 736 RX_MSDU_START_5_RECEPTION_TYPE_MASK, \ 737 RX_MSDU_START_5_RECEPTION_TYPE_LSB)) 738 739 /* 740 * hal_rx_msdu_start_reception_type_get(): API to get the reception type 741 * Interval from rx_msdu_start 742 * 743 * @buf: pointer to the start of RX PKT TLV header 744 * Return: uint32_t(reception_type) 745 */ 746 static uint32_t hal_rx_msdu_start_reception_type_get_6290(uint8_t *buf) 747 { 748 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 749 struct rx_msdu_start *msdu_start = 750 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 751 uint32_t reception_type; 752 753 reception_type = HAL_RX_MSDU_START_RECEPTION_TYPE_GET(msdu_start); 754 755 return reception_type; 756 } 757 758 #define HAL_RX_MSDU_END_DA_IDX_GET(_rx_msdu_end) \ 759 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 760 RX_MSDU_END_13_DA_IDX_OFFSET)), \ 761 RX_MSDU_END_13_DA_IDX_MASK, \ 762 RX_MSDU_END_13_DA_IDX_LSB)) 763 764 /** 765 * hal_rx_msdu_end_da_idx_get_6290: API to get da_idx 766 * from rx_msdu_end TLV 767 * 768 * @ buf: pointer to the start of RX PKT TLV headers 769 * Return: da index 770 */ 771 static uint16_t hal_rx_msdu_end_da_idx_get_6290(uint8_t *buf) 772 { 773 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 774 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 775 uint16_t da_idx; 776 777 da_idx = HAL_RX_MSDU_END_DA_IDX_GET(msdu_end); 778 779 return da_idx; 780 } 781 782