1 /* 2 * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 #include "qdf_util.h" 19 #include "qdf_types.h" 20 #include "qdf_lock.h" 21 #include "qdf_mem.h" 22 #include "qdf_nbuf.h" 23 #include "tcl_data_cmd.h" 24 #include "mac_tcl_reg_seq_hwioreg.h" 25 #include "phyrx_rssi_legacy.h" 26 #include "rx_msdu_start.h" 27 #include "tlv_tag_def.h" 28 #include "hal_hw_headers.h" 29 #include "hal_internal.h" 30 #include "cdp_txrx_mon_struct.h" 31 #include "qdf_trace.h" 32 #include "hal_li_rx.h" 33 #include "hal_tx.h" 34 #include "dp_types.h" 35 #include "hal_api_mon.h" 36 #include "phyrx_other_receive_info_ru_details.h" 37 38 #define HAL_RX_MPDU_GET_SEQUENCE_NUMBER(_rx_mpdu_info) \ 39 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 40 RX_MPDU_INFO_2_MPDU_SEQUENCE_NUMBER_OFFSET)), \ 41 RX_MPDU_INFO_2_MPDU_SEQUENCE_NUMBER_MASK, \ 42 RX_MPDU_INFO_2_MPDU_SEQUENCE_NUMBER_LSB)) 43 44 #define HAL_RX_MSDU_END_DA_IS_MCBC_GET(_rx_msdu_end) \ 45 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 46 RX_MSDU_END_5_DA_IS_MCBC_OFFSET)), \ 47 RX_MSDU_END_5_DA_IS_MCBC_MASK, \ 48 RX_MSDU_END_5_DA_IS_MCBC_LSB)) 49 50 #define HAL_RX_MSDU_END_SA_IS_VALID_GET(_rx_msdu_end) \ 51 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 52 RX_MSDU_END_5_SA_IS_VALID_OFFSET)), \ 53 RX_MSDU_END_5_SA_IS_VALID_MASK, \ 54 RX_MSDU_END_5_SA_IS_VALID_LSB)) 55 56 #define HAL_RX_MSDU_END_SA_IDX_GET(_rx_msdu_end) \ 57 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 58 RX_MSDU_END_13_SA_IDX_OFFSET)), \ 59 RX_MSDU_END_13_SA_IDX_MASK, \ 60 RX_MSDU_END_13_SA_IDX_LSB)) 61 62 #define HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(_rx_msdu_end) \ 63 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 64 RX_MSDU_END_5_L3_HEADER_PADDING_OFFSET)), \ 65 RX_MSDU_END_5_L3_HEADER_PADDING_MASK, \ 66 RX_MSDU_END_5_L3_HEADER_PADDING_LSB)) 67 68 #define HAL_RX_MPDU_ENCRYPTION_INFO_VALID(_rx_mpdu_info) \ 69 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 70 RX_MPDU_INFO_2_FRAME_ENCRYPTION_INFO_VALID_OFFSET)), \ 71 RX_MPDU_INFO_2_FRAME_ENCRYPTION_INFO_VALID_MASK, \ 72 RX_MPDU_INFO_2_FRAME_ENCRYPTION_INFO_VALID_LSB)) 73 74 #define HAL_RX_MPDU_PN_31_0_GET(_rx_mpdu_info) \ 75 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 76 RX_MPDU_INFO_4_PN_31_0_OFFSET)), \ 77 RX_MPDU_INFO_4_PN_31_0_MASK, \ 78 RX_MPDU_INFO_4_PN_31_0_LSB)) 79 80 #define HAL_RX_MPDU_PN_63_32_GET(_rx_mpdu_info) \ 81 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 82 RX_MPDU_INFO_5_PN_63_32_OFFSET)), \ 83 RX_MPDU_INFO_5_PN_63_32_MASK, \ 84 RX_MPDU_INFO_5_PN_63_32_LSB)) 85 86 #define HAL_RX_MPDU_PN_95_64_GET(_rx_mpdu_info) \ 87 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 88 RX_MPDU_INFO_6_PN_95_64_OFFSET)), \ 89 RX_MPDU_INFO_6_PN_95_64_MASK, \ 90 RX_MPDU_INFO_6_PN_95_64_LSB)) 91 92 #define HAL_RX_MPDU_PN_127_96_GET(_rx_mpdu_info) \ 93 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 94 RX_MPDU_INFO_7_PN_127_96_OFFSET)), \ 95 RX_MPDU_INFO_7_PN_127_96_MASK, \ 96 RX_MPDU_INFO_7_PN_127_96_LSB)) 97 98 #define HAL_RX_MSDU_END_FIRST_MSDU_GET(_rx_msdu_end) \ 99 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 100 RX_MSDU_END_5_FIRST_MSDU_OFFSET)), \ 101 RX_MSDU_END_5_FIRST_MSDU_MASK, \ 102 RX_MSDU_END_5_FIRST_MSDU_LSB)) 103 104 #define HAL_RX_MSDU_END_DA_IS_VALID_GET(_rx_msdu_end) \ 105 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 106 RX_MSDU_END_5_DA_IS_VALID_OFFSET)), \ 107 RX_MSDU_END_5_DA_IS_VALID_MASK, \ 108 RX_MSDU_END_5_DA_IS_VALID_LSB)) 109 110 #define HAL_RX_MSDU_END_LAST_MSDU_GET(_rx_msdu_end) \ 111 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 112 RX_MSDU_END_5_LAST_MSDU_OFFSET)), \ 113 RX_MSDU_END_5_LAST_MSDU_MASK, \ 114 RX_MSDU_END_5_LAST_MSDU_LSB)) 115 116 #define HAL_RX_MPDU_GET_MAC_AD4_VALID(_rx_mpdu_info) \ 117 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 118 RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_OFFSET)), \ 119 RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_MASK, \ 120 RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_LSB)) 121 122 #define HAL_RX_MPDU_INFO_SW_PEER_ID_GET(_rx_mpdu_info) \ 123 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_info), \ 124 RX_MPDU_INFO_1_SW_PEER_ID_OFFSET)), \ 125 RX_MPDU_INFO_1_SW_PEER_ID_MASK, \ 126 RX_MPDU_INFO_1_SW_PEER_ID_LSB)) 127 128 #define HAL_RX_MPDU_GET_TODS(_rx_mpdu_info) \ 129 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 130 RX_MPDU_INFO_2_TO_DS_OFFSET)), \ 131 RX_MPDU_INFO_2_TO_DS_MASK, \ 132 RX_MPDU_INFO_2_TO_DS_LSB)) 133 134 #define HAL_RX_MPDU_GET_FROMDS(_rx_mpdu_info) \ 135 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 136 RX_MPDU_INFO_2_FR_DS_OFFSET)), \ 137 RX_MPDU_INFO_2_FR_DS_MASK, \ 138 RX_MPDU_INFO_2_FR_DS_LSB)) 139 140 #define HAL_RX_MPDU_GET_FRAME_CONTROL_VALID(_rx_mpdu_info) \ 141 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 142 RX_MPDU_INFO_2_MPDU_FRAME_CONTROL_VALID_OFFSET)), \ 143 RX_MPDU_INFO_2_MPDU_FRAME_CONTROL_VALID_MASK, \ 144 RX_MPDU_INFO_2_MPDU_FRAME_CONTROL_VALID_LSB)) 145 146 #define HAL_RX_MPDU_MAC_ADDR_AD1_VALID_GET(_rx_mpdu_info) \ 147 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 148 RX_MPDU_INFO_2_MAC_ADDR_AD1_VALID_OFFSET)), \ 149 RX_MPDU_INFO_2_MAC_ADDR_AD1_VALID_MASK, \ 150 RX_MPDU_INFO_2_MAC_ADDR_AD1_VALID_LSB)) 151 152 #define HAL_RX_MPDU_AD1_31_0_GET(_rx_mpdu_info) \ 153 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 154 RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_OFFSET)), \ 155 RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_MASK, \ 156 RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_LSB)) 157 158 #define HAL_RX_MPDU_AD1_47_32_GET(_rx_mpdu_info) \ 159 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 160 RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_OFFSET)), \ 161 RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_MASK, \ 162 RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_LSB)) 163 164 #define HAL_RX_MPDU_MAC_ADDR_AD2_VALID_GET(_rx_mpdu_info) \ 165 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 166 RX_MPDU_INFO_2_MAC_ADDR_AD2_VALID_OFFSET)), \ 167 RX_MPDU_INFO_2_MAC_ADDR_AD2_VALID_MASK, \ 168 RX_MPDU_INFO_2_MAC_ADDR_AD2_VALID_LSB)) 169 170 #define HAL_RX_MPDU_AD2_15_0_GET(_rx_mpdu_info) \ 171 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 172 RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_OFFSET)), \ 173 RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_MASK, \ 174 RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_LSB)) 175 176 #define HAL_RX_MPDU_AD2_47_16_GET(_rx_mpdu_info) \ 177 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 178 RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_OFFSET)), \ 179 RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_MASK, \ 180 RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_LSB)) 181 182 #define HAL_RX_MPDU_MAC_ADDR_AD3_VALID_GET(_rx_mpdu_info) \ 183 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 184 RX_MPDU_INFO_2_MAC_ADDR_AD3_VALID_OFFSET)), \ 185 RX_MPDU_INFO_2_MAC_ADDR_AD3_VALID_MASK, \ 186 RX_MPDU_INFO_2_MAC_ADDR_AD3_VALID_LSB)) 187 188 #define HAL_RX_MPDU_AD3_31_0_GET(_rx_mpdu_info) \ 189 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 190 RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_OFFSET)), \ 191 RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_MASK, \ 192 RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_LSB)) 193 194 #define HAL_RX_MPDU_AD3_47_32_GET(_rx_mpdu_info) \ 195 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 196 RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_OFFSET)), \ 197 RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_MASK, \ 198 RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_LSB)) 199 200 #define HAL_RX_MPDU_MAC_ADDR_AD4_VALID_GET(_rx_mpdu_info) \ 201 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 202 RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_OFFSET)), \ 203 RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_MASK, \ 204 RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_LSB)) 205 206 #define HAL_RX_MPDU_AD4_31_0_GET(_rx_mpdu_info) \ 207 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 208 RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_OFFSET)), \ 209 RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_MASK, \ 210 RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_LSB)) 211 212 #define HAL_RX_MPDU_AD4_47_32_GET(_rx_mpdu_info) \ 213 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 214 RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_OFFSET)), \ 215 RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_MASK, \ 216 RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_LSB)) 217 218 #define HAL_RX_MPDU_GET_SEQUENCE_CONTROL_VALID(_rx_mpdu_info) \ 219 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 220 RX_MPDU_INFO_2_MPDU_SEQUENCE_CONTROL_VALID_OFFSET)), \ 221 RX_MPDU_INFO_2_MPDU_SEQUENCE_CONTROL_VALID_MASK, \ 222 RX_MPDU_INFO_2_MPDU_SEQUENCE_CONTROL_VALID_LSB)) 223 224 #define HAL_RX_MPDU_INFO_QOS_CONTROL_VALID_GET(_rx_mpdu_info) \ 225 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_info), \ 226 RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_OFFSET)), \ 227 RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_MASK, \ 228 RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_LSB)) 229 230 #define HAL_RX_MSDU_END_SA_SW_PEER_ID_GET(_rx_msdu_end) \ 231 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 232 RX_MSDU_END_16_SA_SW_PEER_ID_OFFSET)), \ 233 RX_MSDU_END_16_SA_SW_PEER_ID_MASK, \ 234 RX_MSDU_END_16_SA_SW_PEER_ID_LSB)) 235 236 #define HAL_RX_MSDU0_BUFFER_ADDR_LSB(link_desc_va) \ 237 (uint8_t *)(link_desc_va) + \ 238 RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET 239 240 #define HAL_RX_MSDU_DESC_INFO_PTR_GET(msdu0) \ 241 (uint8_t *)(msdu0) + \ 242 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET 243 244 #define HAL_ENT_MPDU_DESC_INFO(ent_ring_desc) \ 245 (uint8_t *)(ent_ring_desc) + \ 246 RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET 247 248 #define HAL_DST_MPDU_DESC_INFO(dst_ring_desc) \ 249 (uint8_t *)(dst_ring_desc) + \ 250 REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET 251 252 #define HAL_RX_GET_FC_VALID(rx_mpdu_start) \ 253 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_2, MPDU_FRAME_CONTROL_VALID) 254 255 #define HAL_RX_GET_TO_DS_FLAG(rx_mpdu_start) \ 256 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_2, TO_DS) 257 258 #define HAL_RX_GET_MAC_ADDR1_VALID(rx_mpdu_start) \ 259 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_2, MAC_ADDR_AD1_VALID) 260 261 #define HAL_RX_GET_MAC_ADDR2_VALID(rx_mpdu_start) \ 262 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_2, MAC_ADDR_AD2_VALID) 263 264 #define HAL_RX_GET_FILTER_CATEGORY(rx_mpdu_start) \ 265 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_0, RXPCU_MPDU_FILTER_IN_CATEGORY) 266 267 #define HAL_RX_GET_PPDU_ID(rx_mpdu_start) \ 268 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_0, PHY_PPDU_ID) 269 270 #define HAL_RX_GET_SW_FRAME_GROUP_ID(rx_mpdu_start) \ 271 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_0, SW_FRAME_GROUP_ID) 272 273 #define HAL_RX_GET_SW_PEER_ID(rx_mpdu_start) \ 274 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_1, SW_PEER_ID) 275 276 #define HAL_REO_R0_CONFIG(soc, reg_val, reo_params) \ 277 do { \ 278 (reg_val) &= \ 279 ~(HWIO_REO_R0_GENERAL_ENABLE_FRAGMENT_DEST_RING_BMSK |\ 280 HWIO_REO_R0_GENERAL_ENABLE_AGING_LIST_ENABLE_BMSK |\ 281 HWIO_REO_R0_GENERAL_ENABLE_AGING_FLUSH_ENABLE_BMSK);\ 282 (reg_val) |= \ 283 HAL_SM(HWIO_REO_R0_GENERAL_ENABLE, \ 284 FRAGMENT_DEST_RING, \ 285 (reo_params)->frag_dst_ring) | \ 286 HAL_SM(HWIO_REO_R0_GENERAL_ENABLE, \ 287 AGING_LIST_ENABLE, 1) |\ 288 HAL_SM(HWIO_REO_R0_GENERAL_ENABLE, \ 289 AGING_FLUSH_ENABLE, 1);\ 290 HAL_REG_WRITE((soc), \ 291 HWIO_REO_R0_GENERAL_ENABLE_ADDR( \ 292 SEQ_WCSS_UMAC_REO_REG_OFFSET), \ 293 (reg_val)); \ 294 } while (0) 295 296 #define HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr) \ 297 ((struct rx_msdu_desc_info *) \ 298 _OFFSET_TO_BYTE_PTR(msdu_details_ptr, \ 299 UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET)) 300 301 #define HAL_RX_LINK_DESC_MSDU0_PTR(link_desc) \ 302 ((struct rx_msdu_details *) \ 303 _OFFSET_TO_BYTE_PTR((link_desc),\ 304 UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET)) 305 306 #define HAL_RX_MSDU_END_FLOW_IDX_GET(_rx_msdu_end) \ 307 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 308 RX_MSDU_END_14_FLOW_IDX_OFFSET)), \ 309 RX_MSDU_END_14_FLOW_IDX_MASK, \ 310 RX_MSDU_END_14_FLOW_IDX_LSB)) 311 312 #define HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(_rx_msdu_end) \ 313 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 314 RX_MSDU_END_5_FLOW_IDX_INVALID_OFFSET)), \ 315 RX_MSDU_END_5_FLOW_IDX_INVALID_MASK, \ 316 RX_MSDU_END_5_FLOW_IDX_INVALID_LSB)) 317 318 #define HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(_rx_msdu_end) \ 319 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 320 RX_MSDU_END_5_FLOW_IDX_TIMEOUT_OFFSET)), \ 321 RX_MSDU_END_5_FLOW_IDX_TIMEOUT_MASK, \ 322 RX_MSDU_END_5_FLOW_IDX_TIMEOUT_LSB)) 323 324 #define HAL_RX_MSDU_END_FSE_METADATA_GET(_rx_msdu_end) \ 325 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 326 RX_MSDU_END_15_FSE_METADATA_OFFSET)), \ 327 RX_MSDU_END_15_FSE_METADATA_MASK, \ 328 RX_MSDU_END_15_FSE_METADATA_LSB)) 329 330 #define HAL_RX_MSDU_END_CCE_METADATA_GET(_rx_msdu_end) \ 331 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 332 RX_MSDU_END_16_CCE_METADATA_OFFSET)), \ 333 RX_MSDU_END_16_CCE_METADATA_MASK, \ 334 RX_MSDU_END_16_CCE_METADATA_LSB)) 335 336 #define HAL_RX_TLV_GET_TCP_CHKSUM(buf) \ 337 (_HAL_MS( \ 338 (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ 339 msdu_end_tlv.rx_msdu_end), \ 340 RX_MSDU_END_1_TCP_UDP_CHKSUM_OFFSET)), \ 341 RX_MSDU_END_1_TCP_UDP_CHKSUM_MASK, \ 342 RX_MSDU_END_1_TCP_UDP_CHKSUM_LSB)) 343 344 #if defined(QCA_WIFI_QCA6290_11AX) 345 #define HAL_RX_MSDU_START_MIMO_SS_BITMAP(_rx_msdu_start)\ 346 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start),\ 347 RX_MSDU_START_5_MIMO_SS_BITMAP_OFFSET)), \ 348 RX_MSDU_START_5_MIMO_SS_BITMAP_MASK, \ 349 RX_MSDU_START_5_MIMO_SS_BITMAP_LSB)) 350 351 /* 352 * hal_rx_msdu_start_nss_get_6290(): API to get the NSS 353 * Interval from rx_msdu_start 354 * 355 * @buf: pointer to the start of RX PKT TLV header 356 * Return: uint32_t(nss) 357 */ 358 static uint32_t 359 hal_rx_msdu_start_nss_get_6290(uint8_t *buf) 360 { 361 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 362 struct rx_msdu_start *msdu_start = 363 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 364 uint8_t mimo_ss_bitmap; 365 366 mimo_ss_bitmap = HAL_RX_MSDU_START_MIMO_SS_BITMAP(msdu_start); 367 368 return qdf_get_hweight8(mimo_ss_bitmap); 369 } 370 #else 371 static uint32_t 372 hal_rx_msdu_start_nss_get_6290(uint8_t *buf) 373 { 374 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 375 struct rx_msdu_start *msdu_start = 376 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 377 uint32_t nss; 378 379 nss = HAL_RX_MSDU_START_NSS_GET(msdu_start); 380 return nss; 381 } 382 #endif 383 384 /** 385 * hal_rx_mon_hw_desc_get_mpdu_status_6290(): Retrieve MPDU status 386 * 387 * @ hw_desc_addr: Start address of Rx HW TLVs 388 * @ rs: Status for monitor mode 389 * 390 * Return: void 391 */ 392 static void hal_rx_mon_hw_desc_get_mpdu_status_6290(void *hw_desc_addr, 393 struct mon_rx_status *rs) 394 { 395 struct rx_msdu_start *rx_msdu_start; 396 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr; 397 uint32_t reg_value; 398 const uint32_t sgi_hw_to_cdp[] = { 399 CDP_SGI_0_8_US, 400 CDP_SGI_0_4_US, 401 CDP_SGI_1_6_US, 402 CDP_SGI_3_2_US, 403 }; 404 405 rx_msdu_start = &rx_desc->msdu_start_tlv.rx_msdu_start; 406 407 HAL_RX_GET_MSDU_AGGREGATION(rx_desc, rs); 408 409 rs->ant_signal_db = HAL_RX_GET(rx_msdu_start, 410 RX_MSDU_START_5, USER_RSSI); 411 rs->is_stbc = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, STBC); 412 413 reg_value = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, SGI); 414 rs->sgi = sgi_hw_to_cdp[reg_value]; 415 #if !defined(QCA_WIFI_QCA6290_11AX) 416 rs->nr_ant = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, NSS); 417 #endif 418 reg_value = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, RECEPTION_TYPE); 419 rs->beamformed = (reg_value == HAL_RX_RECEPTION_TYPE_MU_MIMO) ? 1 : 0; 420 /* TODO: rs->beamformed should be set for SU beamforming also */ 421 } 422 423 #define LINK_DESC_SIZE (NUM_OF_DWORDS_RX_MSDU_LINK << 2) 424 425 static uint32_t hal_get_link_desc_size_6290(void) 426 { 427 return LINK_DESC_SIZE; 428 } 429 430 431 #ifdef QCA_WIFI_QCA6290_11AX 432 /* 433 * hal_rx_get_tlv_6290(): API to get the tlv 434 * 435 * @rx_tlv: TLV data extracted from the rx packet 436 * Return: uint8_t 437 */ 438 static uint8_t hal_rx_get_tlv_6290(void *rx_tlv) 439 { 440 return HAL_RX_GET(rx_tlv, PHYRX_RSSI_LEGACY_0, RECEIVE_BANDWIDTH); 441 } 442 #else 443 static uint8_t hal_rx_get_tlv_6290(void *rx_tlv) 444 { 445 return HAL_RX_GET(rx_tlv, PHYRX_RSSI_LEGACY_35, RECEIVE_BANDWIDTH); 446 } 447 #endif 448 449 #ifdef QCA_WIFI_QCA6290_11AX 450 /** 451 * hal_rx_proc_phyrx_other_receive_info_tlv_6290() 452 * - process other receive info TLV 453 * @rx_tlv_hdr: pointer to TLV header 454 * @ppdu_info: pointer to ppdu_info 455 * 456 * Return: None 457 */ 458 static 459 void hal_rx_proc_phyrx_other_receive_info_tlv_6290(void *rx_tlv_hdr, 460 void *ppdu_info_handle) 461 { 462 uint32_t tlv_tag, tlv_len; 463 uint32_t temp_len, other_tlv_len, other_tlv_tag; 464 void *rx_tlv = (uint8_t *)rx_tlv_hdr + HAL_RX_TLV32_HDR_SIZE; 465 void *other_tlv_hdr = NULL; 466 void *other_tlv = NULL; 467 uint32_t ru_details_channel_0; 468 struct hal_rx_ppdu_info *ppdu_info = 469 (struct hal_rx_ppdu_info *)ppdu_info_handle; 470 471 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv_hdr); 472 tlv_len = HAL_RX_GET_USER_TLV32_LEN(rx_tlv_hdr); 473 temp_len = 0; 474 475 other_tlv_hdr = rx_tlv + HAL_RX_TLV32_HDR_SIZE; 476 477 other_tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(other_tlv_hdr); 478 other_tlv_len = HAL_RX_GET_USER_TLV32_LEN(other_tlv_hdr); 479 temp_len += other_tlv_len; 480 other_tlv = other_tlv_hdr + HAL_RX_TLV32_HDR_SIZE; 481 482 switch (other_tlv_tag) { 483 case WIFIPHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_E: 484 ru_details_channel_0 = 485 HAL_RX_GET(other_tlv, 486 PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_0, 487 RU_DETAILS_CHANNEL_0); 488 489 qdf_mem_copy(ppdu_info->rx_status.he_RU, 490 &ru_details_channel_0, 491 sizeof(ppdu_info->rx_status.he_RU)); 492 493 if (ppdu_info->rx_status.bw >= HAL_FULL_RX_BW_20) { 494 ppdu_info->rx_status.he_sig_b_common_known |= 495 QDF_MON_STATUS_HE_SIG_B_COMMON_KNOWN_RU0; 496 } 497 if (ppdu_info->rx_status.bw >= HAL_FULL_RX_BW_40) { 498 ppdu_info->rx_status.he_sig_b_common_known |= 499 QDF_MON_STATUS_HE_SIG_B_COMMON_KNOWN_RU1; 500 } 501 if (ppdu_info->rx_status.bw >= HAL_FULL_RX_BW_80) { 502 ppdu_info->rx_status.he_sig_b_common_known |= 503 QDF_MON_STATUS_HE_SIG_B_COMMON_KNOWN_RU2; 504 } 505 if (ppdu_info->rx_status.bw >= HAL_FULL_RX_BW_160) { 506 ppdu_info->rx_status.he_sig_b_common_known |= 507 QDF_MON_STATUS_HE_SIG_B_COMMON_KNOWN_RU3; 508 } 509 break; 510 default: 511 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR, 512 "%s unhandled TLV type: %d, TLV len:%d", 513 __func__, other_tlv_tag, other_tlv_len); 514 break; 515 } 516 } 517 #else 518 static 519 void hal_rx_proc_phyrx_other_receive_info_tlv_6290(void *rx_tlv_hdr, 520 void *ppdu_info_handle) 521 { 522 } 523 #endif /* QCA_WIFI_QCA6290_11AX */ 524 525 /** 526 * hal_rx_dump_msdu_start_tlv_6290() : dump RX msdu_start TLV in structured 527 * human readable format. 528 * @ msdu_start: pointer the msdu_start TLV in pkt. 529 * @ dbg_level: log level. 530 * 531 * Return: void 532 */ 533 static void hal_rx_dump_msdu_start_tlv_6290(void *msdustart, 534 uint8_t dbg_level) 535 { 536 struct rx_msdu_start *msdu_start = (struct rx_msdu_start *)msdustart; 537 538 QDF_TRACE(QDF_MODULE_ID_DP, dbg_level, 539 "rx_msdu_start tlv - " 540 "rxpcu_mpdu_filter_in_category: %d " 541 "sw_frame_group_id: %d " 542 "phy_ppdu_id: %d " 543 "msdu_length: %d " 544 "ipsec_esp: %d " 545 "l3_offset: %d " 546 "ipsec_ah: %d " 547 "l4_offset: %d " 548 "msdu_number: %d " 549 "decap_format: %d " 550 "ipv4_proto: %d " 551 "ipv6_proto: %d " 552 "tcp_proto: %d " 553 "udp_proto: %d " 554 "ip_frag: %d " 555 "tcp_only_ack: %d " 556 "da_is_bcast_mcast: %d " 557 "ip4_protocol_ip6_next_header: %d " 558 "toeplitz_hash_2_or_4: %d " 559 "flow_id_toeplitz: %d " 560 "user_rssi: %d " 561 "pkt_type: %d " 562 "stbc: %d " 563 "sgi: %d " 564 "rate_mcs: %d " 565 "receive_bandwidth: %d " 566 "reception_type: %d " 567 #if !defined(QCA_WIFI_QCA6290_11AX) 568 "toeplitz_hash: %d " 569 "nss: %d " 570 #endif 571 "ppdu_start_timestamp: %d " 572 "sw_phy_meta_data: %d ", 573 msdu_start->rxpcu_mpdu_filter_in_category, 574 msdu_start->sw_frame_group_id, 575 msdu_start->phy_ppdu_id, 576 msdu_start->msdu_length, 577 msdu_start->ipsec_esp, 578 msdu_start->l3_offset, 579 msdu_start->ipsec_ah, 580 msdu_start->l4_offset, 581 msdu_start->msdu_number, 582 msdu_start->decap_format, 583 msdu_start->ipv4_proto, 584 msdu_start->ipv6_proto, 585 msdu_start->tcp_proto, 586 msdu_start->udp_proto, 587 msdu_start->ip_frag, 588 msdu_start->tcp_only_ack, 589 msdu_start->da_is_bcast_mcast, 590 msdu_start->ip4_protocol_ip6_next_header, 591 msdu_start->toeplitz_hash_2_or_4, 592 msdu_start->flow_id_toeplitz, 593 msdu_start->user_rssi, 594 msdu_start->pkt_type, 595 msdu_start->stbc, 596 msdu_start->sgi, 597 msdu_start->rate_mcs, 598 msdu_start->receive_bandwidth, 599 msdu_start->reception_type, 600 #if !defined(QCA_WIFI_QCA6290_11AX) 601 msdu_start->toeplitz_hash, 602 msdu_start->nss, 603 #endif 604 msdu_start->ppdu_start_timestamp, 605 msdu_start->sw_phy_meta_data); 606 } 607 608 /** 609 * hal_rx_dump_msdu_end_tlv_6290: dump RX msdu_end TLV in structured 610 * human readable format. 611 * @ msdu_end: pointer the msdu_end TLV in pkt. 612 * @ dbg_level: log level. 613 * 614 * Return: void 615 */ 616 static void hal_rx_dump_msdu_end_tlv_6290(void *msduend, 617 uint8_t dbg_level) 618 { 619 struct rx_msdu_end *msdu_end = (struct rx_msdu_end *)msduend; 620 621 QDF_TRACE(QDF_MODULE_ID_DP, dbg_level, 622 "rx_msdu_end tlv - " 623 "rxpcu_mpdu_filter_in_category: %d " 624 "sw_frame_group_id: %d " 625 "phy_ppdu_id: %d " 626 "ip_hdr_chksum: %d " 627 "tcp_udp_chksum: %d " 628 "key_id_octet: %d " 629 "cce_super_rule: %d " 630 "cce_classify_not_done_truncat: %d " 631 "cce_classify_not_done_cce_dis: %d " 632 "ext_wapi_pn_63_48: %d " 633 "ext_wapi_pn_95_64: %d " 634 "ext_wapi_pn_127_96: %d " 635 "reported_mpdu_length: %d " 636 "first_msdu: %d " 637 "last_msdu: %d " 638 "sa_idx_timeout: %d " 639 "da_idx_timeout: %d " 640 "msdu_limit_error: %d " 641 "flow_idx_timeout: %d " 642 "flow_idx_invalid: %d " 643 "wifi_parser_error: %d " 644 "amsdu_parser_error: %d " 645 "sa_is_valid: %d " 646 "da_is_valid: %d " 647 "da_is_mcbc: %d " 648 "l3_header_padding: %d " 649 "ipv6_options_crc: %d " 650 "tcp_seq_number: %d " 651 "tcp_ack_number: %d " 652 "tcp_flag: %d " 653 "lro_eligible: %d " 654 "window_size: %d " 655 "da_offset: %d " 656 "sa_offset: %d " 657 "da_offset_valid: %d " 658 "sa_offset_valid: %d " 659 "rule_indication_31_0: %d " 660 "rule_indication_63_32: %d " 661 "sa_idx: %d " 662 "da_idx: %d " 663 "msdu_drop: %d " 664 "reo_destination_indication: %d " 665 "flow_idx: %d " 666 "fse_metadata: %d " 667 "cce_metadata: %d " 668 "sa_sw_peer_id: %d ", 669 msdu_end->rxpcu_mpdu_filter_in_category, 670 msdu_end->sw_frame_group_id, 671 msdu_end->phy_ppdu_id, 672 msdu_end->ip_hdr_chksum, 673 msdu_end->tcp_udp_chksum, 674 msdu_end->key_id_octet, 675 msdu_end->cce_super_rule, 676 msdu_end->cce_classify_not_done_truncate, 677 msdu_end->cce_classify_not_done_cce_dis, 678 msdu_end->ext_wapi_pn_63_48, 679 msdu_end->ext_wapi_pn_95_64, 680 msdu_end->ext_wapi_pn_127_96, 681 msdu_end->reported_mpdu_length, 682 msdu_end->first_msdu, 683 msdu_end->last_msdu, 684 msdu_end->sa_idx_timeout, 685 msdu_end->da_idx_timeout, 686 msdu_end->msdu_limit_error, 687 msdu_end->flow_idx_timeout, 688 msdu_end->flow_idx_invalid, 689 msdu_end->wifi_parser_error, 690 msdu_end->amsdu_parser_error, 691 msdu_end->sa_is_valid, 692 msdu_end->da_is_valid, 693 msdu_end->da_is_mcbc, 694 msdu_end->l3_header_padding, 695 msdu_end->ipv6_options_crc, 696 msdu_end->tcp_seq_number, 697 msdu_end->tcp_ack_number, 698 msdu_end->tcp_flag, 699 msdu_end->lro_eligible, 700 msdu_end->window_size, 701 msdu_end->da_offset, 702 msdu_end->sa_offset, 703 msdu_end->da_offset_valid, 704 msdu_end->sa_offset_valid, 705 msdu_end->rule_indication_31_0, 706 msdu_end->rule_indication_63_32, 707 msdu_end->sa_idx, 708 msdu_end->da_idx, 709 msdu_end->msdu_drop, 710 msdu_end->reo_destination_indication, 711 msdu_end->flow_idx, 712 msdu_end->fse_metadata, 713 msdu_end->cce_metadata, 714 msdu_end->sa_sw_peer_id); 715 } 716 717 718 /* 719 * Get tid from RX_MPDU_START 720 */ 721 #define HAL_RX_MPDU_INFO_TID_GET(_rx_mpdu_info) \ 722 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_info), \ 723 RX_MPDU_INFO_3_TID_OFFSET)), \ 724 RX_MPDU_INFO_3_TID_MASK, \ 725 RX_MPDU_INFO_3_TID_LSB)) 726 727 static uint32_t hal_rx_mpdu_start_tid_get_6290(uint8_t *buf) 728 { 729 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 730 struct rx_mpdu_start *mpdu_start = 731 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 732 uint32_t tid; 733 734 tid = HAL_RX_MPDU_INFO_TID_GET(&mpdu_start->rx_mpdu_info_details); 735 736 return tid; 737 } 738 739 #define HAL_RX_MSDU_START_RECEPTION_TYPE_GET(_rx_msdu_start) \ 740 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start), \ 741 RX_MSDU_START_5_RECEPTION_TYPE_OFFSET)), \ 742 RX_MSDU_START_5_RECEPTION_TYPE_MASK, \ 743 RX_MSDU_START_5_RECEPTION_TYPE_LSB)) 744 745 /* 746 * hal_rx_msdu_start_reception_type_get(): API to get the reception type 747 * Interval from rx_msdu_start 748 * 749 * @buf: pointer to the start of RX PKT TLV header 750 * Return: uint32_t(reception_type) 751 */ 752 static uint32_t hal_rx_msdu_start_reception_type_get_6290(uint8_t *buf) 753 { 754 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 755 struct rx_msdu_start *msdu_start = 756 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 757 uint32_t reception_type; 758 759 reception_type = HAL_RX_MSDU_START_RECEPTION_TYPE_GET(msdu_start); 760 761 return reception_type; 762 } 763 764 #define HAL_RX_MSDU_END_DA_IDX_GET(_rx_msdu_end) \ 765 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 766 RX_MSDU_END_13_DA_IDX_OFFSET)), \ 767 RX_MSDU_END_13_DA_IDX_MASK, \ 768 RX_MSDU_END_13_DA_IDX_LSB)) 769 770 /** 771 * hal_rx_msdu_end_da_idx_get_6290: API to get da_idx 772 * from rx_msdu_end TLV 773 * 774 * @ buf: pointer to the start of RX PKT TLV headers 775 * Return: da index 776 */ 777 static uint16_t hal_rx_msdu_end_da_idx_get_6290(uint8_t *buf) 778 { 779 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 780 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 781 uint16_t da_idx; 782 783 da_idx = HAL_RX_MSDU_END_DA_IDX_GET(msdu_end); 784 785 return da_idx; 786 } 787 788