1 /* 2 * Copyright (c) 2016-2019 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 #include "qdf_util.h" 19 #include "qdf_types.h" 20 #include "qdf_lock.h" 21 #include "qdf_mem.h" 22 #include "qdf_nbuf.h" 23 #include "tcl_data_cmd.h" 24 #include "mac_tcl_reg_seq_hwioreg.h" 25 #include "phyrx_rssi_legacy.h" 26 #include "rx_msdu_start.h" 27 #include "tlv_tag_def.h" 28 #include "hal_hw_headers.h" 29 #include "hal_internal.h" 30 #include "cdp_txrx_mon_struct.h" 31 #include "qdf_trace.h" 32 #include "hal_rx.h" 33 #include "hal_tx.h" 34 #include "dp_types.h" 35 #include "hal_api_mon.h" 36 #include "phyrx_other_receive_info_ru_details.h" 37 38 #define HAL_RX_MPDU_GET_SEQUENCE_NUMBER(_rx_mpdu_info) \ 39 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 40 RX_MPDU_INFO_2_MPDU_SEQUENCE_NUMBER_OFFSET)), \ 41 RX_MPDU_INFO_2_MPDU_SEQUENCE_NUMBER_MASK, \ 42 RX_MPDU_INFO_2_MPDU_SEQUENCE_NUMBER_LSB)) 43 44 #define HAL_RX_MSDU_END_DA_IS_MCBC_GET(_rx_msdu_end) \ 45 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 46 RX_MSDU_END_5_DA_IS_MCBC_OFFSET)), \ 47 RX_MSDU_END_5_DA_IS_MCBC_MASK, \ 48 RX_MSDU_END_5_DA_IS_MCBC_LSB)) 49 50 #define HAL_RX_MSDU_END_SA_IS_VALID_GET(_rx_msdu_end) \ 51 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 52 RX_MSDU_END_5_SA_IS_VALID_OFFSET)), \ 53 RX_MSDU_END_5_SA_IS_VALID_MASK, \ 54 RX_MSDU_END_5_SA_IS_VALID_LSB)) 55 56 #define HAL_RX_MSDU_END_SA_IDX_GET(_rx_msdu_end) \ 57 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 58 RX_MSDU_END_13_SA_IDX_OFFSET)), \ 59 RX_MSDU_END_13_SA_IDX_MASK, \ 60 RX_MSDU_END_13_SA_IDX_LSB)) 61 62 #define HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(_rx_msdu_end) \ 63 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 64 RX_MSDU_END_5_L3_HEADER_PADDING_OFFSET)), \ 65 RX_MSDU_END_5_L3_HEADER_PADDING_MASK, \ 66 RX_MSDU_END_5_L3_HEADER_PADDING_LSB)) 67 68 #define HAL_RX_MPDU_ENCRYPTION_INFO_VALID(_rx_mpdu_info) \ 69 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 70 RX_MPDU_INFO_2_FRAME_ENCRYPTION_INFO_VALID_OFFSET)), \ 71 RX_MPDU_INFO_2_FRAME_ENCRYPTION_INFO_VALID_MASK, \ 72 RX_MPDU_INFO_2_FRAME_ENCRYPTION_INFO_VALID_LSB)) 73 74 #define HAL_RX_MPDU_PN_31_0_GET(_rx_mpdu_info) \ 75 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 76 RX_MPDU_INFO_4_PN_31_0_OFFSET)), \ 77 RX_MPDU_INFO_4_PN_31_0_MASK, \ 78 RX_MPDU_INFO_4_PN_31_0_LSB)) 79 80 #define HAL_RX_MPDU_PN_63_32_GET(_rx_mpdu_info) \ 81 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 82 RX_MPDU_INFO_5_PN_63_32_OFFSET)), \ 83 RX_MPDU_INFO_5_PN_63_32_MASK, \ 84 RX_MPDU_INFO_5_PN_63_32_LSB)) 85 86 #define HAL_RX_MPDU_PN_95_64_GET(_rx_mpdu_info) \ 87 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 88 RX_MPDU_INFO_6_PN_95_64_OFFSET)), \ 89 RX_MPDU_INFO_6_PN_95_64_MASK, \ 90 RX_MPDU_INFO_6_PN_95_64_LSB)) 91 92 #define HAL_RX_MPDU_PN_127_96_GET(_rx_mpdu_info) \ 93 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 94 RX_MPDU_INFO_7_PN_127_96_OFFSET)), \ 95 RX_MPDU_INFO_7_PN_127_96_MASK, \ 96 RX_MPDU_INFO_7_PN_127_96_LSB)) 97 98 #define HAL_RX_MSDU_END_FIRST_MSDU_GET(_rx_msdu_end) \ 99 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 100 RX_MSDU_END_5_FIRST_MSDU_OFFSET)), \ 101 RX_MSDU_END_5_FIRST_MSDU_MASK, \ 102 RX_MSDU_END_5_FIRST_MSDU_LSB)) 103 104 #define HAL_RX_MSDU_END_DA_IS_VALID_GET(_rx_msdu_end) \ 105 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 106 RX_MSDU_END_5_DA_IS_VALID_OFFSET)), \ 107 RX_MSDU_END_5_DA_IS_VALID_MASK, \ 108 RX_MSDU_END_5_DA_IS_VALID_LSB)) 109 110 #define HAL_RX_MSDU_END_LAST_MSDU_GET(_rx_msdu_end) \ 111 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 112 RX_MSDU_END_5_LAST_MSDU_OFFSET)), \ 113 RX_MSDU_END_5_LAST_MSDU_MASK, \ 114 RX_MSDU_END_5_LAST_MSDU_LSB)) 115 116 #define HAL_RX_MPDU_GET_MAC_AD4_VALID(_rx_mpdu_info) \ 117 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 118 RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_OFFSET)), \ 119 RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_MASK, \ 120 RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_LSB)) 121 122 #define HAL_RX_MPDU_INFO_SW_PEER_ID_GET(_rx_mpdu_info) \ 123 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_info), \ 124 RX_MPDU_INFO_1_SW_PEER_ID_OFFSET)), \ 125 RX_MPDU_INFO_1_SW_PEER_ID_MASK, \ 126 RX_MPDU_INFO_1_SW_PEER_ID_LSB)) 127 128 #define HAL_RX_MPDU_GET_TODS(_rx_mpdu_info) \ 129 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 130 RX_MPDU_INFO_2_TO_DS_OFFSET)), \ 131 RX_MPDU_INFO_2_TO_DS_MASK, \ 132 RX_MPDU_INFO_2_TO_DS_LSB)) 133 134 #define HAL_RX_MPDU_GET_FROMDS(_rx_mpdu_info) \ 135 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 136 RX_MPDU_INFO_2_FR_DS_OFFSET)), \ 137 RX_MPDU_INFO_2_FR_DS_MASK, \ 138 RX_MPDU_INFO_2_FR_DS_LSB)) 139 140 #define HAL_RX_MPDU_GET_FRAME_CONTROL_VALID(_rx_mpdu_info) \ 141 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 142 RX_MPDU_INFO_2_MPDU_FRAME_CONTROL_VALID_OFFSET)), \ 143 RX_MPDU_INFO_2_MPDU_FRAME_CONTROL_VALID_MASK, \ 144 RX_MPDU_INFO_2_MPDU_FRAME_CONTROL_VALID_LSB)) 145 146 #define HAL_RX_MPDU_MAC_ADDR_AD1_VALID_GET(_rx_mpdu_info) \ 147 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 148 RX_MPDU_INFO_2_MAC_ADDR_AD1_VALID_OFFSET)), \ 149 RX_MPDU_INFO_2_MAC_ADDR_AD1_VALID_MASK, \ 150 RX_MPDU_INFO_2_MAC_ADDR_AD1_VALID_LSB)) 151 152 #define HAL_RX_MPDU_AD1_31_0_GET(_rx_mpdu_info) \ 153 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 154 RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_OFFSET)), \ 155 RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_MASK, \ 156 RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_LSB)) 157 158 #define HAL_RX_MPDU_AD1_47_32_GET(_rx_mpdu_info) \ 159 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 160 RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_OFFSET)), \ 161 RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_MASK, \ 162 RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_LSB)) 163 164 #define HAL_RX_MPDU_MAC_ADDR_AD2_VALID_GET(_rx_mpdu_info) \ 165 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 166 RX_MPDU_INFO_2_MAC_ADDR_AD2_VALID_OFFSET)), \ 167 RX_MPDU_INFO_2_MAC_ADDR_AD2_VALID_MASK, \ 168 RX_MPDU_INFO_2_MAC_ADDR_AD2_VALID_LSB)) 169 170 #define HAL_RX_MPDU_AD2_15_0_GET(_rx_mpdu_info) \ 171 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 172 RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_OFFSET)), \ 173 RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_MASK, \ 174 RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_LSB)) 175 176 #define HAL_RX_MPDU_AD2_47_16_GET(_rx_mpdu_info) \ 177 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 178 RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_OFFSET)), \ 179 RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_MASK, \ 180 RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_LSB)) 181 182 #define HAL_RX_MPDU_MAC_ADDR_AD3_VALID_GET(_rx_mpdu_info) \ 183 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 184 RX_MPDU_INFO_2_MAC_ADDR_AD3_VALID_OFFSET)), \ 185 RX_MPDU_INFO_2_MAC_ADDR_AD3_VALID_MASK, \ 186 RX_MPDU_INFO_2_MAC_ADDR_AD3_VALID_LSB)) 187 188 #define HAL_RX_MPDU_AD3_31_0_GET(_rx_mpdu_info) \ 189 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 190 RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_OFFSET)), \ 191 RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_MASK, \ 192 RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_LSB)) 193 194 #define HAL_RX_MPDU_AD3_47_32_GET(_rx_mpdu_info) \ 195 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 196 RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_OFFSET)), \ 197 RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_MASK, \ 198 RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_LSB)) 199 200 #define HAL_RX_MPDU_MAC_ADDR_AD4_VALID_GET(_rx_mpdu_info) \ 201 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 202 RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_OFFSET)), \ 203 RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_MASK, \ 204 RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_LSB)) 205 206 #define HAL_RX_MPDU_AD4_31_0_GET(_rx_mpdu_info) \ 207 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 208 RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_OFFSET)), \ 209 RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_MASK, \ 210 RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_LSB)) 211 212 #define HAL_RX_MPDU_AD4_47_32_GET(_rx_mpdu_info) \ 213 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 214 RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_OFFSET)), \ 215 RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_MASK, \ 216 RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_LSB)) 217 218 #define HAL_RX_MPDU_GET_SEQUENCE_CONTROL_VALID(_rx_mpdu_info) \ 219 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 220 RX_MPDU_INFO_2_MPDU_SEQUENCE_CONTROL_VALID_OFFSET)), \ 221 RX_MPDU_INFO_2_MPDU_SEQUENCE_CONTROL_VALID_MASK, \ 222 RX_MPDU_INFO_2_MPDU_SEQUENCE_CONTROL_VALID_LSB)) 223 224 #define HAL_RX_MPDU_INFO_QOS_CONTROL_VALID_GET(_rx_mpdu_info) \ 225 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_info), \ 226 RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_OFFSET)), \ 227 RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_MASK, \ 228 RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_LSB)) 229 230 #define HAL_RX_MSDU_END_SA_SW_PEER_ID_GET(_rx_msdu_end) \ 231 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 232 RX_MSDU_END_16_SA_SW_PEER_ID_OFFSET)), \ 233 RX_MSDU_END_16_SA_SW_PEER_ID_MASK, \ 234 RX_MSDU_END_16_SA_SW_PEER_ID_LSB)) 235 236 #define HAL_RX_MSDU0_BUFFER_ADDR_LSB(link_desc_va) \ 237 (uint8_t *)(link_desc_va) + \ 238 RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET 239 240 #define HAL_RX_MSDU_DESC_INFO_PTR_GET(msdu0) \ 241 (uint8_t *)(msdu0) + \ 242 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET 243 244 #define HAL_ENT_MPDU_DESC_INFO(ent_ring_desc) \ 245 (uint8_t *)(ent_ring_desc) + \ 246 RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET 247 248 #define HAL_DST_MPDU_DESC_INFO(dst_ring_desc) \ 249 (uint8_t *)(dst_ring_desc) + \ 250 REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET 251 252 #define HAL_RX_GET_FC_VALID(rx_mpdu_start) \ 253 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_2, MPDU_FRAME_CONTROL_VALID) 254 255 #define HAL_RX_GET_TO_DS_FLAG(rx_mpdu_start) \ 256 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_2, TO_DS) 257 258 #define HAL_RX_GET_MAC_ADDR2_VALID(rx_mpdu_start) \ 259 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_2, MAC_ADDR_AD2_VALID) 260 261 #define HAL_RX_GET_FILTER_CATEGORY(rx_mpdu_start) \ 262 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_0, RXPCU_MPDU_FILTER_IN_CATEGORY) 263 264 #define HAL_RX_GET_PPDU_ID(rx_mpdu_start) \ 265 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_0, PHY_PPDU_ID) 266 267 #define HAL_REO_R0_CONFIG(soc, reg_val, reo_params) \ 268 do { \ 269 (reg_val) &= \ 270 ~(HWIO_REO_R0_GENERAL_ENABLE_FRAGMENT_DEST_RING_BMSK |\ 271 HWIO_REO_R0_GENERAL_ENABLE_AGING_LIST_ENABLE_BMSK |\ 272 HWIO_REO_R0_GENERAL_ENABLE_AGING_FLUSH_ENABLE_BMSK);\ 273 (reg_val) |= \ 274 HAL_SM(HWIO_REO_R0_GENERAL_ENABLE, \ 275 FRAGMENT_DEST_RING, \ 276 (reo_params)->frag_dst_ring) | \ 277 HAL_SM(HWIO_REO_R0_GENERAL_ENABLE, \ 278 AGING_LIST_ENABLE, 1) |\ 279 HAL_SM(HWIO_REO_R0_GENERAL_ENABLE, \ 280 AGING_FLUSH_ENABLE, 1);\ 281 HAL_REG_WRITE((soc), \ 282 HWIO_REO_R0_GENERAL_ENABLE_ADDR( \ 283 SEQ_WCSS_UMAC_REO_REG_OFFSET), \ 284 (reg_val)); \ 285 } while (0) 286 287 #define HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr) \ 288 ((struct rx_msdu_desc_info *) \ 289 _OFFSET_TO_BYTE_PTR(msdu_details_ptr, \ 290 UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET)) 291 292 #define HAL_RX_LINK_DESC_MSDU0_PTR(link_desc) \ 293 ((struct rx_msdu_details *) \ 294 _OFFSET_TO_BYTE_PTR((link_desc),\ 295 UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET)) 296 297 #define HAL_RX_MSDU_END_FLOW_IDX_GET(_rx_msdu_end) \ 298 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 299 RX_MSDU_END_14_FLOW_IDX_OFFSET)), \ 300 RX_MSDU_END_14_FLOW_IDX_MASK, \ 301 RX_MSDU_END_14_FLOW_IDX_LSB)) 302 303 #define HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(_rx_msdu_end) \ 304 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 305 RX_MSDU_END_5_FLOW_IDX_INVALID_OFFSET)), \ 306 RX_MSDU_END_5_FLOW_IDX_INVALID_MASK, \ 307 RX_MSDU_END_5_FLOW_IDX_INVALID_LSB)) 308 309 #define HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(_rx_msdu_end) \ 310 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 311 RX_MSDU_END_5_FLOW_IDX_TIMEOUT_OFFSET)), \ 312 RX_MSDU_END_5_FLOW_IDX_TIMEOUT_MASK, \ 313 RX_MSDU_END_5_FLOW_IDX_TIMEOUT_LSB)) 314 315 #define HAL_RX_MSDU_END_FSE_METADATA_GET(_rx_msdu_end) \ 316 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 317 RX_MSDU_END_15_FSE_METADATA_OFFSET)), \ 318 RX_MSDU_END_15_FSE_METADATA_MASK, \ 319 RX_MSDU_END_15_FSE_METADATA_LSB)) 320 321 #define HAL_RX_MSDU_END_CCE_METADATA_GET(_rx_msdu_end) \ 322 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 323 RX_MSDU_END_16_CCE_METADATA_OFFSET)), \ 324 RX_MSDU_END_16_CCE_METADATA_MASK, \ 325 RX_MSDU_END_16_CCE_METADATA_LSB)) 326 327 #define HAL_RX_TLV_GET_TCP_CHKSUM(buf) \ 328 (_HAL_MS( \ 329 (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ 330 msdu_end_tlv.rx_msdu_end), \ 331 RX_MSDU_END_1_TCP_UDP_CHKSUM_OFFSET)), \ 332 RX_MSDU_END_1_TCP_UDP_CHKSUM_MASK, \ 333 RX_MSDU_END_1_TCP_UDP_CHKSUM_LSB)) 334 335 #if defined(QCA_WIFI_QCA6290_11AX) 336 #define HAL_RX_MSDU_START_MIMO_SS_BITMAP(_rx_msdu_start)\ 337 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start),\ 338 RX_MSDU_START_5_MIMO_SS_BITMAP_OFFSET)), \ 339 RX_MSDU_START_5_MIMO_SS_BITMAP_MASK, \ 340 RX_MSDU_START_5_MIMO_SS_BITMAP_LSB)) 341 342 /* 343 * hal_rx_msdu_start_nss_get_6290(): API to get the NSS 344 * Interval from rx_msdu_start 345 * 346 * @buf: pointer to the start of RX PKT TLV header 347 * Return: uint32_t(nss) 348 */ 349 static uint32_t 350 hal_rx_msdu_start_nss_get_6290(uint8_t *buf) 351 { 352 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 353 struct rx_msdu_start *msdu_start = 354 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 355 uint8_t mimo_ss_bitmap; 356 357 mimo_ss_bitmap = HAL_RX_MSDU_START_MIMO_SS_BITMAP(msdu_start); 358 359 return qdf_get_hweight8(mimo_ss_bitmap); 360 } 361 #else 362 static uint32_t 363 hal_rx_msdu_start_nss_get_6290(uint8_t *buf) 364 { 365 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 366 struct rx_msdu_start *msdu_start = 367 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 368 uint32_t nss; 369 370 nss = HAL_RX_MSDU_START_NSS_GET(msdu_start); 371 return nss; 372 } 373 #endif 374 375 /** 376 * hal_rx_mon_hw_desc_get_mpdu_status_6290(): Retrieve MPDU status 377 * 378 * @ hw_desc_addr: Start address of Rx HW TLVs 379 * @ rs: Status for monitor mode 380 * 381 * Return: void 382 */ 383 static void hal_rx_mon_hw_desc_get_mpdu_status_6290(void *hw_desc_addr, 384 struct mon_rx_status *rs) 385 { 386 struct rx_msdu_start *rx_msdu_start; 387 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr; 388 uint32_t reg_value; 389 const uint32_t sgi_hw_to_cdp[] = { 390 CDP_SGI_0_8_US, 391 CDP_SGI_0_4_US, 392 CDP_SGI_1_6_US, 393 CDP_SGI_3_2_US, 394 }; 395 396 rx_msdu_start = &rx_desc->msdu_start_tlv.rx_msdu_start; 397 398 HAL_RX_GET_MSDU_AGGREGATION(rx_desc, rs); 399 400 rs->ant_signal_db = HAL_RX_GET(rx_msdu_start, 401 RX_MSDU_START_5, USER_RSSI); 402 rs->is_stbc = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, STBC); 403 404 reg_value = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, SGI); 405 rs->sgi = sgi_hw_to_cdp[reg_value]; 406 #if !defined(QCA_WIFI_QCA6290_11AX) 407 rs->nr_ant = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, NSS); 408 #endif 409 reg_value = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, RECEPTION_TYPE); 410 rs->beamformed = (reg_value == HAL_RX_RECEPTION_TYPE_MU_MIMO) ? 1 : 0; 411 /* TODO: rs->beamformed should be set for SU beamforming also */ 412 } 413 414 #define LINK_DESC_SIZE (NUM_OF_DWORDS_RX_MSDU_LINK << 2) 415 416 static uint32_t hal_get_link_desc_size_6290(void) 417 { 418 return LINK_DESC_SIZE; 419 } 420 421 422 #ifdef QCA_WIFI_QCA6290_11AX 423 /* 424 * hal_rx_get_tlv_6290(): API to get the tlv 425 * 426 * @rx_tlv: TLV data extracted from the rx packet 427 * Return: uint8_t 428 */ 429 static uint8_t hal_rx_get_tlv_6290(void *rx_tlv) 430 { 431 return HAL_RX_GET(rx_tlv, PHYRX_RSSI_LEGACY_0, RECEIVE_BANDWIDTH); 432 } 433 #else 434 static uint8_t hal_rx_get_tlv_6290(void *rx_tlv) 435 { 436 return HAL_RX_GET(rx_tlv, PHYRX_RSSI_LEGACY_35, RECEIVE_BANDWIDTH); 437 } 438 #endif 439 440 #ifdef QCA_WIFI_QCA6290_11AX 441 /** 442 * hal_rx_proc_phyrx_other_receive_info_tlv_6290() 443 * - process other receive info TLV 444 * @rx_tlv_hdr: pointer to TLV header 445 * @ppdu_info: pointer to ppdu_info 446 * 447 * Return: None 448 */ 449 static 450 void hal_rx_proc_phyrx_other_receive_info_tlv_6290(void *rx_tlv_hdr, 451 void *ppdu_info_handle) 452 { 453 uint32_t tlv_tag, tlv_len; 454 uint32_t temp_len, other_tlv_len, other_tlv_tag; 455 void *rx_tlv = (uint8_t *)rx_tlv_hdr + HAL_RX_TLV32_HDR_SIZE; 456 void *other_tlv_hdr = NULL; 457 void *other_tlv = NULL; 458 uint32_t ru_details_channel_0; 459 struct hal_rx_ppdu_info *ppdu_info = 460 (struct hal_rx_ppdu_info *)ppdu_info_handle; 461 462 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv_hdr); 463 tlv_len = HAL_RX_GET_USER_TLV32_LEN(rx_tlv_hdr); 464 temp_len = 0; 465 466 other_tlv_hdr = rx_tlv + HAL_RX_TLV32_HDR_SIZE; 467 468 other_tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(other_tlv_hdr); 469 other_tlv_len = HAL_RX_GET_USER_TLV32_LEN(other_tlv_hdr); 470 temp_len += other_tlv_len; 471 other_tlv = other_tlv_hdr + HAL_RX_TLV32_HDR_SIZE; 472 473 switch (other_tlv_tag) { 474 case WIFIPHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_E: 475 ru_details_channel_0 = 476 HAL_RX_GET(other_tlv, 477 PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_0, 478 RU_DETAILS_CHANNEL_0); 479 480 qdf_mem_copy(ppdu_info->rx_status.he_RU, 481 &ru_details_channel_0, 482 sizeof(ppdu_info->rx_status.he_RU)); 483 484 if (ppdu_info->rx_status.bw >= HAL_FULL_RX_BW_20) { 485 ppdu_info->rx_status.he_sig_b_common_known |= 486 QDF_MON_STATUS_HE_SIG_B_COMMON_KNOWN_RU0; 487 } 488 if (ppdu_info->rx_status.bw >= HAL_FULL_RX_BW_40) { 489 ppdu_info->rx_status.he_sig_b_common_known |= 490 QDF_MON_STATUS_HE_SIG_B_COMMON_KNOWN_RU1; 491 } 492 if (ppdu_info->rx_status.bw >= HAL_FULL_RX_BW_80) { 493 ppdu_info->rx_status.he_sig_b_common_known |= 494 QDF_MON_STATUS_HE_SIG_B_COMMON_KNOWN_RU2; 495 } 496 if (ppdu_info->rx_status.bw >= HAL_FULL_RX_BW_160) { 497 ppdu_info->rx_status.he_sig_b_common_known |= 498 QDF_MON_STATUS_HE_SIG_B_COMMON_KNOWN_RU3; 499 } 500 break; 501 default: 502 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR, 503 "%s unhandled TLV type: %d, TLV len:%d", 504 __func__, other_tlv_tag, other_tlv_len); 505 break; 506 } 507 } 508 #else 509 static 510 void hal_rx_proc_phyrx_other_receive_info_tlv_6290(void *rx_tlv_hdr, 511 void *ppdu_info_handle) 512 { 513 } 514 #endif /* QCA_WIFI_QCA6290_11AX */ 515 516 /** 517 * hal_rx_dump_msdu_start_tlv_6290() : dump RX msdu_start TLV in structured 518 * human readable format. 519 * @ msdu_start: pointer the msdu_start TLV in pkt. 520 * @ dbg_level: log level. 521 * 522 * Return: void 523 */ 524 static void hal_rx_dump_msdu_start_tlv_6290(void *msdustart, 525 uint8_t dbg_level) 526 { 527 struct rx_msdu_start *msdu_start = (struct rx_msdu_start *)msdustart; 528 529 QDF_TRACE(QDF_MODULE_ID_DP, dbg_level, 530 "rx_msdu_start tlv - " 531 "rxpcu_mpdu_filter_in_category: %d " 532 "sw_frame_group_id: %d " 533 "phy_ppdu_id: %d " 534 "msdu_length: %d " 535 "ipsec_esp: %d " 536 "l3_offset: %d " 537 "ipsec_ah: %d " 538 "l4_offset: %d " 539 "msdu_number: %d " 540 "decap_format: %d " 541 "ipv4_proto: %d " 542 "ipv6_proto: %d " 543 "tcp_proto: %d " 544 "udp_proto: %d " 545 "ip_frag: %d " 546 "tcp_only_ack: %d " 547 "da_is_bcast_mcast: %d " 548 "ip4_protocol_ip6_next_header: %d " 549 "toeplitz_hash_2_or_4: %d " 550 "flow_id_toeplitz: %d " 551 "user_rssi: %d " 552 "pkt_type: %d " 553 "stbc: %d " 554 "sgi: %d " 555 "rate_mcs: %d " 556 "receive_bandwidth: %d " 557 "reception_type: %d " 558 #if !defined(QCA_WIFI_QCA6290_11AX) 559 "toeplitz_hash: %d " 560 "nss: %d " 561 #endif 562 "ppdu_start_timestamp: %d " 563 "sw_phy_meta_data: %d ", 564 msdu_start->rxpcu_mpdu_filter_in_category, 565 msdu_start->sw_frame_group_id, 566 msdu_start->phy_ppdu_id, 567 msdu_start->msdu_length, 568 msdu_start->ipsec_esp, 569 msdu_start->l3_offset, 570 msdu_start->ipsec_ah, 571 msdu_start->l4_offset, 572 msdu_start->msdu_number, 573 msdu_start->decap_format, 574 msdu_start->ipv4_proto, 575 msdu_start->ipv6_proto, 576 msdu_start->tcp_proto, 577 msdu_start->udp_proto, 578 msdu_start->ip_frag, 579 msdu_start->tcp_only_ack, 580 msdu_start->da_is_bcast_mcast, 581 msdu_start->ip4_protocol_ip6_next_header, 582 msdu_start->toeplitz_hash_2_or_4, 583 msdu_start->flow_id_toeplitz, 584 msdu_start->user_rssi, 585 msdu_start->pkt_type, 586 msdu_start->stbc, 587 msdu_start->sgi, 588 msdu_start->rate_mcs, 589 msdu_start->receive_bandwidth, 590 msdu_start->reception_type, 591 #if !defined(QCA_WIFI_QCA6290_11AX) 592 msdu_start->toeplitz_hash, 593 msdu_start->nss, 594 #endif 595 msdu_start->ppdu_start_timestamp, 596 msdu_start->sw_phy_meta_data); 597 } 598 599 /** 600 * hal_rx_dump_msdu_end_tlv_6290: dump RX msdu_end TLV in structured 601 * human readable format. 602 * @ msdu_end: pointer the msdu_end TLV in pkt. 603 * @ dbg_level: log level. 604 * 605 * Return: void 606 */ 607 static void hal_rx_dump_msdu_end_tlv_6290(void *msduend, 608 uint8_t dbg_level) 609 { 610 struct rx_msdu_end *msdu_end = (struct rx_msdu_end *)msduend; 611 612 QDF_TRACE(QDF_MODULE_ID_DP, dbg_level, 613 "rx_msdu_end tlv - " 614 "rxpcu_mpdu_filter_in_category: %d " 615 "sw_frame_group_id: %d " 616 "phy_ppdu_id: %d " 617 "ip_hdr_chksum: %d " 618 "tcp_udp_chksum: %d " 619 "key_id_octet: %d " 620 "cce_super_rule: %d " 621 "cce_classify_not_done_truncat: %d " 622 "cce_classify_not_done_cce_dis: %d " 623 "ext_wapi_pn_63_48: %d " 624 "ext_wapi_pn_95_64: %d " 625 "ext_wapi_pn_127_96: %d " 626 "reported_mpdu_length: %d " 627 "first_msdu: %d " 628 "last_msdu: %d " 629 "sa_idx_timeout: %d " 630 "da_idx_timeout: %d " 631 "msdu_limit_error: %d " 632 "flow_idx_timeout: %d " 633 "flow_idx_invalid: %d " 634 "wifi_parser_error: %d " 635 "amsdu_parser_error: %d " 636 "sa_is_valid: %d " 637 "da_is_valid: %d " 638 "da_is_mcbc: %d " 639 "l3_header_padding: %d " 640 "ipv6_options_crc: %d " 641 "tcp_seq_number: %d " 642 "tcp_ack_number: %d " 643 "tcp_flag: %d " 644 "lro_eligible: %d " 645 "window_size: %d " 646 "da_offset: %d " 647 "sa_offset: %d " 648 "da_offset_valid: %d " 649 "sa_offset_valid: %d " 650 "rule_indication_31_0: %d " 651 "rule_indication_63_32: %d " 652 "sa_idx: %d " 653 "da_idx: %d " 654 "msdu_drop: %d " 655 "reo_destination_indication: %d " 656 "flow_idx: %d " 657 "fse_metadata: %d " 658 "cce_metadata: %d " 659 "sa_sw_peer_id: %d ", 660 msdu_end->rxpcu_mpdu_filter_in_category, 661 msdu_end->sw_frame_group_id, 662 msdu_end->phy_ppdu_id, 663 msdu_end->ip_hdr_chksum, 664 msdu_end->tcp_udp_chksum, 665 msdu_end->key_id_octet, 666 msdu_end->cce_super_rule, 667 msdu_end->cce_classify_not_done_truncate, 668 msdu_end->cce_classify_not_done_cce_dis, 669 msdu_end->ext_wapi_pn_63_48, 670 msdu_end->ext_wapi_pn_95_64, 671 msdu_end->ext_wapi_pn_127_96, 672 msdu_end->reported_mpdu_length, 673 msdu_end->first_msdu, 674 msdu_end->last_msdu, 675 msdu_end->sa_idx_timeout, 676 msdu_end->da_idx_timeout, 677 msdu_end->msdu_limit_error, 678 msdu_end->flow_idx_timeout, 679 msdu_end->flow_idx_invalid, 680 msdu_end->wifi_parser_error, 681 msdu_end->amsdu_parser_error, 682 msdu_end->sa_is_valid, 683 msdu_end->da_is_valid, 684 msdu_end->da_is_mcbc, 685 msdu_end->l3_header_padding, 686 msdu_end->ipv6_options_crc, 687 msdu_end->tcp_seq_number, 688 msdu_end->tcp_ack_number, 689 msdu_end->tcp_flag, 690 msdu_end->lro_eligible, 691 msdu_end->window_size, 692 msdu_end->da_offset, 693 msdu_end->sa_offset, 694 msdu_end->da_offset_valid, 695 msdu_end->sa_offset_valid, 696 msdu_end->rule_indication_31_0, 697 msdu_end->rule_indication_63_32, 698 msdu_end->sa_idx, 699 msdu_end->da_idx, 700 msdu_end->msdu_drop, 701 msdu_end->reo_destination_indication, 702 msdu_end->flow_idx, 703 msdu_end->fse_metadata, 704 msdu_end->cce_metadata, 705 msdu_end->sa_sw_peer_id); 706 } 707 708 709 /* 710 * Get tid from RX_MPDU_START 711 */ 712 #define HAL_RX_MPDU_INFO_TID_GET(_rx_mpdu_info) \ 713 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_info), \ 714 RX_MPDU_INFO_3_TID_OFFSET)), \ 715 RX_MPDU_INFO_3_TID_MASK, \ 716 RX_MPDU_INFO_3_TID_LSB)) 717 718 static uint32_t hal_rx_mpdu_start_tid_get_6290(uint8_t *buf) 719 { 720 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 721 struct rx_mpdu_start *mpdu_start = 722 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 723 uint32_t tid; 724 725 tid = HAL_RX_MPDU_INFO_TID_GET(&mpdu_start->rx_mpdu_info_details); 726 727 return tid; 728 } 729 730 #define HAL_RX_MSDU_START_RECEPTION_TYPE_GET(_rx_msdu_start) \ 731 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start), \ 732 RX_MSDU_START_5_RECEPTION_TYPE_OFFSET)), \ 733 RX_MSDU_START_5_RECEPTION_TYPE_MASK, \ 734 RX_MSDU_START_5_RECEPTION_TYPE_LSB)) 735 736 /* 737 * hal_rx_msdu_start_reception_type_get(): API to get the reception type 738 * Interval from rx_msdu_start 739 * 740 * @buf: pointer to the start of RX PKT TLV header 741 * Return: uint32_t(reception_type) 742 */ 743 static uint32_t hal_rx_msdu_start_reception_type_get_6290(uint8_t *buf) 744 { 745 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 746 struct rx_msdu_start *msdu_start = 747 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 748 uint32_t reception_type; 749 750 reception_type = HAL_RX_MSDU_START_RECEPTION_TYPE_GET(msdu_start); 751 752 return reception_type; 753 } 754 755 #define HAL_RX_MSDU_END_DA_IDX_GET(_rx_msdu_end) \ 756 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 757 RX_MSDU_END_13_DA_IDX_OFFSET)), \ 758 RX_MSDU_END_13_DA_IDX_MASK, \ 759 RX_MSDU_END_13_DA_IDX_LSB)) 760 761 /** 762 * hal_rx_msdu_end_da_idx_get_6290: API to get da_idx 763 * from rx_msdu_end TLV 764 * 765 * @ buf: pointer to the start of RX PKT TLV headers 766 * Return: da index 767 */ 768 static uint16_t hal_rx_msdu_end_da_idx_get_6290(uint8_t *buf) 769 { 770 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 771 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 772 uint16_t da_idx; 773 774 da_idx = HAL_RX_MSDU_END_DA_IDX_GET(msdu_end); 775 776 return da_idx; 777 } 778 779