1 /* 2 * Copyright (c) 2016-2020 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 #include "qdf_types.h" 19 #include "qdf_util.h" 20 #include "qdf_types.h" 21 #include "qdf_lock.h" 22 #include "qdf_mem.h" 23 #include "qdf_nbuf.h" 24 #include "hal_hw_headers.h" 25 #include "hal_internal.h" 26 #include "hal_api.h" 27 #include "target_type.h" 28 #include "wcss_version.h" 29 #include "qdf_module.h" 30 31 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_OFFSET \ 32 RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_OFFSET 33 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_MASK \ 34 RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_MASK 35 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_LSB \ 36 RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_LSB 37 #define UNIFIED_PHYRX_HT_SIG_0_HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS_OFFSET \ 38 PHYRX_HT_SIG_0_HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS_OFFSET 39 #define UNIFIED_PHYRX_L_SIG_B_0_L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS_OFFSET \ 40 PHYRX_L_SIG_B_0_L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS_OFFSET 41 #define UNIFIED_PHYRX_L_SIG_A_0_L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS_OFFSET \ 42 PHYRX_L_SIG_A_0_L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS_OFFSET 43 #define UNIFIED_PHYRX_VHT_SIG_A_0_VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS_OFFSET \ 44 PHYRX_VHT_SIG_A_0_VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS_OFFSET 45 #define UNIFIED_PHYRX_HE_SIG_A_SU_0_HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS_OFFSET \ 46 PHYRX_HE_SIG_A_SU_0_HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS_OFFSET 47 #define UNIFIED_PHYRX_HE_SIG_A_MU_DL_0_HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_OFFSET \ 48 PHYRX_HE_SIG_A_MU_DL_0_HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_OFFSET 49 #define UNIFIED_PHYRX_HE_SIG_B1_MU_0_HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_OFFSET \ 50 PHYRX_HE_SIG_B1_MU_0_HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_OFFSET 51 #define UNIFIED_PHYRX_HE_SIG_B2_MU_0_HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_OFFSET \ 52 PHYRX_HE_SIG_B2_MU_0_HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_OFFSET 53 #define UNIFIED_PHYRX_HE_SIG_B2_OFDMA_0_HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_OFFSET \ 54 PHYRX_HE_SIG_B2_OFDMA_0_HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_OFFSET 55 #define UNIFIED_PHYRX_RSSI_LEGACY_3_RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS_OFFSET \ 56 PHYRX_RSSI_LEGACY_3_RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS_OFFSET 57 #define UNIFIED_PHYRX_RSSI_LEGACY_19_RECEIVE_RSSI_INFO_PREAMBLE_RSSI_INFO_DETAILS_OFFSET \ 58 PHYRX_RSSI_LEGACY_19_RECEIVE_RSSI_INFO_PREAMBLE_RSSI_INFO_DETAILS_OFFSET 59 #define UNIFIED_RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET \ 60 RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET 61 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 62 RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET 63 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ 64 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET 65 #define UNIFIED_RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 66 RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET 67 #define UNIFIED_REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 68 REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET 69 #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC \ 70 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER 71 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ 72 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET 73 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 74 RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET 75 #define UNIFIED_TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 76 TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET 77 #define UNIFIED_TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 78 TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET 79 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET \ 80 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET 81 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB \ 82 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB 83 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK \ 84 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK 85 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB \ 86 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB 87 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK \ 88 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK 89 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB \ 90 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB 91 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK \ 92 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK 93 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB \ 94 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB 95 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK \ 96 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK 97 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB \ 98 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB 99 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK \ 100 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK 101 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_MASK \ 102 WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_MASK 103 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_OFFSET \ 104 WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_OFFSET 105 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_LSB \ 106 WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_LSB 107 108 #include "hal_6290_tx.h" 109 #include "hal_6290_rx.h" 110 #include <hal_generic_api.h> 111 #include <hal_wbm.h> 112 113 /** 114 * hal_rx_get_rx_fragment_number_6290(): Function to retrieve rx fragment number 115 * 116 * @nbuf: Network buffer 117 * Returns: rx fragment number 118 */ 119 static 120 uint8_t hal_rx_get_rx_fragment_number_6290(uint8_t *buf) 121 { 122 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 123 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 124 125 /* Return first 4 bits as fragment number */ 126 return (HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info) & 127 DOT11_SEQ_FRAG_MASK); 128 } 129 130 /** 131 * hal_rx_msdu_end_da_is_mcbc_get: API to check if pkt is MCBC 132 * from rx_msdu_end TLV 133 * 134 * @ buf: pointer to the start of RX PKT TLV headers 135 * Return: da_is_mcbc 136 */ 137 static inline uint8_t 138 hal_rx_msdu_end_da_is_mcbc_get_6290(uint8_t *buf) 139 { 140 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 141 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 142 143 return HAL_RX_MSDU_END_DA_IS_MCBC_GET(msdu_end); 144 } 145 146 /** 147 * hal_rx_msdu_end_sa_is_valid_get_6290(): API to get_6290 the 148 * sa_is_valid bit from rx_msdu_end TLV 149 * 150 * @ buf: pointer to the start of RX PKT TLV headers 151 * Return: sa_is_valid bit 152 */ 153 static uint8_t 154 hal_rx_msdu_end_sa_is_valid_get_6290(uint8_t *buf) 155 { 156 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 157 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 158 uint8_t sa_is_valid; 159 160 sa_is_valid = HAL_RX_MSDU_END_SA_IS_VALID_GET(msdu_end); 161 162 return sa_is_valid; 163 } 164 165 /** 166 * hal_rx_msdu_end_sa_idx_get_6290(): API to get_6290 the 167 * sa_idx from rx_msdu_end TLV 168 * 169 * @ buf: pointer to the start of RX PKT TLV headers 170 * Return: sa_idx (SA AST index) 171 */ 172 static 173 uint16_t hal_rx_msdu_end_sa_idx_get_6290(uint8_t *buf) 174 { 175 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 176 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 177 uint16_t sa_idx; 178 179 sa_idx = HAL_RX_MSDU_END_SA_IDX_GET(msdu_end); 180 181 return sa_idx; 182 } 183 184 /** 185 * hal_rx_desc_is_first_msdu_6290() - Check if first msdu 186 * 187 * @hal_soc_hdl: hal_soc handle 188 * @hw_desc_addr: hardware descriptor address 189 * 190 * Return: 0 - success/ non-zero failure 191 */ 192 static uint32_t hal_rx_desc_is_first_msdu_6290(void *hw_desc_addr) 193 { 194 struct rx_pkt_tlvs *rx_tlvs = (struct rx_pkt_tlvs *)hw_desc_addr; 195 struct rx_msdu_end *msdu_end = &rx_tlvs->msdu_end_tlv.rx_msdu_end; 196 197 return HAL_RX_GET(msdu_end, RX_MSDU_END_5, FIRST_MSDU); 198 } 199 200 /** 201 * hal_rx_msdu_end_l3_hdr_padding_get_6290(): API to get_6290 the 202 * l3_header padding from rx_msdu_end TLV 203 * 204 * @ buf: pointer to the start of RX PKT TLV headers 205 * Return: number of l3 header padding bytes 206 */ 207 static uint32_t hal_rx_msdu_end_l3_hdr_padding_get_6290(uint8_t *buf) 208 { 209 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 210 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 211 uint32_t l3_header_padding; 212 213 l3_header_padding = HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(msdu_end); 214 215 return l3_header_padding; 216 } 217 218 /* 219 * @ hal_rx_encryption_info_valid_6290: Returns encryption type. 220 * 221 * @ buf: rx_tlv_hdr of the received packet 222 * @ Return: encryption type 223 */ 224 static uint32_t hal_rx_encryption_info_valid_6290(uint8_t *buf) 225 { 226 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 227 struct rx_mpdu_start *mpdu_start = 228 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 229 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 230 uint32_t encryption_info = HAL_RX_MPDU_ENCRYPTION_INFO_VALID(mpdu_info); 231 232 return encryption_info; 233 } 234 235 /* 236 * hal_rx_print_pn_6290: Prints the PN of rx packet. 237 * @buf: rx_tlv_hdr of the received packet 238 * 239 * Return: void 240 */ 241 static void hal_rx_print_pn_6290(uint8_t *buf) 242 { 243 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 244 struct rx_mpdu_start *mpdu_start = 245 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 246 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 247 248 uint32_t pn_31_0 = HAL_RX_MPDU_PN_31_0_GET(mpdu_info); 249 uint32_t pn_63_32 = HAL_RX_MPDU_PN_63_32_GET(mpdu_info); 250 uint32_t pn_95_64 = HAL_RX_MPDU_PN_95_64_GET(mpdu_info); 251 uint32_t pn_127_96 = HAL_RX_MPDU_PN_127_96_GET(mpdu_info); 252 253 hal_debug("PN number pn_127_96 0x%x pn_95_64 0x%x pn_63_32 0x%x pn_31_0 0x%x ", 254 pn_127_96, pn_95_64, pn_63_32, pn_31_0); 255 } 256 257 /** 258 * hal_rx_msdu_end_first_msdu_get_6290: API to get first msdu status 259 * from rx_msdu_end TLV 260 * 261 * @buf: pointer to the start of RX PKT TLV headers 262 * Return: first_msdu 263 */ 264 static uint8_t 265 hal_rx_msdu_end_first_msdu_get_6290(uint8_t *buf) 266 { 267 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 268 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 269 uint8_t first_msdu; 270 271 first_msdu = HAL_RX_MSDU_END_FIRST_MSDU_GET(msdu_end); 272 273 return first_msdu; 274 } 275 276 /** 277 * hal_rx_msdu_end_da_is_valid_get_6290: API to check if da is valid 278 * from rx_msdu_end TLV 279 * 280 * @ buf: pointer to the start of RX PKT TLV headers 281 * Return: da_is_valid 282 */ 283 static uint8_t hal_rx_msdu_end_da_is_valid_get_6290(uint8_t *buf) 284 { 285 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 286 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 287 uint8_t da_is_valid; 288 289 da_is_valid = HAL_RX_MSDU_END_DA_IS_VALID_GET(msdu_end); 290 291 return da_is_valid; 292 } 293 294 /** 295 * hal_rx_msdu_end_last_msdu_get_6290: API to get last msdu status 296 * from rx_msdu_end TLV 297 * 298 * @ buf: pointer to the start of RX PKT TLV headers 299 * Return: last_msdu 300 */ 301 static uint8_t hal_rx_msdu_end_last_msdu_get_6290(uint8_t *buf) 302 { 303 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 304 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 305 uint8_t last_msdu; 306 307 last_msdu = HAL_RX_MSDU_END_LAST_MSDU_GET(msdu_end); 308 309 return last_msdu; 310 } 311 312 /* 313 * hal_rx_get_mpdu_mac_ad4_valid_6290(): Retrieves if mpdu 4th addr is valid 314 * 315 * @nbuf: Network buffer 316 * Returns: value of mpdu 4th address valid field 317 */ 318 static bool hal_rx_get_mpdu_mac_ad4_valid_6290(uint8_t *buf) 319 { 320 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 321 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 322 bool ad4_valid = 0; 323 324 ad4_valid = HAL_RX_MPDU_GET_MAC_AD4_VALID(rx_mpdu_info); 325 326 return ad4_valid; 327 } 328 329 /** 330 * hal_rx_mpdu_start_sw_peer_id_get_6290: Retrieve sw peer_id 331 * @buf: network buffer 332 * 333 * Return: sw peer_id: 334 */ 335 static uint32_t hal_rx_mpdu_start_sw_peer_id_get_6290(uint8_t *buf) 336 { 337 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 338 struct rx_mpdu_start *mpdu_start = 339 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 340 341 return HAL_RX_MPDU_INFO_SW_PEER_ID_GET( 342 &mpdu_start->rx_mpdu_info_details); 343 } 344 345 /* 346 * hal_rx_mpdu_get_to_ds_6290(): API to get the tods info 347 * from rx_mpdu_start 348 * 349 * @buf: pointer to the start of RX PKT TLV header 350 * Return: uint32_t(to_ds) 351 */ 352 353 static uint32_t hal_rx_mpdu_get_to_ds_6290(uint8_t *buf) 354 { 355 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 356 struct rx_mpdu_start *mpdu_start = 357 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 358 359 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 360 361 return HAL_RX_MPDU_GET_TODS(mpdu_info); 362 } 363 364 /* 365 * hal_rx_mpdu_get_fr_ds_6290(): API to get the from ds info 366 * from rx_mpdu_start 367 * 368 * @buf: pointer to the start of RX PKT TLV header 369 * Return: uint32_t(fr_ds) 370 */ 371 static uint32_t hal_rx_mpdu_get_fr_ds_6290(uint8_t *buf) 372 { 373 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 374 struct rx_mpdu_start *mpdu_start = 375 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 376 377 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 378 379 return HAL_RX_MPDU_GET_FROMDS(mpdu_info); 380 } 381 382 /* 383 * hal_rx_get_mpdu_frame_control_valid_6290(): Retrieves mpdu frame 384 * control valid 385 * 386 * @nbuf: Network buffer 387 * Returns: value of frame control valid field 388 */ 389 static uint8_t hal_rx_get_mpdu_frame_control_valid_6290(uint8_t *buf) 390 { 391 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 392 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 393 394 return HAL_RX_MPDU_GET_FRAME_CONTROL_VALID(rx_mpdu_info); 395 } 396 397 /* 398 * hal_rx_mpdu_get_addr1_6290(): API to check get address1 of the mpdu 399 * 400 * @buf: pointer to the start of RX PKT TLV headera 401 * @mac_addr: pointer to mac address 402 * Return: success/failure 403 */ 404 static QDF_STATUS hal_rx_mpdu_get_addr1_6290(uint8_t *buf, uint8_t *mac_addr) 405 { 406 struct __attribute__((__packed__)) hal_addr1 { 407 uint32_t ad1_31_0; 408 uint16_t ad1_47_32; 409 }; 410 411 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 412 struct rx_mpdu_start *mpdu_start = 413 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 414 415 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 416 struct hal_addr1 *addr = (struct hal_addr1 *)mac_addr; 417 uint32_t mac_addr_ad1_valid; 418 419 mac_addr_ad1_valid = HAL_RX_MPDU_MAC_ADDR_AD1_VALID_GET(mpdu_info); 420 421 if (mac_addr_ad1_valid) { 422 addr->ad1_31_0 = HAL_RX_MPDU_AD1_31_0_GET(mpdu_info); 423 addr->ad1_47_32 = HAL_RX_MPDU_AD1_47_32_GET(mpdu_info); 424 return QDF_STATUS_SUCCESS; 425 } 426 427 return QDF_STATUS_E_FAILURE; 428 } 429 430 /* 431 * hal_rx_mpdu_get_addr2_6290(): API to check get address2 of the mpdu 432 * in the packet 433 * 434 * @buf: pointer to the start of RX PKT TLV header 435 * @mac_addr: pointer to mac address 436 * Return: success/failure 437 */ 438 static QDF_STATUS hal_rx_mpdu_get_addr2_6290(uint8_t *buf, 439 uint8_t *mac_addr) 440 { 441 struct __attribute__((__packed__)) hal_addr2 { 442 uint16_t ad2_15_0; 443 uint32_t ad2_47_16; 444 }; 445 446 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 447 struct rx_mpdu_start *mpdu_start = 448 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 449 450 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 451 struct hal_addr2 *addr = (struct hal_addr2 *)mac_addr; 452 uint32_t mac_addr_ad2_valid; 453 454 mac_addr_ad2_valid = HAL_RX_MPDU_MAC_ADDR_AD2_VALID_GET(mpdu_info); 455 456 if (mac_addr_ad2_valid) { 457 addr->ad2_15_0 = HAL_RX_MPDU_AD2_15_0_GET(mpdu_info); 458 addr->ad2_47_16 = HAL_RX_MPDU_AD2_47_16_GET(mpdu_info); 459 return QDF_STATUS_SUCCESS; 460 } 461 462 return QDF_STATUS_E_FAILURE; 463 } 464 465 /* 466 * hal_rx_mpdu_get_addr3_6290(): API to get address3 of the mpdu 467 * in the packet 468 * 469 * @buf: pointer to the start of RX PKT TLV header 470 * @mac_addr: pointer to mac address 471 * Return: success/failure 472 */ 473 static QDF_STATUS hal_rx_mpdu_get_addr3_6290(uint8_t *buf, uint8_t *mac_addr) 474 { 475 struct __attribute__((__packed__)) hal_addr3 { 476 uint32_t ad3_31_0; 477 uint16_t ad3_47_32; 478 }; 479 480 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 481 struct rx_mpdu_start *mpdu_start = 482 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 483 484 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 485 struct hal_addr3 *addr = (struct hal_addr3 *)mac_addr; 486 uint32_t mac_addr_ad3_valid; 487 488 mac_addr_ad3_valid = HAL_RX_MPDU_MAC_ADDR_AD3_VALID_GET(mpdu_info); 489 490 if (mac_addr_ad3_valid) { 491 addr->ad3_31_0 = HAL_RX_MPDU_AD3_31_0_GET(mpdu_info); 492 addr->ad3_47_32 = HAL_RX_MPDU_AD3_47_32_GET(mpdu_info); 493 return QDF_STATUS_SUCCESS; 494 } 495 496 return QDF_STATUS_E_FAILURE; 497 } 498 499 /* 500 * hal_rx_mpdu_get_addr4_6290(): API to get address4 of the mpdu 501 * in the packet 502 * 503 * @buf: pointer to the start of RX PKT TLV header 504 * @mac_addr: pointer to mac address 505 * Return: success/failure 506 */ 507 static QDF_STATUS hal_rx_mpdu_get_addr4_6290(uint8_t *buf, uint8_t *mac_addr) 508 { 509 struct __attribute__((__packed__)) hal_addr4 { 510 uint32_t ad4_31_0; 511 uint16_t ad4_47_32; 512 }; 513 514 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 515 struct rx_mpdu_start *mpdu_start = 516 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 517 518 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 519 struct hal_addr4 *addr = (struct hal_addr4 *)mac_addr; 520 uint32_t mac_addr_ad4_valid; 521 522 mac_addr_ad4_valid = HAL_RX_MPDU_MAC_ADDR_AD4_VALID_GET(mpdu_info); 523 524 if (mac_addr_ad4_valid) { 525 addr->ad4_31_0 = HAL_RX_MPDU_AD4_31_0_GET(mpdu_info); 526 addr->ad4_47_32 = HAL_RX_MPDU_AD4_47_32_GET(mpdu_info); 527 return QDF_STATUS_SUCCESS; 528 } 529 530 return QDF_STATUS_E_FAILURE; 531 } 532 533 /* 534 * hal_rx_get_mpdu_sequence_control_valid_6290(): Get mpdu 535 * sequence control valid 536 * 537 * @nbuf: Network buffer 538 * Returns: value of sequence control valid field 539 */ 540 static uint8_t hal_rx_get_mpdu_sequence_control_valid_6290(uint8_t *buf) 541 { 542 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 543 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 544 545 return HAL_RX_MPDU_GET_SEQUENCE_CONTROL_VALID(rx_mpdu_info); 546 } 547 548 /** 549 * hal_rx_is_unicast_6290: check packet is unicast frame or not. 550 * 551 * @ buf: pointer to rx pkt TLV. 552 * 553 * Return: true on unicast. 554 */ 555 static bool hal_rx_is_unicast_6290(uint8_t *buf) 556 { 557 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 558 struct rx_mpdu_start *mpdu_start = 559 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 560 uint32_t grp_id; 561 uint8_t *rx_mpdu_info = (uint8_t *)&mpdu_start->rx_mpdu_info_details; 562 563 grp_id = (_HAL_MS((*_OFFSET_TO_WORD_PTR((rx_mpdu_info), 564 RX_MPDU_INFO_0_SW_FRAME_GROUP_ID_OFFSET)), 565 RX_MPDU_INFO_0_SW_FRAME_GROUP_ID_MASK, 566 RX_MPDU_INFO_0_SW_FRAME_GROUP_ID_LSB)); 567 568 return (HAL_MPDU_SW_FRAME_GROUP_UNICAST_DATA == grp_id) ? true : false; 569 } 570 571 /** 572 * hal_rx_tid_get_6290: get tid based on qos control valid. 573 * @hal_soc_hdl: hal soc handle 574 * @ buf: pointer to rx pkt TLV. 575 * 576 * Return: tid 577 */ 578 static uint32_t hal_rx_tid_get_6290(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 579 { 580 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 581 struct rx_mpdu_start *mpdu_start = 582 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 583 uint8_t *rx_mpdu_info = (uint8_t *)&mpdu_start->rx_mpdu_info_details; 584 uint8_t qos_control_valid = 585 (_HAL_MS((*_OFFSET_TO_WORD_PTR((rx_mpdu_info), 586 RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_OFFSET)), 587 RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_MASK, 588 RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_LSB)); 589 590 if (qos_control_valid) 591 return hal_rx_mpdu_start_tid_get_6290(buf); 592 593 return HAL_RX_NON_QOS_TID; 594 } 595 596 /** 597 * hal_rx_hw_desc_get_ppduid_get_6290(): retrieve ppdu id 598 * @hw_desc_addr: hw addr 599 * 600 * Return: ppdu id 601 */ 602 static uint32_t hal_rx_hw_desc_get_ppduid_get_6290(void *hw_desc_addr) 603 { 604 struct rx_mpdu_info *rx_mpdu_info; 605 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr; 606 607 rx_mpdu_info = 608 &rx_desc->mpdu_start_tlv.rx_mpdu_start.rx_mpdu_info_details; 609 610 return HAL_RX_GET(rx_mpdu_info, RX_MPDU_INFO_0, PHY_PPDU_ID); 611 } 612 613 /** 614 * hal_reo_status_get_header_6290 - Process reo desc info 615 * @d - Pointer to reo descriptior 616 * @b - tlv type info 617 * @h1 - Pointer to hal_reo_status_header where info to be stored 618 * 619 * Return - none. 620 * 621 */ 622 static void hal_reo_status_get_header_6290(uint32_t *d, int b, void *h1) 623 { 624 uint32_t val1 = 0; 625 struct hal_reo_status_header *h = 626 (struct hal_reo_status_header *)h1; 627 628 switch (b) { 629 case HAL_REO_QUEUE_STATS_STATUS_TLV: 630 val1 = d[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_0, 631 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 632 break; 633 case HAL_REO_FLUSH_QUEUE_STATUS_TLV: 634 val1 = d[HAL_OFFSET_DW(REO_FLUSH_QUEUE_STATUS_0, 635 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 636 break; 637 case HAL_REO_FLUSH_CACHE_STATUS_TLV: 638 val1 = d[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_0, 639 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 640 break; 641 case HAL_REO_UNBLK_CACHE_STATUS_TLV: 642 val1 = d[HAL_OFFSET_DW(REO_UNBLOCK_CACHE_STATUS_0, 643 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 644 break; 645 case HAL_REO_TIMOUT_LIST_STATUS_TLV: 646 val1 = d[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_0, 647 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 648 break; 649 case HAL_REO_DESC_THRES_STATUS_TLV: 650 val1 = 651 d[HAL_OFFSET_DW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0, 652 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 653 break; 654 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: 655 val1 = d[HAL_OFFSET_DW(REO_UPDATE_RX_REO_QUEUE_STATUS_0, 656 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 657 break; 658 default: 659 qdf_nofl_err("ERROR: Unknown tlv\n"); 660 break; 661 } 662 h->cmd_num = 663 HAL_GET_FIELD( 664 UNIFORM_REO_STATUS_HEADER_0, REO_STATUS_NUMBER, 665 val1); 666 h->exec_time = 667 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_0, 668 CMD_EXECUTION_TIME, val1); 669 h->status = 670 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_0, 671 REO_CMD_EXECUTION_STATUS, val1); 672 switch (b) { 673 case HAL_REO_QUEUE_STATS_STATUS_TLV: 674 val1 = d[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_1, 675 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 676 break; 677 case HAL_REO_FLUSH_QUEUE_STATUS_TLV: 678 val1 = d[HAL_OFFSET_DW(REO_FLUSH_QUEUE_STATUS_1, 679 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 680 break; 681 case HAL_REO_FLUSH_CACHE_STATUS_TLV: 682 val1 = d[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_1, 683 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 684 break; 685 case HAL_REO_UNBLK_CACHE_STATUS_TLV: 686 val1 = d[HAL_OFFSET_DW(REO_UNBLOCK_CACHE_STATUS_1, 687 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 688 break; 689 case HAL_REO_TIMOUT_LIST_STATUS_TLV: 690 val1 = d[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_1, 691 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 692 break; 693 case HAL_REO_DESC_THRES_STATUS_TLV: 694 val1 = 695 d[HAL_OFFSET_DW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_1, 696 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 697 break; 698 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: 699 val1 = d[HAL_OFFSET_DW(REO_UPDATE_RX_REO_QUEUE_STATUS_1, 700 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 701 break; 702 default: 703 qdf_nofl_err("ERROR: Unknown tlv\n"); 704 break; 705 } 706 h->tstamp = 707 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_1, TIMESTAMP, val1); 708 } 709 710 /** 711 * hal_rx_mpdu_start_mpdu_qos_control_valid_get_6290(): 712 * Retrieve qos control valid bit from the tlv. 713 * @buf: pointer to rx pkt TLV. 714 * 715 * Return: qos control value. 716 */ 717 static inline uint32_t 718 hal_rx_mpdu_start_mpdu_qos_control_valid_get_6290(uint8_t *buf) 719 { 720 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 721 struct rx_mpdu_start *mpdu_start = 722 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 723 724 return HAL_RX_MPDU_INFO_QOS_CONTROL_VALID_GET( 725 &mpdu_start->rx_mpdu_info_details); 726 } 727 728 /** 729 * hal_rx_msdu_end_sa_sw_peer_id_get_6290(): API to get the 730 * sa_sw_peer_id from rx_msdu_end TLV 731 * @buf: pointer to the start of RX PKT TLV headers 732 * 733 * Return: sa_sw_peer_id index 734 */ 735 static inline uint32_t 736 hal_rx_msdu_end_sa_sw_peer_id_get_6290(uint8_t *buf) 737 { 738 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 739 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 740 741 return HAL_RX_MSDU_END_SA_SW_PEER_ID_GET(msdu_end); 742 } 743 744 /** 745 * hal_tx_desc_set_mesh_en_6290 - Set mesh_enable flag in Tx descriptor 746 * @desc: Handle to Tx Descriptor 747 * @en: For raw WiFi frames, this indicates transmission to a mesh STA, 748 * enabling the interpretation of the 'Mesh Control Present' bit 749 * (bit 8) of QoS Control (otherwise this bit is ignored), 750 * For native WiFi frames, this indicates that a 'Mesh Control' field 751 * is present between the header and the LLC. 752 * 753 * Return: void 754 */ 755 static inline 756 void hal_tx_desc_set_mesh_en_6290(void *desc, uint8_t en) 757 { 758 HAL_SET_FLD(desc, TCL_DATA_CMD_4, MESH_ENABLE) |= 759 HAL_TX_SM(TCL_DATA_CMD_4, MESH_ENABLE, en); 760 } 761 762 static 763 void *hal_rx_msdu0_buffer_addr_lsb_6290(void *link_desc_va) 764 { 765 return (void *)HAL_RX_MSDU0_BUFFER_ADDR_LSB(link_desc_va); 766 } 767 768 static 769 void *hal_rx_msdu_desc_info_ptr_get_6290(void *msdu0) 770 { 771 return (void *)HAL_RX_MSDU_DESC_INFO_PTR_GET(msdu0); 772 } 773 774 static 775 void *hal_ent_mpdu_desc_info_6290(void *ent_ring_desc) 776 { 777 return (void *)HAL_ENT_MPDU_DESC_INFO(ent_ring_desc); 778 } 779 780 static 781 void *hal_dst_mpdu_desc_info_6290(void *dst_ring_desc) 782 { 783 return (void *)HAL_DST_MPDU_DESC_INFO(dst_ring_desc); 784 } 785 786 static 787 uint8_t hal_rx_get_fc_valid_6290(uint8_t *buf) 788 { 789 return HAL_RX_GET_FC_VALID(buf); 790 } 791 792 static uint8_t hal_rx_get_to_ds_flag_6290(uint8_t *buf) 793 { 794 return HAL_RX_GET_TO_DS_FLAG(buf); 795 } 796 797 static uint8_t hal_rx_get_mac_addr2_valid_6290(uint8_t *buf) 798 { 799 return HAL_RX_GET_MAC_ADDR2_VALID(buf); 800 } 801 802 static uint8_t hal_rx_get_filter_category_6290(uint8_t *buf) 803 { 804 return HAL_RX_GET_FILTER_CATEGORY(buf); 805 } 806 807 static uint32_t 808 hal_rx_get_ppdu_id_6290(uint8_t *buf) 809 { 810 return HAL_RX_GET_PPDU_ID(buf); 811 } 812 813 /** 814 * hal_reo_config_6290(): Set reo config parameters 815 * @soc: hal soc handle 816 * @reg_val: value to be set 817 * @reo_params: reo parameters 818 * 819 * Return: void 820 */ 821 static 822 void hal_reo_config_6290(struct hal_soc *soc, 823 uint32_t reg_val, 824 struct hal_reo_params *reo_params) 825 { 826 HAL_REO_R0_CONFIG(soc, reg_val, reo_params); 827 } 828 829 /** 830 * hal_rx_msdu_desc_info_get_ptr_6290() - Get msdu desc info ptr 831 * @msdu_details_ptr - Pointer to msdu_details_ptr 832 * 833 * Return - Pointer to rx_msdu_desc_info structure. 834 * 835 */ 836 static void *hal_rx_msdu_desc_info_get_ptr_6290(void *msdu_details_ptr) 837 { 838 return HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr); 839 } 840 841 /** 842 * hal_rx_link_desc_msdu0_ptr_6290 - Get pointer to rx_msdu details 843 * @link_desc - Pointer to link desc 844 * 845 * Return - Pointer to rx_msdu_details structure 846 * 847 */ 848 static void *hal_rx_link_desc_msdu0_ptr_6290(void *link_desc) 849 { 850 return HAL_RX_LINK_DESC_MSDU0_PTR(link_desc); 851 } 852 853 /** 854 * hal_rx_msdu_flow_idx_get_6290: API to get flow index 855 * from rx_msdu_end TLV 856 * @buf: pointer to the start of RX PKT TLV headers 857 * 858 * Return: flow index value from MSDU END TLV 859 */ 860 static inline uint32_t hal_rx_msdu_flow_idx_get_6290(uint8_t *buf) 861 { 862 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 863 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 864 865 return HAL_RX_MSDU_END_FLOW_IDX_GET(msdu_end); 866 } 867 868 /** 869 * hal_rx_msdu_flow_idx_invalid_6290: API to get flow index invalid 870 * from rx_msdu_end TLV 871 * @buf: pointer to the start of RX PKT TLV headers 872 * 873 * Return: flow index invalid value from MSDU END TLV 874 */ 875 static bool hal_rx_msdu_flow_idx_invalid_6290(uint8_t *buf) 876 { 877 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 878 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 879 880 return HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(msdu_end); 881 } 882 883 /** 884 * hal_rx_msdu_flow_idx_timeout_6290: API to get flow index timeout 885 * from rx_msdu_end TLV 886 * @buf: pointer to the start of RX PKT TLV headers 887 * 888 * Return: flow index timeout value from MSDU END TLV 889 */ 890 static bool hal_rx_msdu_flow_idx_timeout_6290(uint8_t *buf) 891 { 892 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 893 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 894 895 return HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(msdu_end); 896 } 897 898 /** 899 * hal_rx_msdu_fse_metadata_get_6290: API to get FSE metadata 900 * from rx_msdu_end TLV 901 * @buf: pointer to the start of RX PKT TLV headers 902 * 903 * Return: fse metadata value from MSDU END TLV 904 */ 905 static uint32_t hal_rx_msdu_fse_metadata_get_6290(uint8_t *buf) 906 { 907 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 908 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 909 910 return HAL_RX_MSDU_END_FSE_METADATA_GET(msdu_end); 911 } 912 913 /** 914 * hal_rx_msdu_cce_metadata_get_6290: API to get CCE metadata 915 * from rx_msdu_end TLV 916 * @buf: pointer to the start of RX PKT TLV headers 917 * 918 * Return: cce_metadata 919 */ 920 static uint16_t 921 hal_rx_msdu_cce_metadata_get_6290(uint8_t *buf) 922 { 923 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 924 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 925 926 return HAL_RX_MSDU_END_CCE_METADATA_GET(msdu_end); 927 } 928 929 /** 930 * hal_rx_msdu_get_flow_params_6290: API to get flow index, flow index invalid 931 * and flow index timeout from rx_msdu_end TLV 932 * @buf: pointer to the start of RX PKT TLV headers 933 * @flow_invalid: pointer to return value of flow_idx_valid 934 * @flow_timeout: pointer to return value of flow_idx_timeout 935 * @flow_index: pointer to return value of flow_idx 936 * 937 * Return: none 938 */ 939 static inline void 940 hal_rx_msdu_get_flow_params_6290(uint8_t *buf, 941 bool *flow_invalid, 942 bool *flow_timeout, 943 uint32_t *flow_index) 944 { 945 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 946 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 947 948 *flow_invalid = HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(msdu_end); 949 *flow_timeout = HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(msdu_end); 950 *flow_index = HAL_RX_MSDU_END_FLOW_IDX_GET(msdu_end); 951 } 952 953 /** 954 * hal_rx_tlv_get_tcp_chksum_6290() - API to get tcp checksum 955 * @buf: rx_tlv_hdr 956 * 957 * Return: tcp checksum 958 */ 959 static uint16_t 960 hal_rx_tlv_get_tcp_chksum_6290(uint8_t *buf) 961 { 962 return HAL_RX_TLV_GET_TCP_CHKSUM(buf); 963 } 964 965 /** 966 * hal_rx_get_rx_sequence_6290(): Function to retrieve rx sequence number 967 * @nbuf: Network buffer 968 * 969 * Return: rx sequence number 970 */ 971 static 972 uint16_t hal_rx_get_rx_sequence_6290(uint8_t *buf) 973 { 974 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 975 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 976 977 return HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info); 978 } 979 980 /** 981 * hal_get_window_address_6290(): Function to get hp/tp address 982 * @hal_soc: Pointer to hal_soc 983 * @addr: address offset of register 984 * 985 * Return: modified address offset of register 986 */ 987 static inline qdf_iomem_t hal_get_window_address_6290(struct hal_soc *hal_soc, 988 qdf_iomem_t addr) 989 { 990 return addr; 991 } 992 993 struct hal_hw_txrx_ops qca6290_hal_hw_txrx_ops = { 994 /* init and setup */ 995 hal_srng_dst_hw_init_generic, 996 hal_srng_src_hw_init_generic, 997 hal_get_hw_hptp_generic, 998 hal_reo_setup_generic, 999 hal_setup_link_idle_list_generic, 1000 hal_get_window_address_6290, 1001 1002 /* tx */ 1003 hal_tx_desc_set_dscp_tid_table_id_6290, 1004 hal_tx_set_dscp_tid_map_6290, 1005 hal_tx_update_dscp_tid_6290, 1006 hal_tx_desc_set_lmac_id_6290, 1007 hal_tx_desc_set_buf_addr_generic, 1008 hal_tx_desc_set_search_type_generic, 1009 hal_tx_desc_set_search_index_generic, 1010 hal_tx_desc_set_cache_set_num_generic, 1011 hal_tx_comp_get_status_generic, 1012 hal_tx_comp_get_release_reason_generic, 1013 hal_get_wbm_internal_error_generic, 1014 hal_tx_desc_set_mesh_en_6290, 1015 /* rx */ 1016 hal_rx_msdu_start_nss_get_6290, 1017 hal_rx_mon_hw_desc_get_mpdu_status_6290, 1018 hal_rx_get_tlv_6290, 1019 hal_rx_proc_phyrx_other_receive_info_tlv_6290, 1020 hal_rx_dump_msdu_start_tlv_6290, 1021 hal_rx_dump_msdu_end_tlv_6290, 1022 hal_get_link_desc_size_6290, 1023 hal_rx_mpdu_start_tid_get_6290, 1024 hal_rx_msdu_start_reception_type_get_6290, 1025 hal_rx_msdu_end_da_idx_get_6290, 1026 hal_rx_msdu_desc_info_get_ptr_6290, 1027 hal_rx_link_desc_msdu0_ptr_6290, 1028 hal_reo_status_get_header_6290, 1029 hal_rx_status_get_tlv_info_generic, 1030 hal_rx_wbm_err_info_get_generic, 1031 hal_rx_dump_mpdu_start_tlv_generic, 1032 1033 hal_tx_set_pcp_tid_map_generic, 1034 hal_tx_update_pcp_tid_generic, 1035 hal_tx_update_tidmap_prty_generic, 1036 hal_rx_get_rx_fragment_number_6290, 1037 hal_rx_msdu_end_da_is_mcbc_get_6290, 1038 hal_rx_msdu_end_sa_is_valid_get_6290, 1039 hal_rx_msdu_end_sa_idx_get_6290, 1040 hal_rx_desc_is_first_msdu_6290, 1041 hal_rx_msdu_end_l3_hdr_padding_get_6290, 1042 hal_rx_encryption_info_valid_6290, 1043 hal_rx_print_pn_6290, 1044 hal_rx_msdu_end_first_msdu_get_6290, 1045 hal_rx_msdu_end_da_is_valid_get_6290, 1046 hal_rx_msdu_end_last_msdu_get_6290, 1047 hal_rx_get_mpdu_mac_ad4_valid_6290, 1048 hal_rx_mpdu_start_sw_peer_id_get_6290, 1049 hal_rx_mpdu_get_to_ds_6290, 1050 hal_rx_mpdu_get_fr_ds_6290, 1051 hal_rx_get_mpdu_frame_control_valid_6290, 1052 hal_rx_mpdu_get_addr1_6290, 1053 hal_rx_mpdu_get_addr2_6290, 1054 hal_rx_mpdu_get_addr3_6290, 1055 hal_rx_mpdu_get_addr4_6290, 1056 hal_rx_get_mpdu_sequence_control_valid_6290, 1057 hal_rx_is_unicast_6290, 1058 hal_rx_tid_get_6290, 1059 hal_rx_hw_desc_get_ppduid_get_6290, 1060 hal_rx_mpdu_start_mpdu_qos_control_valid_get_6290, 1061 hal_rx_msdu_end_sa_sw_peer_id_get_6290, 1062 hal_rx_msdu0_buffer_addr_lsb_6290, 1063 hal_rx_msdu_desc_info_ptr_get_6290, 1064 hal_ent_mpdu_desc_info_6290, 1065 hal_dst_mpdu_desc_info_6290, 1066 hal_rx_get_fc_valid_6290, 1067 hal_rx_get_to_ds_flag_6290, 1068 hal_rx_get_mac_addr2_valid_6290, 1069 hal_rx_get_filter_category_6290, 1070 hal_rx_get_ppdu_id_6290, 1071 hal_reo_config_6290, 1072 hal_rx_msdu_flow_idx_get_6290, 1073 hal_rx_msdu_flow_idx_invalid_6290, 1074 hal_rx_msdu_flow_idx_timeout_6290, 1075 hal_rx_msdu_fse_metadata_get_6290, 1076 hal_rx_msdu_cce_metadata_get_6290, 1077 hal_rx_msdu_get_flow_params_6290, 1078 hal_rx_tlv_get_tcp_chksum_6290, 1079 hal_rx_get_rx_sequence_6290, 1080 NULL, 1081 NULL, 1082 /* rx - msdu end fast path info fields */ 1083 hal_rx_msdu_packet_metadata_get_generic, 1084 }; 1085 1086 struct hal_hw_srng_config hw_srng_table_6290[] = { 1087 /* TODO: max_rings can populated by querying HW capabilities */ 1088 { /* REO_DST */ 1089 .start_ring_id = HAL_SRNG_REO2SW1, 1090 .max_rings = 4, 1091 .entry_size = sizeof(struct reo_destination_ring) >> 2, 1092 .lmac_ring = FALSE, 1093 .ring_dir = HAL_SRNG_DST_RING, 1094 .reg_start = { 1095 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR( 1096 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1097 HWIO_REO_R2_REO2SW1_RING_HP_ADDR( 1098 SEQ_WCSS_UMAC_REO_REG_OFFSET) 1099 }, 1100 .reg_size = { 1101 HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(0) - 1102 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(0), 1103 HWIO_REO_R2_REO2SW2_RING_HP_ADDR(0) - 1104 HWIO_REO_R2_REO2SW1_RING_HP_ADDR(0), 1105 }, 1106 .max_size = HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_BMSK >> 1107 HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_SHFT, 1108 }, 1109 { /* REO_EXCEPTION */ 1110 /* Designating REO2TCL ring as exception ring. This ring is 1111 * similar to other REO2SW rings though it is named as REO2TCL. 1112 * Any of theREO2SW rings can be used as exception ring. 1113 */ 1114 .start_ring_id = HAL_SRNG_REO2TCL, 1115 .max_rings = 1, 1116 .entry_size = sizeof(struct reo_destination_ring) >> 2, 1117 .lmac_ring = FALSE, 1118 .ring_dir = HAL_SRNG_DST_RING, 1119 .reg_start = { 1120 HWIO_REO_R0_REO2TCL_RING_BASE_LSB_ADDR( 1121 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1122 HWIO_REO_R2_REO2TCL_RING_HP_ADDR( 1123 SEQ_WCSS_UMAC_REO_REG_OFFSET) 1124 }, 1125 /* Single ring - provide ring size if multiple rings of this 1126 * type are supported 1127 */ 1128 .reg_size = {}, 1129 .max_size = HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_BMSK >> 1130 HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_SHFT, 1131 }, 1132 { /* REO_REINJECT */ 1133 .start_ring_id = HAL_SRNG_SW2REO, 1134 .max_rings = 1, 1135 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 1136 .lmac_ring = FALSE, 1137 .ring_dir = HAL_SRNG_SRC_RING, 1138 .reg_start = { 1139 HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR( 1140 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1141 HWIO_REO_R2_SW2REO_RING_HP_ADDR( 1142 SEQ_WCSS_UMAC_REO_REG_OFFSET) 1143 }, 1144 /* Single ring - provide ring size if multiple rings of this 1145 * type are supported 1146 */ 1147 .reg_size = {}, 1148 .max_size = HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_BMSK >> 1149 HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_SHFT, 1150 }, 1151 { /* REO_CMD */ 1152 .start_ring_id = HAL_SRNG_REO_CMD, 1153 .max_rings = 1, 1154 .entry_size = (sizeof(struct tlv_32_hdr) + 1155 sizeof(struct reo_get_queue_stats)) >> 2, 1156 .lmac_ring = FALSE, 1157 .ring_dir = HAL_SRNG_SRC_RING, 1158 .reg_start = { 1159 HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR( 1160 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1161 HWIO_REO_R2_REO_CMD_RING_HP_ADDR( 1162 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1163 }, 1164 /* Single ring - provide ring size if multiple rings of this 1165 * type are supported 1166 */ 1167 .reg_size = {}, 1168 .max_size = HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_BMSK >> 1169 HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_SHFT, 1170 }, 1171 { /* REO_STATUS */ 1172 .start_ring_id = HAL_SRNG_REO_STATUS, 1173 .max_rings = 1, 1174 .entry_size = (sizeof(struct tlv_32_hdr) + 1175 sizeof(struct reo_get_queue_stats_status)) >> 2, 1176 .lmac_ring = FALSE, 1177 .ring_dir = HAL_SRNG_DST_RING, 1178 .reg_start = { 1179 HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR( 1180 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1181 HWIO_REO_R2_REO_STATUS_RING_HP_ADDR( 1182 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1183 }, 1184 /* Single ring - provide ring size if multiple rings of this 1185 * type are supported 1186 */ 1187 .reg_size = {}, 1188 .max_size = 1189 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> 1190 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, 1191 }, 1192 { /* TCL_DATA */ 1193 .start_ring_id = HAL_SRNG_SW2TCL1, 1194 .max_rings = 3, 1195 .entry_size = (sizeof(struct tlv_32_hdr) + 1196 sizeof(struct tcl_data_cmd)) >> 2, 1197 .lmac_ring = FALSE, 1198 .ring_dir = HAL_SRNG_SRC_RING, 1199 .reg_start = { 1200 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR( 1201 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1202 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR( 1203 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1204 }, 1205 .reg_size = { 1206 HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(0) - 1207 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(0), 1208 HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(0) - 1209 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(0), 1210 }, 1211 .max_size = HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK >> 1212 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT, 1213 }, 1214 { /* TCL_CMD */ 1215 .start_ring_id = HAL_SRNG_SW2TCL_CMD, 1216 .max_rings = 1, 1217 .entry_size = (sizeof(struct tlv_32_hdr) + 1218 sizeof(struct tcl_gse_cmd)) >> 2, 1219 .lmac_ring = FALSE, 1220 .ring_dir = HAL_SRNG_SRC_RING, 1221 .reg_start = { 1222 HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_ADDR( 1223 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1224 HWIO_TCL_R2_SW2TCL_CMD_RING_HP_ADDR( 1225 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1226 }, 1227 /* Single ring - provide ring size if multiple rings of this 1228 * type are supported 1229 */ 1230 .reg_size = {}, 1231 .max_size = 1232 HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RING_SIZE_BMSK >> 1233 HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RING_SIZE_SHFT, 1234 }, 1235 { /* TCL_STATUS */ 1236 .start_ring_id = HAL_SRNG_TCL_STATUS, 1237 .max_rings = 1, 1238 .entry_size = (sizeof(struct tlv_32_hdr) + 1239 sizeof(struct tcl_status_ring)) >> 2, 1240 .lmac_ring = FALSE, 1241 .ring_dir = HAL_SRNG_DST_RING, 1242 .reg_start = { 1243 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR( 1244 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1245 HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR( 1246 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1247 }, 1248 /* Single ring - provide ring size if multiple rings of this 1249 * type are supported 1250 */ 1251 .reg_size = {}, 1252 .max_size = 1253 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_BMSK >> 1254 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_SHFT, 1255 }, 1256 { /* CE_SRC */ 1257 .start_ring_id = HAL_SRNG_CE_0_SRC, 1258 .max_rings = 12, 1259 .entry_size = sizeof(struct ce_src_desc) >> 2, 1260 .lmac_ring = FALSE, 1261 .ring_dir = HAL_SRNG_SRC_RING, 1262 .reg_start = { 1263 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR( 1264 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET), 1265 HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR( 1266 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET), 1267 }, 1268 .reg_size = { 1269 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET - 1270 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET, 1271 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET - 1272 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET, 1273 }, 1274 .max_size = 1275 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >> 1276 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT, 1277 }, 1278 { /* CE_DST */ 1279 .start_ring_id = HAL_SRNG_CE_0_DST, 1280 .max_rings = 12, 1281 .entry_size = 8 >> 2, 1282 /*TODO: entry_size above should actually be 1283 * sizeof(struct ce_dst_desc) >> 2, but couldn't find definition 1284 * of struct ce_dst_desc in HW header files 1285 */ 1286 .lmac_ring = FALSE, 1287 .ring_dir = HAL_SRNG_SRC_RING, 1288 .reg_start = { 1289 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR( 1290 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 1291 HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR( 1292 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 1293 }, 1294 .reg_size = { 1295 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 1296 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 1297 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 1298 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 1299 }, 1300 .max_size = 1301 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >> 1302 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT, 1303 }, 1304 { /* CE_DST_STATUS */ 1305 .start_ring_id = HAL_SRNG_CE_0_DST_STATUS, 1306 .max_rings = 12, 1307 .entry_size = sizeof(struct ce_stat_desc) >> 2, 1308 .lmac_ring = FALSE, 1309 .ring_dir = HAL_SRNG_DST_RING, 1310 .reg_start = { 1311 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR( 1312 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 1313 HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR( 1314 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 1315 }, 1316 /* TODO: check destination status ring registers */ 1317 .reg_size = { 1318 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 1319 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 1320 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 1321 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 1322 }, 1323 .max_size = 1324 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> 1325 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, 1326 }, 1327 { /* WBM_IDLE_LINK */ 1328 .start_ring_id = HAL_SRNG_WBM_IDLE_LINK, 1329 .max_rings = 1, 1330 .entry_size = sizeof(struct wbm_link_descriptor_ring) >> 2, 1331 .lmac_ring = FALSE, 1332 .ring_dir = HAL_SRNG_SRC_RING, 1333 .reg_start = { 1334 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1335 HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1336 }, 1337 /* Single ring - provide ring size if multiple rings of this 1338 * type are supported 1339 */ 1340 .reg_size = {}, 1341 .max_size = 1342 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_BMSK >> 1343 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_SHFT, 1344 }, 1345 { /* SW2WBM_RELEASE */ 1346 .start_ring_id = HAL_SRNG_WBM_SW_RELEASE, 1347 .max_rings = 1, 1348 .entry_size = sizeof(struct wbm_release_ring) >> 2, 1349 .lmac_ring = FALSE, 1350 .ring_dir = HAL_SRNG_SRC_RING, 1351 .reg_start = { 1352 HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1353 HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1354 }, 1355 /* Single ring - provide ring size if multiple rings of this 1356 * type are supported 1357 */ 1358 .reg_size = {}, 1359 .max_size = 1360 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> 1361 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, 1362 }, 1363 { /* WBM2SW_RELEASE */ 1364 .start_ring_id = HAL_SRNG_WBM2SW0_RELEASE, 1365 .max_rings = 4, 1366 .entry_size = sizeof(struct wbm_release_ring) >> 2, 1367 .lmac_ring = FALSE, 1368 .ring_dir = HAL_SRNG_DST_RING, 1369 .reg_start = { 1370 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1371 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1372 }, 1373 .reg_size = { 1374 HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) - 1375 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1376 HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) - 1377 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1378 }, 1379 .max_size = 1380 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> 1381 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, 1382 }, 1383 { /* RXDMA_BUF */ 1384 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA0_BUF0, 1385 #ifdef IPA_OFFLOAD 1386 .max_rings = 3, 1387 #else 1388 .max_rings = 2, 1389 #endif 1390 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 1391 .lmac_ring = TRUE, 1392 .ring_dir = HAL_SRNG_SRC_RING, 1393 /* reg_start is not set because LMAC rings are not accessed 1394 * from host 1395 */ 1396 .reg_start = {}, 1397 .reg_size = {}, 1398 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1399 }, 1400 { /* RXDMA_DST */ 1401 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW0, 1402 .max_rings = 1, 1403 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 1404 .lmac_ring = TRUE, 1405 .ring_dir = HAL_SRNG_DST_RING, 1406 /* reg_start is not set because LMAC rings are not accessed 1407 * from host 1408 */ 1409 .reg_start = {}, 1410 .reg_size = {}, 1411 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1412 }, 1413 { /* RXDMA_MONITOR_BUF */ 1414 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA2_BUF, 1415 .max_rings = 1, 1416 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 1417 .lmac_ring = TRUE, 1418 .ring_dir = HAL_SRNG_SRC_RING, 1419 /* reg_start is not set because LMAC rings are not accessed 1420 * from host 1421 */ 1422 .reg_start = {}, 1423 .reg_size = {}, 1424 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1425 }, 1426 { /* RXDMA_MONITOR_STATUS */ 1427 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_STATBUF, 1428 .max_rings = 1, 1429 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 1430 .lmac_ring = TRUE, 1431 .ring_dir = HAL_SRNG_SRC_RING, 1432 /* reg_start is not set because LMAC rings are not accessed 1433 * from host 1434 */ 1435 .reg_start = {}, 1436 .reg_size = {}, 1437 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1438 }, 1439 { /* RXDMA_MONITOR_DST */ 1440 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW1, 1441 .max_rings = 1, 1442 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 1443 .lmac_ring = TRUE, 1444 .ring_dir = HAL_SRNG_DST_RING, 1445 /* reg_start is not set because LMAC rings are not accessed 1446 * from host 1447 */ 1448 .reg_start = {}, 1449 .reg_size = {}, 1450 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1451 }, 1452 { /* RXDMA_MONITOR_DESC */ 1453 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_DESC, 1454 .max_rings = 1, 1455 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 1456 .lmac_ring = TRUE, 1457 .ring_dir = HAL_SRNG_SRC_RING, 1458 /* reg_start is not set because LMAC rings are not accessed 1459 * from host 1460 */ 1461 .reg_start = {}, 1462 .reg_size = {}, 1463 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1464 }, 1465 { /* DIR_BUF_RX_DMA_SRC */ 1466 .start_ring_id = HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING, 1467 .max_rings = 1, 1468 .entry_size = 2, 1469 .lmac_ring = TRUE, 1470 .ring_dir = HAL_SRNG_SRC_RING, 1471 /* reg_start is not set because LMAC rings are not accessed 1472 * from host 1473 */ 1474 .reg_start = {}, 1475 .reg_size = {}, 1476 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1477 }, 1478 #ifdef WLAN_FEATURE_CIF_CFR 1479 { /* WIFI_POS_SRC */ 1480 .start_ring_id = HAL_SRNG_WIFI_POS_SRC_DMA_RING, 1481 .max_rings = 1, 1482 .entry_size = sizeof(wmi_oem_dma_buf_release_entry) >> 2, 1483 .lmac_ring = TRUE, 1484 .ring_dir = HAL_SRNG_SRC_RING, 1485 /* reg_start is not set because LMAC rings are not accessed 1486 * from host 1487 */ 1488 .reg_start = {}, 1489 .reg_size = {}, 1490 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1491 }, 1492 #endif 1493 }; 1494 1495 int32_t hal_hw_reg_offset_qca6290[] = { 1496 /* dst */ 1497 REG_OFFSET(DST, HP), 1498 REG_OFFSET(DST, TP), 1499 REG_OFFSET(DST, ID), 1500 REG_OFFSET(DST, MISC), 1501 REG_OFFSET(DST, HP_ADDR_LSB), 1502 REG_OFFSET(DST, HP_ADDR_MSB), 1503 REG_OFFSET(DST, MSI1_BASE_LSB), 1504 REG_OFFSET(DST, MSI1_BASE_MSB), 1505 REG_OFFSET(DST, MSI1_DATA), 1506 REG_OFFSET(DST, BASE_LSB), 1507 REG_OFFSET(DST, BASE_MSB), 1508 REG_OFFSET(DST, PRODUCER_INT_SETUP), 1509 /* src */ 1510 REG_OFFSET(SRC, HP), 1511 REG_OFFSET(SRC, TP), 1512 REG_OFFSET(SRC, ID), 1513 REG_OFFSET(SRC, MISC), 1514 REG_OFFSET(SRC, TP_ADDR_LSB), 1515 REG_OFFSET(SRC, TP_ADDR_MSB), 1516 REG_OFFSET(SRC, MSI1_BASE_LSB), 1517 REG_OFFSET(SRC, MSI1_BASE_MSB), 1518 REG_OFFSET(SRC, MSI1_DATA), 1519 REG_OFFSET(SRC, BASE_LSB), 1520 REG_OFFSET(SRC, BASE_MSB), 1521 REG_OFFSET(SRC, CONSUMER_INT_SETUP_IX0), 1522 REG_OFFSET(SRC, CONSUMER_INT_SETUP_IX1), 1523 }; 1524 1525 /** 1526 * hal_qca6290_attach() - Attach 6290 target specific hal_soc ops, 1527 * offset and srng table 1528 */ 1529 void hal_qca6290_attach(struct hal_soc *hal_soc) 1530 { 1531 hal_soc->hw_srng_table = hw_srng_table_6290; 1532 hal_soc->hal_hw_reg_offset = hal_hw_reg_offset_qca6290; 1533 hal_soc->ops = &qca6290_hal_hw_txrx_ops; 1534 } 1535