1 /* 2 * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved. 3 * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 #include "qdf_types.h" 20 #include "qdf_util.h" 21 #include "qdf_types.h" 22 #include "qdf_lock.h" 23 #include "qdf_mem.h" 24 #include "qdf_nbuf.h" 25 #include "hal_li_hw_headers.h" 26 #include "hal_internal.h" 27 #include "hal_api.h" 28 #include "target_type.h" 29 #include "wcss_version.h" 30 #include "qdf_module.h" 31 32 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_OFFSET \ 33 RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_OFFSET 34 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_MASK \ 35 RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_MASK 36 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_LSB \ 37 RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_LSB 38 #define UNIFIED_PHYRX_HT_SIG_0_HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS_OFFSET \ 39 PHYRX_HT_SIG_0_HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS_OFFSET 40 #define UNIFIED_PHYRX_L_SIG_B_0_L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS_OFFSET \ 41 PHYRX_L_SIG_B_0_L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS_OFFSET 42 #define UNIFIED_PHYRX_L_SIG_A_0_L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS_OFFSET \ 43 PHYRX_L_SIG_A_0_L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS_OFFSET 44 #define UNIFIED_PHYRX_VHT_SIG_A_0_VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS_OFFSET \ 45 PHYRX_VHT_SIG_A_0_VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS_OFFSET 46 #define UNIFIED_PHYRX_HE_SIG_A_SU_0_HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS_OFFSET \ 47 PHYRX_HE_SIG_A_SU_0_HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS_OFFSET 48 #define UNIFIED_PHYRX_HE_SIG_A_MU_DL_0_HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_OFFSET \ 49 PHYRX_HE_SIG_A_MU_DL_0_HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_OFFSET 50 #define UNIFIED_PHYRX_HE_SIG_B1_MU_0_HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_OFFSET \ 51 PHYRX_HE_SIG_B1_MU_0_HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_OFFSET 52 #define UNIFIED_PHYRX_HE_SIG_B2_MU_0_HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_OFFSET \ 53 PHYRX_HE_SIG_B2_MU_0_HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_OFFSET 54 #define UNIFIED_PHYRX_HE_SIG_B2_OFDMA_0_HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_OFFSET \ 55 PHYRX_HE_SIG_B2_OFDMA_0_HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_OFFSET 56 #define UNIFIED_PHYRX_RSSI_LEGACY_3_RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS_OFFSET \ 57 PHYRX_RSSI_LEGACY_3_RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS_OFFSET 58 #define UNIFIED_PHYRX_RSSI_LEGACY_19_RECEIVE_RSSI_INFO_PREAMBLE_RSSI_INFO_DETAILS_OFFSET \ 59 PHYRX_RSSI_LEGACY_19_RECEIVE_RSSI_INFO_PREAMBLE_RSSI_INFO_DETAILS_OFFSET 60 #define UNIFIED_RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET \ 61 RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET 62 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 63 RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET 64 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ 65 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET 66 #define UNIFIED_RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 67 RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET 68 #define UNIFIED_REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 69 REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET 70 #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC \ 71 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER 72 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ 73 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET 74 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 75 RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET 76 #define UNIFIED_TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 77 TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET 78 #define UNIFIED_TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 79 TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET 80 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET \ 81 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET 82 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB \ 83 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB 84 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK \ 85 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK 86 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB \ 87 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB 88 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK \ 89 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK 90 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB \ 91 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB 92 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK \ 93 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK 94 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB \ 95 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB 96 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK \ 97 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK 98 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB \ 99 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB 100 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK \ 101 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK 102 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_MASK \ 103 WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_MASK 104 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_OFFSET \ 105 WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_OFFSET 106 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_LSB \ 107 WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_LSB 108 109 #include "hal_6290_tx.h" 110 #include "hal_6290_rx.h" 111 #include <hal_generic_api.h> 112 #include "hal_li_rx.h" 113 #include "hal_li_api.h" 114 #include "hal_li_generic_api.h" 115 116 /** 117 * hal_rx_get_rx_fragment_number_6290() - API to retrieve rx fragment number 118 * @buf: Network buffer 119 * 120 * Return: rx fragment number 121 */ 122 static 123 uint8_t hal_rx_get_rx_fragment_number_6290(uint8_t *buf) 124 { 125 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 126 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 127 128 /* Return first 4 bits as fragment number */ 129 return (HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info) & 130 DOT11_SEQ_FRAG_MASK); 131 } 132 133 /** 134 * hal_rx_msdu_end_da_is_mcbc_get_6290() - API to check if pkt is MCBC 135 * from rx_msdu_end TLV 136 * @buf: pointer to the start of RX PKT TLV headers 137 * 138 * Return: da_is_mcbc 139 */ 140 static inline uint8_t 141 hal_rx_msdu_end_da_is_mcbc_get_6290(uint8_t *buf) 142 { 143 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 144 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 145 146 return HAL_RX_MSDU_END_DA_IS_MCBC_GET(msdu_end); 147 } 148 149 /** 150 * hal_rx_msdu_end_sa_is_valid_get_6290() - API to get_6290 the sa_is_valid bit 151 * from rx_msdu_end TLV 152 * @buf: pointer to the start of RX PKT TLV headers 153 * 154 * Return: sa_is_valid bit 155 */ 156 static uint8_t 157 hal_rx_msdu_end_sa_is_valid_get_6290(uint8_t *buf) 158 { 159 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 160 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 161 uint8_t sa_is_valid; 162 163 sa_is_valid = HAL_RX_MSDU_END_SA_IS_VALID_GET(msdu_end); 164 165 return sa_is_valid; 166 } 167 168 /** 169 * hal_rx_msdu_end_sa_idx_get_6290() - API to get_6290 the sa_idx from 170 * rx_msdu_end TLV 171 * @buf: pointer to the start of RX PKT TLV headers 172 * 173 * Return: sa_idx (SA AST index) 174 */ 175 static 176 uint16_t hal_rx_msdu_end_sa_idx_get_6290(uint8_t *buf) 177 { 178 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 179 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 180 uint16_t sa_idx; 181 182 sa_idx = HAL_RX_MSDU_END_SA_IDX_GET(msdu_end); 183 184 return sa_idx; 185 } 186 187 /** 188 * hal_rx_desc_is_first_msdu_6290() - Check if first msdu 189 * @hw_desc_addr: hardware descriptor address 190 * 191 * Return: 0 - success/ non-zero failure 192 */ 193 static uint32_t hal_rx_desc_is_first_msdu_6290(void *hw_desc_addr) 194 { 195 struct rx_pkt_tlvs *rx_tlvs = (struct rx_pkt_tlvs *)hw_desc_addr; 196 struct rx_msdu_end *msdu_end = &rx_tlvs->msdu_end_tlv.rx_msdu_end; 197 198 return HAL_RX_GET(msdu_end, RX_MSDU_END_5, FIRST_MSDU); 199 } 200 201 /** 202 * hal_rx_msdu_end_l3_hdr_padding_get_6290() - API to get_6290 the l3_header 203 * padding from rx_msdu_end TLV 204 * @buf: pointer to the start of RX PKT TLV headers 205 * 206 * Return: number of l3 header padding bytes 207 */ 208 static uint32_t hal_rx_msdu_end_l3_hdr_padding_get_6290(uint8_t *buf) 209 { 210 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 211 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 212 uint32_t l3_header_padding; 213 214 l3_header_padding = HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(msdu_end); 215 216 return l3_header_padding; 217 } 218 219 /** 220 * hal_rx_encryption_info_valid_6290() - Returns encryption type. 221 * @buf: rx_tlv_hdr of the received packet 222 * 223 * Return: encryption type 224 */ 225 static uint32_t hal_rx_encryption_info_valid_6290(uint8_t *buf) 226 { 227 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 228 struct rx_mpdu_start *mpdu_start = 229 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 230 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 231 uint32_t encryption_info = HAL_RX_MPDU_ENCRYPTION_INFO_VALID(mpdu_info); 232 233 return encryption_info; 234 } 235 236 /** 237 * hal_rx_print_pn_6290() - Prints the PN of rx packet. 238 * @buf: rx_tlv_hdr of the received packet 239 * 240 * Return: void 241 */ 242 static void hal_rx_print_pn_6290(uint8_t *buf) 243 { 244 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 245 struct rx_mpdu_start *mpdu_start = 246 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 247 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 248 249 uint32_t pn_31_0 = HAL_RX_MPDU_PN_31_0_GET(mpdu_info); 250 uint32_t pn_63_32 = HAL_RX_MPDU_PN_63_32_GET(mpdu_info); 251 uint32_t pn_95_64 = HAL_RX_MPDU_PN_95_64_GET(mpdu_info); 252 uint32_t pn_127_96 = HAL_RX_MPDU_PN_127_96_GET(mpdu_info); 253 254 hal_debug("PN number pn_127_96 0x%x pn_95_64 0x%x pn_63_32 0x%x pn_31_0 0x%x", 255 pn_127_96, pn_95_64, pn_63_32, pn_31_0); 256 } 257 258 /** 259 * hal_rx_msdu_end_first_msdu_get_6290() - API to get first msdu status from 260 * rx_msdu_end TLV 261 * @buf: pointer to the start of RX PKT TLV headers 262 * 263 * Return: first_msdu 264 */ 265 static uint8_t 266 hal_rx_msdu_end_first_msdu_get_6290(uint8_t *buf) 267 { 268 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 269 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 270 uint8_t first_msdu; 271 272 first_msdu = HAL_RX_MSDU_END_FIRST_MSDU_GET(msdu_end); 273 274 return first_msdu; 275 } 276 277 /** 278 * hal_rx_msdu_end_da_is_valid_get_6290() - API to check if da is valid from 279 * rx_msdu_end TLV 280 * @buf: pointer to the start of RX PKT TLV headers 281 * 282 * Return: da_is_valid 283 */ 284 static uint8_t hal_rx_msdu_end_da_is_valid_get_6290(uint8_t *buf) 285 { 286 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 287 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 288 uint8_t da_is_valid; 289 290 da_is_valid = HAL_RX_MSDU_END_DA_IS_VALID_GET(msdu_end); 291 292 return da_is_valid; 293 } 294 295 /** 296 * hal_rx_msdu_end_last_msdu_get_6290() - API to get last msdu status 297 * from rx_msdu_end TLV 298 * @buf: pointer to the start of RX PKT TLV headers 299 * 300 * Return: last_msdu 301 */ 302 static uint8_t hal_rx_msdu_end_last_msdu_get_6290(uint8_t *buf) 303 { 304 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 305 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 306 uint8_t last_msdu; 307 308 last_msdu = HAL_RX_MSDU_END_LAST_MSDU_GET(msdu_end); 309 310 return last_msdu; 311 } 312 313 /** 314 * hal_rx_get_mpdu_mac_ad4_valid_6290() - Retrieves if mpdu 4th addr is valid 315 * @buf: Network buffer 316 * 317 * Return: value of mpdu 4th address valid field 318 */ 319 static bool hal_rx_get_mpdu_mac_ad4_valid_6290(uint8_t *buf) 320 { 321 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 322 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 323 bool ad4_valid = 0; 324 325 ad4_valid = HAL_RX_MPDU_GET_MAC_AD4_VALID(rx_mpdu_info); 326 327 return ad4_valid; 328 } 329 330 /** 331 * hal_rx_mpdu_start_sw_peer_id_get_6290() - Retrieve sw peer_id 332 * @buf: network buffer 333 * 334 * Return: sw peer_id: 335 */ 336 static uint32_t hal_rx_mpdu_start_sw_peer_id_get_6290(uint8_t *buf) 337 { 338 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 339 struct rx_mpdu_start *mpdu_start = 340 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 341 342 return HAL_RX_MPDU_INFO_SW_PEER_ID_GET( 343 &mpdu_start->rx_mpdu_info_details); 344 } 345 346 /** 347 * hal_rx_mpdu_get_to_ds_6290() - API to get the tods info from rx_mpdu_start 348 * @buf: pointer to the start of RX PKT TLV header 349 * 350 * Return: uint32_t(to_ds) 351 */ 352 353 static uint32_t hal_rx_mpdu_get_to_ds_6290(uint8_t *buf) 354 { 355 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 356 struct rx_mpdu_start *mpdu_start = 357 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 358 359 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 360 361 return HAL_RX_MPDU_GET_TODS(mpdu_info); 362 } 363 364 /** 365 * hal_rx_mpdu_get_fr_ds_6290() - API to get the from ds info from rx_mpdu_start 366 * @buf: pointer to the start of RX PKT TLV header 367 * 368 * Return: uint32_t(fr_ds) 369 */ 370 static uint32_t hal_rx_mpdu_get_fr_ds_6290(uint8_t *buf) 371 { 372 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 373 struct rx_mpdu_start *mpdu_start = 374 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 375 376 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 377 378 return HAL_RX_MPDU_GET_FROMDS(mpdu_info); 379 } 380 381 /** 382 * hal_rx_get_mpdu_frame_control_valid_6290() - Retrieves mpdu frame control 383 * valid 384 * @buf: Network buffer 385 * 386 * Return: value of frame control valid field 387 */ 388 static uint8_t hal_rx_get_mpdu_frame_control_valid_6290(uint8_t *buf) 389 { 390 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 391 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 392 393 return HAL_RX_MPDU_GET_FRAME_CONTROL_VALID(rx_mpdu_info); 394 } 395 396 /** 397 * hal_rx_mpdu_get_addr1_6290() - API to check get address1 of the mpdu 398 * @buf: pointer to the start of RX PKT TLV headera 399 * @mac_addr: pointer to mac address 400 * 401 * Return: success/failure 402 */ 403 static QDF_STATUS hal_rx_mpdu_get_addr1_6290(uint8_t *buf, uint8_t *mac_addr) 404 { 405 struct __attribute__((__packed__)) hal_addr1 { 406 uint32_t ad1_31_0; 407 uint16_t ad1_47_32; 408 }; 409 410 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 411 struct rx_mpdu_start *mpdu_start = 412 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 413 414 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 415 struct hal_addr1 *addr = (struct hal_addr1 *)mac_addr; 416 uint32_t mac_addr_ad1_valid; 417 418 mac_addr_ad1_valid = HAL_RX_MPDU_MAC_ADDR_AD1_VALID_GET(mpdu_info); 419 420 if (mac_addr_ad1_valid) { 421 addr->ad1_31_0 = HAL_RX_MPDU_AD1_31_0_GET(mpdu_info); 422 addr->ad1_47_32 = HAL_RX_MPDU_AD1_47_32_GET(mpdu_info); 423 return QDF_STATUS_SUCCESS; 424 } 425 426 return QDF_STATUS_E_FAILURE; 427 } 428 429 /** 430 * hal_rx_mpdu_get_addr2_6290() - API to get address2 of the mpdu in the packet 431 * @buf: pointer to the start of RX PKT TLV header 432 * @mac_addr: pointer to mac address 433 * 434 * Return: success/failure 435 */ 436 static QDF_STATUS hal_rx_mpdu_get_addr2_6290(uint8_t *buf, 437 uint8_t *mac_addr) 438 { 439 struct __attribute__((__packed__)) hal_addr2 { 440 uint16_t ad2_15_0; 441 uint32_t ad2_47_16; 442 }; 443 444 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 445 struct rx_mpdu_start *mpdu_start = 446 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 447 448 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 449 struct hal_addr2 *addr = (struct hal_addr2 *)mac_addr; 450 uint32_t mac_addr_ad2_valid; 451 452 mac_addr_ad2_valid = HAL_RX_MPDU_MAC_ADDR_AD2_VALID_GET(mpdu_info); 453 454 if (mac_addr_ad2_valid) { 455 addr->ad2_15_0 = HAL_RX_MPDU_AD2_15_0_GET(mpdu_info); 456 addr->ad2_47_16 = HAL_RX_MPDU_AD2_47_16_GET(mpdu_info); 457 return QDF_STATUS_SUCCESS; 458 } 459 460 return QDF_STATUS_E_FAILURE; 461 } 462 463 /** 464 * hal_rx_mpdu_get_addr3_6290() - API to get address3 of the mpdu in the packet 465 * @buf: pointer to the start of RX PKT TLV header 466 * @mac_addr: pointer to mac address 467 * 468 * Return: success/failure 469 */ 470 static QDF_STATUS hal_rx_mpdu_get_addr3_6290(uint8_t *buf, uint8_t *mac_addr) 471 { 472 struct __attribute__((__packed__)) hal_addr3 { 473 uint32_t ad3_31_0; 474 uint16_t ad3_47_32; 475 }; 476 477 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 478 struct rx_mpdu_start *mpdu_start = 479 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 480 481 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 482 struct hal_addr3 *addr = (struct hal_addr3 *)mac_addr; 483 uint32_t mac_addr_ad3_valid; 484 485 mac_addr_ad3_valid = HAL_RX_MPDU_MAC_ADDR_AD3_VALID_GET(mpdu_info); 486 487 if (mac_addr_ad3_valid) { 488 addr->ad3_31_0 = HAL_RX_MPDU_AD3_31_0_GET(mpdu_info); 489 addr->ad3_47_32 = HAL_RX_MPDU_AD3_47_32_GET(mpdu_info); 490 return QDF_STATUS_SUCCESS; 491 } 492 493 return QDF_STATUS_E_FAILURE; 494 } 495 496 /** 497 * hal_rx_mpdu_get_addr4_6290() - API to get address4 of the mpdu in the packet 498 * @buf: pointer to the start of RX PKT TLV header 499 * @mac_addr: pointer to mac address 500 * 501 * Return: success/failure 502 */ 503 static QDF_STATUS hal_rx_mpdu_get_addr4_6290(uint8_t *buf, uint8_t *mac_addr) 504 { 505 struct __attribute__((__packed__)) hal_addr4 { 506 uint32_t ad4_31_0; 507 uint16_t ad4_47_32; 508 }; 509 510 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 511 struct rx_mpdu_start *mpdu_start = 512 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 513 514 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 515 struct hal_addr4 *addr = (struct hal_addr4 *)mac_addr; 516 uint32_t mac_addr_ad4_valid; 517 518 mac_addr_ad4_valid = HAL_RX_MPDU_MAC_ADDR_AD4_VALID_GET(mpdu_info); 519 520 if (mac_addr_ad4_valid) { 521 addr->ad4_31_0 = HAL_RX_MPDU_AD4_31_0_GET(mpdu_info); 522 addr->ad4_47_32 = HAL_RX_MPDU_AD4_47_32_GET(mpdu_info); 523 return QDF_STATUS_SUCCESS; 524 } 525 526 return QDF_STATUS_E_FAILURE; 527 } 528 529 /** 530 * hal_rx_get_mpdu_sequence_control_valid_6290() - Get mpdu sequence control 531 * valid 532 * @buf: Network buffer 533 * 534 * Return: value of sequence control valid field 535 */ 536 static uint8_t hal_rx_get_mpdu_sequence_control_valid_6290(uint8_t *buf) 537 { 538 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 539 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 540 541 return HAL_RX_MPDU_GET_SEQUENCE_CONTROL_VALID(rx_mpdu_info); 542 } 543 544 /** 545 * hal_rx_is_unicast_6290() - check packet is unicast frame or not. 546 * @buf: pointer to rx pkt TLV. 547 * 548 * Return: true on unicast. 549 */ 550 static bool hal_rx_is_unicast_6290(uint8_t *buf) 551 { 552 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 553 struct rx_mpdu_start *mpdu_start = 554 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 555 uint32_t grp_id; 556 uint8_t *rx_mpdu_info = (uint8_t *)&mpdu_start->rx_mpdu_info_details; 557 558 grp_id = (_HAL_MS((*_OFFSET_TO_WORD_PTR((rx_mpdu_info), 559 RX_MPDU_INFO_0_SW_FRAME_GROUP_ID_OFFSET)), 560 RX_MPDU_INFO_0_SW_FRAME_GROUP_ID_MASK, 561 RX_MPDU_INFO_0_SW_FRAME_GROUP_ID_LSB)); 562 563 return (HAL_MPDU_SW_FRAME_GROUP_UNICAST_DATA == grp_id) ? true : false; 564 } 565 566 /** 567 * hal_rx_tid_get_6290() - get tid based on qos control valid. 568 * @hal_soc_hdl: hal soc handle 569 * @buf: pointer to rx pkt TLV. 570 * 571 * Return: tid 572 */ 573 static uint32_t hal_rx_tid_get_6290(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 574 { 575 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 576 struct rx_mpdu_start *mpdu_start = 577 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 578 uint8_t *rx_mpdu_info = (uint8_t *)&mpdu_start->rx_mpdu_info_details; 579 uint8_t qos_control_valid = 580 (_HAL_MS((*_OFFSET_TO_WORD_PTR((rx_mpdu_info), 581 RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_OFFSET)), 582 RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_MASK, 583 RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_LSB)); 584 585 if (qos_control_valid) 586 return hal_rx_mpdu_start_tid_get_6290(buf); 587 588 return HAL_RX_NON_QOS_TID; 589 } 590 591 /** 592 * hal_rx_hw_desc_get_ppduid_get_6290() - retrieve ppdu id 593 * @rx_tlv_hdr: start address of rx_pkt_tlvs 594 * @rxdma_dst_ring_desc: Rx HW descriptor 595 * 596 * Return: ppdu id 597 */ 598 static uint32_t hal_rx_hw_desc_get_ppduid_get_6290(void *rx_tlv_hdr, 599 void *rxdma_dst_ring_desc) 600 { 601 struct rx_mpdu_info *rx_mpdu_info; 602 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)rx_tlv_hdr; 603 604 rx_mpdu_info = 605 &rx_desc->mpdu_start_tlv.rx_mpdu_start.rx_mpdu_info_details; 606 607 return HAL_RX_GET(rx_mpdu_info, RX_MPDU_INFO_0, PHY_PPDU_ID); 608 } 609 610 /** 611 * hal_reo_status_get_header_6290() - Process reo desc info 612 * @ring_desc: REO status ring descriptor 613 * @b: tlv type info 614 * @h1: Pointer to hal_reo_status_header where info to be stored 615 * 616 * Return: none. 617 * 618 */ 619 static void hal_reo_status_get_header_6290(hal_ring_desc_t ring_desc, int b, 620 void *h1) 621 { 622 uint32_t *d = (uint32_t *)ring_desc; 623 uint32_t val1 = 0; 624 struct hal_reo_status_header *h = 625 (struct hal_reo_status_header *)h1; 626 627 /* Offsets of descriptor fields defined in HW headers start 628 * from the field after TLV header 629 */ 630 d += HAL_GET_NUM_DWORDS(sizeof(struct tlv_32_hdr)); 631 632 switch (b) { 633 case HAL_REO_QUEUE_STATS_STATUS_TLV: 634 val1 = d[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_0, 635 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 636 break; 637 case HAL_REO_FLUSH_QUEUE_STATUS_TLV: 638 val1 = d[HAL_OFFSET_DW(REO_FLUSH_QUEUE_STATUS_0, 639 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 640 break; 641 case HAL_REO_FLUSH_CACHE_STATUS_TLV: 642 val1 = d[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_0, 643 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 644 break; 645 case HAL_REO_UNBLK_CACHE_STATUS_TLV: 646 val1 = d[HAL_OFFSET_DW(REO_UNBLOCK_CACHE_STATUS_0, 647 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 648 break; 649 case HAL_REO_TIMOUT_LIST_STATUS_TLV: 650 val1 = d[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_0, 651 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 652 break; 653 case HAL_REO_DESC_THRES_STATUS_TLV: 654 val1 = 655 d[HAL_OFFSET_DW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0, 656 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 657 break; 658 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: 659 val1 = d[HAL_OFFSET_DW(REO_UPDATE_RX_REO_QUEUE_STATUS_0, 660 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 661 break; 662 default: 663 qdf_nofl_err("ERROR: Unknown tlv\n"); 664 break; 665 } 666 h->cmd_num = 667 HAL_GET_FIELD( 668 UNIFORM_REO_STATUS_HEADER_0, REO_STATUS_NUMBER, 669 val1); 670 h->exec_time = 671 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_0, 672 CMD_EXECUTION_TIME, val1); 673 h->status = 674 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_0, 675 REO_CMD_EXECUTION_STATUS, val1); 676 switch (b) { 677 case HAL_REO_QUEUE_STATS_STATUS_TLV: 678 val1 = d[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_1, 679 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 680 break; 681 case HAL_REO_FLUSH_QUEUE_STATUS_TLV: 682 val1 = d[HAL_OFFSET_DW(REO_FLUSH_QUEUE_STATUS_1, 683 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 684 break; 685 case HAL_REO_FLUSH_CACHE_STATUS_TLV: 686 val1 = d[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_1, 687 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 688 break; 689 case HAL_REO_UNBLK_CACHE_STATUS_TLV: 690 val1 = d[HAL_OFFSET_DW(REO_UNBLOCK_CACHE_STATUS_1, 691 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 692 break; 693 case HAL_REO_TIMOUT_LIST_STATUS_TLV: 694 val1 = d[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_1, 695 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 696 break; 697 case HAL_REO_DESC_THRES_STATUS_TLV: 698 val1 = 699 d[HAL_OFFSET_DW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_1, 700 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 701 break; 702 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: 703 val1 = d[HAL_OFFSET_DW(REO_UPDATE_RX_REO_QUEUE_STATUS_1, 704 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 705 break; 706 default: 707 qdf_nofl_err("ERROR: Unknown tlv\n"); 708 break; 709 } 710 h->tstamp = 711 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_1, TIMESTAMP, val1); 712 } 713 714 /** 715 * hal_rx_mpdu_start_mpdu_qos_control_valid_get_6290() - 716 * Retrieve qos control valid bit from the tlv. 717 * @buf: pointer to rx pkt TLV. 718 * 719 * Return: qos control value. 720 */ 721 static inline uint32_t 722 hal_rx_mpdu_start_mpdu_qos_control_valid_get_6290(uint8_t *buf) 723 { 724 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 725 struct rx_mpdu_start *mpdu_start = 726 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 727 728 return HAL_RX_MPDU_INFO_QOS_CONTROL_VALID_GET( 729 &mpdu_start->rx_mpdu_info_details); 730 } 731 732 /** 733 * hal_rx_msdu_end_sa_sw_peer_id_get_6290() - API to get the 734 * sa_sw_peer_id from rx_msdu_end TLV 735 * @buf: pointer to the start of RX PKT TLV headers 736 * 737 * Return: sa_sw_peer_id index 738 */ 739 static inline uint32_t 740 hal_rx_msdu_end_sa_sw_peer_id_get_6290(uint8_t *buf) 741 { 742 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 743 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 744 745 return HAL_RX_MSDU_END_SA_SW_PEER_ID_GET(msdu_end); 746 } 747 748 /** 749 * hal_tx_desc_set_mesh_en_6290() - Set mesh_enable flag in Tx descriptor 750 * @desc: Handle to Tx Descriptor 751 * @en: For raw WiFi frames, this indicates transmission to a mesh STA, 752 * enabling the interpretation of the 'Mesh Control Present' bit 753 * (bit 8) of QoS Control (otherwise this bit is ignored), 754 * For native WiFi frames, this indicates that a 'Mesh Control' field 755 * is present between the header and the LLC. 756 * 757 * Return: void 758 */ 759 static inline 760 void hal_tx_desc_set_mesh_en_6290(void *desc, uint8_t en) 761 { 762 HAL_SET_FLD(desc, TCL_DATA_CMD_4, MESH_ENABLE) |= 763 HAL_TX_SM(TCL_DATA_CMD_4, MESH_ENABLE, en); 764 } 765 766 static 767 void *hal_rx_msdu0_buffer_addr_lsb_6290(void *link_desc_va) 768 { 769 return (void *)HAL_RX_MSDU0_BUFFER_ADDR_LSB(link_desc_va); 770 } 771 772 static 773 void *hal_rx_msdu_desc_info_ptr_get_6290(void *msdu0) 774 { 775 return (void *)HAL_RX_MSDU_DESC_INFO_PTR_GET(msdu0); 776 } 777 778 static 779 void *hal_ent_mpdu_desc_info_6290(void *ent_ring_desc) 780 { 781 return (void *)HAL_ENT_MPDU_DESC_INFO(ent_ring_desc); 782 } 783 784 static 785 void *hal_dst_mpdu_desc_info_6290(void *dst_ring_desc) 786 { 787 return (void *)HAL_DST_MPDU_DESC_INFO(dst_ring_desc); 788 } 789 790 static 791 uint8_t hal_rx_get_fc_valid_6290(uint8_t *buf) 792 { 793 return HAL_RX_GET_FC_VALID(buf); 794 } 795 796 static uint8_t hal_rx_get_to_ds_flag_6290(uint8_t *buf) 797 { 798 return HAL_RX_GET_TO_DS_FLAG(buf); 799 } 800 801 static uint8_t hal_rx_get_mac_addr2_valid_6290(uint8_t *buf) 802 { 803 return HAL_RX_GET_MAC_ADDR2_VALID(buf); 804 } 805 806 static uint8_t hal_rx_get_filter_category_6290(uint8_t *buf) 807 { 808 return HAL_RX_GET_FILTER_CATEGORY(buf); 809 } 810 811 static uint32_t 812 hal_rx_get_ppdu_id_6290(uint8_t *buf) 813 { 814 return HAL_RX_GET_PPDU_ID(buf); 815 } 816 817 /** 818 * hal_reo_config_6290() - Set reo config parameters 819 * @soc: hal soc handle 820 * @reg_val: value to be set 821 * @reo_params: reo parameters 822 * 823 * Return: void 824 */ 825 static 826 void hal_reo_config_6290(struct hal_soc *soc, 827 uint32_t reg_val, 828 struct hal_reo_params *reo_params) 829 { 830 HAL_REO_R0_CONFIG(soc, reg_val, reo_params); 831 } 832 833 /** 834 * hal_rx_msdu_desc_info_get_ptr_6290() - Get msdu desc info ptr 835 * @msdu_details_ptr: Pointer to msdu_details_ptr 836 * 837 * Return: Pointer to rx_msdu_desc_info structure. 838 * 839 */ 840 static void *hal_rx_msdu_desc_info_get_ptr_6290(void *msdu_details_ptr) 841 { 842 return HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr); 843 } 844 845 /** 846 * hal_rx_link_desc_msdu0_ptr_6290() - Get pointer to rx_msdu details 847 * @link_desc: Pointer to link desc 848 * 849 * Return: Pointer to rx_msdu_details structure 850 * 851 */ 852 static void *hal_rx_link_desc_msdu0_ptr_6290(void *link_desc) 853 { 854 return HAL_RX_LINK_DESC_MSDU0_PTR(link_desc); 855 } 856 857 /** 858 * hal_rx_msdu_flow_idx_get_6290() - API to get flow index 859 * from rx_msdu_end TLV 860 * @buf: pointer to the start of RX PKT TLV headers 861 * 862 * Return: flow index value from MSDU END TLV 863 */ 864 static inline uint32_t hal_rx_msdu_flow_idx_get_6290(uint8_t *buf) 865 { 866 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 867 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 868 869 return HAL_RX_MSDU_END_FLOW_IDX_GET(msdu_end); 870 } 871 872 /** 873 * hal_rx_msdu_flow_idx_invalid_6290() - API to get flow index invalid 874 * from rx_msdu_end TLV 875 * @buf: pointer to the start of RX PKT TLV headers 876 * 877 * Return: flow index invalid value from MSDU END TLV 878 */ 879 static bool hal_rx_msdu_flow_idx_invalid_6290(uint8_t *buf) 880 { 881 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 882 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 883 884 return HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(msdu_end); 885 } 886 887 /** 888 * hal_rx_msdu_flow_idx_timeout_6290() - API to get flow index timeout 889 * from rx_msdu_end TLV 890 * @buf: pointer to the start of RX PKT TLV headers 891 * 892 * Return: flow index timeout value from MSDU END TLV 893 */ 894 static bool hal_rx_msdu_flow_idx_timeout_6290(uint8_t *buf) 895 { 896 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 897 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 898 899 return HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(msdu_end); 900 } 901 902 /** 903 * hal_rx_msdu_fse_metadata_get_6290() - API to get FSE metadata 904 * from rx_msdu_end TLV 905 * @buf: pointer to the start of RX PKT TLV headers 906 * 907 * Return: fse metadata value from MSDU END TLV 908 */ 909 static uint32_t hal_rx_msdu_fse_metadata_get_6290(uint8_t *buf) 910 { 911 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 912 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 913 914 return HAL_RX_MSDU_END_FSE_METADATA_GET(msdu_end); 915 } 916 917 /** 918 * hal_rx_msdu_cce_metadata_get_6290() - API to get CCE metadata 919 * from rx_msdu_end TLV 920 * @buf: pointer to the start of RX PKT TLV headers 921 * 922 * Return: cce_metadata 923 */ 924 static uint16_t 925 hal_rx_msdu_cce_metadata_get_6290(uint8_t *buf) 926 { 927 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 928 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 929 930 return HAL_RX_MSDU_END_CCE_METADATA_GET(msdu_end); 931 } 932 933 /** 934 * hal_rx_msdu_get_flow_params_6290() - API to get flow index, flow index 935 * invalid and flow index timeout from 936 * rx_msdu_end TLV 937 * @buf: pointer to the start of RX PKT TLV headers 938 * @flow_invalid: pointer to return value of flow_idx_valid 939 * @flow_timeout: pointer to return value of flow_idx_timeout 940 * @flow_index: pointer to return value of flow_idx 941 * 942 * Return: none 943 */ 944 static inline void 945 hal_rx_msdu_get_flow_params_6290(uint8_t *buf, 946 bool *flow_invalid, 947 bool *flow_timeout, 948 uint32_t *flow_index) 949 { 950 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 951 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 952 953 *flow_invalid = HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(msdu_end); 954 *flow_timeout = HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(msdu_end); 955 *flow_index = HAL_RX_MSDU_END_FLOW_IDX_GET(msdu_end); 956 } 957 958 /** 959 * hal_rx_tlv_get_tcp_chksum_6290() - API to get tcp checksum 960 * @buf: rx_tlv_hdr 961 * 962 * Return: tcp checksum 963 */ 964 static uint16_t 965 hal_rx_tlv_get_tcp_chksum_6290(uint8_t *buf) 966 { 967 return HAL_RX_TLV_GET_TCP_CHKSUM(buf); 968 } 969 970 /** 971 * hal_rx_get_rx_sequence_6290() - Function to retrieve rx sequence number 972 * @buf: Network buffer 973 * 974 * Return: rx sequence number 975 */ 976 static 977 uint16_t hal_rx_get_rx_sequence_6290(uint8_t *buf) 978 { 979 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 980 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 981 982 return HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info); 983 } 984 985 /** 986 * hal_get_window_address_6290() - Function to get hp/tp address 987 * @hal_soc: Pointer to hal_soc 988 * @addr: address offset of register 989 * 990 * Return: modified address offset of register 991 */ 992 static inline qdf_iomem_t hal_get_window_address_6290(struct hal_soc *hal_soc, 993 qdf_iomem_t addr) 994 { 995 return addr; 996 } 997 998 static 999 void hal_compute_reo_remap_ix2_ix3_6290(uint32_t *ring, uint32_t num_rings, 1000 uint32_t *remap1, uint32_t *remap2) 1001 { 1002 switch (num_rings) { 1003 case 3: 1004 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 1005 HAL_REO_REMAP_IX2(ring[1], 17) | 1006 HAL_REO_REMAP_IX2(ring[2], 18) | 1007 HAL_REO_REMAP_IX2(ring[0], 19) | 1008 HAL_REO_REMAP_IX2(ring[1], 20) | 1009 HAL_REO_REMAP_IX2(ring[2], 21) | 1010 HAL_REO_REMAP_IX2(ring[0], 22) | 1011 HAL_REO_REMAP_IX2(ring[1], 23); 1012 1013 *remap2 = HAL_REO_REMAP_IX3(ring[2], 24) | 1014 HAL_REO_REMAP_IX3(ring[0], 25) | 1015 HAL_REO_REMAP_IX3(ring[1], 26) | 1016 HAL_REO_REMAP_IX3(ring[2], 27) | 1017 HAL_REO_REMAP_IX3(ring[0], 28) | 1018 HAL_REO_REMAP_IX3(ring[1], 29) | 1019 HAL_REO_REMAP_IX3(ring[2], 30) | 1020 HAL_REO_REMAP_IX3(ring[0], 31); 1021 break; 1022 case 4: 1023 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 1024 HAL_REO_REMAP_IX2(ring[1], 17) | 1025 HAL_REO_REMAP_IX2(ring[2], 18) | 1026 HAL_REO_REMAP_IX2(ring[3], 19) | 1027 HAL_REO_REMAP_IX2(ring[0], 20) | 1028 HAL_REO_REMAP_IX2(ring[1], 21) | 1029 HAL_REO_REMAP_IX2(ring[2], 22) | 1030 HAL_REO_REMAP_IX2(ring[3], 23); 1031 1032 *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) | 1033 HAL_REO_REMAP_IX3(ring[1], 25) | 1034 HAL_REO_REMAP_IX3(ring[2], 26) | 1035 HAL_REO_REMAP_IX3(ring[3], 27) | 1036 HAL_REO_REMAP_IX3(ring[0], 28) | 1037 HAL_REO_REMAP_IX3(ring[1], 29) | 1038 HAL_REO_REMAP_IX3(ring[2], 30) | 1039 HAL_REO_REMAP_IX3(ring[3], 31); 1040 break; 1041 } 1042 } 1043 1044 #ifdef WLAN_FEATURE_MARK_FIRST_WAKEUP_PACKET 1045 /** 1046 * hal_get_first_wow_wakeup_packet_6290() - Function to get if the buffer 1047 * is the first one that wakes up host from WoW. 1048 * 1049 * @buf: network buffer 1050 * 1051 * Dummy function for QCA6290 1052 * 1053 * Return: 1 to indicate it is first packet received that wakes up host from 1054 * WoW. Otherwise 0 1055 */ 1056 static inline uint8_t hal_get_first_wow_wakeup_packet_6290(uint8_t *buf) 1057 { 1058 return 0; 1059 } 1060 #endif 1061 1062 static void hal_hw_txrx_ops_attach_6290(struct hal_soc *hal_soc) 1063 { 1064 /* init and setup */ 1065 hal_soc->ops->hal_srng_dst_hw_init = hal_srng_dst_hw_init_generic; 1066 hal_soc->ops->hal_srng_src_hw_init = hal_srng_src_hw_init_generic; 1067 hal_soc->ops->hal_get_hw_hptp = hal_get_hw_hptp_generic; 1068 hal_soc->ops->hal_reo_setup = hal_reo_setup_generic_li; 1069 hal_soc->ops->hal_get_window_address = hal_get_window_address_6290; 1070 1071 /* tx */ 1072 hal_soc->ops->hal_tx_desc_set_dscp_tid_table_id = 1073 hal_tx_desc_set_dscp_tid_table_id_6290; 1074 hal_soc->ops->hal_tx_set_dscp_tid_map = hal_tx_set_dscp_tid_map_6290; 1075 hal_soc->ops->hal_tx_update_dscp_tid = hal_tx_update_dscp_tid_6290; 1076 hal_soc->ops->hal_tx_desc_set_lmac_id = hal_tx_desc_set_lmac_id_6290; 1077 hal_soc->ops->hal_tx_desc_set_buf_addr = 1078 hal_tx_desc_set_buf_addr_generic_li; 1079 hal_soc->ops->hal_tx_desc_set_search_type = 1080 hal_tx_desc_set_search_type_generic_li; 1081 hal_soc->ops->hal_tx_desc_set_search_index = 1082 hal_tx_desc_set_search_index_generic_li; 1083 hal_soc->ops->hal_tx_desc_set_cache_set_num = 1084 hal_tx_desc_set_cache_set_num_generic_li; 1085 hal_soc->ops->hal_tx_comp_get_status = 1086 hal_tx_comp_get_status_generic_li; 1087 hal_soc->ops->hal_tx_comp_get_release_reason = 1088 hal_tx_comp_get_release_reason_generic_li; 1089 hal_soc->ops->hal_get_wbm_internal_error = 1090 hal_get_wbm_internal_error_generic_li; 1091 hal_soc->ops->hal_tx_desc_set_mesh_en = hal_tx_desc_set_mesh_en_6290; 1092 hal_soc->ops->hal_tx_init_cmd_credit_ring = 1093 hal_tx_init_cmd_credit_ring_6290; 1094 1095 /* rx */ 1096 hal_soc->ops->hal_rx_msdu_start_nss_get = 1097 hal_rx_msdu_start_nss_get_6290; 1098 hal_soc->ops->hal_rx_mon_hw_desc_get_mpdu_status = 1099 hal_rx_mon_hw_desc_get_mpdu_status_6290; 1100 hal_soc->ops->hal_rx_get_tlv = hal_rx_get_tlv_6290; 1101 hal_soc->ops->hal_rx_proc_phyrx_other_receive_info_tlv = 1102 hal_rx_proc_phyrx_other_receive_info_tlv_6290; 1103 hal_soc->ops->hal_rx_dump_msdu_start_tlv = 1104 hal_rx_dump_msdu_start_tlv_6290; 1105 hal_soc->ops->hal_rx_dump_msdu_end_tlv = hal_rx_dump_msdu_end_tlv_6290; 1106 hal_soc->ops->hal_get_link_desc_size = hal_get_link_desc_size_6290; 1107 hal_soc->ops->hal_rx_mpdu_start_tid_get = 1108 hal_rx_mpdu_start_tid_get_6290; 1109 hal_soc->ops->hal_rx_msdu_start_reception_type_get = 1110 hal_rx_msdu_start_reception_type_get_6290; 1111 hal_soc->ops->hal_rx_msdu_end_da_idx_get = 1112 hal_rx_msdu_end_da_idx_get_6290; 1113 hal_soc->ops->hal_rx_msdu_desc_info_get_ptr = 1114 hal_rx_msdu_desc_info_get_ptr_6290; 1115 hal_soc->ops->hal_rx_link_desc_msdu0_ptr = 1116 hal_rx_link_desc_msdu0_ptr_6290; 1117 hal_soc->ops->hal_reo_status_get_header = 1118 hal_reo_status_get_header_6290; 1119 hal_soc->ops->hal_rx_status_get_tlv_info = 1120 hal_rx_status_get_tlv_info_generic_li; 1121 hal_soc->ops->hal_rx_wbm_err_info_get = 1122 hal_rx_wbm_err_info_get_generic_li; 1123 hal_soc->ops->hal_rx_dump_mpdu_start_tlv = 1124 hal_rx_dump_mpdu_start_tlv_generic_li; 1125 1126 hal_soc->ops->hal_tx_set_pcp_tid_map = 1127 hal_tx_set_pcp_tid_map_generic_li; 1128 hal_soc->ops->hal_tx_update_pcp_tid_map = 1129 hal_tx_update_pcp_tid_generic_li; 1130 hal_soc->ops->hal_tx_set_tidmap_prty = 1131 hal_tx_update_tidmap_prty_generic_li; 1132 hal_soc->ops->hal_rx_get_rx_fragment_number = 1133 hal_rx_get_rx_fragment_number_6290; 1134 hal_soc->ops->hal_rx_msdu_end_da_is_mcbc_get = 1135 hal_rx_msdu_end_da_is_mcbc_get_6290; 1136 hal_soc->ops->hal_rx_msdu_end_sa_is_valid_get = 1137 hal_rx_msdu_end_sa_is_valid_get_6290; 1138 hal_soc->ops->hal_rx_msdu_end_sa_idx_get = 1139 hal_rx_msdu_end_sa_idx_get_6290; 1140 hal_soc->ops->hal_rx_desc_is_first_msdu = 1141 hal_rx_desc_is_first_msdu_6290; 1142 hal_soc->ops->hal_rx_msdu_end_l3_hdr_padding_get = 1143 hal_rx_msdu_end_l3_hdr_padding_get_6290; 1144 hal_soc->ops->hal_rx_encryption_info_valid = 1145 hal_rx_encryption_info_valid_6290; 1146 hal_soc->ops->hal_rx_print_pn = hal_rx_print_pn_6290; 1147 hal_soc->ops->hal_rx_msdu_end_first_msdu_get = 1148 hal_rx_msdu_end_first_msdu_get_6290; 1149 hal_soc->ops->hal_rx_msdu_end_da_is_valid_get = 1150 hal_rx_msdu_end_da_is_valid_get_6290; 1151 hal_soc->ops->hal_rx_msdu_end_last_msdu_get = 1152 hal_rx_msdu_end_last_msdu_get_6290; 1153 hal_soc->ops->hal_rx_get_mpdu_mac_ad4_valid = 1154 hal_rx_get_mpdu_mac_ad4_valid_6290; 1155 hal_soc->ops->hal_rx_mpdu_start_sw_peer_id_get = 1156 hal_rx_mpdu_start_sw_peer_id_get_6290; 1157 hal_soc->ops->hal_rx_tlv_peer_meta_data_get = 1158 hal_rx_mpdu_peer_meta_data_get_li; 1159 hal_soc->ops->hal_rx_mpdu_get_to_ds = hal_rx_mpdu_get_to_ds_6290; 1160 hal_soc->ops->hal_rx_mpdu_get_fr_ds = hal_rx_mpdu_get_fr_ds_6290; 1161 hal_soc->ops->hal_rx_get_mpdu_frame_control_valid = 1162 hal_rx_get_mpdu_frame_control_valid_6290; 1163 hal_soc->ops->hal_rx_get_frame_ctrl_field = 1164 hal_rx_get_frame_ctrl_field_li; 1165 hal_soc->ops->hal_rx_mpdu_get_addr1 = hal_rx_mpdu_get_addr1_6290; 1166 hal_soc->ops->hal_rx_mpdu_get_addr2 = hal_rx_mpdu_get_addr2_6290; 1167 hal_soc->ops->hal_rx_mpdu_get_addr3 = hal_rx_mpdu_get_addr3_6290; 1168 hal_soc->ops->hal_rx_mpdu_get_addr4 = hal_rx_mpdu_get_addr4_6290; 1169 hal_soc->ops->hal_rx_get_mpdu_sequence_control_valid = 1170 hal_rx_get_mpdu_sequence_control_valid_6290; 1171 hal_soc->ops->hal_rx_is_unicast = hal_rx_is_unicast_6290; 1172 hal_soc->ops->hal_rx_tid_get = hal_rx_tid_get_6290; 1173 hal_soc->ops->hal_rx_hw_desc_get_ppduid_get = 1174 hal_rx_hw_desc_get_ppduid_get_6290; 1175 hal_soc->ops->hal_rx_mpdu_start_mpdu_qos_control_valid_get = 1176 hal_rx_mpdu_start_mpdu_qos_control_valid_get_6290; 1177 hal_soc->ops->hal_rx_msdu_end_sa_sw_peer_id_get = 1178 hal_rx_msdu_end_sa_sw_peer_id_get_6290; 1179 hal_soc->ops->hal_rx_msdu0_buffer_addr_lsb = 1180 hal_rx_msdu0_buffer_addr_lsb_6290; 1181 hal_soc->ops->hal_rx_msdu_desc_info_ptr_get = 1182 hal_rx_msdu_desc_info_ptr_get_6290; 1183 hal_soc->ops->hal_ent_mpdu_desc_info = hal_ent_mpdu_desc_info_6290; 1184 hal_soc->ops->hal_dst_mpdu_desc_info = hal_dst_mpdu_desc_info_6290; 1185 hal_soc->ops->hal_rx_get_fc_valid = hal_rx_get_fc_valid_6290; 1186 hal_soc->ops->hal_rx_get_to_ds_flag = hal_rx_get_to_ds_flag_6290; 1187 hal_soc->ops->hal_rx_get_mac_addr2_valid = 1188 hal_rx_get_mac_addr2_valid_6290; 1189 hal_soc->ops->hal_rx_get_filter_category = 1190 hal_rx_get_filter_category_6290; 1191 hal_soc->ops->hal_rx_get_ppdu_id = hal_rx_get_ppdu_id_6290; 1192 hal_soc->ops->hal_reo_config = hal_reo_config_6290; 1193 hal_soc->ops->hal_rx_msdu_flow_idx_get = hal_rx_msdu_flow_idx_get_6290; 1194 hal_soc->ops->hal_rx_msdu_flow_idx_invalid = 1195 hal_rx_msdu_flow_idx_invalid_6290; 1196 hal_soc->ops->hal_rx_msdu_flow_idx_timeout = 1197 hal_rx_msdu_flow_idx_timeout_6290; 1198 hal_soc->ops->hal_rx_msdu_fse_metadata_get = 1199 hal_rx_msdu_fse_metadata_get_6290; 1200 hal_soc->ops->hal_rx_msdu_cce_match_get = 1201 hal_rx_msdu_cce_match_get_li; 1202 hal_soc->ops->hal_rx_msdu_cce_metadata_get = 1203 hal_rx_msdu_cce_metadata_get_6290; 1204 hal_soc->ops->hal_rx_msdu_get_flow_params = 1205 hal_rx_msdu_get_flow_params_6290; 1206 hal_soc->ops->hal_rx_tlv_get_tcp_chksum = 1207 hal_rx_tlv_get_tcp_chksum_6290; 1208 hal_soc->ops->hal_rx_get_rx_sequence = hal_rx_get_rx_sequence_6290; 1209 /* rx - msdu end fast path info fields */ 1210 hal_soc->ops->hal_rx_msdu_packet_metadata_get = 1211 hal_rx_msdu_packet_metadata_get_generic_li; 1212 /* rx - TLV struct offsets */ 1213 hal_soc->ops->hal_rx_msdu_end_offset_get = 1214 hal_rx_msdu_end_offset_get_generic; 1215 hal_soc->ops->hal_rx_attn_offset_get = 1216 hal_rx_attn_offset_get_generic; 1217 hal_soc->ops->hal_rx_msdu_start_offset_get = 1218 hal_rx_msdu_start_offset_get_generic; 1219 hal_soc->ops->hal_rx_mpdu_start_offset_get = 1220 hal_rx_mpdu_start_offset_get_generic; 1221 hal_soc->ops->hal_rx_mpdu_end_offset_get = 1222 hal_rx_mpdu_end_offset_get_generic; 1223 #ifndef NO_RX_PKT_HDR_TLV 1224 hal_soc->ops->hal_rx_pkt_tlv_offset_get = 1225 hal_rx_pkt_tlv_offset_get_generic; 1226 #endif 1227 hal_soc->ops->hal_compute_reo_remap_ix2_ix3 = 1228 hal_compute_reo_remap_ix2_ix3_6290; 1229 hal_soc->ops->hal_setup_link_idle_list = 1230 hal_setup_link_idle_list_generic_li; 1231 #ifdef WLAN_FEATURE_MARK_FIRST_WAKEUP_PACKET 1232 hal_soc->ops->hal_get_first_wow_wakeup_packet = 1233 hal_get_first_wow_wakeup_packet_6290; 1234 #endif 1235 hal_soc->ops->hal_compute_reo_remap_ix0 = NULL; 1236 }; 1237 1238 struct hal_hw_srng_config hw_srng_table_6290[] = { 1239 /* TODO: max_rings can populated by querying HW capabilities */ 1240 { /* REO_DST */ 1241 .start_ring_id = HAL_SRNG_REO2SW1, 1242 .max_rings = 4, 1243 .entry_size = sizeof(struct reo_destination_ring) >> 2, 1244 .lmac_ring = FALSE, 1245 .ring_dir = HAL_SRNG_DST_RING, 1246 .reg_start = { 1247 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR( 1248 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1249 HWIO_REO_R2_REO2SW1_RING_HP_ADDR( 1250 SEQ_WCSS_UMAC_REO_REG_OFFSET) 1251 }, 1252 .reg_size = { 1253 HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(0) - 1254 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(0), 1255 HWIO_REO_R2_REO2SW2_RING_HP_ADDR(0) - 1256 HWIO_REO_R2_REO2SW1_RING_HP_ADDR(0), 1257 }, 1258 .max_size = HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_BMSK >> 1259 HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_SHFT, 1260 }, 1261 { /* REO_EXCEPTION */ 1262 /* Designating REO2TCL ring as exception ring. This ring is 1263 * similar to other REO2SW rings though it is named as REO2TCL. 1264 * Any of theREO2SW rings can be used as exception ring. 1265 */ 1266 .start_ring_id = HAL_SRNG_REO2TCL, 1267 .max_rings = 1, 1268 .entry_size = sizeof(struct reo_destination_ring) >> 2, 1269 .lmac_ring = FALSE, 1270 .ring_dir = HAL_SRNG_DST_RING, 1271 .reg_start = { 1272 HWIO_REO_R0_REO2TCL_RING_BASE_LSB_ADDR( 1273 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1274 HWIO_REO_R2_REO2TCL_RING_HP_ADDR( 1275 SEQ_WCSS_UMAC_REO_REG_OFFSET) 1276 }, 1277 /* Single ring - provide ring size if multiple rings of this 1278 * type are supported 1279 */ 1280 .reg_size = {}, 1281 .max_size = HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_BMSK >> 1282 HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_SHFT, 1283 }, 1284 { /* REO_REINJECT */ 1285 .start_ring_id = HAL_SRNG_SW2REO, 1286 .max_rings = 1, 1287 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 1288 .lmac_ring = FALSE, 1289 .ring_dir = HAL_SRNG_SRC_RING, 1290 .reg_start = { 1291 HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR( 1292 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1293 HWIO_REO_R2_SW2REO_RING_HP_ADDR( 1294 SEQ_WCSS_UMAC_REO_REG_OFFSET) 1295 }, 1296 /* Single ring - provide ring size if multiple rings of this 1297 * type are supported 1298 */ 1299 .reg_size = {}, 1300 .max_size = HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_BMSK >> 1301 HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_SHFT, 1302 }, 1303 { /* REO_CMD */ 1304 .start_ring_id = HAL_SRNG_REO_CMD, 1305 .max_rings = 1, 1306 .entry_size = (sizeof(struct tlv_32_hdr) + 1307 sizeof(struct reo_get_queue_stats)) >> 2, 1308 .lmac_ring = FALSE, 1309 .ring_dir = HAL_SRNG_SRC_RING, 1310 .reg_start = { 1311 HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR( 1312 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1313 HWIO_REO_R2_REO_CMD_RING_HP_ADDR( 1314 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1315 }, 1316 /* Single ring - provide ring size if multiple rings of this 1317 * type are supported 1318 */ 1319 .reg_size = {}, 1320 .max_size = HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_BMSK >> 1321 HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_SHFT, 1322 }, 1323 { /* REO_STATUS */ 1324 .start_ring_id = HAL_SRNG_REO_STATUS, 1325 .max_rings = 1, 1326 .entry_size = (sizeof(struct tlv_32_hdr) + 1327 sizeof(struct reo_get_queue_stats_status)) >> 2, 1328 .lmac_ring = FALSE, 1329 .ring_dir = HAL_SRNG_DST_RING, 1330 .reg_start = { 1331 HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR( 1332 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1333 HWIO_REO_R2_REO_STATUS_RING_HP_ADDR( 1334 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1335 }, 1336 /* Single ring - provide ring size if multiple rings of this 1337 * type are supported 1338 */ 1339 .reg_size = {}, 1340 .max_size = 1341 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> 1342 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, 1343 }, 1344 { /* TCL_DATA */ 1345 .start_ring_id = HAL_SRNG_SW2TCL1, 1346 .max_rings = 3, 1347 .entry_size = (sizeof(struct tlv_32_hdr) + 1348 sizeof(struct tcl_data_cmd)) >> 2, 1349 .lmac_ring = FALSE, 1350 .ring_dir = HAL_SRNG_SRC_RING, 1351 .reg_start = { 1352 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR( 1353 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1354 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR( 1355 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1356 }, 1357 .reg_size = { 1358 HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(0) - 1359 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(0), 1360 HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(0) - 1361 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(0), 1362 }, 1363 .max_size = HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK >> 1364 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT, 1365 }, 1366 { /* TCL_CMD */ 1367 .start_ring_id = HAL_SRNG_SW2TCL_CMD, 1368 .max_rings = 1, 1369 .entry_size = (sizeof(struct tlv_32_hdr) + 1370 sizeof(struct tcl_gse_cmd)) >> 2, 1371 .lmac_ring = FALSE, 1372 .ring_dir = HAL_SRNG_SRC_RING, 1373 .reg_start = { 1374 HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_ADDR( 1375 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1376 HWIO_TCL_R2_SW2TCL_CMD_RING_HP_ADDR( 1377 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1378 }, 1379 /* Single ring - provide ring size if multiple rings of this 1380 * type are supported 1381 */ 1382 .reg_size = {}, 1383 .max_size = 1384 HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RING_SIZE_BMSK >> 1385 HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RING_SIZE_SHFT, 1386 }, 1387 { /* TCL_STATUS */ 1388 .start_ring_id = HAL_SRNG_TCL_STATUS, 1389 .max_rings = 1, 1390 .entry_size = (sizeof(struct tlv_32_hdr) + 1391 sizeof(struct tcl_status_ring)) >> 2, 1392 .lmac_ring = FALSE, 1393 .ring_dir = HAL_SRNG_DST_RING, 1394 .reg_start = { 1395 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR( 1396 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1397 HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR( 1398 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1399 }, 1400 /* Single ring - provide ring size if multiple rings of this 1401 * type are supported 1402 */ 1403 .reg_size = {}, 1404 .max_size = 1405 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_BMSK >> 1406 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_SHFT, 1407 }, 1408 { /* CE_SRC */ 1409 .start_ring_id = HAL_SRNG_CE_0_SRC, 1410 .max_rings = 12, 1411 .entry_size = sizeof(struct ce_src_desc) >> 2, 1412 .lmac_ring = FALSE, 1413 .ring_dir = HAL_SRNG_SRC_RING, 1414 .reg_start = { 1415 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR( 1416 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET), 1417 HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR( 1418 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET), 1419 }, 1420 .reg_size = { 1421 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET - 1422 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET, 1423 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET - 1424 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET, 1425 }, 1426 .max_size = 1427 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >> 1428 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT, 1429 }, 1430 { /* CE_DST */ 1431 .start_ring_id = HAL_SRNG_CE_0_DST, 1432 .max_rings = 12, 1433 .entry_size = 8 >> 2, 1434 /*TODO: entry_size above should actually be 1435 * sizeof(struct ce_dst_desc) >> 2, but couldn't find definition 1436 * of struct ce_dst_desc in HW header files 1437 */ 1438 .lmac_ring = FALSE, 1439 .ring_dir = HAL_SRNG_SRC_RING, 1440 .reg_start = { 1441 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR( 1442 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 1443 HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR( 1444 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 1445 }, 1446 .reg_size = { 1447 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 1448 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 1449 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 1450 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 1451 }, 1452 .max_size = 1453 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >> 1454 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT, 1455 }, 1456 { /* CE_DST_STATUS */ 1457 .start_ring_id = HAL_SRNG_CE_0_DST_STATUS, 1458 .max_rings = 12, 1459 .entry_size = sizeof(struct ce_stat_desc) >> 2, 1460 .lmac_ring = FALSE, 1461 .ring_dir = HAL_SRNG_DST_RING, 1462 .reg_start = { 1463 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR( 1464 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 1465 HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR( 1466 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 1467 }, 1468 /* TODO: check destination status ring registers */ 1469 .reg_size = { 1470 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 1471 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 1472 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 1473 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 1474 }, 1475 .max_size = 1476 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> 1477 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, 1478 }, 1479 { /* WBM_IDLE_LINK */ 1480 .start_ring_id = HAL_SRNG_WBM_IDLE_LINK, 1481 .max_rings = 1, 1482 .entry_size = sizeof(struct wbm_link_descriptor_ring) >> 2, 1483 .lmac_ring = FALSE, 1484 .ring_dir = HAL_SRNG_SRC_RING, 1485 .reg_start = { 1486 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1487 HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1488 }, 1489 /* Single ring - provide ring size if multiple rings of this 1490 * type are supported 1491 */ 1492 .reg_size = {}, 1493 .max_size = 1494 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_BMSK >> 1495 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_SHFT, 1496 }, 1497 { /* SW2WBM_RELEASE */ 1498 .start_ring_id = HAL_SRNG_WBM_SW_RELEASE, 1499 .max_rings = 1, 1500 .entry_size = sizeof(struct wbm_release_ring) >> 2, 1501 .lmac_ring = FALSE, 1502 .ring_dir = HAL_SRNG_SRC_RING, 1503 .reg_start = { 1504 HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1505 HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1506 }, 1507 /* Single ring - provide ring size if multiple rings of this 1508 * type are supported 1509 */ 1510 .reg_size = {}, 1511 .max_size = 1512 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> 1513 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, 1514 }, 1515 { /* WBM2SW_RELEASE */ 1516 .start_ring_id = HAL_SRNG_WBM2SW0_RELEASE, 1517 .max_rings = 4, 1518 .entry_size = sizeof(struct wbm_release_ring) >> 2, 1519 .lmac_ring = FALSE, 1520 .ring_dir = HAL_SRNG_DST_RING, 1521 .reg_start = { 1522 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1523 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1524 }, 1525 .reg_size = { 1526 HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) - 1527 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1528 HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) - 1529 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1530 }, 1531 .max_size = 1532 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> 1533 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, 1534 }, 1535 { /* RXDMA_BUF */ 1536 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA0_BUF0, 1537 #ifdef IPA_OFFLOAD 1538 .max_rings = 3, 1539 #else 1540 .max_rings = 2, 1541 #endif 1542 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 1543 .lmac_ring = TRUE, 1544 .ring_dir = HAL_SRNG_SRC_RING, 1545 /* reg_start is not set because LMAC rings are not accessed 1546 * from host 1547 */ 1548 .reg_start = {}, 1549 .reg_size = {}, 1550 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1551 }, 1552 { /* RXDMA_DST */ 1553 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW0, 1554 .max_rings = 1, 1555 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 1556 .lmac_ring = TRUE, 1557 .ring_dir = HAL_SRNG_DST_RING, 1558 /* reg_start is not set because LMAC rings are not accessed 1559 * from host 1560 */ 1561 .reg_start = {}, 1562 .reg_size = {}, 1563 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1564 }, 1565 { /* RXDMA_MONITOR_BUF */ 1566 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA2_BUF, 1567 .max_rings = 1, 1568 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 1569 .lmac_ring = TRUE, 1570 .ring_dir = HAL_SRNG_SRC_RING, 1571 /* reg_start is not set because LMAC rings are not accessed 1572 * from host 1573 */ 1574 .reg_start = {}, 1575 .reg_size = {}, 1576 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1577 }, 1578 { /* RXDMA_MONITOR_STATUS */ 1579 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_STATBUF, 1580 .max_rings = 1, 1581 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 1582 .lmac_ring = TRUE, 1583 .ring_dir = HAL_SRNG_SRC_RING, 1584 /* reg_start is not set because LMAC rings are not accessed 1585 * from host 1586 */ 1587 .reg_start = {}, 1588 .reg_size = {}, 1589 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1590 }, 1591 { /* RXDMA_MONITOR_DST */ 1592 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW1, 1593 .max_rings = 1, 1594 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 1595 .lmac_ring = TRUE, 1596 .ring_dir = HAL_SRNG_DST_RING, 1597 /* reg_start is not set because LMAC rings are not accessed 1598 * from host 1599 */ 1600 .reg_start = {}, 1601 .reg_size = {}, 1602 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1603 }, 1604 { /* RXDMA_MONITOR_DESC */ 1605 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_DESC, 1606 .max_rings = 1, 1607 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 1608 .lmac_ring = TRUE, 1609 .ring_dir = HAL_SRNG_SRC_RING, 1610 /* reg_start is not set because LMAC rings are not accessed 1611 * from host 1612 */ 1613 .reg_start = {}, 1614 .reg_size = {}, 1615 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1616 }, 1617 { /* DIR_BUF_RX_DMA_SRC */ 1618 .start_ring_id = HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING, 1619 .max_rings = 1, 1620 .entry_size = 2, 1621 .lmac_ring = TRUE, 1622 .ring_dir = HAL_SRNG_SRC_RING, 1623 /* reg_start is not set because LMAC rings are not accessed 1624 * from host 1625 */ 1626 .reg_start = {}, 1627 .reg_size = {}, 1628 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1629 }, 1630 #ifdef WLAN_FEATURE_CIF_CFR 1631 { /* WIFI_POS_SRC */ 1632 .start_ring_id = HAL_SRNG_WIFI_POS_SRC_DMA_RING, 1633 .max_rings = 1, 1634 .entry_size = sizeof(wmi_oem_dma_buf_release_entry) >> 2, 1635 .lmac_ring = TRUE, 1636 .ring_dir = HAL_SRNG_SRC_RING, 1637 /* reg_start is not set because LMAC rings are not accessed 1638 * from host 1639 */ 1640 .reg_start = {}, 1641 .reg_size = {}, 1642 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1643 }, 1644 #endif 1645 { /* REO2PPE */ 0}, 1646 { /* PPE2TCL */ 0}, 1647 { /* PPE_RELEASE */ 0}, 1648 { /* TX_MONITOR_BUF */ 0}, 1649 { /* TX_MONITOR_DST */ 0}, 1650 { /* SW2RXDMA_NEW */ 0}, 1651 { /* SW2RXDMA_LINK_RELEASE */ 0}, 1652 }; 1653 1654 /** 1655 * hal_qca6290_attach() - Attach 6290 target specific hal_soc ops, 1656 * offset and srng table 1657 * @hal_soc: Pointer to hal_soc 1658 */ 1659 void hal_qca6290_attach(struct hal_soc *hal_soc) 1660 { 1661 hal_soc->hw_srng_table = hw_srng_table_6290; 1662 hal_srng_hw_reg_offset_init_generic(hal_soc); 1663 1664 hal_hw_txrx_default_ops_attach_li(hal_soc); 1665 hal_hw_txrx_ops_attach_6290(hal_soc); 1666 } 1667