1 /* 2 * Copyright (c) 2016-2019 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 #include "qdf_types.h" 19 #include "qdf_util.h" 20 #include "qdf_types.h" 21 #include "qdf_lock.h" 22 #include "qdf_mem.h" 23 #include "qdf_nbuf.h" 24 #include "hal_hw_headers.h" 25 #include "hal_internal.h" 26 #include "hal_api.h" 27 #include "target_type.h" 28 #include "wcss_version.h" 29 #include "qdf_module.h" 30 31 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_OFFSET \ 32 RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_OFFSET 33 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_MASK \ 34 RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_MASK 35 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_LSB \ 36 RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_LSB 37 #define UNIFIED_PHYRX_HT_SIG_0_HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS_OFFSET \ 38 PHYRX_HT_SIG_0_HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS_OFFSET 39 #define UNIFIED_PHYRX_L_SIG_B_0_L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS_OFFSET \ 40 PHYRX_L_SIG_B_0_L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS_OFFSET 41 #define UNIFIED_PHYRX_L_SIG_A_0_L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS_OFFSET \ 42 PHYRX_L_SIG_A_0_L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS_OFFSET 43 #define UNIFIED_PHYRX_VHT_SIG_A_0_VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS_OFFSET \ 44 PHYRX_VHT_SIG_A_0_VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS_OFFSET 45 #define UNIFIED_PHYRX_HE_SIG_A_SU_0_HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS_OFFSET \ 46 PHYRX_HE_SIG_A_SU_0_HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS_OFFSET 47 #define UNIFIED_PHYRX_HE_SIG_A_MU_DL_0_HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_OFFSET \ 48 PHYRX_HE_SIG_A_MU_DL_0_HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_OFFSET 49 #define UNIFIED_PHYRX_HE_SIG_B1_MU_0_HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_OFFSET \ 50 PHYRX_HE_SIG_B1_MU_0_HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_OFFSET 51 #define UNIFIED_PHYRX_HE_SIG_B2_MU_0_HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_OFFSET \ 52 PHYRX_HE_SIG_B2_MU_0_HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_OFFSET 53 #define UNIFIED_PHYRX_HE_SIG_B2_OFDMA_0_HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_OFFSET \ 54 PHYRX_HE_SIG_B2_OFDMA_0_HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_OFFSET 55 #define UNIFIED_PHYRX_RSSI_LEGACY_3_RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS_OFFSET \ 56 PHYRX_RSSI_LEGACY_3_RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS_OFFSET 57 #define UNIFIED_PHYRX_RSSI_LEGACY_19_RECEIVE_RSSI_INFO_PREAMBLE_RSSI_INFO_DETAILS_OFFSET \ 58 PHYRX_RSSI_LEGACY_19_RECEIVE_RSSI_INFO_PREAMBLE_RSSI_INFO_DETAILS_OFFSET 59 #define UNIFIED_RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET \ 60 RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET 61 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 62 RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET 63 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ 64 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET 65 #define UNIFIED_RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 66 RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET 67 #define UNIFIED_REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 68 REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET 69 #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC \ 70 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER 71 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ 72 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET 73 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 74 RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET 75 #define UNIFIED_TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 76 TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET 77 #define UNIFIED_TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 78 TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET 79 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET \ 80 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET 81 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB \ 82 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB 83 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK \ 84 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK 85 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB \ 86 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB 87 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK \ 88 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK 89 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB \ 90 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB 91 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK \ 92 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK 93 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB \ 94 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB 95 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK \ 96 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK 97 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB \ 98 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB 99 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK \ 100 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK 101 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_MASK \ 102 WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_MASK 103 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_OFFSET \ 104 WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_OFFSET 105 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_LSB \ 106 WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_LSB 107 108 #include "hal_6290_tx.h" 109 #include "hal_6290_rx.h" 110 #include <hal_generic_api.h> 111 #include <hal_wbm.h> 112 113 struct hal_hw_txrx_ops qca6290_hal_hw_txrx_ops = { 114 /* init and setup */ 115 hal_srng_dst_hw_init_generic, 116 hal_srng_src_hw_init_generic, 117 hal_get_hw_hptp_generic, 118 hal_reo_setup_generic, 119 hal_setup_link_idle_list_generic, 120 121 /* tx */ 122 hal_tx_desc_set_dscp_tid_table_id_6290, 123 hal_tx_set_dscp_tid_map_6290, 124 hal_tx_update_dscp_tid_6290, 125 hal_tx_desc_set_lmac_id_6290, 126 hal_tx_desc_set_buf_addr_generic, 127 hal_tx_desc_set_search_type_generic, 128 hal_tx_desc_set_search_index_generic, 129 hal_tx_comp_get_status_generic, 130 hal_tx_comp_get_release_reason_generic, 131 132 /* rx */ 133 hal_rx_msdu_start_nss_get_6290, 134 hal_rx_mon_hw_desc_get_mpdu_status_6290, 135 hal_rx_get_tlv_6290, 136 hal_rx_proc_phyrx_other_receive_info_tlv_6290, 137 hal_rx_dump_msdu_start_tlv_6290, 138 hal_rx_dump_msdu_end_tlv_6290, 139 hal_get_link_desc_size_6290, 140 hal_rx_mpdu_start_tid_get_6290, 141 hal_rx_msdu_start_reception_type_get_6290, 142 hal_rx_msdu_end_da_idx_get_6290, 143 hal_rx_msdu_desc_info_get_ptr_generic, 144 hal_rx_link_desc_msdu0_ptr_generic, 145 hal_reo_status_get_header_generic, 146 hal_rx_status_get_tlv_info_generic, 147 hal_rx_wbm_err_info_get_generic, 148 hal_rx_dump_mpdu_start_tlv_generic, 149 150 hal_tx_set_pcp_tid_map_generic, 151 hal_tx_update_pcp_tid_generic, 152 hal_tx_update_tidmap_prty_generic, 153 }; 154 155 struct hal_hw_srng_config hw_srng_table_6290[] = { 156 /* TODO: max_rings can populated by querying HW capabilities */ 157 { /* REO_DST */ 158 .start_ring_id = HAL_SRNG_REO2SW1, 159 .max_rings = 4, 160 .entry_size = sizeof(struct reo_destination_ring) >> 2, 161 .lmac_ring = FALSE, 162 .ring_dir = HAL_SRNG_DST_RING, 163 .reg_start = { 164 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR( 165 SEQ_WCSS_UMAC_REO_REG_OFFSET), 166 HWIO_REO_R2_REO2SW1_RING_HP_ADDR( 167 SEQ_WCSS_UMAC_REO_REG_OFFSET) 168 }, 169 .reg_size = { 170 HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(0) - 171 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(0), 172 HWIO_REO_R2_REO2SW2_RING_HP_ADDR(0) - 173 HWIO_REO_R2_REO2SW1_RING_HP_ADDR(0), 174 }, 175 .max_size = HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_BMSK >> 176 HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_SHFT, 177 }, 178 { /* REO_EXCEPTION */ 179 /* Designating REO2TCL ring as exception ring. This ring is 180 * similar to other REO2SW rings though it is named as REO2TCL. 181 * Any of theREO2SW rings can be used as exception ring. 182 */ 183 .start_ring_id = HAL_SRNG_REO2TCL, 184 .max_rings = 1, 185 .entry_size = sizeof(struct reo_destination_ring) >> 2, 186 .lmac_ring = FALSE, 187 .ring_dir = HAL_SRNG_DST_RING, 188 .reg_start = { 189 HWIO_REO_R0_REO2TCL_RING_BASE_LSB_ADDR( 190 SEQ_WCSS_UMAC_REO_REG_OFFSET), 191 HWIO_REO_R2_REO2TCL_RING_HP_ADDR( 192 SEQ_WCSS_UMAC_REO_REG_OFFSET) 193 }, 194 /* Single ring - provide ring size if multiple rings of this 195 * type are supported 196 */ 197 .reg_size = {}, 198 .max_size = HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_BMSK >> 199 HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_SHFT, 200 }, 201 { /* REO_REINJECT */ 202 .start_ring_id = HAL_SRNG_SW2REO, 203 .max_rings = 1, 204 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 205 .lmac_ring = FALSE, 206 .ring_dir = HAL_SRNG_SRC_RING, 207 .reg_start = { 208 HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR( 209 SEQ_WCSS_UMAC_REO_REG_OFFSET), 210 HWIO_REO_R2_SW2REO_RING_HP_ADDR( 211 SEQ_WCSS_UMAC_REO_REG_OFFSET) 212 }, 213 /* Single ring - provide ring size if multiple rings of this 214 * type are supported 215 */ 216 .reg_size = {}, 217 .max_size = HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_BMSK >> 218 HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_SHFT, 219 }, 220 { /* REO_CMD */ 221 .start_ring_id = HAL_SRNG_REO_CMD, 222 .max_rings = 1, 223 .entry_size = (sizeof(struct tlv_32_hdr) + 224 sizeof(struct reo_get_queue_stats)) >> 2, 225 .lmac_ring = FALSE, 226 .ring_dir = HAL_SRNG_SRC_RING, 227 .reg_start = { 228 HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR( 229 SEQ_WCSS_UMAC_REO_REG_OFFSET), 230 HWIO_REO_R2_REO_CMD_RING_HP_ADDR( 231 SEQ_WCSS_UMAC_REO_REG_OFFSET), 232 }, 233 /* Single ring - provide ring size if multiple rings of this 234 * type are supported 235 */ 236 .reg_size = {}, 237 .max_size = HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_BMSK >> 238 HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_SHFT, 239 }, 240 { /* REO_STATUS */ 241 .start_ring_id = HAL_SRNG_REO_STATUS, 242 .max_rings = 1, 243 .entry_size = (sizeof(struct tlv_32_hdr) + 244 sizeof(struct reo_get_queue_stats_status)) >> 2, 245 .lmac_ring = FALSE, 246 .ring_dir = HAL_SRNG_DST_RING, 247 .reg_start = { 248 HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR( 249 SEQ_WCSS_UMAC_REO_REG_OFFSET), 250 HWIO_REO_R2_REO_STATUS_RING_HP_ADDR( 251 SEQ_WCSS_UMAC_REO_REG_OFFSET), 252 }, 253 /* Single ring - provide ring size if multiple rings of this 254 * type are supported 255 */ 256 .reg_size = {}, 257 .max_size = 258 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> 259 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, 260 }, 261 { /* TCL_DATA */ 262 .start_ring_id = HAL_SRNG_SW2TCL1, 263 .max_rings = 3, 264 .entry_size = (sizeof(struct tlv_32_hdr) + 265 sizeof(struct tcl_data_cmd)) >> 2, 266 .lmac_ring = FALSE, 267 .ring_dir = HAL_SRNG_SRC_RING, 268 .reg_start = { 269 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR( 270 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 271 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR( 272 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 273 }, 274 .reg_size = { 275 HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(0) - 276 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(0), 277 HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(0) - 278 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(0), 279 }, 280 .max_size = HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK >> 281 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT, 282 }, 283 { /* TCL_CMD */ 284 .start_ring_id = HAL_SRNG_SW2TCL_CMD, 285 .max_rings = 1, 286 .entry_size = (sizeof(struct tlv_32_hdr) + 287 sizeof(struct tcl_gse_cmd)) >> 2, 288 .lmac_ring = FALSE, 289 .ring_dir = HAL_SRNG_SRC_RING, 290 .reg_start = { 291 HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_ADDR( 292 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 293 HWIO_TCL_R2_SW2TCL_CMD_RING_HP_ADDR( 294 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 295 }, 296 /* Single ring - provide ring size if multiple rings of this 297 * type are supported 298 */ 299 .reg_size = {}, 300 .max_size = 301 HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RING_SIZE_BMSK >> 302 HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RING_SIZE_SHFT, 303 }, 304 { /* TCL_STATUS */ 305 .start_ring_id = HAL_SRNG_TCL_STATUS, 306 .max_rings = 1, 307 .entry_size = (sizeof(struct tlv_32_hdr) + 308 sizeof(struct tcl_status_ring)) >> 2, 309 .lmac_ring = FALSE, 310 .ring_dir = HAL_SRNG_DST_RING, 311 .reg_start = { 312 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR( 313 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 314 HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR( 315 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 316 }, 317 /* Single ring - provide ring size if multiple rings of this 318 * type are supported 319 */ 320 .reg_size = {}, 321 .max_size = 322 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_BMSK >> 323 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_SHFT, 324 }, 325 { /* CE_SRC */ 326 .start_ring_id = HAL_SRNG_CE_0_SRC, 327 .max_rings = 12, 328 .entry_size = sizeof(struct ce_src_desc) >> 2, 329 .lmac_ring = FALSE, 330 .ring_dir = HAL_SRNG_SRC_RING, 331 .reg_start = { 332 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR( 333 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET), 334 HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR( 335 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET), 336 }, 337 .reg_size = { 338 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET - 339 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET, 340 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET - 341 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET, 342 }, 343 .max_size = 344 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >> 345 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT, 346 }, 347 { /* CE_DST */ 348 .start_ring_id = HAL_SRNG_CE_0_DST, 349 .max_rings = 12, 350 .entry_size = 8 >> 2, 351 /*TODO: entry_size above should actually be 352 * sizeof(struct ce_dst_desc) >> 2, but couldn't find definition 353 * of struct ce_dst_desc in HW header files 354 */ 355 .lmac_ring = FALSE, 356 .ring_dir = HAL_SRNG_SRC_RING, 357 .reg_start = { 358 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR( 359 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 360 HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR( 361 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 362 }, 363 .reg_size = { 364 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 365 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 366 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 367 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 368 }, 369 .max_size = 370 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >> 371 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT, 372 }, 373 { /* CE_DST_STATUS */ 374 .start_ring_id = HAL_SRNG_CE_0_DST_STATUS, 375 .max_rings = 12, 376 .entry_size = sizeof(struct ce_stat_desc) >> 2, 377 .lmac_ring = FALSE, 378 .ring_dir = HAL_SRNG_DST_RING, 379 .reg_start = { 380 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR( 381 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 382 HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR( 383 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 384 }, 385 /* TODO: check destination status ring registers */ 386 .reg_size = { 387 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 388 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 389 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 390 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 391 }, 392 .max_size = 393 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> 394 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, 395 }, 396 { /* WBM_IDLE_LINK */ 397 .start_ring_id = HAL_SRNG_WBM_IDLE_LINK, 398 .max_rings = 1, 399 .entry_size = sizeof(struct wbm_link_descriptor_ring) >> 2, 400 .lmac_ring = FALSE, 401 .ring_dir = HAL_SRNG_SRC_RING, 402 .reg_start = { 403 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 404 HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 405 }, 406 /* Single ring - provide ring size if multiple rings of this 407 * type are supported 408 */ 409 .reg_size = {}, 410 .max_size = 411 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_BMSK >> 412 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_SHFT, 413 }, 414 { /* SW2WBM_RELEASE */ 415 .start_ring_id = HAL_SRNG_WBM_SW_RELEASE, 416 .max_rings = 1, 417 .entry_size = sizeof(struct wbm_release_ring) >> 2, 418 .lmac_ring = FALSE, 419 .ring_dir = HAL_SRNG_SRC_RING, 420 .reg_start = { 421 HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 422 HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 423 }, 424 /* Single ring - provide ring size if multiple rings of this 425 * type are supported 426 */ 427 .reg_size = {}, 428 .max_size = 429 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> 430 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, 431 }, 432 { /* WBM2SW_RELEASE */ 433 .start_ring_id = HAL_SRNG_WBM2SW0_RELEASE, 434 .max_rings = 4, 435 .entry_size = sizeof(struct wbm_release_ring) >> 2, 436 .lmac_ring = FALSE, 437 .ring_dir = HAL_SRNG_DST_RING, 438 .reg_start = { 439 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 440 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 441 }, 442 .reg_size = { 443 HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) - 444 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 445 HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) - 446 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 447 }, 448 .max_size = 449 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> 450 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, 451 }, 452 { /* RXDMA_BUF */ 453 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA0_BUF0, 454 #ifdef IPA_OFFLOAD 455 .max_rings = 3, 456 #else 457 .max_rings = 2, 458 #endif 459 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 460 .lmac_ring = TRUE, 461 .ring_dir = HAL_SRNG_SRC_RING, 462 /* reg_start is not set because LMAC rings are not accessed 463 * from host 464 */ 465 .reg_start = {}, 466 .reg_size = {}, 467 .max_size = HAL_RXDMA_MAX_RING_SIZE, 468 }, 469 { /* RXDMA_DST */ 470 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW0, 471 .max_rings = 1, 472 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 473 .lmac_ring = TRUE, 474 .ring_dir = HAL_SRNG_DST_RING, 475 /* reg_start is not set because LMAC rings are not accessed 476 * from host 477 */ 478 .reg_start = {}, 479 .reg_size = {}, 480 .max_size = HAL_RXDMA_MAX_RING_SIZE, 481 }, 482 { /* RXDMA_MONITOR_BUF */ 483 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA2_BUF, 484 .max_rings = 1, 485 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 486 .lmac_ring = TRUE, 487 .ring_dir = HAL_SRNG_SRC_RING, 488 /* reg_start is not set because LMAC rings are not accessed 489 * from host 490 */ 491 .reg_start = {}, 492 .reg_size = {}, 493 .max_size = HAL_RXDMA_MAX_RING_SIZE, 494 }, 495 { /* RXDMA_MONITOR_STATUS */ 496 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_STATBUF, 497 .max_rings = 1, 498 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 499 .lmac_ring = TRUE, 500 .ring_dir = HAL_SRNG_SRC_RING, 501 /* reg_start is not set because LMAC rings are not accessed 502 * from host 503 */ 504 .reg_start = {}, 505 .reg_size = {}, 506 .max_size = HAL_RXDMA_MAX_RING_SIZE, 507 }, 508 { /* RXDMA_MONITOR_DST */ 509 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW1, 510 .max_rings = 1, 511 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 512 .lmac_ring = TRUE, 513 .ring_dir = HAL_SRNG_DST_RING, 514 /* reg_start is not set because LMAC rings are not accessed 515 * from host 516 */ 517 .reg_start = {}, 518 .reg_size = {}, 519 .max_size = HAL_RXDMA_MAX_RING_SIZE, 520 }, 521 { /* RXDMA_MONITOR_DESC */ 522 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_DESC, 523 .max_rings = 1, 524 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 525 .lmac_ring = TRUE, 526 .ring_dir = HAL_SRNG_SRC_RING, 527 /* reg_start is not set because LMAC rings are not accessed 528 * from host 529 */ 530 .reg_start = {}, 531 .reg_size = {}, 532 .max_size = HAL_RXDMA_MAX_RING_SIZE, 533 }, 534 { /* DIR_BUF_RX_DMA_SRC */ 535 .start_ring_id = HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING, 536 .max_rings = 1, 537 .entry_size = 2, 538 .lmac_ring = TRUE, 539 .ring_dir = HAL_SRNG_SRC_RING, 540 /* reg_start is not set because LMAC rings are not accessed 541 * from host 542 */ 543 .reg_start = {}, 544 .reg_size = {}, 545 .max_size = HAL_RXDMA_MAX_RING_SIZE, 546 }, 547 #ifdef WLAN_FEATURE_CIF_CFR 548 { /* WIFI_POS_SRC */ 549 .start_ring_id = HAL_SRNG_WIFI_POS_SRC_DMA_RING, 550 .max_rings = 1, 551 .entry_size = sizeof(wmi_oem_dma_buf_release_entry) >> 2, 552 .lmac_ring = TRUE, 553 .ring_dir = HAL_SRNG_SRC_RING, 554 /* reg_start is not set because LMAC rings are not accessed 555 * from host 556 */ 557 .reg_start = {}, 558 .reg_size = {}, 559 .max_size = HAL_RXDMA_MAX_RING_SIZE, 560 }, 561 #endif 562 }; 563 564 int32_t hal_hw_reg_offset_qca6290[] = { 565 /* dst */ 566 REG_OFFSET(DST, HP), 567 REG_OFFSET(DST, TP), 568 REG_OFFSET(DST, ID), 569 REG_OFFSET(DST, MISC), 570 REG_OFFSET(DST, HP_ADDR_LSB), 571 REG_OFFSET(DST, HP_ADDR_MSB), 572 REG_OFFSET(DST, MSI1_BASE_LSB), 573 REG_OFFSET(DST, MSI1_BASE_MSB), 574 REG_OFFSET(DST, MSI1_DATA), 575 REG_OFFSET(DST, BASE_LSB), 576 REG_OFFSET(DST, BASE_MSB), 577 REG_OFFSET(DST, PRODUCER_INT_SETUP), 578 /* src */ 579 REG_OFFSET(SRC, HP), 580 REG_OFFSET(SRC, TP), 581 REG_OFFSET(SRC, ID), 582 REG_OFFSET(SRC, MISC), 583 REG_OFFSET(SRC, TP_ADDR_LSB), 584 REG_OFFSET(SRC, TP_ADDR_MSB), 585 REG_OFFSET(SRC, MSI1_BASE_LSB), 586 REG_OFFSET(SRC, MSI1_BASE_MSB), 587 REG_OFFSET(SRC, MSI1_DATA), 588 REG_OFFSET(SRC, BASE_LSB), 589 REG_OFFSET(SRC, BASE_MSB), 590 REG_OFFSET(SRC, CONSUMER_INT_SETUP_IX0), 591 REG_OFFSET(SRC, CONSUMER_INT_SETUP_IX1), 592 }; 593 594 /** 595 * hal_qca6290_attach() - Attach 6290 target specific hal_soc ops, 596 * offset and srng table 597 */ 598 void hal_qca6290_attach(struct hal_soc *hal_soc) 599 { 600 hal_soc->hw_srng_table = hw_srng_table_6290; 601 hal_soc->hal_hw_reg_offset = hal_hw_reg_offset_qca6290; 602 hal_soc->ops = &qca6290_hal_hw_txrx_ops; 603 } 604