1 /* 2 * Copyright (c) 2016-2018 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 #include "qdf_types.h" 19 #include "qdf_util.h" 20 #include "qdf_types.h" 21 #include "qdf_lock.h" 22 #include "qdf_mem.h" 23 #include "qdf_nbuf.h" 24 #include "hal_hw_headers.h" 25 #include "hal_internal.h" 26 #include "hal_api.h" 27 #include "target_type.h" 28 #include "wcss_version.h" 29 #include "qdf_module.h" 30 31 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_OFFSET \ 32 RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_OFFSET 33 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_MASK \ 34 RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_MASK 35 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_LSB \ 36 RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_LSB 37 #define UNIFIED_PHYRX_HT_SIG_0_HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS_OFFSET \ 38 PHYRX_HT_SIG_0_HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS_OFFSET 39 #define UNIFIED_PHYRX_L_SIG_B_0_L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS_OFFSET \ 40 PHYRX_L_SIG_B_0_L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS_OFFSET 41 #define UNIFIED_PHYRX_L_SIG_A_0_L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS_OFFSET \ 42 PHYRX_L_SIG_A_0_L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS_OFFSET 43 #define UNIFIED_PHYRX_VHT_SIG_A_0_VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS_OFFSET \ 44 PHYRX_VHT_SIG_A_0_VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS_OFFSET 45 #define UNIFIED_PHYRX_HE_SIG_A_SU_0_HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS_OFFSET \ 46 PHYRX_HE_SIG_A_SU_0_HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS_OFFSET 47 #define UNIFIED_PHYRX_HE_SIG_A_MU_DL_0_HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_OFFSET \ 48 PHYRX_HE_SIG_A_MU_DL_0_HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_OFFSET 49 #define UNIFIED_PHYRX_HE_SIG_B1_MU_0_HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_OFFSET \ 50 PHYRX_HE_SIG_B1_MU_0_HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_OFFSET 51 #define UNIFIED_PHYRX_HE_SIG_B2_MU_0_HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_OFFSET \ 52 PHYRX_HE_SIG_B2_MU_0_HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_OFFSET 53 #define UNIFIED_PHYRX_HE_SIG_B2_OFDMA_0_HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_OFFSET \ 54 PHYRX_HE_SIG_B2_OFDMA_0_HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_OFFSET 55 #define UNIFIED_PHYRX_RSSI_LEGACY_3_RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS_OFFSET \ 56 PHYRX_RSSI_LEGACY_3_RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS_OFFSET 57 #define UNIFIED_RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET \ 58 RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET 59 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 60 RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET 61 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ 62 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET 63 #define UNIFIED_RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 64 RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET 65 #define UNIFIED_REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 66 REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET 67 #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC \ 68 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER 69 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ 70 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET 71 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 72 RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET 73 #define UNIFIED_TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 74 TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET 75 #define UNIFIED_TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 76 TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET 77 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET \ 78 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET 79 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB \ 80 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB 81 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK \ 82 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK 83 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB \ 84 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB 85 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK \ 86 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK 87 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB \ 88 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB 89 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK \ 90 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK 91 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB \ 92 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB 93 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK \ 94 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK 95 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB \ 96 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB 97 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK \ 98 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK 99 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_MASK \ 100 WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_MASK 101 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_OFFSET \ 102 WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_OFFSET 103 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_LSB \ 104 WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_LSB 105 106 #include "hal_6290_tx.h" 107 #include "hal_6290_rx.h" 108 #include <hal_generic_api.h> 109 #include <hal_wbm.h> 110 111 struct hal_hw_txrx_ops qca6290_hal_hw_txrx_ops = { 112 /* init and setup */ 113 hal_srng_dst_hw_init_generic, 114 hal_srng_src_hw_init_generic, 115 hal_reo_setup_generic, 116 hal_setup_link_idle_list_generic, 117 118 /* tx */ 119 hal_tx_desc_set_dscp_tid_table_id_6290, 120 hal_tx_set_dscp_tid_map_6290, 121 hal_tx_update_dscp_tid_6290, 122 hal_tx_desc_set_lmac_id_6290, 123 hal_tx_desc_set_buf_addr_generic, 124 hal_tx_desc_set_search_type_generic, 125 hal_tx_desc_set_search_index_generic, 126 hal_tx_comp_get_status_generic, 127 hal_tx_comp_get_release_reason_generic, 128 129 /* rx */ 130 hal_rx_msdu_start_nss_get_6290, 131 hal_rx_mon_hw_desc_get_mpdu_status_6290, 132 hal_rx_get_tlv_6290, 133 hal_rx_proc_phyrx_other_receive_info_tlv_6290, 134 hal_rx_dump_msdu_start_tlv_6290, 135 hal_rx_dump_msdu_end_tlv_6290, 136 hal_get_link_desc_size_6290, 137 hal_rx_mpdu_start_tid_get_6290, 138 hal_rx_msdu_start_reception_type_get_6290, 139 hal_rx_msdu_end_da_idx_get_6290, 140 hal_rx_msdu_desc_info_get_ptr_generic, 141 hal_rx_link_desc_msdu0_ptr_generic, 142 hal_reo_status_get_header_generic, 143 hal_rx_status_get_tlv_info_generic, 144 hal_rx_wbm_err_info_get_generic, 145 hal_rx_dump_mpdu_start_tlv_generic, 146 }; 147 148 struct hal_hw_srng_config hw_srng_table_6290[] = { 149 /* TODO: max_rings can populated by querying HW capabilities */ 150 { /* REO_DST */ 151 .start_ring_id = HAL_SRNG_REO2SW1, 152 .max_rings = 4, 153 .entry_size = sizeof(struct reo_destination_ring) >> 2, 154 .lmac_ring = FALSE, 155 .ring_dir = HAL_SRNG_DST_RING, 156 .reg_start = { 157 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR( 158 SEQ_WCSS_UMAC_REO_REG_OFFSET), 159 HWIO_REO_R2_REO2SW1_RING_HP_ADDR( 160 SEQ_WCSS_UMAC_REO_REG_OFFSET) 161 }, 162 .reg_size = { 163 HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(0) - 164 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(0), 165 HWIO_REO_R2_REO2SW2_RING_HP_ADDR(0) - 166 HWIO_REO_R2_REO2SW1_RING_HP_ADDR(0), 167 }, 168 .max_size = HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_BMSK >> 169 HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_SHFT, 170 }, 171 { /* REO_EXCEPTION */ 172 /* Designating REO2TCL ring as exception ring. This ring is 173 * similar to other REO2SW rings though it is named as REO2TCL. 174 * Any of theREO2SW rings can be used as exception ring. 175 */ 176 .start_ring_id = HAL_SRNG_REO2TCL, 177 .max_rings = 1, 178 .entry_size = sizeof(struct reo_destination_ring) >> 2, 179 .lmac_ring = FALSE, 180 .ring_dir = HAL_SRNG_DST_RING, 181 .reg_start = { 182 HWIO_REO_R0_REO2TCL_RING_BASE_LSB_ADDR( 183 SEQ_WCSS_UMAC_REO_REG_OFFSET), 184 HWIO_REO_R2_REO2TCL_RING_HP_ADDR( 185 SEQ_WCSS_UMAC_REO_REG_OFFSET) 186 }, 187 /* Single ring - provide ring size if multiple rings of this 188 * type are supported 189 */ 190 .reg_size = {}, 191 .max_size = HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_BMSK >> 192 HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_SHFT, 193 }, 194 { /* REO_REINJECT */ 195 .start_ring_id = HAL_SRNG_SW2REO, 196 .max_rings = 1, 197 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 198 .lmac_ring = FALSE, 199 .ring_dir = HAL_SRNG_SRC_RING, 200 .reg_start = { 201 HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR( 202 SEQ_WCSS_UMAC_REO_REG_OFFSET), 203 HWIO_REO_R2_SW2REO_RING_HP_ADDR( 204 SEQ_WCSS_UMAC_REO_REG_OFFSET) 205 }, 206 /* Single ring - provide ring size if multiple rings of this 207 * type are supported 208 */ 209 .reg_size = {}, 210 .max_size = HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_BMSK >> 211 HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_SHFT, 212 }, 213 { /* REO_CMD */ 214 .start_ring_id = HAL_SRNG_REO_CMD, 215 .max_rings = 1, 216 .entry_size = (sizeof(struct tlv_32_hdr) + 217 sizeof(struct reo_get_queue_stats)) >> 2, 218 .lmac_ring = FALSE, 219 .ring_dir = HAL_SRNG_SRC_RING, 220 .reg_start = { 221 HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR( 222 SEQ_WCSS_UMAC_REO_REG_OFFSET), 223 HWIO_REO_R2_REO_CMD_RING_HP_ADDR( 224 SEQ_WCSS_UMAC_REO_REG_OFFSET), 225 }, 226 /* Single ring - provide ring size if multiple rings of this 227 * type are supported 228 */ 229 .reg_size = {}, 230 .max_size = HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_BMSK >> 231 HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_SHFT, 232 }, 233 { /* REO_STATUS */ 234 .start_ring_id = HAL_SRNG_REO_STATUS, 235 .max_rings = 1, 236 .entry_size = (sizeof(struct tlv_32_hdr) + 237 sizeof(struct reo_get_queue_stats_status)) >> 2, 238 .lmac_ring = FALSE, 239 .ring_dir = HAL_SRNG_DST_RING, 240 .reg_start = { 241 HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR( 242 SEQ_WCSS_UMAC_REO_REG_OFFSET), 243 HWIO_REO_R2_REO_STATUS_RING_HP_ADDR( 244 SEQ_WCSS_UMAC_REO_REG_OFFSET), 245 }, 246 /* Single ring - provide ring size if multiple rings of this 247 * type are supported 248 */ 249 .reg_size = {}, 250 .max_size = 251 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> 252 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, 253 }, 254 { /* TCL_DATA */ 255 .start_ring_id = HAL_SRNG_SW2TCL1, 256 .max_rings = 3, 257 .entry_size = (sizeof(struct tlv_32_hdr) + 258 sizeof(struct tcl_data_cmd)) >> 2, 259 .lmac_ring = FALSE, 260 .ring_dir = HAL_SRNG_SRC_RING, 261 .reg_start = { 262 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR( 263 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 264 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR( 265 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 266 }, 267 .reg_size = { 268 HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(0) - 269 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(0), 270 HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(0) - 271 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(0), 272 }, 273 .max_size = HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK >> 274 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT, 275 }, 276 { /* TCL_CMD */ 277 .start_ring_id = HAL_SRNG_SW2TCL_CMD, 278 .max_rings = 1, 279 .entry_size = (sizeof(struct tlv_32_hdr) + 280 sizeof(struct tcl_gse_cmd)) >> 2, 281 .lmac_ring = FALSE, 282 .ring_dir = HAL_SRNG_SRC_RING, 283 .reg_start = { 284 HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_ADDR( 285 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 286 HWIO_TCL_R2_SW2TCL_CMD_RING_HP_ADDR( 287 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 288 }, 289 /* Single ring - provide ring size if multiple rings of this 290 * type are supported 291 */ 292 .reg_size = {}, 293 .max_size = 294 HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RING_SIZE_BMSK >> 295 HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RING_SIZE_SHFT, 296 }, 297 { /* TCL_STATUS */ 298 .start_ring_id = HAL_SRNG_TCL_STATUS, 299 .max_rings = 1, 300 .entry_size = (sizeof(struct tlv_32_hdr) + 301 sizeof(struct tcl_status_ring)) >> 2, 302 .lmac_ring = FALSE, 303 .ring_dir = HAL_SRNG_DST_RING, 304 .reg_start = { 305 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR( 306 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 307 HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR( 308 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 309 }, 310 /* Single ring - provide ring size if multiple rings of this 311 * type are supported 312 */ 313 .reg_size = {}, 314 .max_size = 315 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_BMSK >> 316 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_SHFT, 317 }, 318 { /* CE_SRC */ 319 .start_ring_id = HAL_SRNG_CE_0_SRC, 320 .max_rings = 12, 321 .entry_size = sizeof(struct ce_src_desc) >> 2, 322 .lmac_ring = FALSE, 323 .ring_dir = HAL_SRNG_SRC_RING, 324 .reg_start = { 325 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR( 326 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET), 327 HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR( 328 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET), 329 }, 330 .reg_size = { 331 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET - 332 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET, 333 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET - 334 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET, 335 }, 336 .max_size = 337 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >> 338 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT, 339 }, 340 { /* CE_DST */ 341 .start_ring_id = HAL_SRNG_CE_0_DST, 342 .max_rings = 12, 343 .entry_size = 8 >> 2, 344 /*TODO: entry_size above should actually be 345 * sizeof(struct ce_dst_desc) >> 2, but couldn't find definition 346 * of struct ce_dst_desc in HW header files 347 */ 348 .lmac_ring = FALSE, 349 .ring_dir = HAL_SRNG_SRC_RING, 350 .reg_start = { 351 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR( 352 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 353 HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR( 354 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 355 }, 356 .reg_size = { 357 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 358 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 359 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 360 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 361 }, 362 .max_size = 363 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >> 364 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT, 365 }, 366 { /* CE_DST_STATUS */ 367 .start_ring_id = HAL_SRNG_CE_0_DST_STATUS, 368 .max_rings = 12, 369 .entry_size = sizeof(struct ce_stat_desc) >> 2, 370 .lmac_ring = FALSE, 371 .ring_dir = HAL_SRNG_DST_RING, 372 .reg_start = { 373 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR( 374 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 375 HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR( 376 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 377 }, 378 /* TODO: check destination status ring registers */ 379 .reg_size = { 380 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 381 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 382 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 383 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 384 }, 385 .max_size = 386 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> 387 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, 388 }, 389 { /* WBM_IDLE_LINK */ 390 .start_ring_id = HAL_SRNG_WBM_IDLE_LINK, 391 .max_rings = 1, 392 .entry_size = sizeof(struct wbm_link_descriptor_ring) >> 2, 393 .lmac_ring = FALSE, 394 .ring_dir = HAL_SRNG_SRC_RING, 395 .reg_start = { 396 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 397 HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 398 }, 399 /* Single ring - provide ring size if multiple rings of this 400 * type are supported 401 */ 402 .reg_size = {}, 403 .max_size = 404 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_BMSK >> 405 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_SHFT, 406 }, 407 { /* SW2WBM_RELEASE */ 408 .start_ring_id = HAL_SRNG_WBM_SW_RELEASE, 409 .max_rings = 1, 410 .entry_size = sizeof(struct wbm_release_ring) >> 2, 411 .lmac_ring = FALSE, 412 .ring_dir = HAL_SRNG_SRC_RING, 413 .reg_start = { 414 HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 415 HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 416 }, 417 /* Single ring - provide ring size if multiple rings of this 418 * type are supported 419 */ 420 .reg_size = {}, 421 .max_size = 422 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> 423 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, 424 }, 425 { /* WBM2SW_RELEASE */ 426 .start_ring_id = HAL_SRNG_WBM2SW0_RELEASE, 427 .max_rings = 4, 428 .entry_size = sizeof(struct wbm_release_ring) >> 2, 429 .lmac_ring = FALSE, 430 .ring_dir = HAL_SRNG_DST_RING, 431 .reg_start = { 432 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 433 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 434 }, 435 .reg_size = { 436 HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) - 437 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 438 HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) - 439 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 440 }, 441 .max_size = 442 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> 443 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, 444 }, 445 { /* RXDMA_BUF */ 446 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA0_BUF0, 447 #ifdef IPA_OFFLOAD 448 .max_rings = 3, 449 #else 450 .max_rings = 2, 451 #endif 452 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 453 .lmac_ring = TRUE, 454 .ring_dir = HAL_SRNG_SRC_RING, 455 /* reg_start is not set because LMAC rings are not accessed 456 * from host 457 */ 458 .reg_start = {}, 459 .reg_size = {}, 460 .max_size = HAL_RXDMA_MAX_RING_SIZE, 461 }, 462 { /* RXDMA_DST */ 463 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW0, 464 .max_rings = 1, 465 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 466 .lmac_ring = TRUE, 467 .ring_dir = HAL_SRNG_DST_RING, 468 /* reg_start is not set because LMAC rings are not accessed 469 * from host 470 */ 471 .reg_start = {}, 472 .reg_size = {}, 473 .max_size = HAL_RXDMA_MAX_RING_SIZE, 474 }, 475 { /* RXDMA_MONITOR_BUF */ 476 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA2_BUF, 477 .max_rings = 1, 478 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 479 .lmac_ring = TRUE, 480 .ring_dir = HAL_SRNG_SRC_RING, 481 /* reg_start is not set because LMAC rings are not accessed 482 * from host 483 */ 484 .reg_start = {}, 485 .reg_size = {}, 486 .max_size = HAL_RXDMA_MAX_RING_SIZE, 487 }, 488 { /* RXDMA_MONITOR_STATUS */ 489 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_STATBUF, 490 .max_rings = 1, 491 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 492 .lmac_ring = TRUE, 493 .ring_dir = HAL_SRNG_SRC_RING, 494 /* reg_start is not set because LMAC rings are not accessed 495 * from host 496 */ 497 .reg_start = {}, 498 .reg_size = {}, 499 .max_size = HAL_RXDMA_MAX_RING_SIZE, 500 }, 501 { /* RXDMA_MONITOR_DST */ 502 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW1, 503 .max_rings = 1, 504 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 505 .lmac_ring = TRUE, 506 .ring_dir = HAL_SRNG_DST_RING, 507 /* reg_start is not set because LMAC rings are not accessed 508 * from host 509 */ 510 .reg_start = {}, 511 .reg_size = {}, 512 .max_size = HAL_RXDMA_MAX_RING_SIZE, 513 }, 514 { /* RXDMA_MONITOR_DESC */ 515 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_DESC, 516 .max_rings = 1, 517 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 518 .lmac_ring = TRUE, 519 .ring_dir = HAL_SRNG_SRC_RING, 520 /* reg_start is not set because LMAC rings are not accessed 521 * from host 522 */ 523 .reg_start = {}, 524 .reg_size = {}, 525 .max_size = HAL_RXDMA_MAX_RING_SIZE, 526 }, 527 { /* DIR_BUF_RX_DMA_SRC */ 528 .start_ring_id = HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING, 529 .max_rings = 1, 530 .entry_size = 2, 531 .lmac_ring = TRUE, 532 .ring_dir = HAL_SRNG_SRC_RING, 533 /* reg_start is not set because LMAC rings are not accessed 534 * from host 535 */ 536 .reg_start = {}, 537 .reg_size = {}, 538 .max_size = HAL_RXDMA_MAX_RING_SIZE, 539 }, 540 #ifdef WLAN_FEATURE_CIF_CFR 541 { /* WIFI_POS_SRC */ 542 .start_ring_id = HAL_SRNG_WIFI_POS_SRC_DMA_RING, 543 .max_rings = 1, 544 .entry_size = sizeof(wmi_oem_dma_buf_release_entry) >> 2, 545 .lmac_ring = TRUE, 546 .ring_dir = HAL_SRNG_SRC_RING, 547 /* reg_start is not set because LMAC rings are not accessed 548 * from host 549 */ 550 .reg_start = {}, 551 .reg_size = {}, 552 .max_size = HAL_RXDMA_MAX_RING_SIZE, 553 }, 554 #endif 555 }; 556 557 int32_t hal_hw_reg_offset_qca6290[] = { 558 /* dst */ 559 REG_OFFSET(DST, HP), 560 REG_OFFSET(DST, TP), 561 REG_OFFSET(DST, ID), 562 REG_OFFSET(DST, MISC), 563 REG_OFFSET(DST, HP_ADDR_LSB), 564 REG_OFFSET(DST, HP_ADDR_MSB), 565 REG_OFFSET(DST, MSI1_BASE_LSB), 566 REG_OFFSET(DST, MSI1_BASE_MSB), 567 REG_OFFSET(DST, MSI1_DATA), 568 REG_OFFSET(DST, BASE_LSB), 569 REG_OFFSET(DST, BASE_MSB), 570 REG_OFFSET(DST, PRODUCER_INT_SETUP), 571 /* src */ 572 REG_OFFSET(SRC, HP), 573 REG_OFFSET(SRC, TP), 574 REG_OFFSET(SRC, ID), 575 REG_OFFSET(SRC, MISC), 576 REG_OFFSET(SRC, TP_ADDR_LSB), 577 REG_OFFSET(SRC, TP_ADDR_MSB), 578 REG_OFFSET(SRC, MSI1_BASE_LSB), 579 REG_OFFSET(SRC, MSI1_BASE_MSB), 580 REG_OFFSET(SRC, MSI1_DATA), 581 REG_OFFSET(SRC, BASE_LSB), 582 REG_OFFSET(SRC, BASE_MSB), 583 REG_OFFSET(SRC, CONSUMER_INT_SETUP_IX0), 584 REG_OFFSET(SRC, CONSUMER_INT_SETUP_IX1), 585 }; 586 587 /** 588 * hal_qca6290_attach() - Attach 6290 target specific hal_soc ops, 589 * offset and srng table 590 */ 591 void hal_qca6290_attach(struct hal_soc *hal_soc) 592 { 593 hal_soc->hw_srng_table = hw_srng_table_6290; 594 hal_soc->hal_hw_reg_offset = hal_hw_reg_offset_qca6290; 595 hal_soc->ops = &qca6290_hal_hw_txrx_ops; 596 } 597