1 /* 2 * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved. 3 * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 #include "qdf_types.h" 20 #include "qdf_util.h" 21 #include "qdf_types.h" 22 #include "qdf_lock.h" 23 #include "qdf_mem.h" 24 #include "qdf_nbuf.h" 25 #include "hal_li_hw_headers.h" 26 #include "hal_internal.h" 27 #include "hal_api.h" 28 #include "target_type.h" 29 #include "wcss_version.h" 30 #include "qdf_module.h" 31 32 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_OFFSET \ 33 RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_OFFSET 34 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_MASK \ 35 RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_MASK 36 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_LSB \ 37 RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_LSB 38 #define UNIFIED_PHYRX_HT_SIG_0_HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS_OFFSET \ 39 PHYRX_HT_SIG_0_HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS_OFFSET 40 #define UNIFIED_PHYRX_L_SIG_B_0_L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS_OFFSET \ 41 PHYRX_L_SIG_B_0_L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS_OFFSET 42 #define UNIFIED_PHYRX_L_SIG_A_0_L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS_OFFSET \ 43 PHYRX_L_SIG_A_0_L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS_OFFSET 44 #define UNIFIED_PHYRX_VHT_SIG_A_0_VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS_OFFSET \ 45 PHYRX_VHT_SIG_A_0_VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS_OFFSET 46 #define UNIFIED_PHYRX_HE_SIG_A_SU_0_HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS_OFFSET \ 47 PHYRX_HE_SIG_A_SU_0_HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS_OFFSET 48 #define UNIFIED_PHYRX_HE_SIG_A_MU_DL_0_HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_OFFSET \ 49 PHYRX_HE_SIG_A_MU_DL_0_HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_OFFSET 50 #define UNIFIED_PHYRX_HE_SIG_B1_MU_0_HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_OFFSET \ 51 PHYRX_HE_SIG_B1_MU_0_HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_OFFSET 52 #define UNIFIED_PHYRX_HE_SIG_B2_MU_0_HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_OFFSET \ 53 PHYRX_HE_SIG_B2_MU_0_HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_OFFSET 54 #define UNIFIED_PHYRX_HE_SIG_B2_OFDMA_0_HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_OFFSET \ 55 PHYRX_HE_SIG_B2_OFDMA_0_HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_OFFSET 56 #define UNIFIED_PHYRX_RSSI_LEGACY_3_RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS_OFFSET \ 57 PHYRX_RSSI_LEGACY_3_RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS_OFFSET 58 #define UNIFIED_PHYRX_RSSI_LEGACY_19_RECEIVE_RSSI_INFO_PREAMBLE_RSSI_INFO_DETAILS_OFFSET \ 59 PHYRX_RSSI_LEGACY_19_RECEIVE_RSSI_INFO_PREAMBLE_RSSI_INFO_DETAILS_OFFSET 60 #define UNIFIED_RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET \ 61 RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET 62 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 63 RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET 64 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ 65 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET 66 #define UNIFIED_RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 67 RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET 68 #define UNIFIED_REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 69 REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET 70 #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC \ 71 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER 72 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ 73 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET 74 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 75 RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET 76 #define UNIFIED_TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 77 TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET 78 #define UNIFIED_TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 79 TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET 80 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET \ 81 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET 82 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB \ 83 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB 84 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK \ 85 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK 86 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB \ 87 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB 88 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK \ 89 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK 90 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB \ 91 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB 92 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK \ 93 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK 94 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB \ 95 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB 96 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK \ 97 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK 98 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB \ 99 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB 100 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK \ 101 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK 102 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_MASK \ 103 WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_MASK 104 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_OFFSET \ 105 WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_OFFSET 106 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_LSB \ 107 WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_LSB 108 109 #include "hal_6290_tx.h" 110 #include "hal_6290_rx.h" 111 #include <hal_generic_api.h> 112 #include "hal_li_rx.h" 113 #include "hal_li_api.h" 114 #include "hal_li_generic_api.h" 115 116 /** 117 * hal_rx_get_rx_fragment_number_6290(): Function to retrieve rx fragment number 118 * 119 * @nbuf: Network buffer 120 * Returns: rx fragment number 121 */ 122 static 123 uint8_t hal_rx_get_rx_fragment_number_6290(uint8_t *buf) 124 { 125 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 126 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 127 128 /* Return first 4 bits as fragment number */ 129 return (HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info) & 130 DOT11_SEQ_FRAG_MASK); 131 } 132 133 /** 134 * hal_rx_msdu_end_da_is_mcbc_get: API to check if pkt is MCBC 135 * from rx_msdu_end TLV 136 * 137 * @ buf: pointer to the start of RX PKT TLV headers 138 * Return: da_is_mcbc 139 */ 140 static inline uint8_t 141 hal_rx_msdu_end_da_is_mcbc_get_6290(uint8_t *buf) 142 { 143 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 144 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 145 146 return HAL_RX_MSDU_END_DA_IS_MCBC_GET(msdu_end); 147 } 148 149 /** 150 * hal_rx_msdu_end_sa_is_valid_get_6290(): API to get_6290 the 151 * sa_is_valid bit from rx_msdu_end TLV 152 * 153 * @ buf: pointer to the start of RX PKT TLV headers 154 * Return: sa_is_valid bit 155 */ 156 static uint8_t 157 hal_rx_msdu_end_sa_is_valid_get_6290(uint8_t *buf) 158 { 159 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 160 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 161 uint8_t sa_is_valid; 162 163 sa_is_valid = HAL_RX_MSDU_END_SA_IS_VALID_GET(msdu_end); 164 165 return sa_is_valid; 166 } 167 168 /** 169 * hal_rx_msdu_end_sa_idx_get_6290(): API to get_6290 the 170 * sa_idx from rx_msdu_end TLV 171 * 172 * @ buf: pointer to the start of RX PKT TLV headers 173 * Return: sa_idx (SA AST index) 174 */ 175 static 176 uint16_t hal_rx_msdu_end_sa_idx_get_6290(uint8_t *buf) 177 { 178 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 179 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 180 uint16_t sa_idx; 181 182 sa_idx = HAL_RX_MSDU_END_SA_IDX_GET(msdu_end); 183 184 return sa_idx; 185 } 186 187 /** 188 * hal_rx_desc_is_first_msdu_6290() - Check if first msdu 189 * 190 * @hal_soc_hdl: hal_soc handle 191 * @hw_desc_addr: hardware descriptor address 192 * 193 * Return: 0 - success/ non-zero failure 194 */ 195 static uint32_t hal_rx_desc_is_first_msdu_6290(void *hw_desc_addr) 196 { 197 struct rx_pkt_tlvs *rx_tlvs = (struct rx_pkt_tlvs *)hw_desc_addr; 198 struct rx_msdu_end *msdu_end = &rx_tlvs->msdu_end_tlv.rx_msdu_end; 199 200 return HAL_RX_GET(msdu_end, RX_MSDU_END_5, FIRST_MSDU); 201 } 202 203 /** 204 * hal_rx_msdu_end_l3_hdr_padding_get_6290(): API to get_6290 the 205 * l3_header padding from rx_msdu_end TLV 206 * 207 * @ buf: pointer to the start of RX PKT TLV headers 208 * Return: number of l3 header padding bytes 209 */ 210 static uint32_t hal_rx_msdu_end_l3_hdr_padding_get_6290(uint8_t *buf) 211 { 212 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 213 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 214 uint32_t l3_header_padding; 215 216 l3_header_padding = HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(msdu_end); 217 218 return l3_header_padding; 219 } 220 221 /* 222 * @ hal_rx_encryption_info_valid_6290: Returns encryption type. 223 * 224 * @ buf: rx_tlv_hdr of the received packet 225 * @ Return: encryption type 226 */ 227 static uint32_t hal_rx_encryption_info_valid_6290(uint8_t *buf) 228 { 229 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 230 struct rx_mpdu_start *mpdu_start = 231 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 232 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 233 uint32_t encryption_info = HAL_RX_MPDU_ENCRYPTION_INFO_VALID(mpdu_info); 234 235 return encryption_info; 236 } 237 238 /* 239 * hal_rx_print_pn_6290: Prints the PN of rx packet. 240 * @buf: rx_tlv_hdr of the received packet 241 * 242 * Return: void 243 */ 244 static void hal_rx_print_pn_6290(uint8_t *buf) 245 { 246 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 247 struct rx_mpdu_start *mpdu_start = 248 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 249 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 250 251 uint32_t pn_31_0 = HAL_RX_MPDU_PN_31_0_GET(mpdu_info); 252 uint32_t pn_63_32 = HAL_RX_MPDU_PN_63_32_GET(mpdu_info); 253 uint32_t pn_95_64 = HAL_RX_MPDU_PN_95_64_GET(mpdu_info); 254 uint32_t pn_127_96 = HAL_RX_MPDU_PN_127_96_GET(mpdu_info); 255 256 hal_debug("PN number pn_127_96 0x%x pn_95_64 0x%x pn_63_32 0x%x pn_31_0 0x%x ", 257 pn_127_96, pn_95_64, pn_63_32, pn_31_0); 258 } 259 260 /** 261 * hal_rx_msdu_end_first_msdu_get_6290: API to get first msdu status 262 * from rx_msdu_end TLV 263 * 264 * @buf: pointer to the start of RX PKT TLV headers 265 * Return: first_msdu 266 */ 267 static uint8_t 268 hal_rx_msdu_end_first_msdu_get_6290(uint8_t *buf) 269 { 270 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 271 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 272 uint8_t first_msdu; 273 274 first_msdu = HAL_RX_MSDU_END_FIRST_MSDU_GET(msdu_end); 275 276 return first_msdu; 277 } 278 279 /** 280 * hal_rx_msdu_end_da_is_valid_get_6290: API to check if da is valid 281 * from rx_msdu_end TLV 282 * 283 * @ buf: pointer to the start of RX PKT TLV headers 284 * Return: da_is_valid 285 */ 286 static uint8_t hal_rx_msdu_end_da_is_valid_get_6290(uint8_t *buf) 287 { 288 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 289 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 290 uint8_t da_is_valid; 291 292 da_is_valid = HAL_RX_MSDU_END_DA_IS_VALID_GET(msdu_end); 293 294 return da_is_valid; 295 } 296 297 /** 298 * hal_rx_msdu_end_last_msdu_get_6290: API to get last msdu status 299 * from rx_msdu_end TLV 300 * 301 * @ buf: pointer to the start of RX PKT TLV headers 302 * Return: last_msdu 303 */ 304 static uint8_t hal_rx_msdu_end_last_msdu_get_6290(uint8_t *buf) 305 { 306 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 307 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 308 uint8_t last_msdu; 309 310 last_msdu = HAL_RX_MSDU_END_LAST_MSDU_GET(msdu_end); 311 312 return last_msdu; 313 } 314 315 /* 316 * hal_rx_get_mpdu_mac_ad4_valid_6290(): Retrieves if mpdu 4th addr is valid 317 * 318 * @nbuf: Network buffer 319 * Returns: value of mpdu 4th address valid field 320 */ 321 static bool hal_rx_get_mpdu_mac_ad4_valid_6290(uint8_t *buf) 322 { 323 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 324 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 325 bool ad4_valid = 0; 326 327 ad4_valid = HAL_RX_MPDU_GET_MAC_AD4_VALID(rx_mpdu_info); 328 329 return ad4_valid; 330 } 331 332 /** 333 * hal_rx_mpdu_start_sw_peer_id_get_6290: Retrieve sw peer_id 334 * @buf: network buffer 335 * 336 * Return: sw peer_id: 337 */ 338 static uint32_t hal_rx_mpdu_start_sw_peer_id_get_6290(uint8_t *buf) 339 { 340 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 341 struct rx_mpdu_start *mpdu_start = 342 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 343 344 return HAL_RX_MPDU_INFO_SW_PEER_ID_GET( 345 &mpdu_start->rx_mpdu_info_details); 346 } 347 348 /* 349 * hal_rx_mpdu_get_to_ds_6290(): API to get the tods info 350 * from rx_mpdu_start 351 * 352 * @buf: pointer to the start of RX PKT TLV header 353 * Return: uint32_t(to_ds) 354 */ 355 356 static uint32_t hal_rx_mpdu_get_to_ds_6290(uint8_t *buf) 357 { 358 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 359 struct rx_mpdu_start *mpdu_start = 360 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 361 362 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 363 364 return HAL_RX_MPDU_GET_TODS(mpdu_info); 365 } 366 367 /* 368 * hal_rx_mpdu_get_fr_ds_6290(): API to get the from ds info 369 * from rx_mpdu_start 370 * 371 * @buf: pointer to the start of RX PKT TLV header 372 * Return: uint32_t(fr_ds) 373 */ 374 static uint32_t hal_rx_mpdu_get_fr_ds_6290(uint8_t *buf) 375 { 376 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 377 struct rx_mpdu_start *mpdu_start = 378 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 379 380 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 381 382 return HAL_RX_MPDU_GET_FROMDS(mpdu_info); 383 } 384 385 /* 386 * hal_rx_get_mpdu_frame_control_valid_6290(): Retrieves mpdu frame 387 * control valid 388 * 389 * @nbuf: Network buffer 390 * Returns: value of frame control valid field 391 */ 392 static uint8_t hal_rx_get_mpdu_frame_control_valid_6290(uint8_t *buf) 393 { 394 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 395 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 396 397 return HAL_RX_MPDU_GET_FRAME_CONTROL_VALID(rx_mpdu_info); 398 } 399 400 /* 401 * hal_rx_mpdu_get_addr1_6290(): API to check get address1 of the mpdu 402 * 403 * @buf: pointer to the start of RX PKT TLV headera 404 * @mac_addr: pointer to mac address 405 * Return: success/failure 406 */ 407 static QDF_STATUS hal_rx_mpdu_get_addr1_6290(uint8_t *buf, uint8_t *mac_addr) 408 { 409 struct __attribute__((__packed__)) hal_addr1 { 410 uint32_t ad1_31_0; 411 uint16_t ad1_47_32; 412 }; 413 414 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 415 struct rx_mpdu_start *mpdu_start = 416 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 417 418 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 419 struct hal_addr1 *addr = (struct hal_addr1 *)mac_addr; 420 uint32_t mac_addr_ad1_valid; 421 422 mac_addr_ad1_valid = HAL_RX_MPDU_MAC_ADDR_AD1_VALID_GET(mpdu_info); 423 424 if (mac_addr_ad1_valid) { 425 addr->ad1_31_0 = HAL_RX_MPDU_AD1_31_0_GET(mpdu_info); 426 addr->ad1_47_32 = HAL_RX_MPDU_AD1_47_32_GET(mpdu_info); 427 return QDF_STATUS_SUCCESS; 428 } 429 430 return QDF_STATUS_E_FAILURE; 431 } 432 433 /* 434 * hal_rx_mpdu_get_addr2_6290(): API to check get address2 of the mpdu 435 * in the packet 436 * 437 * @buf: pointer to the start of RX PKT TLV header 438 * @mac_addr: pointer to mac address 439 * Return: success/failure 440 */ 441 static QDF_STATUS hal_rx_mpdu_get_addr2_6290(uint8_t *buf, 442 uint8_t *mac_addr) 443 { 444 struct __attribute__((__packed__)) hal_addr2 { 445 uint16_t ad2_15_0; 446 uint32_t ad2_47_16; 447 }; 448 449 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 450 struct rx_mpdu_start *mpdu_start = 451 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 452 453 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 454 struct hal_addr2 *addr = (struct hal_addr2 *)mac_addr; 455 uint32_t mac_addr_ad2_valid; 456 457 mac_addr_ad2_valid = HAL_RX_MPDU_MAC_ADDR_AD2_VALID_GET(mpdu_info); 458 459 if (mac_addr_ad2_valid) { 460 addr->ad2_15_0 = HAL_RX_MPDU_AD2_15_0_GET(mpdu_info); 461 addr->ad2_47_16 = HAL_RX_MPDU_AD2_47_16_GET(mpdu_info); 462 return QDF_STATUS_SUCCESS; 463 } 464 465 return QDF_STATUS_E_FAILURE; 466 } 467 468 /* 469 * hal_rx_mpdu_get_addr3_6290(): API to get address3 of the mpdu 470 * in the packet 471 * 472 * @buf: pointer to the start of RX PKT TLV header 473 * @mac_addr: pointer to mac address 474 * Return: success/failure 475 */ 476 static QDF_STATUS hal_rx_mpdu_get_addr3_6290(uint8_t *buf, uint8_t *mac_addr) 477 { 478 struct __attribute__((__packed__)) hal_addr3 { 479 uint32_t ad3_31_0; 480 uint16_t ad3_47_32; 481 }; 482 483 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 484 struct rx_mpdu_start *mpdu_start = 485 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 486 487 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 488 struct hal_addr3 *addr = (struct hal_addr3 *)mac_addr; 489 uint32_t mac_addr_ad3_valid; 490 491 mac_addr_ad3_valid = HAL_RX_MPDU_MAC_ADDR_AD3_VALID_GET(mpdu_info); 492 493 if (mac_addr_ad3_valid) { 494 addr->ad3_31_0 = HAL_RX_MPDU_AD3_31_0_GET(mpdu_info); 495 addr->ad3_47_32 = HAL_RX_MPDU_AD3_47_32_GET(mpdu_info); 496 return QDF_STATUS_SUCCESS; 497 } 498 499 return QDF_STATUS_E_FAILURE; 500 } 501 502 /* 503 * hal_rx_mpdu_get_addr4_6290(): API to get address4 of the mpdu 504 * in the packet 505 * 506 * @buf: pointer to the start of RX PKT TLV header 507 * @mac_addr: pointer to mac address 508 * Return: success/failure 509 */ 510 static QDF_STATUS hal_rx_mpdu_get_addr4_6290(uint8_t *buf, uint8_t *mac_addr) 511 { 512 struct __attribute__((__packed__)) hal_addr4 { 513 uint32_t ad4_31_0; 514 uint16_t ad4_47_32; 515 }; 516 517 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 518 struct rx_mpdu_start *mpdu_start = 519 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 520 521 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 522 struct hal_addr4 *addr = (struct hal_addr4 *)mac_addr; 523 uint32_t mac_addr_ad4_valid; 524 525 mac_addr_ad4_valid = HAL_RX_MPDU_MAC_ADDR_AD4_VALID_GET(mpdu_info); 526 527 if (mac_addr_ad4_valid) { 528 addr->ad4_31_0 = HAL_RX_MPDU_AD4_31_0_GET(mpdu_info); 529 addr->ad4_47_32 = HAL_RX_MPDU_AD4_47_32_GET(mpdu_info); 530 return QDF_STATUS_SUCCESS; 531 } 532 533 return QDF_STATUS_E_FAILURE; 534 } 535 536 /* 537 * hal_rx_get_mpdu_sequence_control_valid_6290(): Get mpdu 538 * sequence control valid 539 * 540 * @nbuf: Network buffer 541 * Returns: value of sequence control valid field 542 */ 543 static uint8_t hal_rx_get_mpdu_sequence_control_valid_6290(uint8_t *buf) 544 { 545 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 546 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 547 548 return HAL_RX_MPDU_GET_SEQUENCE_CONTROL_VALID(rx_mpdu_info); 549 } 550 551 /** 552 * hal_rx_is_unicast_6290: check packet is unicast frame or not. 553 * 554 * @ buf: pointer to rx pkt TLV. 555 * 556 * Return: true on unicast. 557 */ 558 static bool hal_rx_is_unicast_6290(uint8_t *buf) 559 { 560 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 561 struct rx_mpdu_start *mpdu_start = 562 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 563 uint32_t grp_id; 564 uint8_t *rx_mpdu_info = (uint8_t *)&mpdu_start->rx_mpdu_info_details; 565 566 grp_id = (_HAL_MS((*_OFFSET_TO_WORD_PTR((rx_mpdu_info), 567 RX_MPDU_INFO_0_SW_FRAME_GROUP_ID_OFFSET)), 568 RX_MPDU_INFO_0_SW_FRAME_GROUP_ID_MASK, 569 RX_MPDU_INFO_0_SW_FRAME_GROUP_ID_LSB)); 570 571 return (HAL_MPDU_SW_FRAME_GROUP_UNICAST_DATA == grp_id) ? true : false; 572 } 573 574 /** 575 * hal_rx_tid_get_6290: get tid based on qos control valid. 576 * @hal_soc_hdl: hal soc handle 577 * @ buf: pointer to rx pkt TLV. 578 * 579 * Return: tid 580 */ 581 static uint32_t hal_rx_tid_get_6290(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 582 { 583 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 584 struct rx_mpdu_start *mpdu_start = 585 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 586 uint8_t *rx_mpdu_info = (uint8_t *)&mpdu_start->rx_mpdu_info_details; 587 uint8_t qos_control_valid = 588 (_HAL_MS((*_OFFSET_TO_WORD_PTR((rx_mpdu_info), 589 RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_OFFSET)), 590 RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_MASK, 591 RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_LSB)); 592 593 if (qos_control_valid) 594 return hal_rx_mpdu_start_tid_get_6290(buf); 595 596 return HAL_RX_NON_QOS_TID; 597 } 598 599 /** 600 * hal_rx_hw_desc_get_ppduid_get_6290(): retrieve ppdu id 601 * @rx_tlv_hdr: start address of rx_pkt_tlvs 602 * @rxdma_dst_ring_desc: Rx HW descriptor 603 * 604 * Return: ppdu id 605 */ 606 static uint32_t hal_rx_hw_desc_get_ppduid_get_6290(void *rx_tlv_hdr, 607 void *rxdma_dst_ring_desc) 608 { 609 struct rx_mpdu_info *rx_mpdu_info; 610 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)rx_tlv_hdr; 611 612 rx_mpdu_info = 613 &rx_desc->mpdu_start_tlv.rx_mpdu_start.rx_mpdu_info_details; 614 615 return HAL_RX_GET(rx_mpdu_info, RX_MPDU_INFO_0, PHY_PPDU_ID); 616 } 617 618 /** 619 * hal_reo_status_get_header_6290 - Process reo desc info 620 * @ring_desc: REO status ring descriptor 621 * @b - tlv type info 622 * @h1 - Pointer to hal_reo_status_header where info to be stored 623 * 624 * Return - none. 625 * 626 */ 627 static void hal_reo_status_get_header_6290(hal_ring_desc_t ring_desc, int b, 628 void *h1) 629 { 630 uint32_t *d = (uint32_t *)ring_desc; 631 uint32_t val1 = 0; 632 struct hal_reo_status_header *h = 633 (struct hal_reo_status_header *)h1; 634 635 /* Offsets of descriptor fields defined in HW headers start 636 * from the field after TLV header 637 */ 638 d += HAL_GET_NUM_DWORDS(sizeof(struct tlv_32_hdr)); 639 640 switch (b) { 641 case HAL_REO_QUEUE_STATS_STATUS_TLV: 642 val1 = d[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_0, 643 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 644 break; 645 case HAL_REO_FLUSH_QUEUE_STATUS_TLV: 646 val1 = d[HAL_OFFSET_DW(REO_FLUSH_QUEUE_STATUS_0, 647 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 648 break; 649 case HAL_REO_FLUSH_CACHE_STATUS_TLV: 650 val1 = d[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_0, 651 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 652 break; 653 case HAL_REO_UNBLK_CACHE_STATUS_TLV: 654 val1 = d[HAL_OFFSET_DW(REO_UNBLOCK_CACHE_STATUS_0, 655 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 656 break; 657 case HAL_REO_TIMOUT_LIST_STATUS_TLV: 658 val1 = d[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_0, 659 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 660 break; 661 case HAL_REO_DESC_THRES_STATUS_TLV: 662 val1 = 663 d[HAL_OFFSET_DW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0, 664 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 665 break; 666 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: 667 val1 = d[HAL_OFFSET_DW(REO_UPDATE_RX_REO_QUEUE_STATUS_0, 668 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 669 break; 670 default: 671 qdf_nofl_err("ERROR: Unknown tlv\n"); 672 break; 673 } 674 h->cmd_num = 675 HAL_GET_FIELD( 676 UNIFORM_REO_STATUS_HEADER_0, REO_STATUS_NUMBER, 677 val1); 678 h->exec_time = 679 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_0, 680 CMD_EXECUTION_TIME, val1); 681 h->status = 682 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_0, 683 REO_CMD_EXECUTION_STATUS, val1); 684 switch (b) { 685 case HAL_REO_QUEUE_STATS_STATUS_TLV: 686 val1 = d[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_1, 687 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 688 break; 689 case HAL_REO_FLUSH_QUEUE_STATUS_TLV: 690 val1 = d[HAL_OFFSET_DW(REO_FLUSH_QUEUE_STATUS_1, 691 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 692 break; 693 case HAL_REO_FLUSH_CACHE_STATUS_TLV: 694 val1 = d[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_1, 695 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 696 break; 697 case HAL_REO_UNBLK_CACHE_STATUS_TLV: 698 val1 = d[HAL_OFFSET_DW(REO_UNBLOCK_CACHE_STATUS_1, 699 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 700 break; 701 case HAL_REO_TIMOUT_LIST_STATUS_TLV: 702 val1 = d[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_1, 703 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 704 break; 705 case HAL_REO_DESC_THRES_STATUS_TLV: 706 val1 = 707 d[HAL_OFFSET_DW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_1, 708 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 709 break; 710 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: 711 val1 = d[HAL_OFFSET_DW(REO_UPDATE_RX_REO_QUEUE_STATUS_1, 712 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 713 break; 714 default: 715 qdf_nofl_err("ERROR: Unknown tlv\n"); 716 break; 717 } 718 h->tstamp = 719 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_1, TIMESTAMP, val1); 720 } 721 722 /** 723 * hal_rx_mpdu_start_mpdu_qos_control_valid_get_6290(): 724 * Retrieve qos control valid bit from the tlv. 725 * @buf: pointer to rx pkt TLV. 726 * 727 * Return: qos control value. 728 */ 729 static inline uint32_t 730 hal_rx_mpdu_start_mpdu_qos_control_valid_get_6290(uint8_t *buf) 731 { 732 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 733 struct rx_mpdu_start *mpdu_start = 734 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 735 736 return HAL_RX_MPDU_INFO_QOS_CONTROL_VALID_GET( 737 &mpdu_start->rx_mpdu_info_details); 738 } 739 740 /** 741 * hal_rx_msdu_end_sa_sw_peer_id_get_6290(): API to get the 742 * sa_sw_peer_id from rx_msdu_end TLV 743 * @buf: pointer to the start of RX PKT TLV headers 744 * 745 * Return: sa_sw_peer_id index 746 */ 747 static inline uint32_t 748 hal_rx_msdu_end_sa_sw_peer_id_get_6290(uint8_t *buf) 749 { 750 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 751 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 752 753 return HAL_RX_MSDU_END_SA_SW_PEER_ID_GET(msdu_end); 754 } 755 756 /** 757 * hal_tx_desc_set_mesh_en_6290 - Set mesh_enable flag in Tx descriptor 758 * @desc: Handle to Tx Descriptor 759 * @en: For raw WiFi frames, this indicates transmission to a mesh STA, 760 * enabling the interpretation of the 'Mesh Control Present' bit 761 * (bit 8) of QoS Control (otherwise this bit is ignored), 762 * For native WiFi frames, this indicates that a 'Mesh Control' field 763 * is present between the header and the LLC. 764 * 765 * Return: void 766 */ 767 static inline 768 void hal_tx_desc_set_mesh_en_6290(void *desc, uint8_t en) 769 { 770 HAL_SET_FLD(desc, TCL_DATA_CMD_4, MESH_ENABLE) |= 771 HAL_TX_SM(TCL_DATA_CMD_4, MESH_ENABLE, en); 772 } 773 774 static 775 void *hal_rx_msdu0_buffer_addr_lsb_6290(void *link_desc_va) 776 { 777 return (void *)HAL_RX_MSDU0_BUFFER_ADDR_LSB(link_desc_va); 778 } 779 780 static 781 void *hal_rx_msdu_desc_info_ptr_get_6290(void *msdu0) 782 { 783 return (void *)HAL_RX_MSDU_DESC_INFO_PTR_GET(msdu0); 784 } 785 786 static 787 void *hal_ent_mpdu_desc_info_6290(void *ent_ring_desc) 788 { 789 return (void *)HAL_ENT_MPDU_DESC_INFO(ent_ring_desc); 790 } 791 792 static 793 void *hal_dst_mpdu_desc_info_6290(void *dst_ring_desc) 794 { 795 return (void *)HAL_DST_MPDU_DESC_INFO(dst_ring_desc); 796 } 797 798 static 799 uint8_t hal_rx_get_fc_valid_6290(uint8_t *buf) 800 { 801 return HAL_RX_GET_FC_VALID(buf); 802 } 803 804 static uint8_t hal_rx_get_to_ds_flag_6290(uint8_t *buf) 805 { 806 return HAL_RX_GET_TO_DS_FLAG(buf); 807 } 808 809 static uint8_t hal_rx_get_mac_addr2_valid_6290(uint8_t *buf) 810 { 811 return HAL_RX_GET_MAC_ADDR2_VALID(buf); 812 } 813 814 static uint8_t hal_rx_get_filter_category_6290(uint8_t *buf) 815 { 816 return HAL_RX_GET_FILTER_CATEGORY(buf); 817 } 818 819 static uint32_t 820 hal_rx_get_ppdu_id_6290(uint8_t *buf) 821 { 822 return HAL_RX_GET_PPDU_ID(buf); 823 } 824 825 /** 826 * hal_reo_config_6290(): Set reo config parameters 827 * @soc: hal soc handle 828 * @reg_val: value to be set 829 * @reo_params: reo parameters 830 * 831 * Return: void 832 */ 833 static 834 void hal_reo_config_6290(struct hal_soc *soc, 835 uint32_t reg_val, 836 struct hal_reo_params *reo_params) 837 { 838 HAL_REO_R0_CONFIG(soc, reg_val, reo_params); 839 } 840 841 /** 842 * hal_rx_msdu_desc_info_get_ptr_6290() - Get msdu desc info ptr 843 * @msdu_details_ptr - Pointer to msdu_details_ptr 844 * 845 * Return - Pointer to rx_msdu_desc_info structure. 846 * 847 */ 848 static void *hal_rx_msdu_desc_info_get_ptr_6290(void *msdu_details_ptr) 849 { 850 return HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr); 851 } 852 853 /** 854 * hal_rx_link_desc_msdu0_ptr_6290 - Get pointer to rx_msdu details 855 * @link_desc - Pointer to link desc 856 * 857 * Return - Pointer to rx_msdu_details structure 858 * 859 */ 860 static void *hal_rx_link_desc_msdu0_ptr_6290(void *link_desc) 861 { 862 return HAL_RX_LINK_DESC_MSDU0_PTR(link_desc); 863 } 864 865 /** 866 * hal_rx_msdu_flow_idx_get_6290: API to get flow index 867 * from rx_msdu_end TLV 868 * @buf: pointer to the start of RX PKT TLV headers 869 * 870 * Return: flow index value from MSDU END TLV 871 */ 872 static inline uint32_t hal_rx_msdu_flow_idx_get_6290(uint8_t *buf) 873 { 874 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 875 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 876 877 return HAL_RX_MSDU_END_FLOW_IDX_GET(msdu_end); 878 } 879 880 /** 881 * hal_rx_msdu_flow_idx_invalid_6290: API to get flow index invalid 882 * from rx_msdu_end TLV 883 * @buf: pointer to the start of RX PKT TLV headers 884 * 885 * Return: flow index invalid value from MSDU END TLV 886 */ 887 static bool hal_rx_msdu_flow_idx_invalid_6290(uint8_t *buf) 888 { 889 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 890 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 891 892 return HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(msdu_end); 893 } 894 895 /** 896 * hal_rx_msdu_flow_idx_timeout_6290: API to get flow index timeout 897 * from rx_msdu_end TLV 898 * @buf: pointer to the start of RX PKT TLV headers 899 * 900 * Return: flow index timeout value from MSDU END TLV 901 */ 902 static bool hal_rx_msdu_flow_idx_timeout_6290(uint8_t *buf) 903 { 904 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 905 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 906 907 return HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(msdu_end); 908 } 909 910 /** 911 * hal_rx_msdu_fse_metadata_get_6290: API to get FSE metadata 912 * from rx_msdu_end TLV 913 * @buf: pointer to the start of RX PKT TLV headers 914 * 915 * Return: fse metadata value from MSDU END TLV 916 */ 917 static uint32_t hal_rx_msdu_fse_metadata_get_6290(uint8_t *buf) 918 { 919 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 920 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 921 922 return HAL_RX_MSDU_END_FSE_METADATA_GET(msdu_end); 923 } 924 925 /** 926 * hal_rx_msdu_cce_metadata_get_6290: API to get CCE metadata 927 * from rx_msdu_end TLV 928 * @buf: pointer to the start of RX PKT TLV headers 929 * 930 * Return: cce_metadata 931 */ 932 static uint16_t 933 hal_rx_msdu_cce_metadata_get_6290(uint8_t *buf) 934 { 935 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 936 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 937 938 return HAL_RX_MSDU_END_CCE_METADATA_GET(msdu_end); 939 } 940 941 /** 942 * hal_rx_msdu_get_flow_params_6290: API to get flow index, flow index invalid 943 * and flow index timeout from rx_msdu_end TLV 944 * @buf: pointer to the start of RX PKT TLV headers 945 * @flow_invalid: pointer to return value of flow_idx_valid 946 * @flow_timeout: pointer to return value of flow_idx_timeout 947 * @flow_index: pointer to return value of flow_idx 948 * 949 * Return: none 950 */ 951 static inline void 952 hal_rx_msdu_get_flow_params_6290(uint8_t *buf, 953 bool *flow_invalid, 954 bool *flow_timeout, 955 uint32_t *flow_index) 956 { 957 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 958 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 959 960 *flow_invalid = HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(msdu_end); 961 *flow_timeout = HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(msdu_end); 962 *flow_index = HAL_RX_MSDU_END_FLOW_IDX_GET(msdu_end); 963 } 964 965 /** 966 * hal_rx_tlv_get_tcp_chksum_6290() - API to get tcp checksum 967 * @buf: rx_tlv_hdr 968 * 969 * Return: tcp checksum 970 */ 971 static uint16_t 972 hal_rx_tlv_get_tcp_chksum_6290(uint8_t *buf) 973 { 974 return HAL_RX_TLV_GET_TCP_CHKSUM(buf); 975 } 976 977 /** 978 * hal_rx_get_rx_sequence_6290(): Function to retrieve rx sequence number 979 * @nbuf: Network buffer 980 * 981 * Return: rx sequence number 982 */ 983 static 984 uint16_t hal_rx_get_rx_sequence_6290(uint8_t *buf) 985 { 986 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 987 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 988 989 return HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info); 990 } 991 992 /** 993 * hal_get_window_address_6290(): Function to get hp/tp address 994 * @hal_soc: Pointer to hal_soc 995 * @addr: address offset of register 996 * 997 * Return: modified address offset of register 998 */ 999 static inline qdf_iomem_t hal_get_window_address_6290(struct hal_soc *hal_soc, 1000 qdf_iomem_t addr) 1001 { 1002 return addr; 1003 } 1004 1005 static 1006 void hal_compute_reo_remap_ix2_ix3_6290(uint32_t *ring, uint32_t num_rings, 1007 uint32_t *remap1, uint32_t *remap2) 1008 { 1009 switch (num_rings) { 1010 case 3: 1011 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 1012 HAL_REO_REMAP_IX2(ring[1], 17) | 1013 HAL_REO_REMAP_IX2(ring[2], 18) | 1014 HAL_REO_REMAP_IX2(ring[0], 19) | 1015 HAL_REO_REMAP_IX2(ring[1], 20) | 1016 HAL_REO_REMAP_IX2(ring[2], 21) | 1017 HAL_REO_REMAP_IX2(ring[0], 22) | 1018 HAL_REO_REMAP_IX2(ring[1], 23); 1019 1020 *remap2 = HAL_REO_REMAP_IX3(ring[2], 24) | 1021 HAL_REO_REMAP_IX3(ring[0], 25) | 1022 HAL_REO_REMAP_IX3(ring[1], 26) | 1023 HAL_REO_REMAP_IX3(ring[2], 27) | 1024 HAL_REO_REMAP_IX3(ring[0], 28) | 1025 HAL_REO_REMAP_IX3(ring[1], 29) | 1026 HAL_REO_REMAP_IX3(ring[2], 30) | 1027 HAL_REO_REMAP_IX3(ring[0], 31); 1028 break; 1029 case 4: 1030 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 1031 HAL_REO_REMAP_IX2(ring[1], 17) | 1032 HAL_REO_REMAP_IX2(ring[2], 18) | 1033 HAL_REO_REMAP_IX2(ring[3], 19) | 1034 HAL_REO_REMAP_IX2(ring[0], 20) | 1035 HAL_REO_REMAP_IX2(ring[1], 21) | 1036 HAL_REO_REMAP_IX2(ring[2], 22) | 1037 HAL_REO_REMAP_IX2(ring[3], 23); 1038 1039 *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) | 1040 HAL_REO_REMAP_IX3(ring[1], 25) | 1041 HAL_REO_REMAP_IX3(ring[2], 26) | 1042 HAL_REO_REMAP_IX3(ring[3], 27) | 1043 HAL_REO_REMAP_IX3(ring[0], 28) | 1044 HAL_REO_REMAP_IX3(ring[1], 29) | 1045 HAL_REO_REMAP_IX3(ring[2], 30) | 1046 HAL_REO_REMAP_IX3(ring[3], 31); 1047 break; 1048 } 1049 } 1050 1051 #ifdef WLAN_FEATURE_MARK_FIRST_WAKEUP_PACKET 1052 /** 1053 * hal_get_first_wow_wakeup_packet_6290(): Function to get if the buffer 1054 * is the first one that wakes up host from WoW. 1055 * 1056 * @buf: network buffer 1057 * 1058 * Dummy function for QCA6290 1059 * 1060 * Returns: 1 to indicate it is first packet received that wakes up host from 1061 * WoW. Otherwise 0 1062 */ 1063 static inline uint8_t hal_get_first_wow_wakeup_packet_6290(uint8_t *buf) 1064 { 1065 return 0; 1066 } 1067 #endif 1068 1069 static void hal_hw_txrx_ops_attach_6290(struct hal_soc *hal_soc) 1070 { 1071 /* init and setup */ 1072 hal_soc->ops->hal_srng_dst_hw_init = hal_srng_dst_hw_init_generic; 1073 hal_soc->ops->hal_srng_src_hw_init = hal_srng_src_hw_init_generic; 1074 hal_soc->ops->hal_get_hw_hptp = hal_get_hw_hptp_generic; 1075 hal_soc->ops->hal_reo_setup = hal_reo_setup_generic_li; 1076 hal_soc->ops->hal_get_window_address = hal_get_window_address_6290; 1077 1078 /* tx */ 1079 hal_soc->ops->hal_tx_desc_set_dscp_tid_table_id = 1080 hal_tx_desc_set_dscp_tid_table_id_6290; 1081 hal_soc->ops->hal_tx_set_dscp_tid_map = hal_tx_set_dscp_tid_map_6290; 1082 hal_soc->ops->hal_tx_update_dscp_tid = hal_tx_update_dscp_tid_6290; 1083 hal_soc->ops->hal_tx_desc_set_lmac_id = hal_tx_desc_set_lmac_id_6290; 1084 hal_soc->ops->hal_tx_desc_set_buf_addr = 1085 hal_tx_desc_set_buf_addr_generic_li; 1086 hal_soc->ops->hal_tx_desc_set_search_type = 1087 hal_tx_desc_set_search_type_generic_li; 1088 hal_soc->ops->hal_tx_desc_set_search_index = 1089 hal_tx_desc_set_search_index_generic_li; 1090 hal_soc->ops->hal_tx_desc_set_cache_set_num = 1091 hal_tx_desc_set_cache_set_num_generic_li; 1092 hal_soc->ops->hal_tx_comp_get_status = 1093 hal_tx_comp_get_status_generic_li; 1094 hal_soc->ops->hal_tx_comp_get_release_reason = 1095 hal_tx_comp_get_release_reason_generic_li; 1096 hal_soc->ops->hal_get_wbm_internal_error = 1097 hal_get_wbm_internal_error_generic_li; 1098 hal_soc->ops->hal_tx_desc_set_mesh_en = hal_tx_desc_set_mesh_en_6290; 1099 hal_soc->ops->hal_tx_init_cmd_credit_ring = 1100 hal_tx_init_cmd_credit_ring_6290; 1101 1102 /* rx */ 1103 hal_soc->ops->hal_rx_msdu_start_nss_get = 1104 hal_rx_msdu_start_nss_get_6290; 1105 hal_soc->ops->hal_rx_mon_hw_desc_get_mpdu_status = 1106 hal_rx_mon_hw_desc_get_mpdu_status_6290; 1107 hal_soc->ops->hal_rx_get_tlv = hal_rx_get_tlv_6290; 1108 hal_soc->ops->hal_rx_proc_phyrx_other_receive_info_tlv = 1109 hal_rx_proc_phyrx_other_receive_info_tlv_6290; 1110 hal_soc->ops->hal_rx_dump_msdu_start_tlv = 1111 hal_rx_dump_msdu_start_tlv_6290; 1112 hal_soc->ops->hal_rx_dump_msdu_end_tlv = hal_rx_dump_msdu_end_tlv_6290; 1113 hal_soc->ops->hal_get_link_desc_size = hal_get_link_desc_size_6290; 1114 hal_soc->ops->hal_rx_mpdu_start_tid_get = 1115 hal_rx_mpdu_start_tid_get_6290; 1116 hal_soc->ops->hal_rx_msdu_start_reception_type_get = 1117 hal_rx_msdu_start_reception_type_get_6290; 1118 hal_soc->ops->hal_rx_msdu_end_da_idx_get = 1119 hal_rx_msdu_end_da_idx_get_6290; 1120 hal_soc->ops->hal_rx_msdu_desc_info_get_ptr = 1121 hal_rx_msdu_desc_info_get_ptr_6290; 1122 hal_soc->ops->hal_rx_link_desc_msdu0_ptr = 1123 hal_rx_link_desc_msdu0_ptr_6290; 1124 hal_soc->ops->hal_reo_status_get_header = 1125 hal_reo_status_get_header_6290; 1126 hal_soc->ops->hal_rx_status_get_tlv_info = 1127 hal_rx_status_get_tlv_info_generic_li; 1128 hal_soc->ops->hal_rx_wbm_err_info_get = 1129 hal_rx_wbm_err_info_get_generic_li; 1130 hal_soc->ops->hal_rx_dump_mpdu_start_tlv = 1131 hal_rx_dump_mpdu_start_tlv_generic_li; 1132 1133 hal_soc->ops->hal_tx_set_pcp_tid_map = 1134 hal_tx_set_pcp_tid_map_generic_li; 1135 hal_soc->ops->hal_tx_update_pcp_tid_map = 1136 hal_tx_update_pcp_tid_generic_li; 1137 hal_soc->ops->hal_tx_set_tidmap_prty = 1138 hal_tx_update_tidmap_prty_generic_li; 1139 hal_soc->ops->hal_rx_get_rx_fragment_number = 1140 hal_rx_get_rx_fragment_number_6290; 1141 hal_soc->ops->hal_rx_msdu_end_da_is_mcbc_get = 1142 hal_rx_msdu_end_da_is_mcbc_get_6290; 1143 hal_soc->ops->hal_rx_msdu_end_sa_is_valid_get = 1144 hal_rx_msdu_end_sa_is_valid_get_6290; 1145 hal_soc->ops->hal_rx_msdu_end_sa_idx_get = 1146 hal_rx_msdu_end_sa_idx_get_6290; 1147 hal_soc->ops->hal_rx_desc_is_first_msdu = 1148 hal_rx_desc_is_first_msdu_6290; 1149 hal_soc->ops->hal_rx_msdu_end_l3_hdr_padding_get = 1150 hal_rx_msdu_end_l3_hdr_padding_get_6290; 1151 hal_soc->ops->hal_rx_encryption_info_valid = 1152 hal_rx_encryption_info_valid_6290; 1153 hal_soc->ops->hal_rx_print_pn = hal_rx_print_pn_6290; 1154 hal_soc->ops->hal_rx_msdu_end_first_msdu_get = 1155 hal_rx_msdu_end_first_msdu_get_6290; 1156 hal_soc->ops->hal_rx_msdu_end_da_is_valid_get = 1157 hal_rx_msdu_end_da_is_valid_get_6290; 1158 hal_soc->ops->hal_rx_msdu_end_last_msdu_get = 1159 hal_rx_msdu_end_last_msdu_get_6290; 1160 hal_soc->ops->hal_rx_get_mpdu_mac_ad4_valid = 1161 hal_rx_get_mpdu_mac_ad4_valid_6290; 1162 hal_soc->ops->hal_rx_mpdu_start_sw_peer_id_get = 1163 hal_rx_mpdu_start_sw_peer_id_get_6290; 1164 hal_soc->ops->hal_rx_mpdu_peer_meta_data_get = 1165 hal_rx_mpdu_peer_meta_data_get_li; 1166 hal_soc->ops->hal_rx_mpdu_get_to_ds = hal_rx_mpdu_get_to_ds_6290; 1167 hal_soc->ops->hal_rx_mpdu_get_fr_ds = hal_rx_mpdu_get_fr_ds_6290; 1168 hal_soc->ops->hal_rx_get_mpdu_frame_control_valid = 1169 hal_rx_get_mpdu_frame_control_valid_6290; 1170 hal_soc->ops->hal_rx_mpdu_get_addr1 = hal_rx_mpdu_get_addr1_6290; 1171 hal_soc->ops->hal_rx_mpdu_get_addr2 = hal_rx_mpdu_get_addr2_6290; 1172 hal_soc->ops->hal_rx_mpdu_get_addr3 = hal_rx_mpdu_get_addr3_6290; 1173 hal_soc->ops->hal_rx_mpdu_get_addr4 = hal_rx_mpdu_get_addr4_6290; 1174 hal_soc->ops->hal_rx_get_mpdu_sequence_control_valid = 1175 hal_rx_get_mpdu_sequence_control_valid_6290; 1176 hal_soc->ops->hal_rx_is_unicast = hal_rx_is_unicast_6290; 1177 hal_soc->ops->hal_rx_tid_get = hal_rx_tid_get_6290; 1178 hal_soc->ops->hal_rx_hw_desc_get_ppduid_get = 1179 hal_rx_hw_desc_get_ppduid_get_6290; 1180 hal_soc->ops->hal_rx_mpdu_start_mpdu_qos_control_valid_get = 1181 hal_rx_mpdu_start_mpdu_qos_control_valid_get_6290; 1182 hal_soc->ops->hal_rx_msdu_end_sa_sw_peer_id_get = 1183 hal_rx_msdu_end_sa_sw_peer_id_get_6290; 1184 hal_soc->ops->hal_rx_msdu0_buffer_addr_lsb = 1185 hal_rx_msdu0_buffer_addr_lsb_6290; 1186 hal_soc->ops->hal_rx_msdu_desc_info_ptr_get = 1187 hal_rx_msdu_desc_info_ptr_get_6290; 1188 hal_soc->ops->hal_ent_mpdu_desc_info = hal_ent_mpdu_desc_info_6290; 1189 hal_soc->ops->hal_dst_mpdu_desc_info = hal_dst_mpdu_desc_info_6290; 1190 hal_soc->ops->hal_rx_get_fc_valid = hal_rx_get_fc_valid_6290; 1191 hal_soc->ops->hal_rx_get_to_ds_flag = hal_rx_get_to_ds_flag_6290; 1192 hal_soc->ops->hal_rx_get_mac_addr2_valid = 1193 hal_rx_get_mac_addr2_valid_6290; 1194 hal_soc->ops->hal_rx_get_filter_category = 1195 hal_rx_get_filter_category_6290; 1196 hal_soc->ops->hal_rx_get_ppdu_id = hal_rx_get_ppdu_id_6290; 1197 hal_soc->ops->hal_reo_config = hal_reo_config_6290; 1198 hal_soc->ops->hal_rx_msdu_flow_idx_get = hal_rx_msdu_flow_idx_get_6290; 1199 hal_soc->ops->hal_rx_msdu_flow_idx_invalid = 1200 hal_rx_msdu_flow_idx_invalid_6290; 1201 hal_soc->ops->hal_rx_msdu_flow_idx_timeout = 1202 hal_rx_msdu_flow_idx_timeout_6290; 1203 hal_soc->ops->hal_rx_msdu_fse_metadata_get = 1204 hal_rx_msdu_fse_metadata_get_6290; 1205 hal_soc->ops->hal_rx_msdu_cce_match_get = 1206 hal_rx_msdu_cce_match_get_li; 1207 hal_soc->ops->hal_rx_msdu_cce_metadata_get = 1208 hal_rx_msdu_cce_metadata_get_6290; 1209 hal_soc->ops->hal_rx_msdu_get_flow_params = 1210 hal_rx_msdu_get_flow_params_6290; 1211 hal_soc->ops->hal_rx_tlv_get_tcp_chksum = 1212 hal_rx_tlv_get_tcp_chksum_6290; 1213 hal_soc->ops->hal_rx_get_rx_sequence = hal_rx_get_rx_sequence_6290; 1214 /* rx - msdu end fast path info fields */ 1215 hal_soc->ops->hal_rx_msdu_packet_metadata_get = 1216 hal_rx_msdu_packet_metadata_get_generic_li; 1217 /* rx - TLV struct offsets */ 1218 hal_soc->ops->hal_rx_msdu_end_offset_get = 1219 hal_rx_msdu_end_offset_get_generic; 1220 hal_soc->ops->hal_rx_attn_offset_get = 1221 hal_rx_attn_offset_get_generic; 1222 hal_soc->ops->hal_rx_msdu_start_offset_get = 1223 hal_rx_msdu_start_offset_get_generic; 1224 hal_soc->ops->hal_rx_mpdu_start_offset_get = 1225 hal_rx_mpdu_start_offset_get_generic; 1226 hal_soc->ops->hal_rx_mpdu_end_offset_get = 1227 hal_rx_mpdu_end_offset_get_generic; 1228 #ifndef NO_RX_PKT_HDR_TLV 1229 hal_soc->ops->hal_rx_pkt_tlv_offset_get = 1230 hal_rx_pkt_tlv_offset_get_generic; 1231 #endif 1232 hal_soc->ops->hal_compute_reo_remap_ix2_ix3 = 1233 hal_compute_reo_remap_ix2_ix3_6290; 1234 hal_soc->ops->hal_setup_link_idle_list = 1235 hal_setup_link_idle_list_generic_li; 1236 #ifdef WLAN_FEATURE_MARK_FIRST_WAKEUP_PACKET 1237 hal_soc->ops->hal_get_first_wow_wakeup_packet = 1238 hal_get_first_wow_wakeup_packet_6290; 1239 #endif 1240 hal_soc->ops->hal_compute_reo_remap_ix0 = NULL; 1241 }; 1242 1243 struct hal_hw_srng_config hw_srng_table_6290[] = { 1244 /* TODO: max_rings can populated by querying HW capabilities */ 1245 { /* REO_DST */ 1246 .start_ring_id = HAL_SRNG_REO2SW1, 1247 .max_rings = 4, 1248 .entry_size = sizeof(struct reo_destination_ring) >> 2, 1249 .lmac_ring = FALSE, 1250 .ring_dir = HAL_SRNG_DST_RING, 1251 .reg_start = { 1252 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR( 1253 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1254 HWIO_REO_R2_REO2SW1_RING_HP_ADDR( 1255 SEQ_WCSS_UMAC_REO_REG_OFFSET) 1256 }, 1257 .reg_size = { 1258 HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(0) - 1259 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(0), 1260 HWIO_REO_R2_REO2SW2_RING_HP_ADDR(0) - 1261 HWIO_REO_R2_REO2SW1_RING_HP_ADDR(0), 1262 }, 1263 .max_size = HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_BMSK >> 1264 HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_SHFT, 1265 }, 1266 { /* REO_EXCEPTION */ 1267 /* Designating REO2TCL ring as exception ring. This ring is 1268 * similar to other REO2SW rings though it is named as REO2TCL. 1269 * Any of theREO2SW rings can be used as exception ring. 1270 */ 1271 .start_ring_id = HAL_SRNG_REO2TCL, 1272 .max_rings = 1, 1273 .entry_size = sizeof(struct reo_destination_ring) >> 2, 1274 .lmac_ring = FALSE, 1275 .ring_dir = HAL_SRNG_DST_RING, 1276 .reg_start = { 1277 HWIO_REO_R0_REO2TCL_RING_BASE_LSB_ADDR( 1278 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1279 HWIO_REO_R2_REO2TCL_RING_HP_ADDR( 1280 SEQ_WCSS_UMAC_REO_REG_OFFSET) 1281 }, 1282 /* Single ring - provide ring size if multiple rings of this 1283 * type are supported 1284 */ 1285 .reg_size = {}, 1286 .max_size = HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_BMSK >> 1287 HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_SHFT, 1288 }, 1289 { /* REO_REINJECT */ 1290 .start_ring_id = HAL_SRNG_SW2REO, 1291 .max_rings = 1, 1292 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 1293 .lmac_ring = FALSE, 1294 .ring_dir = HAL_SRNG_SRC_RING, 1295 .reg_start = { 1296 HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR( 1297 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1298 HWIO_REO_R2_SW2REO_RING_HP_ADDR( 1299 SEQ_WCSS_UMAC_REO_REG_OFFSET) 1300 }, 1301 /* Single ring - provide ring size if multiple rings of this 1302 * type are supported 1303 */ 1304 .reg_size = {}, 1305 .max_size = HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_BMSK >> 1306 HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_SHFT, 1307 }, 1308 { /* REO_CMD */ 1309 .start_ring_id = HAL_SRNG_REO_CMD, 1310 .max_rings = 1, 1311 .entry_size = (sizeof(struct tlv_32_hdr) + 1312 sizeof(struct reo_get_queue_stats)) >> 2, 1313 .lmac_ring = FALSE, 1314 .ring_dir = HAL_SRNG_SRC_RING, 1315 .reg_start = { 1316 HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR( 1317 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1318 HWIO_REO_R2_REO_CMD_RING_HP_ADDR( 1319 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1320 }, 1321 /* Single ring - provide ring size if multiple rings of this 1322 * type are supported 1323 */ 1324 .reg_size = {}, 1325 .max_size = HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_BMSK >> 1326 HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_SHFT, 1327 }, 1328 { /* REO_STATUS */ 1329 .start_ring_id = HAL_SRNG_REO_STATUS, 1330 .max_rings = 1, 1331 .entry_size = (sizeof(struct tlv_32_hdr) + 1332 sizeof(struct reo_get_queue_stats_status)) >> 2, 1333 .lmac_ring = FALSE, 1334 .ring_dir = HAL_SRNG_DST_RING, 1335 .reg_start = { 1336 HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR( 1337 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1338 HWIO_REO_R2_REO_STATUS_RING_HP_ADDR( 1339 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1340 }, 1341 /* Single ring - provide ring size if multiple rings of this 1342 * type are supported 1343 */ 1344 .reg_size = {}, 1345 .max_size = 1346 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> 1347 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, 1348 }, 1349 { /* TCL_DATA */ 1350 .start_ring_id = HAL_SRNG_SW2TCL1, 1351 .max_rings = 3, 1352 .entry_size = (sizeof(struct tlv_32_hdr) + 1353 sizeof(struct tcl_data_cmd)) >> 2, 1354 .lmac_ring = FALSE, 1355 .ring_dir = HAL_SRNG_SRC_RING, 1356 .reg_start = { 1357 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR( 1358 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1359 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR( 1360 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1361 }, 1362 .reg_size = { 1363 HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(0) - 1364 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(0), 1365 HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(0) - 1366 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(0), 1367 }, 1368 .max_size = HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK >> 1369 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT, 1370 }, 1371 { /* TCL_CMD */ 1372 .start_ring_id = HAL_SRNG_SW2TCL_CMD, 1373 .max_rings = 1, 1374 .entry_size = (sizeof(struct tlv_32_hdr) + 1375 sizeof(struct tcl_gse_cmd)) >> 2, 1376 .lmac_ring = FALSE, 1377 .ring_dir = HAL_SRNG_SRC_RING, 1378 .reg_start = { 1379 HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_ADDR( 1380 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1381 HWIO_TCL_R2_SW2TCL_CMD_RING_HP_ADDR( 1382 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1383 }, 1384 /* Single ring - provide ring size if multiple rings of this 1385 * type are supported 1386 */ 1387 .reg_size = {}, 1388 .max_size = 1389 HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RING_SIZE_BMSK >> 1390 HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RING_SIZE_SHFT, 1391 }, 1392 { /* TCL_STATUS */ 1393 .start_ring_id = HAL_SRNG_TCL_STATUS, 1394 .max_rings = 1, 1395 .entry_size = (sizeof(struct tlv_32_hdr) + 1396 sizeof(struct tcl_status_ring)) >> 2, 1397 .lmac_ring = FALSE, 1398 .ring_dir = HAL_SRNG_DST_RING, 1399 .reg_start = { 1400 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR( 1401 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1402 HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR( 1403 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1404 }, 1405 /* Single ring - provide ring size if multiple rings of this 1406 * type are supported 1407 */ 1408 .reg_size = {}, 1409 .max_size = 1410 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_BMSK >> 1411 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_SHFT, 1412 }, 1413 { /* CE_SRC */ 1414 .start_ring_id = HAL_SRNG_CE_0_SRC, 1415 .max_rings = 12, 1416 .entry_size = sizeof(struct ce_src_desc) >> 2, 1417 .lmac_ring = FALSE, 1418 .ring_dir = HAL_SRNG_SRC_RING, 1419 .reg_start = { 1420 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR( 1421 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET), 1422 HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR( 1423 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET), 1424 }, 1425 .reg_size = { 1426 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET - 1427 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET, 1428 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET - 1429 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET, 1430 }, 1431 .max_size = 1432 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >> 1433 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT, 1434 }, 1435 { /* CE_DST */ 1436 .start_ring_id = HAL_SRNG_CE_0_DST, 1437 .max_rings = 12, 1438 .entry_size = 8 >> 2, 1439 /*TODO: entry_size above should actually be 1440 * sizeof(struct ce_dst_desc) >> 2, but couldn't find definition 1441 * of struct ce_dst_desc in HW header files 1442 */ 1443 .lmac_ring = FALSE, 1444 .ring_dir = HAL_SRNG_SRC_RING, 1445 .reg_start = { 1446 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR( 1447 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 1448 HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR( 1449 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 1450 }, 1451 .reg_size = { 1452 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 1453 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 1454 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 1455 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 1456 }, 1457 .max_size = 1458 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >> 1459 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT, 1460 }, 1461 { /* CE_DST_STATUS */ 1462 .start_ring_id = HAL_SRNG_CE_0_DST_STATUS, 1463 .max_rings = 12, 1464 .entry_size = sizeof(struct ce_stat_desc) >> 2, 1465 .lmac_ring = FALSE, 1466 .ring_dir = HAL_SRNG_DST_RING, 1467 .reg_start = { 1468 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR( 1469 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 1470 HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR( 1471 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 1472 }, 1473 /* TODO: check destination status ring registers */ 1474 .reg_size = { 1475 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 1476 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 1477 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 1478 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 1479 }, 1480 .max_size = 1481 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> 1482 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, 1483 }, 1484 { /* WBM_IDLE_LINK */ 1485 .start_ring_id = HAL_SRNG_WBM_IDLE_LINK, 1486 .max_rings = 1, 1487 .entry_size = sizeof(struct wbm_link_descriptor_ring) >> 2, 1488 .lmac_ring = FALSE, 1489 .ring_dir = HAL_SRNG_SRC_RING, 1490 .reg_start = { 1491 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1492 HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1493 }, 1494 /* Single ring - provide ring size if multiple rings of this 1495 * type are supported 1496 */ 1497 .reg_size = {}, 1498 .max_size = 1499 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_BMSK >> 1500 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_SHFT, 1501 }, 1502 { /* SW2WBM_RELEASE */ 1503 .start_ring_id = HAL_SRNG_WBM_SW_RELEASE, 1504 .max_rings = 1, 1505 .entry_size = sizeof(struct wbm_release_ring) >> 2, 1506 .lmac_ring = FALSE, 1507 .ring_dir = HAL_SRNG_SRC_RING, 1508 .reg_start = { 1509 HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1510 HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1511 }, 1512 /* Single ring - provide ring size if multiple rings of this 1513 * type are supported 1514 */ 1515 .reg_size = {}, 1516 .max_size = 1517 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> 1518 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, 1519 }, 1520 { /* WBM2SW_RELEASE */ 1521 .start_ring_id = HAL_SRNG_WBM2SW0_RELEASE, 1522 .max_rings = 4, 1523 .entry_size = sizeof(struct wbm_release_ring) >> 2, 1524 .lmac_ring = FALSE, 1525 .ring_dir = HAL_SRNG_DST_RING, 1526 .reg_start = { 1527 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1528 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1529 }, 1530 .reg_size = { 1531 HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) - 1532 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1533 HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) - 1534 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1535 }, 1536 .max_size = 1537 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> 1538 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, 1539 }, 1540 { /* RXDMA_BUF */ 1541 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA0_BUF0, 1542 #ifdef IPA_OFFLOAD 1543 .max_rings = 3, 1544 #else 1545 .max_rings = 2, 1546 #endif 1547 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 1548 .lmac_ring = TRUE, 1549 .ring_dir = HAL_SRNG_SRC_RING, 1550 /* reg_start is not set because LMAC rings are not accessed 1551 * from host 1552 */ 1553 .reg_start = {}, 1554 .reg_size = {}, 1555 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1556 }, 1557 { /* RXDMA_DST */ 1558 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW0, 1559 .max_rings = 1, 1560 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 1561 .lmac_ring = TRUE, 1562 .ring_dir = HAL_SRNG_DST_RING, 1563 /* reg_start is not set because LMAC rings are not accessed 1564 * from host 1565 */ 1566 .reg_start = {}, 1567 .reg_size = {}, 1568 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1569 }, 1570 { /* RXDMA_MONITOR_BUF */ 1571 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA2_BUF, 1572 .max_rings = 1, 1573 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 1574 .lmac_ring = TRUE, 1575 .ring_dir = HAL_SRNG_SRC_RING, 1576 /* reg_start is not set because LMAC rings are not accessed 1577 * from host 1578 */ 1579 .reg_start = {}, 1580 .reg_size = {}, 1581 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1582 }, 1583 { /* RXDMA_MONITOR_STATUS */ 1584 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_STATBUF, 1585 .max_rings = 1, 1586 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 1587 .lmac_ring = TRUE, 1588 .ring_dir = HAL_SRNG_SRC_RING, 1589 /* reg_start is not set because LMAC rings are not accessed 1590 * from host 1591 */ 1592 .reg_start = {}, 1593 .reg_size = {}, 1594 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1595 }, 1596 { /* RXDMA_MONITOR_DST */ 1597 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW1, 1598 .max_rings = 1, 1599 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 1600 .lmac_ring = TRUE, 1601 .ring_dir = HAL_SRNG_DST_RING, 1602 /* reg_start is not set because LMAC rings are not accessed 1603 * from host 1604 */ 1605 .reg_start = {}, 1606 .reg_size = {}, 1607 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1608 }, 1609 { /* RXDMA_MONITOR_DESC */ 1610 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_DESC, 1611 .max_rings = 1, 1612 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 1613 .lmac_ring = TRUE, 1614 .ring_dir = HAL_SRNG_SRC_RING, 1615 /* reg_start is not set because LMAC rings are not accessed 1616 * from host 1617 */ 1618 .reg_start = {}, 1619 .reg_size = {}, 1620 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1621 }, 1622 { /* DIR_BUF_RX_DMA_SRC */ 1623 .start_ring_id = HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING, 1624 .max_rings = 1, 1625 .entry_size = 2, 1626 .lmac_ring = TRUE, 1627 .ring_dir = HAL_SRNG_SRC_RING, 1628 /* reg_start is not set because LMAC rings are not accessed 1629 * from host 1630 */ 1631 .reg_start = {}, 1632 .reg_size = {}, 1633 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1634 }, 1635 #ifdef WLAN_FEATURE_CIF_CFR 1636 { /* WIFI_POS_SRC */ 1637 .start_ring_id = HAL_SRNG_WIFI_POS_SRC_DMA_RING, 1638 .max_rings = 1, 1639 .entry_size = sizeof(wmi_oem_dma_buf_release_entry) >> 2, 1640 .lmac_ring = TRUE, 1641 .ring_dir = HAL_SRNG_SRC_RING, 1642 /* reg_start is not set because LMAC rings are not accessed 1643 * from host 1644 */ 1645 .reg_start = {}, 1646 .reg_size = {}, 1647 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1648 }, 1649 #endif 1650 { /* REO2PPE */ 0}, 1651 { /* PPE2TCL */ 0}, 1652 { /* PPE_RELEASE */ 0}, 1653 { /* TX_MONITOR_BUF */ 0}, 1654 { /* TX_MONITOR_DST */ 0}, 1655 { /* SW2RXDMA_NEW */ 0}, 1656 }; 1657 1658 /** 1659 * hal_qca6290_attach() - Attach 6290 target specific hal_soc ops, 1660 * offset and srng table 1661 */ 1662 void hal_qca6290_attach(struct hal_soc *hal_soc) 1663 { 1664 hal_soc->hw_srng_table = hw_srng_table_6290; 1665 hal_srng_hw_reg_offset_init_generic(hal_soc); 1666 1667 hal_hw_txrx_default_ops_attach_li(hal_soc); 1668 hal_hw_txrx_ops_attach_6290(hal_soc); 1669 } 1670