1 /* 2 * Copyright (c) 2016-2020 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 #include "qdf_types.h" 19 #include "qdf_util.h" 20 #include "qdf_types.h" 21 #include "qdf_lock.h" 22 #include "qdf_mem.h" 23 #include "qdf_nbuf.h" 24 #include "hal_hw_headers.h" 25 #include "hal_internal.h" 26 #include "hal_api.h" 27 #include "target_type.h" 28 #include "wcss_version.h" 29 #include "qdf_module.h" 30 31 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_OFFSET \ 32 RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_OFFSET 33 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_MASK \ 34 RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_MASK 35 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_LSB \ 36 RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_LSB 37 #define UNIFIED_PHYRX_HT_SIG_0_HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS_OFFSET \ 38 PHYRX_HT_SIG_0_HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS_OFFSET 39 #define UNIFIED_PHYRX_L_SIG_B_0_L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS_OFFSET \ 40 PHYRX_L_SIG_B_0_L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS_OFFSET 41 #define UNIFIED_PHYRX_L_SIG_A_0_L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS_OFFSET \ 42 PHYRX_L_SIG_A_0_L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS_OFFSET 43 #define UNIFIED_PHYRX_VHT_SIG_A_0_VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS_OFFSET \ 44 PHYRX_VHT_SIG_A_0_VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS_OFFSET 45 #define UNIFIED_PHYRX_HE_SIG_A_SU_0_HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS_OFFSET \ 46 PHYRX_HE_SIG_A_SU_0_HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS_OFFSET 47 #define UNIFIED_PHYRX_HE_SIG_A_MU_DL_0_HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_OFFSET \ 48 PHYRX_HE_SIG_A_MU_DL_0_HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_OFFSET 49 #define UNIFIED_PHYRX_HE_SIG_B1_MU_0_HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_OFFSET \ 50 PHYRX_HE_SIG_B1_MU_0_HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_OFFSET 51 #define UNIFIED_PHYRX_HE_SIG_B2_MU_0_HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_OFFSET \ 52 PHYRX_HE_SIG_B2_MU_0_HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_OFFSET 53 #define UNIFIED_PHYRX_HE_SIG_B2_OFDMA_0_HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_OFFSET \ 54 PHYRX_HE_SIG_B2_OFDMA_0_HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_OFFSET 55 #define UNIFIED_PHYRX_RSSI_LEGACY_3_RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS_OFFSET \ 56 PHYRX_RSSI_LEGACY_3_RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS_OFFSET 57 #define UNIFIED_PHYRX_RSSI_LEGACY_19_RECEIVE_RSSI_INFO_PREAMBLE_RSSI_INFO_DETAILS_OFFSET \ 58 PHYRX_RSSI_LEGACY_19_RECEIVE_RSSI_INFO_PREAMBLE_RSSI_INFO_DETAILS_OFFSET 59 #define UNIFIED_RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET \ 60 RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET 61 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 62 RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET 63 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ 64 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET 65 #define UNIFIED_RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 66 RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET 67 #define UNIFIED_REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 68 REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET 69 #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC \ 70 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER 71 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ 72 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET 73 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 74 RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET 75 #define UNIFIED_TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 76 TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET 77 #define UNIFIED_TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 78 TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET 79 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET \ 80 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET 81 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB \ 82 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB 83 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK \ 84 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK 85 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB \ 86 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB 87 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK \ 88 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK 89 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB \ 90 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB 91 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK \ 92 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK 93 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB \ 94 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB 95 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK \ 96 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK 97 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB \ 98 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB 99 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK \ 100 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK 101 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_MASK \ 102 WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_MASK 103 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_OFFSET \ 104 WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_OFFSET 105 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_LSB \ 106 WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_LSB 107 108 #include "hal_6290_tx.h" 109 #include "hal_6290_rx.h" 110 #include <hal_generic_api.h> 111 #include <hal_wbm.h> 112 113 /** 114 * hal_rx_get_rx_fragment_number_6290(): Function to retrieve rx fragment number 115 * 116 * @nbuf: Network buffer 117 * Returns: rx fragment number 118 */ 119 static 120 uint8_t hal_rx_get_rx_fragment_number_6290(uint8_t *buf) 121 { 122 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 123 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 124 125 /* Return first 4 bits as fragment number */ 126 return (HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info) & 127 DOT11_SEQ_FRAG_MASK); 128 } 129 130 /** 131 * hal_rx_msdu_end_da_is_mcbc_get: API to check if pkt is MCBC 132 * from rx_msdu_end TLV 133 * 134 * @ buf: pointer to the start of RX PKT TLV headers 135 * Return: da_is_mcbc 136 */ 137 static inline uint8_t 138 hal_rx_msdu_end_da_is_mcbc_get_6290(uint8_t *buf) 139 { 140 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 141 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 142 143 return HAL_RX_MSDU_END_DA_IS_MCBC_GET(msdu_end); 144 } 145 146 /** 147 * hal_rx_msdu_end_sa_is_valid_get_6290(): API to get_6290 the 148 * sa_is_valid bit from rx_msdu_end TLV 149 * 150 * @ buf: pointer to the start of RX PKT TLV headers 151 * Return: sa_is_valid bit 152 */ 153 static uint8_t 154 hal_rx_msdu_end_sa_is_valid_get_6290(uint8_t *buf) 155 { 156 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 157 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 158 uint8_t sa_is_valid; 159 160 sa_is_valid = HAL_RX_MSDU_END_SA_IS_VALID_GET(msdu_end); 161 162 return sa_is_valid; 163 } 164 165 /** 166 * hal_rx_msdu_end_sa_idx_get_6290(): API to get_6290 the 167 * sa_idx from rx_msdu_end TLV 168 * 169 * @ buf: pointer to the start of RX PKT TLV headers 170 * Return: sa_idx (SA AST index) 171 */ 172 static 173 uint16_t hal_rx_msdu_end_sa_idx_get_6290(uint8_t *buf) 174 { 175 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 176 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 177 uint16_t sa_idx; 178 179 sa_idx = HAL_RX_MSDU_END_SA_IDX_GET(msdu_end); 180 181 return sa_idx; 182 } 183 184 /** 185 * hal_rx_desc_is_first_msdu_6290() - Check if first msdu 186 * 187 * @hal_soc_hdl: hal_soc handle 188 * @hw_desc_addr: hardware descriptor address 189 * 190 * Return: 0 - success/ non-zero failure 191 */ 192 static uint32_t hal_rx_desc_is_first_msdu_6290(void *hw_desc_addr) 193 { 194 struct rx_pkt_tlvs *rx_tlvs = (struct rx_pkt_tlvs *)hw_desc_addr; 195 struct rx_msdu_end *msdu_end = &rx_tlvs->msdu_end_tlv.rx_msdu_end; 196 197 return HAL_RX_GET(msdu_end, RX_MSDU_END_5, FIRST_MSDU); 198 } 199 200 /** 201 * hal_rx_msdu_end_l3_hdr_padding_get_6290(): API to get_6290 the 202 * l3_header padding from rx_msdu_end TLV 203 * 204 * @ buf: pointer to the start of RX PKT TLV headers 205 * Return: number of l3 header padding bytes 206 */ 207 static uint32_t hal_rx_msdu_end_l3_hdr_padding_get_6290(uint8_t *buf) 208 { 209 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 210 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 211 uint32_t l3_header_padding; 212 213 l3_header_padding = HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(msdu_end); 214 215 return l3_header_padding; 216 } 217 218 /* 219 * @ hal_rx_encryption_info_valid_6290: Returns encryption type. 220 * 221 * @ buf: rx_tlv_hdr of the received packet 222 * @ Return: encryption type 223 */ 224 static uint32_t hal_rx_encryption_info_valid_6290(uint8_t *buf) 225 { 226 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 227 struct rx_mpdu_start *mpdu_start = 228 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 229 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 230 uint32_t encryption_info = HAL_RX_MPDU_ENCRYPTION_INFO_VALID(mpdu_info); 231 232 return encryption_info; 233 } 234 235 /* 236 * hal_rx_print_pn_6290: Prints the PN of rx packet. 237 * @buf: rx_tlv_hdr of the received packet 238 * 239 * Return: void 240 */ 241 static void hal_rx_print_pn_6290(uint8_t *buf) 242 { 243 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 244 struct rx_mpdu_start *mpdu_start = 245 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 246 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 247 248 uint32_t pn_31_0 = HAL_RX_MPDU_PN_31_0_GET(mpdu_info); 249 uint32_t pn_63_32 = HAL_RX_MPDU_PN_63_32_GET(mpdu_info); 250 uint32_t pn_95_64 = HAL_RX_MPDU_PN_95_64_GET(mpdu_info); 251 uint32_t pn_127_96 = HAL_RX_MPDU_PN_127_96_GET(mpdu_info); 252 253 hal_debug("PN number pn_127_96 0x%x pn_95_64 0x%x pn_63_32 0x%x pn_31_0 0x%x ", 254 pn_127_96, pn_95_64, pn_63_32, pn_31_0); 255 } 256 257 /** 258 * hal_rx_msdu_end_first_msdu_get_6290: API to get first msdu status 259 * from rx_msdu_end TLV 260 * 261 * @buf: pointer to the start of RX PKT TLV headers 262 * Return: first_msdu 263 */ 264 static uint8_t 265 hal_rx_msdu_end_first_msdu_get_6290(uint8_t *buf) 266 { 267 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 268 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 269 uint8_t first_msdu; 270 271 first_msdu = HAL_RX_MSDU_END_FIRST_MSDU_GET(msdu_end); 272 273 return first_msdu; 274 } 275 276 /** 277 * hal_rx_msdu_end_da_is_valid_get_6290: API to check if da is valid 278 * from rx_msdu_end TLV 279 * 280 * @ buf: pointer to the start of RX PKT TLV headers 281 * Return: da_is_valid 282 */ 283 static uint8_t hal_rx_msdu_end_da_is_valid_get_6290(uint8_t *buf) 284 { 285 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 286 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 287 uint8_t da_is_valid; 288 289 da_is_valid = HAL_RX_MSDU_END_DA_IS_VALID_GET(msdu_end); 290 291 return da_is_valid; 292 } 293 294 /** 295 * hal_rx_msdu_end_last_msdu_get_6290: API to get last msdu status 296 * from rx_msdu_end TLV 297 * 298 * @ buf: pointer to the start of RX PKT TLV headers 299 * Return: last_msdu 300 */ 301 static uint8_t hal_rx_msdu_end_last_msdu_get_6290(uint8_t *buf) 302 { 303 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 304 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 305 uint8_t last_msdu; 306 307 last_msdu = HAL_RX_MSDU_END_LAST_MSDU_GET(msdu_end); 308 309 return last_msdu; 310 } 311 312 /* 313 * hal_rx_get_mpdu_mac_ad4_valid_6290(): Retrieves if mpdu 4th addr is valid 314 * 315 * @nbuf: Network buffer 316 * Returns: value of mpdu 4th address valid field 317 */ 318 static bool hal_rx_get_mpdu_mac_ad4_valid_6290(uint8_t *buf) 319 { 320 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 321 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 322 bool ad4_valid = 0; 323 324 ad4_valid = HAL_RX_MPDU_GET_MAC_AD4_VALID(rx_mpdu_info); 325 326 return ad4_valid; 327 } 328 329 /** 330 * hal_rx_mpdu_start_sw_peer_id_get_6290: Retrieve sw peer_id 331 * @buf: network buffer 332 * 333 * Return: sw peer_id: 334 */ 335 static uint32_t hal_rx_mpdu_start_sw_peer_id_get_6290(uint8_t *buf) 336 { 337 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 338 struct rx_mpdu_start *mpdu_start = 339 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 340 341 return HAL_RX_MPDU_INFO_SW_PEER_ID_GET( 342 &mpdu_start->rx_mpdu_info_details); 343 } 344 345 /* 346 * hal_rx_mpdu_get_to_ds_6290(): API to get the tods info 347 * from rx_mpdu_start 348 * 349 * @buf: pointer to the start of RX PKT TLV header 350 * Return: uint32_t(to_ds) 351 */ 352 353 static uint32_t hal_rx_mpdu_get_to_ds_6290(uint8_t *buf) 354 { 355 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 356 struct rx_mpdu_start *mpdu_start = 357 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 358 359 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 360 361 return HAL_RX_MPDU_GET_TODS(mpdu_info); 362 } 363 364 /* 365 * hal_rx_mpdu_get_fr_ds_6290(): API to get the from ds info 366 * from rx_mpdu_start 367 * 368 * @buf: pointer to the start of RX PKT TLV header 369 * Return: uint32_t(fr_ds) 370 */ 371 static uint32_t hal_rx_mpdu_get_fr_ds_6290(uint8_t *buf) 372 { 373 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 374 struct rx_mpdu_start *mpdu_start = 375 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 376 377 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 378 379 return HAL_RX_MPDU_GET_FROMDS(mpdu_info); 380 } 381 382 /* 383 * hal_rx_get_mpdu_frame_control_valid_6290(): Retrieves mpdu frame 384 * control valid 385 * 386 * @nbuf: Network buffer 387 * Returns: value of frame control valid field 388 */ 389 static uint8_t hal_rx_get_mpdu_frame_control_valid_6290(uint8_t *buf) 390 { 391 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 392 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 393 394 return HAL_RX_MPDU_GET_FRAME_CONTROL_VALID(rx_mpdu_info); 395 } 396 397 /* 398 * hal_rx_mpdu_get_addr1_6290(): API to check get address1 of the mpdu 399 * 400 * @buf: pointer to the start of RX PKT TLV headera 401 * @mac_addr: pointer to mac address 402 * Return: success/failure 403 */ 404 static QDF_STATUS hal_rx_mpdu_get_addr1_6290(uint8_t *buf, uint8_t *mac_addr) 405 { 406 struct __attribute__((__packed__)) hal_addr1 { 407 uint32_t ad1_31_0; 408 uint16_t ad1_47_32; 409 }; 410 411 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 412 struct rx_mpdu_start *mpdu_start = 413 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 414 415 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 416 struct hal_addr1 *addr = (struct hal_addr1 *)mac_addr; 417 uint32_t mac_addr_ad1_valid; 418 419 mac_addr_ad1_valid = HAL_RX_MPDU_MAC_ADDR_AD1_VALID_GET(mpdu_info); 420 421 if (mac_addr_ad1_valid) { 422 addr->ad1_31_0 = HAL_RX_MPDU_AD1_31_0_GET(mpdu_info); 423 addr->ad1_47_32 = HAL_RX_MPDU_AD1_47_32_GET(mpdu_info); 424 return QDF_STATUS_SUCCESS; 425 } 426 427 return QDF_STATUS_E_FAILURE; 428 } 429 430 /* 431 * hal_rx_mpdu_get_addr2_6290(): API to check get address2 of the mpdu 432 * in the packet 433 * 434 * @buf: pointer to the start of RX PKT TLV header 435 * @mac_addr: pointer to mac address 436 * Return: success/failure 437 */ 438 static QDF_STATUS hal_rx_mpdu_get_addr2_6290(uint8_t *buf, 439 uint8_t *mac_addr) 440 { 441 struct __attribute__((__packed__)) hal_addr2 { 442 uint16_t ad2_15_0; 443 uint32_t ad2_47_16; 444 }; 445 446 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 447 struct rx_mpdu_start *mpdu_start = 448 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 449 450 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 451 struct hal_addr2 *addr = (struct hal_addr2 *)mac_addr; 452 uint32_t mac_addr_ad2_valid; 453 454 mac_addr_ad2_valid = HAL_RX_MPDU_MAC_ADDR_AD2_VALID_GET(mpdu_info); 455 456 if (mac_addr_ad2_valid) { 457 addr->ad2_15_0 = HAL_RX_MPDU_AD2_15_0_GET(mpdu_info); 458 addr->ad2_47_16 = HAL_RX_MPDU_AD2_47_16_GET(mpdu_info); 459 return QDF_STATUS_SUCCESS; 460 } 461 462 return QDF_STATUS_E_FAILURE; 463 } 464 465 /* 466 * hal_rx_mpdu_get_addr3_6290(): API to get address3 of the mpdu 467 * in the packet 468 * 469 * @buf: pointer to the start of RX PKT TLV header 470 * @mac_addr: pointer to mac address 471 * Return: success/failure 472 */ 473 static QDF_STATUS hal_rx_mpdu_get_addr3_6290(uint8_t *buf, uint8_t *mac_addr) 474 { 475 struct __attribute__((__packed__)) hal_addr3 { 476 uint32_t ad3_31_0; 477 uint16_t ad3_47_32; 478 }; 479 480 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 481 struct rx_mpdu_start *mpdu_start = 482 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 483 484 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 485 struct hal_addr3 *addr = (struct hal_addr3 *)mac_addr; 486 uint32_t mac_addr_ad3_valid; 487 488 mac_addr_ad3_valid = HAL_RX_MPDU_MAC_ADDR_AD3_VALID_GET(mpdu_info); 489 490 if (mac_addr_ad3_valid) { 491 addr->ad3_31_0 = HAL_RX_MPDU_AD3_31_0_GET(mpdu_info); 492 addr->ad3_47_32 = HAL_RX_MPDU_AD3_47_32_GET(mpdu_info); 493 return QDF_STATUS_SUCCESS; 494 } 495 496 return QDF_STATUS_E_FAILURE; 497 } 498 499 /* 500 * hal_rx_mpdu_get_addr4_6290(): API to get address4 of the mpdu 501 * in the packet 502 * 503 * @buf: pointer to the start of RX PKT TLV header 504 * @mac_addr: pointer to mac address 505 * Return: success/failure 506 */ 507 static QDF_STATUS hal_rx_mpdu_get_addr4_6290(uint8_t *buf, uint8_t *mac_addr) 508 { 509 struct __attribute__((__packed__)) hal_addr4 { 510 uint32_t ad4_31_0; 511 uint16_t ad4_47_32; 512 }; 513 514 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 515 struct rx_mpdu_start *mpdu_start = 516 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 517 518 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 519 struct hal_addr4 *addr = (struct hal_addr4 *)mac_addr; 520 uint32_t mac_addr_ad4_valid; 521 522 mac_addr_ad4_valid = HAL_RX_MPDU_MAC_ADDR_AD4_VALID_GET(mpdu_info); 523 524 if (mac_addr_ad4_valid) { 525 addr->ad4_31_0 = HAL_RX_MPDU_AD4_31_0_GET(mpdu_info); 526 addr->ad4_47_32 = HAL_RX_MPDU_AD4_47_32_GET(mpdu_info); 527 return QDF_STATUS_SUCCESS; 528 } 529 530 return QDF_STATUS_E_FAILURE; 531 } 532 533 /* 534 * hal_rx_get_mpdu_sequence_control_valid_6290(): Get mpdu 535 * sequence control valid 536 * 537 * @nbuf: Network buffer 538 * Returns: value of sequence control valid field 539 */ 540 static uint8_t hal_rx_get_mpdu_sequence_control_valid_6290(uint8_t *buf) 541 { 542 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 543 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 544 545 return HAL_RX_MPDU_GET_SEQUENCE_CONTROL_VALID(rx_mpdu_info); 546 } 547 548 /** 549 * hal_rx_is_unicast_6290: check packet is unicast frame or not. 550 * 551 * @ buf: pointer to rx pkt TLV. 552 * 553 * Return: true on unicast. 554 */ 555 static bool hal_rx_is_unicast_6290(uint8_t *buf) 556 { 557 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 558 struct rx_mpdu_start *mpdu_start = 559 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 560 uint32_t grp_id; 561 uint8_t *rx_mpdu_info = (uint8_t *)&mpdu_start->rx_mpdu_info_details; 562 563 grp_id = (_HAL_MS((*_OFFSET_TO_WORD_PTR((rx_mpdu_info), 564 RX_MPDU_INFO_0_SW_FRAME_GROUP_ID_OFFSET)), 565 RX_MPDU_INFO_0_SW_FRAME_GROUP_ID_MASK, 566 RX_MPDU_INFO_0_SW_FRAME_GROUP_ID_LSB)); 567 568 return (HAL_MPDU_SW_FRAME_GROUP_UNICAST_DATA == grp_id) ? true : false; 569 } 570 571 /** 572 * hal_rx_tid_get_6290: get tid based on qos control valid. 573 * @hal_soc_hdl: hal soc handle 574 * @ buf: pointer to rx pkt TLV. 575 * 576 * Return: tid 577 */ 578 static uint32_t hal_rx_tid_get_6290(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 579 { 580 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 581 struct rx_mpdu_start *mpdu_start = 582 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 583 uint8_t *rx_mpdu_info = (uint8_t *)&mpdu_start->rx_mpdu_info_details; 584 uint8_t qos_control_valid = 585 (_HAL_MS((*_OFFSET_TO_WORD_PTR((rx_mpdu_info), 586 RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_OFFSET)), 587 RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_MASK, 588 RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_LSB)); 589 590 if (qos_control_valid) 591 return hal_rx_mpdu_start_tid_get_6290(buf); 592 593 return HAL_RX_NON_QOS_TID; 594 } 595 596 /** 597 * hal_rx_hw_desc_get_ppduid_get_6290(): retrieve ppdu id 598 * @rx_tlv_hdr: start address of rx_pkt_tlvs 599 * @rxdma_dst_ring_desc: Rx HW descriptor 600 * 601 * Return: ppdu id 602 */ 603 static uint32_t hal_rx_hw_desc_get_ppduid_get_6290(void *rx_tlv_hdr, 604 void *rxdma_dst_ring_desc) 605 { 606 struct rx_mpdu_info *rx_mpdu_info; 607 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)rx_tlv_hdr; 608 609 rx_mpdu_info = 610 &rx_desc->mpdu_start_tlv.rx_mpdu_start.rx_mpdu_info_details; 611 612 return HAL_RX_GET(rx_mpdu_info, RX_MPDU_INFO_0, PHY_PPDU_ID); 613 } 614 615 /** 616 * hal_reo_status_get_header_6290 - Process reo desc info 617 * @d - Pointer to reo descriptior 618 * @b - tlv type info 619 * @h1 - Pointer to hal_reo_status_header where info to be stored 620 * 621 * Return - none. 622 * 623 */ 624 static void hal_reo_status_get_header_6290(uint32_t *d, int b, void *h1) 625 { 626 uint32_t val1 = 0; 627 struct hal_reo_status_header *h = 628 (struct hal_reo_status_header *)h1; 629 630 switch (b) { 631 case HAL_REO_QUEUE_STATS_STATUS_TLV: 632 val1 = d[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_0, 633 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 634 break; 635 case HAL_REO_FLUSH_QUEUE_STATUS_TLV: 636 val1 = d[HAL_OFFSET_DW(REO_FLUSH_QUEUE_STATUS_0, 637 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 638 break; 639 case HAL_REO_FLUSH_CACHE_STATUS_TLV: 640 val1 = d[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_0, 641 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 642 break; 643 case HAL_REO_UNBLK_CACHE_STATUS_TLV: 644 val1 = d[HAL_OFFSET_DW(REO_UNBLOCK_CACHE_STATUS_0, 645 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 646 break; 647 case HAL_REO_TIMOUT_LIST_STATUS_TLV: 648 val1 = d[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_0, 649 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 650 break; 651 case HAL_REO_DESC_THRES_STATUS_TLV: 652 val1 = 653 d[HAL_OFFSET_DW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0, 654 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 655 break; 656 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: 657 val1 = d[HAL_OFFSET_DW(REO_UPDATE_RX_REO_QUEUE_STATUS_0, 658 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 659 break; 660 default: 661 qdf_nofl_err("ERROR: Unknown tlv\n"); 662 break; 663 } 664 h->cmd_num = 665 HAL_GET_FIELD( 666 UNIFORM_REO_STATUS_HEADER_0, REO_STATUS_NUMBER, 667 val1); 668 h->exec_time = 669 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_0, 670 CMD_EXECUTION_TIME, val1); 671 h->status = 672 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_0, 673 REO_CMD_EXECUTION_STATUS, val1); 674 switch (b) { 675 case HAL_REO_QUEUE_STATS_STATUS_TLV: 676 val1 = d[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_1, 677 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 678 break; 679 case HAL_REO_FLUSH_QUEUE_STATUS_TLV: 680 val1 = d[HAL_OFFSET_DW(REO_FLUSH_QUEUE_STATUS_1, 681 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 682 break; 683 case HAL_REO_FLUSH_CACHE_STATUS_TLV: 684 val1 = d[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_1, 685 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 686 break; 687 case HAL_REO_UNBLK_CACHE_STATUS_TLV: 688 val1 = d[HAL_OFFSET_DW(REO_UNBLOCK_CACHE_STATUS_1, 689 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 690 break; 691 case HAL_REO_TIMOUT_LIST_STATUS_TLV: 692 val1 = d[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_1, 693 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 694 break; 695 case HAL_REO_DESC_THRES_STATUS_TLV: 696 val1 = 697 d[HAL_OFFSET_DW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_1, 698 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 699 break; 700 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: 701 val1 = d[HAL_OFFSET_DW(REO_UPDATE_RX_REO_QUEUE_STATUS_1, 702 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 703 break; 704 default: 705 qdf_nofl_err("ERROR: Unknown tlv\n"); 706 break; 707 } 708 h->tstamp = 709 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_1, TIMESTAMP, val1); 710 } 711 712 /** 713 * hal_rx_mpdu_start_mpdu_qos_control_valid_get_6290(): 714 * Retrieve qos control valid bit from the tlv. 715 * @buf: pointer to rx pkt TLV. 716 * 717 * Return: qos control value. 718 */ 719 static inline uint32_t 720 hal_rx_mpdu_start_mpdu_qos_control_valid_get_6290(uint8_t *buf) 721 { 722 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 723 struct rx_mpdu_start *mpdu_start = 724 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 725 726 return HAL_RX_MPDU_INFO_QOS_CONTROL_VALID_GET( 727 &mpdu_start->rx_mpdu_info_details); 728 } 729 730 /** 731 * hal_rx_msdu_end_sa_sw_peer_id_get_6290(): API to get the 732 * sa_sw_peer_id from rx_msdu_end TLV 733 * @buf: pointer to the start of RX PKT TLV headers 734 * 735 * Return: sa_sw_peer_id index 736 */ 737 static inline uint32_t 738 hal_rx_msdu_end_sa_sw_peer_id_get_6290(uint8_t *buf) 739 { 740 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 741 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 742 743 return HAL_RX_MSDU_END_SA_SW_PEER_ID_GET(msdu_end); 744 } 745 746 /** 747 * hal_tx_desc_set_mesh_en_6290 - Set mesh_enable flag in Tx descriptor 748 * @desc: Handle to Tx Descriptor 749 * @en: For raw WiFi frames, this indicates transmission to a mesh STA, 750 * enabling the interpretation of the 'Mesh Control Present' bit 751 * (bit 8) of QoS Control (otherwise this bit is ignored), 752 * For native WiFi frames, this indicates that a 'Mesh Control' field 753 * is present between the header and the LLC. 754 * 755 * Return: void 756 */ 757 static inline 758 void hal_tx_desc_set_mesh_en_6290(void *desc, uint8_t en) 759 { 760 HAL_SET_FLD(desc, TCL_DATA_CMD_4, MESH_ENABLE) |= 761 HAL_TX_SM(TCL_DATA_CMD_4, MESH_ENABLE, en); 762 } 763 764 static 765 void *hal_rx_msdu0_buffer_addr_lsb_6290(void *link_desc_va) 766 { 767 return (void *)HAL_RX_MSDU0_BUFFER_ADDR_LSB(link_desc_va); 768 } 769 770 static 771 void *hal_rx_msdu_desc_info_ptr_get_6290(void *msdu0) 772 { 773 return (void *)HAL_RX_MSDU_DESC_INFO_PTR_GET(msdu0); 774 } 775 776 static 777 void *hal_ent_mpdu_desc_info_6290(void *ent_ring_desc) 778 { 779 return (void *)HAL_ENT_MPDU_DESC_INFO(ent_ring_desc); 780 } 781 782 static 783 void *hal_dst_mpdu_desc_info_6290(void *dst_ring_desc) 784 { 785 return (void *)HAL_DST_MPDU_DESC_INFO(dst_ring_desc); 786 } 787 788 static 789 uint8_t hal_rx_get_fc_valid_6290(uint8_t *buf) 790 { 791 return HAL_RX_GET_FC_VALID(buf); 792 } 793 794 static uint8_t hal_rx_get_to_ds_flag_6290(uint8_t *buf) 795 { 796 return HAL_RX_GET_TO_DS_FLAG(buf); 797 } 798 799 static uint8_t hal_rx_get_mac_addr2_valid_6290(uint8_t *buf) 800 { 801 return HAL_RX_GET_MAC_ADDR2_VALID(buf); 802 } 803 804 static uint8_t hal_rx_get_filter_category_6290(uint8_t *buf) 805 { 806 return HAL_RX_GET_FILTER_CATEGORY(buf); 807 } 808 809 static uint32_t 810 hal_rx_get_ppdu_id_6290(uint8_t *buf) 811 { 812 return HAL_RX_GET_PPDU_ID(buf); 813 } 814 815 /** 816 * hal_reo_config_6290(): Set reo config parameters 817 * @soc: hal soc handle 818 * @reg_val: value to be set 819 * @reo_params: reo parameters 820 * 821 * Return: void 822 */ 823 static 824 void hal_reo_config_6290(struct hal_soc *soc, 825 uint32_t reg_val, 826 struct hal_reo_params *reo_params) 827 { 828 HAL_REO_R0_CONFIG(soc, reg_val, reo_params); 829 } 830 831 /** 832 * hal_rx_msdu_desc_info_get_ptr_6290() - Get msdu desc info ptr 833 * @msdu_details_ptr - Pointer to msdu_details_ptr 834 * 835 * Return - Pointer to rx_msdu_desc_info structure. 836 * 837 */ 838 static void *hal_rx_msdu_desc_info_get_ptr_6290(void *msdu_details_ptr) 839 { 840 return HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr); 841 } 842 843 /** 844 * hal_rx_link_desc_msdu0_ptr_6290 - Get pointer to rx_msdu details 845 * @link_desc - Pointer to link desc 846 * 847 * Return - Pointer to rx_msdu_details structure 848 * 849 */ 850 static void *hal_rx_link_desc_msdu0_ptr_6290(void *link_desc) 851 { 852 return HAL_RX_LINK_DESC_MSDU0_PTR(link_desc); 853 } 854 855 /** 856 * hal_rx_msdu_flow_idx_get_6290: API to get flow index 857 * from rx_msdu_end TLV 858 * @buf: pointer to the start of RX PKT TLV headers 859 * 860 * Return: flow index value from MSDU END TLV 861 */ 862 static inline uint32_t hal_rx_msdu_flow_idx_get_6290(uint8_t *buf) 863 { 864 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 865 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 866 867 return HAL_RX_MSDU_END_FLOW_IDX_GET(msdu_end); 868 } 869 870 /** 871 * hal_rx_msdu_flow_idx_invalid_6290: API to get flow index invalid 872 * from rx_msdu_end TLV 873 * @buf: pointer to the start of RX PKT TLV headers 874 * 875 * Return: flow index invalid value from MSDU END TLV 876 */ 877 static bool hal_rx_msdu_flow_idx_invalid_6290(uint8_t *buf) 878 { 879 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 880 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 881 882 return HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(msdu_end); 883 } 884 885 /** 886 * hal_rx_msdu_flow_idx_timeout_6290: API to get flow index timeout 887 * from rx_msdu_end TLV 888 * @buf: pointer to the start of RX PKT TLV headers 889 * 890 * Return: flow index timeout value from MSDU END TLV 891 */ 892 static bool hal_rx_msdu_flow_idx_timeout_6290(uint8_t *buf) 893 { 894 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 895 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 896 897 return HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(msdu_end); 898 } 899 900 /** 901 * hal_rx_msdu_fse_metadata_get_6290: API to get FSE metadata 902 * from rx_msdu_end TLV 903 * @buf: pointer to the start of RX PKT TLV headers 904 * 905 * Return: fse metadata value from MSDU END TLV 906 */ 907 static uint32_t hal_rx_msdu_fse_metadata_get_6290(uint8_t *buf) 908 { 909 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 910 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 911 912 return HAL_RX_MSDU_END_FSE_METADATA_GET(msdu_end); 913 } 914 915 /** 916 * hal_rx_msdu_cce_metadata_get_6290: API to get CCE metadata 917 * from rx_msdu_end TLV 918 * @buf: pointer to the start of RX PKT TLV headers 919 * 920 * Return: cce_metadata 921 */ 922 static uint16_t 923 hal_rx_msdu_cce_metadata_get_6290(uint8_t *buf) 924 { 925 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 926 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 927 928 return HAL_RX_MSDU_END_CCE_METADATA_GET(msdu_end); 929 } 930 931 /** 932 * hal_rx_msdu_get_flow_params_6290: API to get flow index, flow index invalid 933 * and flow index timeout from rx_msdu_end TLV 934 * @buf: pointer to the start of RX PKT TLV headers 935 * @flow_invalid: pointer to return value of flow_idx_valid 936 * @flow_timeout: pointer to return value of flow_idx_timeout 937 * @flow_index: pointer to return value of flow_idx 938 * 939 * Return: none 940 */ 941 static inline void 942 hal_rx_msdu_get_flow_params_6290(uint8_t *buf, 943 bool *flow_invalid, 944 bool *flow_timeout, 945 uint32_t *flow_index) 946 { 947 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 948 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 949 950 *flow_invalid = HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(msdu_end); 951 *flow_timeout = HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(msdu_end); 952 *flow_index = HAL_RX_MSDU_END_FLOW_IDX_GET(msdu_end); 953 } 954 955 /** 956 * hal_rx_tlv_get_tcp_chksum_6290() - API to get tcp checksum 957 * @buf: rx_tlv_hdr 958 * 959 * Return: tcp checksum 960 */ 961 static uint16_t 962 hal_rx_tlv_get_tcp_chksum_6290(uint8_t *buf) 963 { 964 return HAL_RX_TLV_GET_TCP_CHKSUM(buf); 965 } 966 967 /** 968 * hal_rx_get_rx_sequence_6290(): Function to retrieve rx sequence number 969 * @nbuf: Network buffer 970 * 971 * Return: rx sequence number 972 */ 973 static 974 uint16_t hal_rx_get_rx_sequence_6290(uint8_t *buf) 975 { 976 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 977 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 978 979 return HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info); 980 } 981 982 /** 983 * hal_get_window_address_6290(): Function to get hp/tp address 984 * @hal_soc: Pointer to hal_soc 985 * @addr: address offset of register 986 * 987 * Return: modified address offset of register 988 */ 989 static inline qdf_iomem_t hal_get_window_address_6290(struct hal_soc *hal_soc, 990 qdf_iomem_t addr) 991 { 992 return addr; 993 } 994 995 static 996 void hal_compute_reo_remap_ix2_ix3_6290(uint32_t *ring, uint32_t num_rings, 997 uint32_t *remap1, uint32_t *remap2) 998 { 999 switch (num_rings) { 1000 case 3: 1001 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 1002 HAL_REO_REMAP_IX2(ring[1], 17) | 1003 HAL_REO_REMAP_IX2(ring[2], 18) | 1004 HAL_REO_REMAP_IX2(ring[0], 19) | 1005 HAL_REO_REMAP_IX2(ring[1], 20) | 1006 HAL_REO_REMAP_IX2(ring[2], 21) | 1007 HAL_REO_REMAP_IX2(ring[0], 22) | 1008 HAL_REO_REMAP_IX2(ring[1], 23); 1009 1010 *remap2 = HAL_REO_REMAP_IX3(ring[2], 24) | 1011 HAL_REO_REMAP_IX3(ring[0], 25) | 1012 HAL_REO_REMAP_IX3(ring[1], 26) | 1013 HAL_REO_REMAP_IX3(ring[2], 27) | 1014 HAL_REO_REMAP_IX3(ring[0], 28) | 1015 HAL_REO_REMAP_IX3(ring[1], 29) | 1016 HAL_REO_REMAP_IX3(ring[2], 30) | 1017 HAL_REO_REMAP_IX3(ring[0], 31); 1018 break; 1019 case 4: 1020 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 1021 HAL_REO_REMAP_IX2(ring[1], 17) | 1022 HAL_REO_REMAP_IX2(ring[2], 18) | 1023 HAL_REO_REMAP_IX2(ring[3], 19) | 1024 HAL_REO_REMAP_IX2(ring[0], 20) | 1025 HAL_REO_REMAP_IX2(ring[1], 21) | 1026 HAL_REO_REMAP_IX2(ring[2], 22) | 1027 HAL_REO_REMAP_IX2(ring[3], 23); 1028 1029 *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) | 1030 HAL_REO_REMAP_IX3(ring[1], 25) | 1031 HAL_REO_REMAP_IX3(ring[2], 26) | 1032 HAL_REO_REMAP_IX3(ring[3], 27) | 1033 HAL_REO_REMAP_IX3(ring[0], 28) | 1034 HAL_REO_REMAP_IX3(ring[1], 29) | 1035 HAL_REO_REMAP_IX3(ring[2], 30) | 1036 HAL_REO_REMAP_IX3(ring[3], 31); 1037 break; 1038 } 1039 } 1040 1041 struct hal_hw_txrx_ops qca6290_hal_hw_txrx_ops = { 1042 /* init and setup */ 1043 hal_srng_dst_hw_init_generic, 1044 hal_srng_src_hw_init_generic, 1045 hal_get_hw_hptp_generic, 1046 hal_reo_setup_generic, 1047 hal_setup_link_idle_list_generic, 1048 hal_get_window_address_6290, 1049 NULL, 1050 1051 /* tx */ 1052 hal_tx_desc_set_dscp_tid_table_id_6290, 1053 hal_tx_set_dscp_tid_map_6290, 1054 hal_tx_update_dscp_tid_6290, 1055 hal_tx_desc_set_lmac_id_6290, 1056 hal_tx_desc_set_buf_addr_generic, 1057 hal_tx_desc_set_search_type_generic, 1058 hal_tx_desc_set_search_index_generic, 1059 hal_tx_desc_set_cache_set_num_generic, 1060 hal_tx_comp_get_status_generic, 1061 hal_tx_comp_get_release_reason_generic, 1062 hal_get_wbm_internal_error_generic, 1063 hal_tx_desc_set_mesh_en_6290, 1064 hal_tx_init_cmd_credit_ring_6290, 1065 1066 /* rx */ 1067 hal_rx_msdu_start_nss_get_6290, 1068 hal_rx_mon_hw_desc_get_mpdu_status_6290, 1069 hal_rx_get_tlv_6290, 1070 hal_rx_proc_phyrx_other_receive_info_tlv_6290, 1071 hal_rx_dump_msdu_start_tlv_6290, 1072 hal_rx_dump_msdu_end_tlv_6290, 1073 hal_get_link_desc_size_6290, 1074 hal_rx_mpdu_start_tid_get_6290, 1075 hal_rx_msdu_start_reception_type_get_6290, 1076 hal_rx_msdu_end_da_idx_get_6290, 1077 hal_rx_msdu_desc_info_get_ptr_6290, 1078 hal_rx_link_desc_msdu0_ptr_6290, 1079 hal_reo_status_get_header_6290, 1080 hal_rx_status_get_tlv_info_generic, 1081 hal_rx_wbm_err_info_get_generic, 1082 hal_rx_dump_mpdu_start_tlv_generic, 1083 1084 hal_tx_set_pcp_tid_map_generic, 1085 hal_tx_update_pcp_tid_generic, 1086 hal_tx_update_tidmap_prty_generic, 1087 hal_rx_get_rx_fragment_number_6290, 1088 hal_rx_msdu_end_da_is_mcbc_get_6290, 1089 hal_rx_msdu_end_sa_is_valid_get_6290, 1090 hal_rx_msdu_end_sa_idx_get_6290, 1091 hal_rx_desc_is_first_msdu_6290, 1092 hal_rx_msdu_end_l3_hdr_padding_get_6290, 1093 hal_rx_encryption_info_valid_6290, 1094 hal_rx_print_pn_6290, 1095 hal_rx_msdu_end_first_msdu_get_6290, 1096 hal_rx_msdu_end_da_is_valid_get_6290, 1097 hal_rx_msdu_end_last_msdu_get_6290, 1098 hal_rx_get_mpdu_mac_ad4_valid_6290, 1099 hal_rx_mpdu_start_sw_peer_id_get_6290, 1100 hal_rx_mpdu_get_to_ds_6290, 1101 hal_rx_mpdu_get_fr_ds_6290, 1102 hal_rx_get_mpdu_frame_control_valid_6290, 1103 hal_rx_mpdu_get_addr1_6290, 1104 hal_rx_mpdu_get_addr2_6290, 1105 hal_rx_mpdu_get_addr3_6290, 1106 hal_rx_mpdu_get_addr4_6290, 1107 hal_rx_get_mpdu_sequence_control_valid_6290, 1108 hal_rx_is_unicast_6290, 1109 hal_rx_tid_get_6290, 1110 hal_rx_hw_desc_get_ppduid_get_6290, 1111 hal_rx_mpdu_start_mpdu_qos_control_valid_get_6290, 1112 hal_rx_msdu_end_sa_sw_peer_id_get_6290, 1113 hal_rx_msdu0_buffer_addr_lsb_6290, 1114 hal_rx_msdu_desc_info_ptr_get_6290, 1115 hal_ent_mpdu_desc_info_6290, 1116 hal_dst_mpdu_desc_info_6290, 1117 hal_rx_get_fc_valid_6290, 1118 hal_rx_get_to_ds_flag_6290, 1119 hal_rx_get_mac_addr2_valid_6290, 1120 hal_rx_get_filter_category_6290, 1121 hal_rx_get_ppdu_id_6290, 1122 hal_reo_config_6290, 1123 hal_rx_msdu_flow_idx_get_6290, 1124 hal_rx_msdu_flow_idx_invalid_6290, 1125 hal_rx_msdu_flow_idx_timeout_6290, 1126 hal_rx_msdu_fse_metadata_get_6290, 1127 hal_rx_msdu_cce_metadata_get_6290, 1128 hal_rx_msdu_get_flow_params_6290, 1129 hal_rx_tlv_get_tcp_chksum_6290, 1130 hal_rx_get_rx_sequence_6290, 1131 NULL, 1132 NULL, 1133 /* rx - msdu end fast path info fields */ 1134 hal_rx_msdu_packet_metadata_get_generic, 1135 NULL, 1136 NULL, 1137 NULL, 1138 NULL, 1139 NULL, 1140 NULL, 1141 NULL, 1142 NULL, 1143 NULL, 1144 /* rx - TLV struct offsets */ 1145 hal_rx_msdu_end_offset_get_generic, 1146 hal_rx_attn_offset_get_generic, 1147 hal_rx_msdu_start_offset_get_generic, 1148 hal_rx_mpdu_start_offset_get_generic, 1149 hal_rx_mpdu_end_offset_get_generic, 1150 NULL, 1151 hal_compute_reo_remap_ix2_ix3_6290, 1152 NULL, 1153 NULL, 1154 NULL, 1155 NULL 1156 }; 1157 1158 struct hal_hw_srng_config hw_srng_table_6290[] = { 1159 /* TODO: max_rings can populated by querying HW capabilities */ 1160 { /* REO_DST */ 1161 .start_ring_id = HAL_SRNG_REO2SW1, 1162 .max_rings = 4, 1163 .entry_size = sizeof(struct reo_destination_ring) >> 2, 1164 .lmac_ring = FALSE, 1165 .ring_dir = HAL_SRNG_DST_RING, 1166 .reg_start = { 1167 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR( 1168 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1169 HWIO_REO_R2_REO2SW1_RING_HP_ADDR( 1170 SEQ_WCSS_UMAC_REO_REG_OFFSET) 1171 }, 1172 .reg_size = { 1173 HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(0) - 1174 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(0), 1175 HWIO_REO_R2_REO2SW2_RING_HP_ADDR(0) - 1176 HWIO_REO_R2_REO2SW1_RING_HP_ADDR(0), 1177 }, 1178 .max_size = HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_BMSK >> 1179 HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_SHFT, 1180 }, 1181 { /* REO_EXCEPTION */ 1182 /* Designating REO2TCL ring as exception ring. This ring is 1183 * similar to other REO2SW rings though it is named as REO2TCL. 1184 * Any of theREO2SW rings can be used as exception ring. 1185 */ 1186 .start_ring_id = HAL_SRNG_REO2TCL, 1187 .max_rings = 1, 1188 .entry_size = sizeof(struct reo_destination_ring) >> 2, 1189 .lmac_ring = FALSE, 1190 .ring_dir = HAL_SRNG_DST_RING, 1191 .reg_start = { 1192 HWIO_REO_R0_REO2TCL_RING_BASE_LSB_ADDR( 1193 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1194 HWIO_REO_R2_REO2TCL_RING_HP_ADDR( 1195 SEQ_WCSS_UMAC_REO_REG_OFFSET) 1196 }, 1197 /* Single ring - provide ring size if multiple rings of this 1198 * type are supported 1199 */ 1200 .reg_size = {}, 1201 .max_size = HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_BMSK >> 1202 HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_SHFT, 1203 }, 1204 { /* REO_REINJECT */ 1205 .start_ring_id = HAL_SRNG_SW2REO, 1206 .max_rings = 1, 1207 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 1208 .lmac_ring = FALSE, 1209 .ring_dir = HAL_SRNG_SRC_RING, 1210 .reg_start = { 1211 HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR( 1212 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1213 HWIO_REO_R2_SW2REO_RING_HP_ADDR( 1214 SEQ_WCSS_UMAC_REO_REG_OFFSET) 1215 }, 1216 /* Single ring - provide ring size if multiple rings of this 1217 * type are supported 1218 */ 1219 .reg_size = {}, 1220 .max_size = HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_BMSK >> 1221 HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_SHFT, 1222 }, 1223 { /* REO_CMD */ 1224 .start_ring_id = HAL_SRNG_REO_CMD, 1225 .max_rings = 1, 1226 .entry_size = (sizeof(struct tlv_32_hdr) + 1227 sizeof(struct reo_get_queue_stats)) >> 2, 1228 .lmac_ring = FALSE, 1229 .ring_dir = HAL_SRNG_SRC_RING, 1230 .reg_start = { 1231 HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR( 1232 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1233 HWIO_REO_R2_REO_CMD_RING_HP_ADDR( 1234 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1235 }, 1236 /* Single ring - provide ring size if multiple rings of this 1237 * type are supported 1238 */ 1239 .reg_size = {}, 1240 .max_size = HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_BMSK >> 1241 HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_SHFT, 1242 }, 1243 { /* REO_STATUS */ 1244 .start_ring_id = HAL_SRNG_REO_STATUS, 1245 .max_rings = 1, 1246 .entry_size = (sizeof(struct tlv_32_hdr) + 1247 sizeof(struct reo_get_queue_stats_status)) >> 2, 1248 .lmac_ring = FALSE, 1249 .ring_dir = HAL_SRNG_DST_RING, 1250 .reg_start = { 1251 HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR( 1252 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1253 HWIO_REO_R2_REO_STATUS_RING_HP_ADDR( 1254 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1255 }, 1256 /* Single ring - provide ring size if multiple rings of this 1257 * type are supported 1258 */ 1259 .reg_size = {}, 1260 .max_size = 1261 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> 1262 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, 1263 }, 1264 { /* TCL_DATA */ 1265 .start_ring_id = HAL_SRNG_SW2TCL1, 1266 .max_rings = 3, 1267 .entry_size = (sizeof(struct tlv_32_hdr) + 1268 sizeof(struct tcl_data_cmd)) >> 2, 1269 .lmac_ring = FALSE, 1270 .ring_dir = HAL_SRNG_SRC_RING, 1271 .reg_start = { 1272 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR( 1273 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1274 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR( 1275 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1276 }, 1277 .reg_size = { 1278 HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(0) - 1279 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(0), 1280 HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(0) - 1281 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(0), 1282 }, 1283 .max_size = HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK >> 1284 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT, 1285 }, 1286 { /* TCL_CMD */ 1287 .start_ring_id = HAL_SRNG_SW2TCL_CMD, 1288 .max_rings = 1, 1289 .entry_size = (sizeof(struct tlv_32_hdr) + 1290 sizeof(struct tcl_gse_cmd)) >> 2, 1291 .lmac_ring = FALSE, 1292 .ring_dir = HAL_SRNG_SRC_RING, 1293 .reg_start = { 1294 HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_ADDR( 1295 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1296 HWIO_TCL_R2_SW2TCL_CMD_RING_HP_ADDR( 1297 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1298 }, 1299 /* Single ring - provide ring size if multiple rings of this 1300 * type are supported 1301 */ 1302 .reg_size = {}, 1303 .max_size = 1304 HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RING_SIZE_BMSK >> 1305 HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RING_SIZE_SHFT, 1306 }, 1307 { /* TCL_STATUS */ 1308 .start_ring_id = HAL_SRNG_TCL_STATUS, 1309 .max_rings = 1, 1310 .entry_size = (sizeof(struct tlv_32_hdr) + 1311 sizeof(struct tcl_status_ring)) >> 2, 1312 .lmac_ring = FALSE, 1313 .ring_dir = HAL_SRNG_DST_RING, 1314 .reg_start = { 1315 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR( 1316 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1317 HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR( 1318 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1319 }, 1320 /* Single ring - provide ring size if multiple rings of this 1321 * type are supported 1322 */ 1323 .reg_size = {}, 1324 .max_size = 1325 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_BMSK >> 1326 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_SHFT, 1327 }, 1328 { /* CE_SRC */ 1329 .start_ring_id = HAL_SRNG_CE_0_SRC, 1330 .max_rings = 12, 1331 .entry_size = sizeof(struct ce_src_desc) >> 2, 1332 .lmac_ring = FALSE, 1333 .ring_dir = HAL_SRNG_SRC_RING, 1334 .reg_start = { 1335 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR( 1336 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET), 1337 HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR( 1338 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET), 1339 }, 1340 .reg_size = { 1341 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET - 1342 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET, 1343 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET - 1344 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET, 1345 }, 1346 .max_size = 1347 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >> 1348 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT, 1349 }, 1350 { /* CE_DST */ 1351 .start_ring_id = HAL_SRNG_CE_0_DST, 1352 .max_rings = 12, 1353 .entry_size = 8 >> 2, 1354 /*TODO: entry_size above should actually be 1355 * sizeof(struct ce_dst_desc) >> 2, but couldn't find definition 1356 * of struct ce_dst_desc in HW header files 1357 */ 1358 .lmac_ring = FALSE, 1359 .ring_dir = HAL_SRNG_SRC_RING, 1360 .reg_start = { 1361 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR( 1362 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 1363 HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR( 1364 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 1365 }, 1366 .reg_size = { 1367 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 1368 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 1369 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 1370 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 1371 }, 1372 .max_size = 1373 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >> 1374 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT, 1375 }, 1376 { /* CE_DST_STATUS */ 1377 .start_ring_id = HAL_SRNG_CE_0_DST_STATUS, 1378 .max_rings = 12, 1379 .entry_size = sizeof(struct ce_stat_desc) >> 2, 1380 .lmac_ring = FALSE, 1381 .ring_dir = HAL_SRNG_DST_RING, 1382 .reg_start = { 1383 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR( 1384 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 1385 HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR( 1386 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 1387 }, 1388 /* TODO: check destination status ring registers */ 1389 .reg_size = { 1390 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 1391 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 1392 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 1393 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 1394 }, 1395 .max_size = 1396 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> 1397 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, 1398 }, 1399 { /* WBM_IDLE_LINK */ 1400 .start_ring_id = HAL_SRNG_WBM_IDLE_LINK, 1401 .max_rings = 1, 1402 .entry_size = sizeof(struct wbm_link_descriptor_ring) >> 2, 1403 .lmac_ring = FALSE, 1404 .ring_dir = HAL_SRNG_SRC_RING, 1405 .reg_start = { 1406 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1407 HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1408 }, 1409 /* Single ring - provide ring size if multiple rings of this 1410 * type are supported 1411 */ 1412 .reg_size = {}, 1413 .max_size = 1414 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_BMSK >> 1415 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_SHFT, 1416 }, 1417 { /* SW2WBM_RELEASE */ 1418 .start_ring_id = HAL_SRNG_WBM_SW_RELEASE, 1419 .max_rings = 1, 1420 .entry_size = sizeof(struct wbm_release_ring) >> 2, 1421 .lmac_ring = FALSE, 1422 .ring_dir = HAL_SRNG_SRC_RING, 1423 .reg_start = { 1424 HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1425 HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1426 }, 1427 /* Single ring - provide ring size if multiple rings of this 1428 * type are supported 1429 */ 1430 .reg_size = {}, 1431 .max_size = 1432 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> 1433 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, 1434 }, 1435 { /* WBM2SW_RELEASE */ 1436 .start_ring_id = HAL_SRNG_WBM2SW0_RELEASE, 1437 .max_rings = 4, 1438 .entry_size = sizeof(struct wbm_release_ring) >> 2, 1439 .lmac_ring = FALSE, 1440 .ring_dir = HAL_SRNG_DST_RING, 1441 .reg_start = { 1442 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1443 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1444 }, 1445 .reg_size = { 1446 HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) - 1447 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1448 HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) - 1449 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1450 }, 1451 .max_size = 1452 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> 1453 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, 1454 }, 1455 { /* RXDMA_BUF */ 1456 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA0_BUF0, 1457 #ifdef IPA_OFFLOAD 1458 .max_rings = 3, 1459 #else 1460 .max_rings = 2, 1461 #endif 1462 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 1463 .lmac_ring = TRUE, 1464 .ring_dir = HAL_SRNG_SRC_RING, 1465 /* reg_start is not set because LMAC rings are not accessed 1466 * from host 1467 */ 1468 .reg_start = {}, 1469 .reg_size = {}, 1470 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1471 }, 1472 { /* RXDMA_DST */ 1473 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW0, 1474 .max_rings = 1, 1475 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 1476 .lmac_ring = TRUE, 1477 .ring_dir = HAL_SRNG_DST_RING, 1478 /* reg_start is not set because LMAC rings are not accessed 1479 * from host 1480 */ 1481 .reg_start = {}, 1482 .reg_size = {}, 1483 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1484 }, 1485 { /* RXDMA_MONITOR_BUF */ 1486 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA2_BUF, 1487 .max_rings = 1, 1488 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 1489 .lmac_ring = TRUE, 1490 .ring_dir = HAL_SRNG_SRC_RING, 1491 /* reg_start is not set because LMAC rings are not accessed 1492 * from host 1493 */ 1494 .reg_start = {}, 1495 .reg_size = {}, 1496 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1497 }, 1498 { /* RXDMA_MONITOR_STATUS */ 1499 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_STATBUF, 1500 .max_rings = 1, 1501 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 1502 .lmac_ring = TRUE, 1503 .ring_dir = HAL_SRNG_SRC_RING, 1504 /* reg_start is not set because LMAC rings are not accessed 1505 * from host 1506 */ 1507 .reg_start = {}, 1508 .reg_size = {}, 1509 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1510 }, 1511 { /* RXDMA_MONITOR_DST */ 1512 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW1, 1513 .max_rings = 1, 1514 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 1515 .lmac_ring = TRUE, 1516 .ring_dir = HAL_SRNG_DST_RING, 1517 /* reg_start is not set because LMAC rings are not accessed 1518 * from host 1519 */ 1520 .reg_start = {}, 1521 .reg_size = {}, 1522 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1523 }, 1524 { /* RXDMA_MONITOR_DESC */ 1525 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_DESC, 1526 .max_rings = 1, 1527 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 1528 .lmac_ring = TRUE, 1529 .ring_dir = HAL_SRNG_SRC_RING, 1530 /* reg_start is not set because LMAC rings are not accessed 1531 * from host 1532 */ 1533 .reg_start = {}, 1534 .reg_size = {}, 1535 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1536 }, 1537 { /* DIR_BUF_RX_DMA_SRC */ 1538 .start_ring_id = HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING, 1539 .max_rings = 1, 1540 .entry_size = 2, 1541 .lmac_ring = TRUE, 1542 .ring_dir = HAL_SRNG_SRC_RING, 1543 /* reg_start is not set because LMAC rings are not accessed 1544 * from host 1545 */ 1546 .reg_start = {}, 1547 .reg_size = {}, 1548 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1549 }, 1550 #ifdef WLAN_FEATURE_CIF_CFR 1551 { /* WIFI_POS_SRC */ 1552 .start_ring_id = HAL_SRNG_WIFI_POS_SRC_DMA_RING, 1553 .max_rings = 1, 1554 .entry_size = sizeof(wmi_oem_dma_buf_release_entry) >> 2, 1555 .lmac_ring = TRUE, 1556 .ring_dir = HAL_SRNG_SRC_RING, 1557 /* reg_start is not set because LMAC rings are not accessed 1558 * from host 1559 */ 1560 .reg_start = {}, 1561 .reg_size = {}, 1562 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1563 }, 1564 #endif 1565 }; 1566 1567 int32_t hal_hw_reg_offset_qca6290[] = { 1568 /* dst */ 1569 REG_OFFSET(DST, HP), 1570 REG_OFFSET(DST, TP), 1571 REG_OFFSET(DST, ID), 1572 REG_OFFSET(DST, MISC), 1573 REG_OFFSET(DST, HP_ADDR_LSB), 1574 REG_OFFSET(DST, HP_ADDR_MSB), 1575 REG_OFFSET(DST, MSI1_BASE_LSB), 1576 REG_OFFSET(DST, MSI1_BASE_MSB), 1577 REG_OFFSET(DST, MSI1_DATA), 1578 REG_OFFSET(DST, BASE_LSB), 1579 REG_OFFSET(DST, BASE_MSB), 1580 REG_OFFSET(DST, PRODUCER_INT_SETUP), 1581 /* src */ 1582 REG_OFFSET(SRC, HP), 1583 REG_OFFSET(SRC, TP), 1584 REG_OFFSET(SRC, ID), 1585 REG_OFFSET(SRC, MISC), 1586 REG_OFFSET(SRC, TP_ADDR_LSB), 1587 REG_OFFSET(SRC, TP_ADDR_MSB), 1588 REG_OFFSET(SRC, MSI1_BASE_LSB), 1589 REG_OFFSET(SRC, MSI1_BASE_MSB), 1590 REG_OFFSET(SRC, MSI1_DATA), 1591 REG_OFFSET(SRC, BASE_LSB), 1592 REG_OFFSET(SRC, BASE_MSB), 1593 REG_OFFSET(SRC, CONSUMER_INT_SETUP_IX0), 1594 REG_OFFSET(SRC, CONSUMER_INT_SETUP_IX1), 1595 }; 1596 1597 /** 1598 * hal_qca6290_attach() - Attach 6290 target specific hal_soc ops, 1599 * offset and srng table 1600 */ 1601 void hal_qca6290_attach(struct hal_soc *hal_soc) 1602 { 1603 hal_soc->hw_srng_table = hw_srng_table_6290; 1604 hal_soc->hal_hw_reg_offset = hal_hw_reg_offset_qca6290; 1605 hal_soc->ops = &qca6290_hal_hw_txrx_ops; 1606 } 1607