1 /* 2 * Copyright (c) 2016-2018 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 #include "qdf_types.h" 19 #include "qdf_util.h" 20 #include "qdf_types.h" 21 #include "qdf_lock.h" 22 #include "qdf_mem.h" 23 #include "qdf_nbuf.h" 24 #include "hal_hw_headers.h" 25 #include "hal_internal.h" 26 #include "hal_api.h" 27 #include "target_type.h" 28 #include "wcss_version.h" 29 #include "qdf_module.h" 30 31 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_OFFSET \ 32 RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_OFFSET 33 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_MASK \ 34 RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_MASK 35 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_LSB \ 36 RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_LSB 37 #define UNIFIED_PHYRX_HT_SIG_0_HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS_OFFSET \ 38 PHYRX_HT_SIG_0_HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS_OFFSET 39 #define UNIFIED_PHYRX_L_SIG_B_0_L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS_OFFSET \ 40 PHYRX_L_SIG_B_0_L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS_OFFSET 41 #define UNIFIED_PHYRX_L_SIG_A_0_L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS_OFFSET \ 42 PHYRX_L_SIG_A_0_L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS_OFFSET 43 #define UNIFIED_PHYRX_VHT_SIG_A_0_VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS_OFFSET \ 44 PHYRX_VHT_SIG_A_0_VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS_OFFSET 45 #define UNIFIED_PHYRX_HE_SIG_A_SU_0_HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS_OFFSET \ 46 PHYRX_HE_SIG_A_SU_0_HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS_OFFSET 47 #define UNIFIED_PHYRX_HE_SIG_A_MU_DL_0_HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_OFFSET \ 48 PHYRX_HE_SIG_A_MU_DL_0_HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_OFFSET 49 #define UNIFIED_PHYRX_HE_SIG_B1_MU_0_HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_OFFSET \ 50 PHYRX_HE_SIG_B1_MU_0_HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_OFFSET 51 #define UNIFIED_PHYRX_HE_SIG_B2_MU_0_HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_OFFSET \ 52 PHYRX_HE_SIG_B2_MU_0_HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_OFFSET 53 #define UNIFIED_PHYRX_HE_SIG_B2_OFDMA_0_HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_OFFSET \ 54 PHYRX_HE_SIG_B2_OFDMA_0_HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_OFFSET 55 #define UNIFIED_PHYRX_RSSI_LEGACY_3_RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS_OFFSET \ 56 PHYRX_RSSI_LEGACY_3_RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS_OFFSET 57 #define UNIFIED_RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET \ 58 RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET 59 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 60 RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET 61 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ 62 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET 63 #define UNIFIED_RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 64 RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET 65 #define UNIFIED_REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 66 REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET 67 #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC \ 68 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER 69 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ 70 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET 71 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 72 RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET 73 #define UNIFIED_TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 74 TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET 75 #define UNIFIED_TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 76 TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET 77 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET \ 78 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET 79 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB \ 80 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB 81 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK \ 82 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK 83 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB \ 84 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB 85 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK \ 86 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK 87 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB \ 88 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB 89 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK \ 90 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK 91 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB \ 92 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB 93 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK \ 94 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK 95 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB \ 96 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB 97 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK \ 98 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK 99 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_MASK \ 100 WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_MASK 101 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_OFFSET \ 102 WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_OFFSET 103 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_LSB \ 104 WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_LSB 105 106 #include "hal_6290_tx.h" 107 #include "hal_6290_rx.h" 108 #include <hal_generic_api.h> 109 #include <hal_wbm.h> 110 111 struct hal_hw_txrx_ops qca6290_hal_hw_txrx_ops = { 112 /* init and setup */ 113 hal_srng_dst_hw_init_generic, 114 hal_srng_src_hw_init_generic, 115 hal_reo_setup_generic, 116 hal_setup_link_idle_list_generic, 117 118 /* tx */ 119 hal_tx_desc_set_dscp_tid_table_id_6290, 120 hal_tx_set_dscp_tid_map_6290, 121 hal_tx_update_dscp_tid_6290, 122 hal_tx_desc_set_lmac_id_6290, 123 hal_tx_desc_set_buf_addr_generic, 124 hal_tx_comp_get_status_generic, 125 126 /* rx */ 127 hal_rx_msdu_start_nss_get_6290, 128 hal_rx_mon_hw_desc_get_mpdu_status_6290, 129 hal_rx_get_tlv_6290, 130 hal_rx_proc_phyrx_other_receive_info_tlv_6290, 131 hal_rx_dump_msdu_start_tlv_6290, 132 hal_rx_dump_msdu_end_tlv_6290, 133 hal_get_link_desc_size_6290, 134 hal_rx_mpdu_start_tid_get_6290, 135 hal_rx_msdu_start_reception_type_get_6290, 136 hal_rx_msdu_end_da_idx_get_6290, 137 hal_rx_msdu_desc_info_get_ptr_generic, 138 hal_rx_link_desc_msdu0_ptr_generic, 139 hal_reo_status_get_header_generic, 140 hal_rx_status_get_tlv_info_generic, 141 }; 142 143 struct hal_hw_srng_config hw_srng_table_6290[] = { 144 /* TODO: max_rings can populated by querying HW capabilities */ 145 { /* REO_DST */ 146 .start_ring_id = HAL_SRNG_REO2SW1, 147 .max_rings = 4, 148 .entry_size = sizeof(struct reo_destination_ring) >> 2, 149 .lmac_ring = FALSE, 150 .ring_dir = HAL_SRNG_DST_RING, 151 .reg_start = { 152 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR( 153 SEQ_WCSS_UMAC_REO_REG_OFFSET), 154 HWIO_REO_R2_REO2SW1_RING_HP_ADDR( 155 SEQ_WCSS_UMAC_REO_REG_OFFSET) 156 }, 157 .reg_size = { 158 HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(0) - 159 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(0), 160 HWIO_REO_R2_REO2SW2_RING_HP_ADDR(0) - 161 HWIO_REO_R2_REO2SW1_RING_HP_ADDR(0), 162 }, 163 .max_size = HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_BMSK >> 164 HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_SHFT, 165 }, 166 { /* REO_EXCEPTION */ 167 /* Designating REO2TCL ring as exception ring. This ring is 168 * similar to other REO2SW rings though it is named as REO2TCL. 169 * Any of theREO2SW rings can be used as exception ring. 170 */ 171 .start_ring_id = HAL_SRNG_REO2TCL, 172 .max_rings = 1, 173 .entry_size = sizeof(struct reo_destination_ring) >> 2, 174 .lmac_ring = FALSE, 175 .ring_dir = HAL_SRNG_DST_RING, 176 .reg_start = { 177 HWIO_REO_R0_REO2TCL_RING_BASE_LSB_ADDR( 178 SEQ_WCSS_UMAC_REO_REG_OFFSET), 179 HWIO_REO_R2_REO2TCL_RING_HP_ADDR( 180 SEQ_WCSS_UMAC_REO_REG_OFFSET) 181 }, 182 /* Single ring - provide ring size if multiple rings of this 183 * type are supported 184 */ 185 .reg_size = {}, 186 .max_size = HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_BMSK >> 187 HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_SHFT, 188 }, 189 { /* REO_REINJECT */ 190 .start_ring_id = HAL_SRNG_SW2REO, 191 .max_rings = 1, 192 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 193 .lmac_ring = FALSE, 194 .ring_dir = HAL_SRNG_SRC_RING, 195 .reg_start = { 196 HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR( 197 SEQ_WCSS_UMAC_REO_REG_OFFSET), 198 HWIO_REO_R2_SW2REO_RING_HP_ADDR( 199 SEQ_WCSS_UMAC_REO_REG_OFFSET) 200 }, 201 /* Single ring - provide ring size if multiple rings of this 202 * type are supported 203 */ 204 .reg_size = {}, 205 .max_size = HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_BMSK >> 206 HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_SHFT, 207 }, 208 { /* REO_CMD */ 209 .start_ring_id = HAL_SRNG_REO_CMD, 210 .max_rings = 1, 211 .entry_size = (sizeof(struct tlv_32_hdr) + 212 sizeof(struct reo_get_queue_stats)) >> 2, 213 .lmac_ring = FALSE, 214 .ring_dir = HAL_SRNG_SRC_RING, 215 .reg_start = { 216 HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR( 217 SEQ_WCSS_UMAC_REO_REG_OFFSET), 218 HWIO_REO_R2_REO_CMD_RING_HP_ADDR( 219 SEQ_WCSS_UMAC_REO_REG_OFFSET), 220 }, 221 /* Single ring - provide ring size if multiple rings of this 222 * type are supported 223 */ 224 .reg_size = {}, 225 .max_size = HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_BMSK >> 226 HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_SHFT, 227 }, 228 { /* REO_STATUS */ 229 .start_ring_id = HAL_SRNG_REO_STATUS, 230 .max_rings = 1, 231 .entry_size = (sizeof(struct tlv_32_hdr) + 232 sizeof(struct reo_get_queue_stats_status)) >> 2, 233 .lmac_ring = FALSE, 234 .ring_dir = HAL_SRNG_DST_RING, 235 .reg_start = { 236 HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR( 237 SEQ_WCSS_UMAC_REO_REG_OFFSET), 238 HWIO_REO_R2_REO_STATUS_RING_HP_ADDR( 239 SEQ_WCSS_UMAC_REO_REG_OFFSET), 240 }, 241 /* Single ring - provide ring size if multiple rings of this 242 * type are supported 243 */ 244 .reg_size = {}, 245 .max_size = 246 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> 247 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, 248 }, 249 { /* TCL_DATA */ 250 .start_ring_id = HAL_SRNG_SW2TCL1, 251 .max_rings = 3, 252 .entry_size = (sizeof(struct tlv_32_hdr) + 253 sizeof(struct tcl_data_cmd)) >> 2, 254 .lmac_ring = FALSE, 255 .ring_dir = HAL_SRNG_SRC_RING, 256 .reg_start = { 257 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR( 258 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 259 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR( 260 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 261 }, 262 .reg_size = { 263 HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(0) - 264 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(0), 265 HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(0) - 266 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(0), 267 }, 268 .max_size = HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK >> 269 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT, 270 }, 271 { /* TCL_CMD */ 272 .start_ring_id = HAL_SRNG_SW2TCL_CMD, 273 .max_rings = 1, 274 .entry_size = (sizeof(struct tlv_32_hdr) + 275 sizeof(struct tcl_gse_cmd)) >> 2, 276 .lmac_ring = FALSE, 277 .ring_dir = HAL_SRNG_SRC_RING, 278 .reg_start = { 279 HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_ADDR( 280 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 281 HWIO_TCL_R2_SW2TCL_CMD_RING_HP_ADDR( 282 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 283 }, 284 /* Single ring - provide ring size if multiple rings of this 285 * type are supported 286 */ 287 .reg_size = {}, 288 .max_size = 289 HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RING_SIZE_BMSK >> 290 HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RING_SIZE_SHFT, 291 }, 292 { /* TCL_STATUS */ 293 .start_ring_id = HAL_SRNG_TCL_STATUS, 294 .max_rings = 1, 295 .entry_size = (sizeof(struct tlv_32_hdr) + 296 sizeof(struct tcl_status_ring)) >> 2, 297 .lmac_ring = FALSE, 298 .ring_dir = HAL_SRNG_DST_RING, 299 .reg_start = { 300 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR( 301 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 302 HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR( 303 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 304 }, 305 /* Single ring - provide ring size if multiple rings of this 306 * type are supported 307 */ 308 .reg_size = {}, 309 .max_size = 310 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_BMSK >> 311 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_SHFT, 312 }, 313 { /* CE_SRC */ 314 .start_ring_id = HAL_SRNG_CE_0_SRC, 315 .max_rings = 12, 316 .entry_size = sizeof(struct ce_src_desc) >> 2, 317 .lmac_ring = FALSE, 318 .ring_dir = HAL_SRNG_SRC_RING, 319 .reg_start = { 320 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR( 321 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET), 322 HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR( 323 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET), 324 }, 325 .reg_size = { 326 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET - 327 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET, 328 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET - 329 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET, 330 }, 331 .max_size = 332 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >> 333 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT, 334 }, 335 { /* CE_DST */ 336 .start_ring_id = HAL_SRNG_CE_0_DST, 337 .max_rings = 12, 338 .entry_size = 8 >> 2, 339 /*TODO: entry_size above should actually be 340 * sizeof(struct ce_dst_desc) >> 2, but couldn't find definition 341 * of struct ce_dst_desc in HW header files 342 */ 343 .lmac_ring = FALSE, 344 .ring_dir = HAL_SRNG_SRC_RING, 345 .reg_start = { 346 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR( 347 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 348 HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR( 349 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 350 }, 351 .reg_size = { 352 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 353 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 354 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 355 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 356 }, 357 .max_size = 358 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >> 359 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT, 360 }, 361 { /* CE_DST_STATUS */ 362 .start_ring_id = HAL_SRNG_CE_0_DST_STATUS, 363 .max_rings = 12, 364 .entry_size = sizeof(struct ce_stat_desc) >> 2, 365 .lmac_ring = FALSE, 366 .ring_dir = HAL_SRNG_DST_RING, 367 .reg_start = { 368 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR( 369 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 370 HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR( 371 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 372 }, 373 /* TODO: check destination status ring registers */ 374 .reg_size = { 375 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 376 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 377 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 378 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 379 }, 380 .max_size = 381 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> 382 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, 383 }, 384 { /* WBM_IDLE_LINK */ 385 .start_ring_id = HAL_SRNG_WBM_IDLE_LINK, 386 .max_rings = 1, 387 .entry_size = sizeof(struct wbm_link_descriptor_ring) >> 2, 388 .lmac_ring = FALSE, 389 .ring_dir = HAL_SRNG_SRC_RING, 390 .reg_start = { 391 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 392 HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 393 }, 394 /* Single ring - provide ring size if multiple rings of this 395 * type are supported 396 */ 397 .reg_size = {}, 398 .max_size = 399 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_BMSK >> 400 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_SHFT, 401 }, 402 { /* SW2WBM_RELEASE */ 403 .start_ring_id = HAL_SRNG_WBM_SW_RELEASE, 404 .max_rings = 1, 405 .entry_size = sizeof(struct wbm_release_ring) >> 2, 406 .lmac_ring = FALSE, 407 .ring_dir = HAL_SRNG_SRC_RING, 408 .reg_start = { 409 HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 410 HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 411 }, 412 /* Single ring - provide ring size if multiple rings of this 413 * type are supported 414 */ 415 .reg_size = {}, 416 .max_size = 417 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> 418 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, 419 }, 420 { /* WBM2SW_RELEASE */ 421 .start_ring_id = HAL_SRNG_WBM2SW0_RELEASE, 422 .max_rings = 4, 423 .entry_size = sizeof(struct wbm_release_ring) >> 2, 424 .lmac_ring = FALSE, 425 .ring_dir = HAL_SRNG_DST_RING, 426 .reg_start = { 427 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 428 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 429 }, 430 .reg_size = { 431 HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) - 432 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 433 HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) - 434 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 435 }, 436 .max_size = 437 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> 438 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, 439 }, 440 { /* RXDMA_BUF */ 441 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA0_BUF0, 442 #ifdef IPA_OFFLOAD 443 .max_rings = 3, 444 #else 445 .max_rings = 2, 446 #endif 447 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 448 .lmac_ring = TRUE, 449 .ring_dir = HAL_SRNG_SRC_RING, 450 /* reg_start is not set because LMAC rings are not accessed 451 * from host 452 */ 453 .reg_start = {}, 454 .reg_size = {}, 455 .max_size = HAL_RXDMA_MAX_RING_SIZE, 456 }, 457 { /* RXDMA_DST */ 458 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW0, 459 .max_rings = 1, 460 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 461 .lmac_ring = TRUE, 462 .ring_dir = HAL_SRNG_DST_RING, 463 /* reg_start is not set because LMAC rings are not accessed 464 * from host 465 */ 466 .reg_start = {}, 467 .reg_size = {}, 468 .max_size = HAL_RXDMA_MAX_RING_SIZE, 469 }, 470 { /* RXDMA_MONITOR_BUF */ 471 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA2_BUF, 472 .max_rings = 1, 473 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 474 .lmac_ring = TRUE, 475 .ring_dir = HAL_SRNG_SRC_RING, 476 /* reg_start is not set because LMAC rings are not accessed 477 * from host 478 */ 479 .reg_start = {}, 480 .reg_size = {}, 481 .max_size = HAL_RXDMA_MAX_RING_SIZE, 482 }, 483 { /* RXDMA_MONITOR_STATUS */ 484 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_STATBUF, 485 .max_rings = 1, 486 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 487 .lmac_ring = TRUE, 488 .ring_dir = HAL_SRNG_SRC_RING, 489 /* reg_start is not set because LMAC rings are not accessed 490 * from host 491 */ 492 .reg_start = {}, 493 .reg_size = {}, 494 .max_size = HAL_RXDMA_MAX_RING_SIZE, 495 }, 496 { /* RXDMA_MONITOR_DST */ 497 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW1, 498 .max_rings = 1, 499 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 500 .lmac_ring = TRUE, 501 .ring_dir = HAL_SRNG_DST_RING, 502 /* reg_start is not set because LMAC rings are not accessed 503 * from host 504 */ 505 .reg_start = {}, 506 .reg_size = {}, 507 .max_size = HAL_RXDMA_MAX_RING_SIZE, 508 }, 509 { /* RXDMA_MONITOR_DESC */ 510 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_DESC, 511 .max_rings = 1, 512 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 513 .lmac_ring = TRUE, 514 .ring_dir = HAL_SRNG_SRC_RING, 515 /* reg_start is not set because LMAC rings are not accessed 516 * from host 517 */ 518 .reg_start = {}, 519 .reg_size = {}, 520 .max_size = HAL_RXDMA_MAX_RING_SIZE, 521 }, 522 { /* DIR_BUF_RX_DMA_SRC */ 523 .start_ring_id = HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING, 524 .max_rings = 1, 525 .entry_size = 2, 526 .lmac_ring = TRUE, 527 .ring_dir = HAL_SRNG_SRC_RING, 528 /* reg_start is not set because LMAC rings are not accessed 529 * from host 530 */ 531 .reg_start = {}, 532 .reg_size = {}, 533 .max_size = HAL_RXDMA_MAX_RING_SIZE, 534 }, 535 #ifdef WLAN_FEATURE_CIF_CFR 536 { /* WIFI_POS_SRC */ 537 .start_ring_id = HAL_SRNG_WIFI_POS_SRC_DMA_RING, 538 .max_rings = 1, 539 .entry_size = sizeof(wmi_oem_dma_buf_release_entry) >> 2, 540 .lmac_ring = TRUE, 541 .ring_dir = HAL_SRNG_SRC_RING, 542 /* reg_start is not set because LMAC rings are not accessed 543 * from host 544 */ 545 .reg_start = {}, 546 .reg_size = {}, 547 .max_size = HAL_RXDMA_MAX_RING_SIZE, 548 }, 549 #endif 550 }; 551 552 int32_t hal_hw_reg_offset_qca6290[] = { 553 /* dst */ 554 REG_OFFSET(DST, HP), 555 REG_OFFSET(DST, TP), 556 REG_OFFSET(DST, ID), 557 REG_OFFSET(DST, MISC), 558 REG_OFFSET(DST, HP_ADDR_LSB), 559 REG_OFFSET(DST, HP_ADDR_MSB), 560 REG_OFFSET(DST, MSI1_BASE_LSB), 561 REG_OFFSET(DST, MSI1_BASE_MSB), 562 REG_OFFSET(DST, MSI1_DATA), 563 REG_OFFSET(DST, BASE_LSB), 564 REG_OFFSET(DST, BASE_MSB), 565 REG_OFFSET(DST, PRODUCER_INT_SETUP), 566 /* src */ 567 REG_OFFSET(SRC, HP), 568 REG_OFFSET(SRC, TP), 569 REG_OFFSET(SRC, ID), 570 REG_OFFSET(SRC, MISC), 571 REG_OFFSET(SRC, TP_ADDR_LSB), 572 REG_OFFSET(SRC, TP_ADDR_MSB), 573 REG_OFFSET(SRC, MSI1_BASE_LSB), 574 REG_OFFSET(SRC, MSI1_BASE_MSB), 575 REG_OFFSET(SRC, MSI1_DATA), 576 REG_OFFSET(SRC, BASE_LSB), 577 REG_OFFSET(SRC, BASE_MSB), 578 REG_OFFSET(SRC, CONSUMER_INT_SETUP_IX0), 579 REG_OFFSET(SRC, CONSUMER_INT_SETUP_IX1), 580 }; 581 582 /** 583 * hal_qca6290_attach() - Attach 6290 target specific hal_soc ops, 584 * offset and srng table 585 */ 586 void hal_qca6290_attach(struct hal_soc *hal_soc) 587 { 588 hal_soc->hw_srng_table = hw_srng_table_6290; 589 hal_soc->hal_hw_reg_offset = hal_hw_reg_offset_qca6290; 590 hal_soc->ops = &qca6290_hal_hw_txrx_ops; 591 } 592