1 /* 2 * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 #include "qdf_types.h" 19 #include "qdf_util.h" 20 #include "qdf_types.h" 21 #include "qdf_lock.h" 22 #include "qdf_mem.h" 23 #include "qdf_nbuf.h" 24 #include "hal_li_hw_headers.h" 25 #include "hal_internal.h" 26 #include "hal_api.h" 27 #include "target_type.h" 28 #include "wcss_version.h" 29 #include "qdf_module.h" 30 31 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_OFFSET \ 32 RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_OFFSET 33 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_MASK \ 34 RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_MASK 35 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_LSB \ 36 RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_LSB 37 #define UNIFIED_PHYRX_HT_SIG_0_HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS_OFFSET \ 38 PHYRX_HT_SIG_0_HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS_OFFSET 39 #define UNIFIED_PHYRX_L_SIG_B_0_L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS_OFFSET \ 40 PHYRX_L_SIG_B_0_L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS_OFFSET 41 #define UNIFIED_PHYRX_L_SIG_A_0_L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS_OFFSET \ 42 PHYRX_L_SIG_A_0_L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS_OFFSET 43 #define UNIFIED_PHYRX_VHT_SIG_A_0_VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS_OFFSET \ 44 PHYRX_VHT_SIG_A_0_VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS_OFFSET 45 #define UNIFIED_PHYRX_HE_SIG_A_SU_0_HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS_OFFSET \ 46 PHYRX_HE_SIG_A_SU_0_HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS_OFFSET 47 #define UNIFIED_PHYRX_HE_SIG_A_MU_DL_0_HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_OFFSET \ 48 PHYRX_HE_SIG_A_MU_DL_0_HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_OFFSET 49 #define UNIFIED_PHYRX_HE_SIG_B1_MU_0_HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_OFFSET \ 50 PHYRX_HE_SIG_B1_MU_0_HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_OFFSET 51 #define UNIFIED_PHYRX_HE_SIG_B2_MU_0_HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_OFFSET \ 52 PHYRX_HE_SIG_B2_MU_0_HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_OFFSET 53 #define UNIFIED_PHYRX_HE_SIG_B2_OFDMA_0_HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_OFFSET \ 54 PHYRX_HE_SIG_B2_OFDMA_0_HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_OFFSET 55 #define UNIFIED_PHYRX_RSSI_LEGACY_3_RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS_OFFSET \ 56 PHYRX_RSSI_LEGACY_3_RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS_OFFSET 57 #define UNIFIED_PHYRX_RSSI_LEGACY_19_RECEIVE_RSSI_INFO_PREAMBLE_RSSI_INFO_DETAILS_OFFSET \ 58 PHYRX_RSSI_LEGACY_19_RECEIVE_RSSI_INFO_PREAMBLE_RSSI_INFO_DETAILS_OFFSET 59 #define UNIFIED_RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET \ 60 RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET 61 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 62 RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET 63 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ 64 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET 65 #define UNIFIED_RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 66 RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET 67 #define UNIFIED_REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 68 REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET 69 #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC \ 70 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER 71 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ 72 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET 73 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 74 RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET 75 #define UNIFIED_TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 76 TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET 77 #define UNIFIED_TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 78 TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET 79 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET \ 80 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET 81 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB \ 82 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB 83 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK \ 84 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK 85 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB \ 86 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB 87 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK \ 88 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK 89 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB \ 90 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB 91 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK \ 92 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK 93 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB \ 94 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB 95 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK \ 96 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK 97 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB \ 98 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB 99 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK \ 100 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK 101 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_MASK \ 102 WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_MASK 103 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_OFFSET \ 104 WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_OFFSET 105 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_LSB \ 106 WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_LSB 107 108 #include "hal_6290_tx.h" 109 #include "hal_6290_rx.h" 110 #include <hal_generic_api.h> 111 #include "hal_li_rx.h" 112 #include "hal_li_api.h" 113 #include "hal_li_generic_api.h" 114 115 /** 116 * hal_rx_get_rx_fragment_number_6290(): Function to retrieve rx fragment number 117 * 118 * @nbuf: Network buffer 119 * Returns: rx fragment number 120 */ 121 static 122 uint8_t hal_rx_get_rx_fragment_number_6290(uint8_t *buf) 123 { 124 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 125 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 126 127 /* Return first 4 bits as fragment number */ 128 return (HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info) & 129 DOT11_SEQ_FRAG_MASK); 130 } 131 132 /** 133 * hal_rx_msdu_end_da_is_mcbc_get: API to check if pkt is MCBC 134 * from rx_msdu_end TLV 135 * 136 * @ buf: pointer to the start of RX PKT TLV headers 137 * Return: da_is_mcbc 138 */ 139 static inline uint8_t 140 hal_rx_msdu_end_da_is_mcbc_get_6290(uint8_t *buf) 141 { 142 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 143 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 144 145 return HAL_RX_MSDU_END_DA_IS_MCBC_GET(msdu_end); 146 } 147 148 /** 149 * hal_rx_msdu_end_sa_is_valid_get_6290(): API to get_6290 the 150 * sa_is_valid bit from rx_msdu_end TLV 151 * 152 * @ buf: pointer to the start of RX PKT TLV headers 153 * Return: sa_is_valid bit 154 */ 155 static uint8_t 156 hal_rx_msdu_end_sa_is_valid_get_6290(uint8_t *buf) 157 { 158 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 159 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 160 uint8_t sa_is_valid; 161 162 sa_is_valid = HAL_RX_MSDU_END_SA_IS_VALID_GET(msdu_end); 163 164 return sa_is_valid; 165 } 166 167 /** 168 * hal_rx_msdu_end_sa_idx_get_6290(): API to get_6290 the 169 * sa_idx from rx_msdu_end TLV 170 * 171 * @ buf: pointer to the start of RX PKT TLV headers 172 * Return: sa_idx (SA AST index) 173 */ 174 static 175 uint16_t hal_rx_msdu_end_sa_idx_get_6290(uint8_t *buf) 176 { 177 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 178 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 179 uint16_t sa_idx; 180 181 sa_idx = HAL_RX_MSDU_END_SA_IDX_GET(msdu_end); 182 183 return sa_idx; 184 } 185 186 /** 187 * hal_rx_desc_is_first_msdu_6290() - Check if first msdu 188 * 189 * @hal_soc_hdl: hal_soc handle 190 * @hw_desc_addr: hardware descriptor address 191 * 192 * Return: 0 - success/ non-zero failure 193 */ 194 static uint32_t hal_rx_desc_is_first_msdu_6290(void *hw_desc_addr) 195 { 196 struct rx_pkt_tlvs *rx_tlvs = (struct rx_pkt_tlvs *)hw_desc_addr; 197 struct rx_msdu_end *msdu_end = &rx_tlvs->msdu_end_tlv.rx_msdu_end; 198 199 return HAL_RX_GET(msdu_end, RX_MSDU_END_5, FIRST_MSDU); 200 } 201 202 /** 203 * hal_rx_msdu_end_l3_hdr_padding_get_6290(): API to get_6290 the 204 * l3_header padding from rx_msdu_end TLV 205 * 206 * @ buf: pointer to the start of RX PKT TLV headers 207 * Return: number of l3 header padding bytes 208 */ 209 static uint32_t hal_rx_msdu_end_l3_hdr_padding_get_6290(uint8_t *buf) 210 { 211 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 212 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 213 uint32_t l3_header_padding; 214 215 l3_header_padding = HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(msdu_end); 216 217 return l3_header_padding; 218 } 219 220 /* 221 * @ hal_rx_encryption_info_valid_6290: Returns encryption type. 222 * 223 * @ buf: rx_tlv_hdr of the received packet 224 * @ Return: encryption type 225 */ 226 static uint32_t hal_rx_encryption_info_valid_6290(uint8_t *buf) 227 { 228 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 229 struct rx_mpdu_start *mpdu_start = 230 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 231 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 232 uint32_t encryption_info = HAL_RX_MPDU_ENCRYPTION_INFO_VALID(mpdu_info); 233 234 return encryption_info; 235 } 236 237 /* 238 * hal_rx_print_pn_6290: Prints the PN of rx packet. 239 * @buf: rx_tlv_hdr of the received packet 240 * 241 * Return: void 242 */ 243 static void hal_rx_print_pn_6290(uint8_t *buf) 244 { 245 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 246 struct rx_mpdu_start *mpdu_start = 247 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 248 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 249 250 uint32_t pn_31_0 = HAL_RX_MPDU_PN_31_0_GET(mpdu_info); 251 uint32_t pn_63_32 = HAL_RX_MPDU_PN_63_32_GET(mpdu_info); 252 uint32_t pn_95_64 = HAL_RX_MPDU_PN_95_64_GET(mpdu_info); 253 uint32_t pn_127_96 = HAL_RX_MPDU_PN_127_96_GET(mpdu_info); 254 255 hal_debug("PN number pn_127_96 0x%x pn_95_64 0x%x pn_63_32 0x%x pn_31_0 0x%x ", 256 pn_127_96, pn_95_64, pn_63_32, pn_31_0); 257 } 258 259 /** 260 * hal_rx_msdu_end_first_msdu_get_6290: API to get first msdu status 261 * from rx_msdu_end TLV 262 * 263 * @buf: pointer to the start of RX PKT TLV headers 264 * Return: first_msdu 265 */ 266 static uint8_t 267 hal_rx_msdu_end_first_msdu_get_6290(uint8_t *buf) 268 { 269 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 270 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 271 uint8_t first_msdu; 272 273 first_msdu = HAL_RX_MSDU_END_FIRST_MSDU_GET(msdu_end); 274 275 return first_msdu; 276 } 277 278 /** 279 * hal_rx_msdu_end_da_is_valid_get_6290: API to check if da is valid 280 * from rx_msdu_end TLV 281 * 282 * @ buf: pointer to the start of RX PKT TLV headers 283 * Return: da_is_valid 284 */ 285 static uint8_t hal_rx_msdu_end_da_is_valid_get_6290(uint8_t *buf) 286 { 287 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 288 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 289 uint8_t da_is_valid; 290 291 da_is_valid = HAL_RX_MSDU_END_DA_IS_VALID_GET(msdu_end); 292 293 return da_is_valid; 294 } 295 296 /** 297 * hal_rx_msdu_end_last_msdu_get_6290: API to get last msdu status 298 * from rx_msdu_end TLV 299 * 300 * @ buf: pointer to the start of RX PKT TLV headers 301 * Return: last_msdu 302 */ 303 static uint8_t hal_rx_msdu_end_last_msdu_get_6290(uint8_t *buf) 304 { 305 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 306 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 307 uint8_t last_msdu; 308 309 last_msdu = HAL_RX_MSDU_END_LAST_MSDU_GET(msdu_end); 310 311 return last_msdu; 312 } 313 314 /* 315 * hal_rx_get_mpdu_mac_ad4_valid_6290(): Retrieves if mpdu 4th addr is valid 316 * 317 * @nbuf: Network buffer 318 * Returns: value of mpdu 4th address valid field 319 */ 320 static bool hal_rx_get_mpdu_mac_ad4_valid_6290(uint8_t *buf) 321 { 322 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 323 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 324 bool ad4_valid = 0; 325 326 ad4_valid = HAL_RX_MPDU_GET_MAC_AD4_VALID(rx_mpdu_info); 327 328 return ad4_valid; 329 } 330 331 /** 332 * hal_rx_mpdu_start_sw_peer_id_get_6290: Retrieve sw peer_id 333 * @buf: network buffer 334 * 335 * Return: sw peer_id: 336 */ 337 static uint32_t hal_rx_mpdu_start_sw_peer_id_get_6290(uint8_t *buf) 338 { 339 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 340 struct rx_mpdu_start *mpdu_start = 341 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 342 343 return HAL_RX_MPDU_INFO_SW_PEER_ID_GET( 344 &mpdu_start->rx_mpdu_info_details); 345 } 346 347 /* 348 * hal_rx_mpdu_get_to_ds_6290(): API to get the tods info 349 * from rx_mpdu_start 350 * 351 * @buf: pointer to the start of RX PKT TLV header 352 * Return: uint32_t(to_ds) 353 */ 354 355 static uint32_t hal_rx_mpdu_get_to_ds_6290(uint8_t *buf) 356 { 357 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 358 struct rx_mpdu_start *mpdu_start = 359 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 360 361 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 362 363 return HAL_RX_MPDU_GET_TODS(mpdu_info); 364 } 365 366 /* 367 * hal_rx_mpdu_get_fr_ds_6290(): API to get the from ds info 368 * from rx_mpdu_start 369 * 370 * @buf: pointer to the start of RX PKT TLV header 371 * Return: uint32_t(fr_ds) 372 */ 373 static uint32_t hal_rx_mpdu_get_fr_ds_6290(uint8_t *buf) 374 { 375 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 376 struct rx_mpdu_start *mpdu_start = 377 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 378 379 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 380 381 return HAL_RX_MPDU_GET_FROMDS(mpdu_info); 382 } 383 384 /* 385 * hal_rx_get_mpdu_frame_control_valid_6290(): Retrieves mpdu frame 386 * control valid 387 * 388 * @nbuf: Network buffer 389 * Returns: value of frame control valid field 390 */ 391 static uint8_t hal_rx_get_mpdu_frame_control_valid_6290(uint8_t *buf) 392 { 393 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 394 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 395 396 return HAL_RX_MPDU_GET_FRAME_CONTROL_VALID(rx_mpdu_info); 397 } 398 399 /* 400 * hal_rx_mpdu_get_addr1_6290(): API to check get address1 of the mpdu 401 * 402 * @buf: pointer to the start of RX PKT TLV headera 403 * @mac_addr: pointer to mac address 404 * Return: success/failure 405 */ 406 static QDF_STATUS hal_rx_mpdu_get_addr1_6290(uint8_t *buf, uint8_t *mac_addr) 407 { 408 struct __attribute__((__packed__)) hal_addr1 { 409 uint32_t ad1_31_0; 410 uint16_t ad1_47_32; 411 }; 412 413 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 414 struct rx_mpdu_start *mpdu_start = 415 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 416 417 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 418 struct hal_addr1 *addr = (struct hal_addr1 *)mac_addr; 419 uint32_t mac_addr_ad1_valid; 420 421 mac_addr_ad1_valid = HAL_RX_MPDU_MAC_ADDR_AD1_VALID_GET(mpdu_info); 422 423 if (mac_addr_ad1_valid) { 424 addr->ad1_31_0 = HAL_RX_MPDU_AD1_31_0_GET(mpdu_info); 425 addr->ad1_47_32 = HAL_RX_MPDU_AD1_47_32_GET(mpdu_info); 426 return QDF_STATUS_SUCCESS; 427 } 428 429 return QDF_STATUS_E_FAILURE; 430 } 431 432 /* 433 * hal_rx_mpdu_get_addr2_6290(): API to check get address2 of the mpdu 434 * in the packet 435 * 436 * @buf: pointer to the start of RX PKT TLV header 437 * @mac_addr: pointer to mac address 438 * Return: success/failure 439 */ 440 static QDF_STATUS hal_rx_mpdu_get_addr2_6290(uint8_t *buf, 441 uint8_t *mac_addr) 442 { 443 struct __attribute__((__packed__)) hal_addr2 { 444 uint16_t ad2_15_0; 445 uint32_t ad2_47_16; 446 }; 447 448 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 449 struct rx_mpdu_start *mpdu_start = 450 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 451 452 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 453 struct hal_addr2 *addr = (struct hal_addr2 *)mac_addr; 454 uint32_t mac_addr_ad2_valid; 455 456 mac_addr_ad2_valid = HAL_RX_MPDU_MAC_ADDR_AD2_VALID_GET(mpdu_info); 457 458 if (mac_addr_ad2_valid) { 459 addr->ad2_15_0 = HAL_RX_MPDU_AD2_15_0_GET(mpdu_info); 460 addr->ad2_47_16 = HAL_RX_MPDU_AD2_47_16_GET(mpdu_info); 461 return QDF_STATUS_SUCCESS; 462 } 463 464 return QDF_STATUS_E_FAILURE; 465 } 466 467 /* 468 * hal_rx_mpdu_get_addr3_6290(): API to get address3 of the mpdu 469 * in the packet 470 * 471 * @buf: pointer to the start of RX PKT TLV header 472 * @mac_addr: pointer to mac address 473 * Return: success/failure 474 */ 475 static QDF_STATUS hal_rx_mpdu_get_addr3_6290(uint8_t *buf, uint8_t *mac_addr) 476 { 477 struct __attribute__((__packed__)) hal_addr3 { 478 uint32_t ad3_31_0; 479 uint16_t ad3_47_32; 480 }; 481 482 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 483 struct rx_mpdu_start *mpdu_start = 484 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 485 486 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 487 struct hal_addr3 *addr = (struct hal_addr3 *)mac_addr; 488 uint32_t mac_addr_ad3_valid; 489 490 mac_addr_ad3_valid = HAL_RX_MPDU_MAC_ADDR_AD3_VALID_GET(mpdu_info); 491 492 if (mac_addr_ad3_valid) { 493 addr->ad3_31_0 = HAL_RX_MPDU_AD3_31_0_GET(mpdu_info); 494 addr->ad3_47_32 = HAL_RX_MPDU_AD3_47_32_GET(mpdu_info); 495 return QDF_STATUS_SUCCESS; 496 } 497 498 return QDF_STATUS_E_FAILURE; 499 } 500 501 /* 502 * hal_rx_mpdu_get_addr4_6290(): API to get address4 of the mpdu 503 * in the packet 504 * 505 * @buf: pointer to the start of RX PKT TLV header 506 * @mac_addr: pointer to mac address 507 * Return: success/failure 508 */ 509 static QDF_STATUS hal_rx_mpdu_get_addr4_6290(uint8_t *buf, uint8_t *mac_addr) 510 { 511 struct __attribute__((__packed__)) hal_addr4 { 512 uint32_t ad4_31_0; 513 uint16_t ad4_47_32; 514 }; 515 516 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 517 struct rx_mpdu_start *mpdu_start = 518 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 519 520 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 521 struct hal_addr4 *addr = (struct hal_addr4 *)mac_addr; 522 uint32_t mac_addr_ad4_valid; 523 524 mac_addr_ad4_valid = HAL_RX_MPDU_MAC_ADDR_AD4_VALID_GET(mpdu_info); 525 526 if (mac_addr_ad4_valid) { 527 addr->ad4_31_0 = HAL_RX_MPDU_AD4_31_0_GET(mpdu_info); 528 addr->ad4_47_32 = HAL_RX_MPDU_AD4_47_32_GET(mpdu_info); 529 return QDF_STATUS_SUCCESS; 530 } 531 532 return QDF_STATUS_E_FAILURE; 533 } 534 535 /* 536 * hal_rx_get_mpdu_sequence_control_valid_6290(): Get mpdu 537 * sequence control valid 538 * 539 * @nbuf: Network buffer 540 * Returns: value of sequence control valid field 541 */ 542 static uint8_t hal_rx_get_mpdu_sequence_control_valid_6290(uint8_t *buf) 543 { 544 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 545 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 546 547 return HAL_RX_MPDU_GET_SEQUENCE_CONTROL_VALID(rx_mpdu_info); 548 } 549 550 /** 551 * hal_rx_is_unicast_6290: check packet is unicast frame or not. 552 * 553 * @ buf: pointer to rx pkt TLV. 554 * 555 * Return: true on unicast. 556 */ 557 static bool hal_rx_is_unicast_6290(uint8_t *buf) 558 { 559 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 560 struct rx_mpdu_start *mpdu_start = 561 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 562 uint32_t grp_id; 563 uint8_t *rx_mpdu_info = (uint8_t *)&mpdu_start->rx_mpdu_info_details; 564 565 grp_id = (_HAL_MS((*_OFFSET_TO_WORD_PTR((rx_mpdu_info), 566 RX_MPDU_INFO_0_SW_FRAME_GROUP_ID_OFFSET)), 567 RX_MPDU_INFO_0_SW_FRAME_GROUP_ID_MASK, 568 RX_MPDU_INFO_0_SW_FRAME_GROUP_ID_LSB)); 569 570 return (HAL_MPDU_SW_FRAME_GROUP_UNICAST_DATA == grp_id) ? true : false; 571 } 572 573 /** 574 * hal_rx_tid_get_6290: get tid based on qos control valid. 575 * @hal_soc_hdl: hal soc handle 576 * @ buf: pointer to rx pkt TLV. 577 * 578 * Return: tid 579 */ 580 static uint32_t hal_rx_tid_get_6290(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 581 { 582 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 583 struct rx_mpdu_start *mpdu_start = 584 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 585 uint8_t *rx_mpdu_info = (uint8_t *)&mpdu_start->rx_mpdu_info_details; 586 uint8_t qos_control_valid = 587 (_HAL_MS((*_OFFSET_TO_WORD_PTR((rx_mpdu_info), 588 RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_OFFSET)), 589 RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_MASK, 590 RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_LSB)); 591 592 if (qos_control_valid) 593 return hal_rx_mpdu_start_tid_get_6290(buf); 594 595 return HAL_RX_NON_QOS_TID; 596 } 597 598 /** 599 * hal_rx_hw_desc_get_ppduid_get_6290(): retrieve ppdu id 600 * @rx_tlv_hdr: start address of rx_pkt_tlvs 601 * @rxdma_dst_ring_desc: Rx HW descriptor 602 * 603 * Return: ppdu id 604 */ 605 static uint32_t hal_rx_hw_desc_get_ppduid_get_6290(void *rx_tlv_hdr, 606 void *rxdma_dst_ring_desc) 607 { 608 struct rx_mpdu_info *rx_mpdu_info; 609 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)rx_tlv_hdr; 610 611 rx_mpdu_info = 612 &rx_desc->mpdu_start_tlv.rx_mpdu_start.rx_mpdu_info_details; 613 614 return HAL_RX_GET(rx_mpdu_info, RX_MPDU_INFO_0, PHY_PPDU_ID); 615 } 616 617 /** 618 * hal_reo_status_get_header_6290 - Process reo desc info 619 * @ring_desc: REO status ring descriptor 620 * @b - tlv type info 621 * @h1 - Pointer to hal_reo_status_header where info to be stored 622 * 623 * Return - none. 624 * 625 */ 626 static void hal_reo_status_get_header_6290(hal_ring_desc_t ring_desc, int b, 627 void *h1) 628 { 629 uint32_t *d = (uint32_t *)ring_desc; 630 uint32_t val1 = 0; 631 struct hal_reo_status_header *h = 632 (struct hal_reo_status_header *)h1; 633 634 /* Offsets of descriptor fields defined in HW headers start 635 * from the field after TLV header 636 */ 637 d += HAL_GET_NUM_DWORDS(sizeof(struct tlv_32_hdr)); 638 639 switch (b) { 640 case HAL_REO_QUEUE_STATS_STATUS_TLV: 641 val1 = d[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_0, 642 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 643 break; 644 case HAL_REO_FLUSH_QUEUE_STATUS_TLV: 645 val1 = d[HAL_OFFSET_DW(REO_FLUSH_QUEUE_STATUS_0, 646 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 647 break; 648 case HAL_REO_FLUSH_CACHE_STATUS_TLV: 649 val1 = d[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_0, 650 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 651 break; 652 case HAL_REO_UNBLK_CACHE_STATUS_TLV: 653 val1 = d[HAL_OFFSET_DW(REO_UNBLOCK_CACHE_STATUS_0, 654 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 655 break; 656 case HAL_REO_TIMOUT_LIST_STATUS_TLV: 657 val1 = d[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_0, 658 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 659 break; 660 case HAL_REO_DESC_THRES_STATUS_TLV: 661 val1 = 662 d[HAL_OFFSET_DW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0, 663 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 664 break; 665 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: 666 val1 = d[HAL_OFFSET_DW(REO_UPDATE_RX_REO_QUEUE_STATUS_0, 667 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 668 break; 669 default: 670 qdf_nofl_err("ERROR: Unknown tlv\n"); 671 break; 672 } 673 h->cmd_num = 674 HAL_GET_FIELD( 675 UNIFORM_REO_STATUS_HEADER_0, REO_STATUS_NUMBER, 676 val1); 677 h->exec_time = 678 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_0, 679 CMD_EXECUTION_TIME, val1); 680 h->status = 681 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_0, 682 REO_CMD_EXECUTION_STATUS, val1); 683 switch (b) { 684 case HAL_REO_QUEUE_STATS_STATUS_TLV: 685 val1 = d[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_1, 686 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 687 break; 688 case HAL_REO_FLUSH_QUEUE_STATUS_TLV: 689 val1 = d[HAL_OFFSET_DW(REO_FLUSH_QUEUE_STATUS_1, 690 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 691 break; 692 case HAL_REO_FLUSH_CACHE_STATUS_TLV: 693 val1 = d[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_1, 694 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 695 break; 696 case HAL_REO_UNBLK_CACHE_STATUS_TLV: 697 val1 = d[HAL_OFFSET_DW(REO_UNBLOCK_CACHE_STATUS_1, 698 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 699 break; 700 case HAL_REO_TIMOUT_LIST_STATUS_TLV: 701 val1 = d[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_1, 702 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 703 break; 704 case HAL_REO_DESC_THRES_STATUS_TLV: 705 val1 = 706 d[HAL_OFFSET_DW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_1, 707 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 708 break; 709 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: 710 val1 = d[HAL_OFFSET_DW(REO_UPDATE_RX_REO_QUEUE_STATUS_1, 711 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 712 break; 713 default: 714 qdf_nofl_err("ERROR: Unknown tlv\n"); 715 break; 716 } 717 h->tstamp = 718 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_1, TIMESTAMP, val1); 719 } 720 721 /** 722 * hal_rx_mpdu_start_mpdu_qos_control_valid_get_6290(): 723 * Retrieve qos control valid bit from the tlv. 724 * @buf: pointer to rx pkt TLV. 725 * 726 * Return: qos control value. 727 */ 728 static inline uint32_t 729 hal_rx_mpdu_start_mpdu_qos_control_valid_get_6290(uint8_t *buf) 730 { 731 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 732 struct rx_mpdu_start *mpdu_start = 733 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 734 735 return HAL_RX_MPDU_INFO_QOS_CONTROL_VALID_GET( 736 &mpdu_start->rx_mpdu_info_details); 737 } 738 739 /** 740 * hal_rx_msdu_end_sa_sw_peer_id_get_6290(): API to get the 741 * sa_sw_peer_id from rx_msdu_end TLV 742 * @buf: pointer to the start of RX PKT TLV headers 743 * 744 * Return: sa_sw_peer_id index 745 */ 746 static inline uint32_t 747 hal_rx_msdu_end_sa_sw_peer_id_get_6290(uint8_t *buf) 748 { 749 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 750 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 751 752 return HAL_RX_MSDU_END_SA_SW_PEER_ID_GET(msdu_end); 753 } 754 755 /** 756 * hal_tx_desc_set_mesh_en_6290 - Set mesh_enable flag in Tx descriptor 757 * @desc: Handle to Tx Descriptor 758 * @en: For raw WiFi frames, this indicates transmission to a mesh STA, 759 * enabling the interpretation of the 'Mesh Control Present' bit 760 * (bit 8) of QoS Control (otherwise this bit is ignored), 761 * For native WiFi frames, this indicates that a 'Mesh Control' field 762 * is present between the header and the LLC. 763 * 764 * Return: void 765 */ 766 static inline 767 void hal_tx_desc_set_mesh_en_6290(void *desc, uint8_t en) 768 { 769 HAL_SET_FLD(desc, TCL_DATA_CMD_4, MESH_ENABLE) |= 770 HAL_TX_SM(TCL_DATA_CMD_4, MESH_ENABLE, en); 771 } 772 773 static 774 void *hal_rx_msdu0_buffer_addr_lsb_6290(void *link_desc_va) 775 { 776 return (void *)HAL_RX_MSDU0_BUFFER_ADDR_LSB(link_desc_va); 777 } 778 779 static 780 void *hal_rx_msdu_desc_info_ptr_get_6290(void *msdu0) 781 { 782 return (void *)HAL_RX_MSDU_DESC_INFO_PTR_GET(msdu0); 783 } 784 785 static 786 void *hal_ent_mpdu_desc_info_6290(void *ent_ring_desc) 787 { 788 return (void *)HAL_ENT_MPDU_DESC_INFO(ent_ring_desc); 789 } 790 791 static 792 void *hal_dst_mpdu_desc_info_6290(void *dst_ring_desc) 793 { 794 return (void *)HAL_DST_MPDU_DESC_INFO(dst_ring_desc); 795 } 796 797 static 798 uint8_t hal_rx_get_fc_valid_6290(uint8_t *buf) 799 { 800 return HAL_RX_GET_FC_VALID(buf); 801 } 802 803 static uint8_t hal_rx_get_to_ds_flag_6290(uint8_t *buf) 804 { 805 return HAL_RX_GET_TO_DS_FLAG(buf); 806 } 807 808 static uint8_t hal_rx_get_mac_addr2_valid_6290(uint8_t *buf) 809 { 810 return HAL_RX_GET_MAC_ADDR2_VALID(buf); 811 } 812 813 static uint8_t hal_rx_get_filter_category_6290(uint8_t *buf) 814 { 815 return HAL_RX_GET_FILTER_CATEGORY(buf); 816 } 817 818 static uint32_t 819 hal_rx_get_ppdu_id_6290(uint8_t *buf) 820 { 821 return HAL_RX_GET_PPDU_ID(buf); 822 } 823 824 /** 825 * hal_reo_config_6290(): Set reo config parameters 826 * @soc: hal soc handle 827 * @reg_val: value to be set 828 * @reo_params: reo parameters 829 * 830 * Return: void 831 */ 832 static 833 void hal_reo_config_6290(struct hal_soc *soc, 834 uint32_t reg_val, 835 struct hal_reo_params *reo_params) 836 { 837 HAL_REO_R0_CONFIG(soc, reg_val, reo_params); 838 } 839 840 /** 841 * hal_rx_msdu_desc_info_get_ptr_6290() - Get msdu desc info ptr 842 * @msdu_details_ptr - Pointer to msdu_details_ptr 843 * 844 * Return - Pointer to rx_msdu_desc_info structure. 845 * 846 */ 847 static void *hal_rx_msdu_desc_info_get_ptr_6290(void *msdu_details_ptr) 848 { 849 return HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr); 850 } 851 852 /** 853 * hal_rx_link_desc_msdu0_ptr_6290 - Get pointer to rx_msdu details 854 * @link_desc - Pointer to link desc 855 * 856 * Return - Pointer to rx_msdu_details structure 857 * 858 */ 859 static void *hal_rx_link_desc_msdu0_ptr_6290(void *link_desc) 860 { 861 return HAL_RX_LINK_DESC_MSDU0_PTR(link_desc); 862 } 863 864 /** 865 * hal_rx_msdu_flow_idx_get_6290: API to get flow index 866 * from rx_msdu_end TLV 867 * @buf: pointer to the start of RX PKT TLV headers 868 * 869 * Return: flow index value from MSDU END TLV 870 */ 871 static inline uint32_t hal_rx_msdu_flow_idx_get_6290(uint8_t *buf) 872 { 873 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 874 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 875 876 return HAL_RX_MSDU_END_FLOW_IDX_GET(msdu_end); 877 } 878 879 /** 880 * hal_rx_msdu_flow_idx_invalid_6290: API to get flow index invalid 881 * from rx_msdu_end TLV 882 * @buf: pointer to the start of RX PKT TLV headers 883 * 884 * Return: flow index invalid value from MSDU END TLV 885 */ 886 static bool hal_rx_msdu_flow_idx_invalid_6290(uint8_t *buf) 887 { 888 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 889 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 890 891 return HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(msdu_end); 892 } 893 894 /** 895 * hal_rx_msdu_flow_idx_timeout_6290: API to get flow index timeout 896 * from rx_msdu_end TLV 897 * @buf: pointer to the start of RX PKT TLV headers 898 * 899 * Return: flow index timeout value from MSDU END TLV 900 */ 901 static bool hal_rx_msdu_flow_idx_timeout_6290(uint8_t *buf) 902 { 903 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 904 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 905 906 return HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(msdu_end); 907 } 908 909 /** 910 * hal_rx_msdu_fse_metadata_get_6290: API to get FSE metadata 911 * from rx_msdu_end TLV 912 * @buf: pointer to the start of RX PKT TLV headers 913 * 914 * Return: fse metadata value from MSDU END TLV 915 */ 916 static uint32_t hal_rx_msdu_fse_metadata_get_6290(uint8_t *buf) 917 { 918 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 919 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 920 921 return HAL_RX_MSDU_END_FSE_METADATA_GET(msdu_end); 922 } 923 924 /** 925 * hal_rx_msdu_cce_metadata_get_6290: API to get CCE metadata 926 * from rx_msdu_end TLV 927 * @buf: pointer to the start of RX PKT TLV headers 928 * 929 * Return: cce_metadata 930 */ 931 static uint16_t 932 hal_rx_msdu_cce_metadata_get_6290(uint8_t *buf) 933 { 934 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 935 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 936 937 return HAL_RX_MSDU_END_CCE_METADATA_GET(msdu_end); 938 } 939 940 /** 941 * hal_rx_msdu_get_flow_params_6290: API to get flow index, flow index invalid 942 * and flow index timeout from rx_msdu_end TLV 943 * @buf: pointer to the start of RX PKT TLV headers 944 * @flow_invalid: pointer to return value of flow_idx_valid 945 * @flow_timeout: pointer to return value of flow_idx_timeout 946 * @flow_index: pointer to return value of flow_idx 947 * 948 * Return: none 949 */ 950 static inline void 951 hal_rx_msdu_get_flow_params_6290(uint8_t *buf, 952 bool *flow_invalid, 953 bool *flow_timeout, 954 uint32_t *flow_index) 955 { 956 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 957 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 958 959 *flow_invalid = HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(msdu_end); 960 *flow_timeout = HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(msdu_end); 961 *flow_index = HAL_RX_MSDU_END_FLOW_IDX_GET(msdu_end); 962 } 963 964 /** 965 * hal_rx_tlv_get_tcp_chksum_6290() - API to get tcp checksum 966 * @buf: rx_tlv_hdr 967 * 968 * Return: tcp checksum 969 */ 970 static uint16_t 971 hal_rx_tlv_get_tcp_chksum_6290(uint8_t *buf) 972 { 973 return HAL_RX_TLV_GET_TCP_CHKSUM(buf); 974 } 975 976 /** 977 * hal_rx_get_rx_sequence_6290(): Function to retrieve rx sequence number 978 * @nbuf: Network buffer 979 * 980 * Return: rx sequence number 981 */ 982 static 983 uint16_t hal_rx_get_rx_sequence_6290(uint8_t *buf) 984 { 985 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 986 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 987 988 return HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info); 989 } 990 991 /** 992 * hal_get_window_address_6290(): Function to get hp/tp address 993 * @hal_soc: Pointer to hal_soc 994 * @addr: address offset of register 995 * 996 * Return: modified address offset of register 997 */ 998 static inline qdf_iomem_t hal_get_window_address_6290(struct hal_soc *hal_soc, 999 qdf_iomem_t addr) 1000 { 1001 return addr; 1002 } 1003 1004 static 1005 void hal_compute_reo_remap_ix2_ix3_6290(uint32_t *ring, uint32_t num_rings, 1006 uint32_t *remap1, uint32_t *remap2) 1007 { 1008 switch (num_rings) { 1009 case 3: 1010 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 1011 HAL_REO_REMAP_IX2(ring[1], 17) | 1012 HAL_REO_REMAP_IX2(ring[2], 18) | 1013 HAL_REO_REMAP_IX2(ring[0], 19) | 1014 HAL_REO_REMAP_IX2(ring[1], 20) | 1015 HAL_REO_REMAP_IX2(ring[2], 21) | 1016 HAL_REO_REMAP_IX2(ring[0], 22) | 1017 HAL_REO_REMAP_IX2(ring[1], 23); 1018 1019 *remap2 = HAL_REO_REMAP_IX3(ring[2], 24) | 1020 HAL_REO_REMAP_IX3(ring[0], 25) | 1021 HAL_REO_REMAP_IX3(ring[1], 26) | 1022 HAL_REO_REMAP_IX3(ring[2], 27) | 1023 HAL_REO_REMAP_IX3(ring[0], 28) | 1024 HAL_REO_REMAP_IX3(ring[1], 29) | 1025 HAL_REO_REMAP_IX3(ring[2], 30) | 1026 HAL_REO_REMAP_IX3(ring[0], 31); 1027 break; 1028 case 4: 1029 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 1030 HAL_REO_REMAP_IX2(ring[1], 17) | 1031 HAL_REO_REMAP_IX2(ring[2], 18) | 1032 HAL_REO_REMAP_IX2(ring[3], 19) | 1033 HAL_REO_REMAP_IX2(ring[0], 20) | 1034 HAL_REO_REMAP_IX2(ring[1], 21) | 1035 HAL_REO_REMAP_IX2(ring[2], 22) | 1036 HAL_REO_REMAP_IX2(ring[3], 23); 1037 1038 *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) | 1039 HAL_REO_REMAP_IX3(ring[1], 25) | 1040 HAL_REO_REMAP_IX3(ring[2], 26) | 1041 HAL_REO_REMAP_IX3(ring[3], 27) | 1042 HAL_REO_REMAP_IX3(ring[0], 28) | 1043 HAL_REO_REMAP_IX3(ring[1], 29) | 1044 HAL_REO_REMAP_IX3(ring[2], 30) | 1045 HAL_REO_REMAP_IX3(ring[3], 31); 1046 break; 1047 } 1048 } 1049 1050 static void hal_hw_txrx_ops_attach_6290(struct hal_soc *hal_soc) 1051 { 1052 /* init and setup */ 1053 hal_soc->ops->hal_srng_dst_hw_init = hal_srng_dst_hw_init_generic; 1054 hal_soc->ops->hal_srng_src_hw_init = hal_srng_src_hw_init_generic; 1055 hal_soc->ops->hal_get_hw_hptp = hal_get_hw_hptp_generic; 1056 hal_soc->ops->hal_reo_setup = hal_reo_setup_generic_li; 1057 hal_soc->ops->hal_get_window_address = hal_get_window_address_6290; 1058 1059 /* tx */ 1060 hal_soc->ops->hal_tx_desc_set_dscp_tid_table_id = 1061 hal_tx_desc_set_dscp_tid_table_id_6290; 1062 hal_soc->ops->hal_tx_set_dscp_tid_map = hal_tx_set_dscp_tid_map_6290; 1063 hal_soc->ops->hal_tx_update_dscp_tid = hal_tx_update_dscp_tid_6290; 1064 hal_soc->ops->hal_tx_desc_set_lmac_id = hal_tx_desc_set_lmac_id_6290; 1065 hal_soc->ops->hal_tx_desc_set_buf_addr = 1066 hal_tx_desc_set_buf_addr_generic_li; 1067 hal_soc->ops->hal_tx_desc_set_search_type = 1068 hal_tx_desc_set_search_type_generic_li; 1069 hal_soc->ops->hal_tx_desc_set_search_index = 1070 hal_tx_desc_set_search_index_generic_li; 1071 hal_soc->ops->hal_tx_desc_set_cache_set_num = 1072 hal_tx_desc_set_cache_set_num_generic_li; 1073 hal_soc->ops->hal_tx_comp_get_status = 1074 hal_tx_comp_get_status_generic_li; 1075 hal_soc->ops->hal_tx_comp_get_release_reason = 1076 hal_tx_comp_get_release_reason_generic_li; 1077 hal_soc->ops->hal_get_wbm_internal_error = 1078 hal_get_wbm_internal_error_generic_li; 1079 hal_soc->ops->hal_tx_desc_set_mesh_en = hal_tx_desc_set_mesh_en_6290; 1080 hal_soc->ops->hal_tx_init_cmd_credit_ring = 1081 hal_tx_init_cmd_credit_ring_6290; 1082 1083 /* rx */ 1084 hal_soc->ops->hal_rx_msdu_start_nss_get = 1085 hal_rx_msdu_start_nss_get_6290; 1086 hal_soc->ops->hal_rx_mon_hw_desc_get_mpdu_status = 1087 hal_rx_mon_hw_desc_get_mpdu_status_6290; 1088 hal_soc->ops->hal_rx_get_tlv = hal_rx_get_tlv_6290; 1089 hal_soc->ops->hal_rx_proc_phyrx_other_receive_info_tlv = 1090 hal_rx_proc_phyrx_other_receive_info_tlv_6290; 1091 hal_soc->ops->hal_rx_dump_msdu_start_tlv = 1092 hal_rx_dump_msdu_start_tlv_6290; 1093 hal_soc->ops->hal_rx_dump_msdu_end_tlv = hal_rx_dump_msdu_end_tlv_6290; 1094 hal_soc->ops->hal_get_link_desc_size = hal_get_link_desc_size_6290; 1095 hal_soc->ops->hal_rx_mpdu_start_tid_get = 1096 hal_rx_mpdu_start_tid_get_6290; 1097 hal_soc->ops->hal_rx_msdu_start_reception_type_get = 1098 hal_rx_msdu_start_reception_type_get_6290; 1099 hal_soc->ops->hal_rx_msdu_end_da_idx_get = 1100 hal_rx_msdu_end_da_idx_get_6290; 1101 hal_soc->ops->hal_rx_msdu_desc_info_get_ptr = 1102 hal_rx_msdu_desc_info_get_ptr_6290; 1103 hal_soc->ops->hal_rx_link_desc_msdu0_ptr = 1104 hal_rx_link_desc_msdu0_ptr_6290; 1105 hal_soc->ops->hal_reo_status_get_header = 1106 hal_reo_status_get_header_6290; 1107 hal_soc->ops->hal_rx_status_get_tlv_info = 1108 hal_rx_status_get_tlv_info_generic_li; 1109 hal_soc->ops->hal_rx_wbm_err_info_get = 1110 hal_rx_wbm_err_info_get_generic_li; 1111 hal_soc->ops->hal_rx_dump_mpdu_start_tlv = 1112 hal_rx_dump_mpdu_start_tlv_generic_li; 1113 1114 hal_soc->ops->hal_tx_set_pcp_tid_map = 1115 hal_tx_set_pcp_tid_map_generic_li; 1116 hal_soc->ops->hal_tx_update_pcp_tid_map = 1117 hal_tx_update_pcp_tid_generic_li; 1118 hal_soc->ops->hal_tx_set_tidmap_prty = 1119 hal_tx_update_tidmap_prty_generic_li; 1120 hal_soc->ops->hal_rx_get_rx_fragment_number = 1121 hal_rx_get_rx_fragment_number_6290; 1122 hal_soc->ops->hal_rx_msdu_end_da_is_mcbc_get = 1123 hal_rx_msdu_end_da_is_mcbc_get_6290; 1124 hal_soc->ops->hal_rx_msdu_end_sa_is_valid_get = 1125 hal_rx_msdu_end_sa_is_valid_get_6290; 1126 hal_soc->ops->hal_rx_msdu_end_sa_idx_get = 1127 hal_rx_msdu_end_sa_idx_get_6290; 1128 hal_soc->ops->hal_rx_desc_is_first_msdu = 1129 hal_rx_desc_is_first_msdu_6290; 1130 hal_soc->ops->hal_rx_msdu_end_l3_hdr_padding_get = 1131 hal_rx_msdu_end_l3_hdr_padding_get_6290; 1132 hal_soc->ops->hal_rx_encryption_info_valid = 1133 hal_rx_encryption_info_valid_6290; 1134 hal_soc->ops->hal_rx_print_pn = hal_rx_print_pn_6290; 1135 hal_soc->ops->hal_rx_msdu_end_first_msdu_get = 1136 hal_rx_msdu_end_first_msdu_get_6290; 1137 hal_soc->ops->hal_rx_msdu_end_da_is_valid_get = 1138 hal_rx_msdu_end_da_is_valid_get_6290; 1139 hal_soc->ops->hal_rx_msdu_end_last_msdu_get = 1140 hal_rx_msdu_end_last_msdu_get_6290; 1141 hal_soc->ops->hal_rx_get_mpdu_mac_ad4_valid = 1142 hal_rx_get_mpdu_mac_ad4_valid_6290; 1143 hal_soc->ops->hal_rx_mpdu_start_sw_peer_id_get = 1144 hal_rx_mpdu_start_sw_peer_id_get_6290; 1145 hal_soc->ops->hal_rx_mpdu_get_to_ds = hal_rx_mpdu_get_to_ds_6290; 1146 hal_soc->ops->hal_rx_mpdu_get_fr_ds = hal_rx_mpdu_get_fr_ds_6290; 1147 hal_soc->ops->hal_rx_get_mpdu_frame_control_valid = 1148 hal_rx_get_mpdu_frame_control_valid_6290; 1149 hal_soc->ops->hal_rx_mpdu_get_addr1 = hal_rx_mpdu_get_addr1_6290; 1150 hal_soc->ops->hal_rx_mpdu_get_addr2 = hal_rx_mpdu_get_addr2_6290; 1151 hal_soc->ops->hal_rx_mpdu_get_addr3 = hal_rx_mpdu_get_addr3_6290; 1152 hal_soc->ops->hal_rx_mpdu_get_addr4 = hal_rx_mpdu_get_addr4_6290; 1153 hal_soc->ops->hal_rx_get_mpdu_sequence_control_valid = 1154 hal_rx_get_mpdu_sequence_control_valid_6290; 1155 hal_soc->ops->hal_rx_is_unicast = hal_rx_is_unicast_6290; 1156 hal_soc->ops->hal_rx_tid_get = hal_rx_tid_get_6290; 1157 hal_soc->ops->hal_rx_hw_desc_get_ppduid_get = 1158 hal_rx_hw_desc_get_ppduid_get_6290; 1159 hal_soc->ops->hal_rx_mpdu_start_mpdu_qos_control_valid_get = 1160 hal_rx_mpdu_start_mpdu_qos_control_valid_get_6290; 1161 hal_soc->ops->hal_rx_msdu_end_sa_sw_peer_id_get = 1162 hal_rx_msdu_end_sa_sw_peer_id_get_6290; 1163 hal_soc->ops->hal_rx_msdu0_buffer_addr_lsb = 1164 hal_rx_msdu0_buffer_addr_lsb_6290; 1165 hal_soc->ops->hal_rx_msdu_desc_info_ptr_get = 1166 hal_rx_msdu_desc_info_ptr_get_6290; 1167 hal_soc->ops->hal_ent_mpdu_desc_info = hal_ent_mpdu_desc_info_6290; 1168 hal_soc->ops->hal_dst_mpdu_desc_info = hal_dst_mpdu_desc_info_6290; 1169 hal_soc->ops->hal_rx_get_fc_valid = hal_rx_get_fc_valid_6290; 1170 hal_soc->ops->hal_rx_get_to_ds_flag = hal_rx_get_to_ds_flag_6290; 1171 hal_soc->ops->hal_rx_get_mac_addr2_valid = 1172 hal_rx_get_mac_addr2_valid_6290; 1173 hal_soc->ops->hal_rx_get_filter_category = 1174 hal_rx_get_filter_category_6290; 1175 hal_soc->ops->hal_rx_get_ppdu_id = hal_rx_get_ppdu_id_6290; 1176 hal_soc->ops->hal_reo_config = hal_reo_config_6290; 1177 hal_soc->ops->hal_rx_msdu_flow_idx_get = hal_rx_msdu_flow_idx_get_6290; 1178 hal_soc->ops->hal_rx_msdu_flow_idx_invalid = 1179 hal_rx_msdu_flow_idx_invalid_6290; 1180 hal_soc->ops->hal_rx_msdu_flow_idx_timeout = 1181 hal_rx_msdu_flow_idx_timeout_6290; 1182 hal_soc->ops->hal_rx_msdu_fse_metadata_get = 1183 hal_rx_msdu_fse_metadata_get_6290; 1184 hal_soc->ops->hal_rx_msdu_cce_metadata_get = 1185 hal_rx_msdu_cce_metadata_get_6290; 1186 hal_soc->ops->hal_rx_msdu_get_flow_params = 1187 hal_rx_msdu_get_flow_params_6290; 1188 hal_soc->ops->hal_rx_tlv_get_tcp_chksum = 1189 hal_rx_tlv_get_tcp_chksum_6290; 1190 hal_soc->ops->hal_rx_get_rx_sequence = hal_rx_get_rx_sequence_6290; 1191 /* rx - msdu end fast path info fields */ 1192 hal_soc->ops->hal_rx_msdu_packet_metadata_get = 1193 hal_rx_msdu_packet_metadata_get_generic_li; 1194 /* rx - TLV struct offsets */ 1195 hal_soc->ops->hal_rx_msdu_end_offset_get = 1196 hal_rx_msdu_end_offset_get_generic; 1197 hal_soc->ops->hal_rx_attn_offset_get = 1198 hal_rx_attn_offset_get_generic; 1199 hal_soc->ops->hal_rx_msdu_start_offset_get = 1200 hal_rx_msdu_start_offset_get_generic; 1201 hal_soc->ops->hal_rx_mpdu_start_offset_get = 1202 hal_rx_mpdu_start_offset_get_generic; 1203 hal_soc->ops->hal_rx_mpdu_end_offset_get = 1204 hal_rx_mpdu_end_offset_get_generic; 1205 #ifndef NO_RX_PKT_HDR_TLV 1206 hal_soc->ops->hal_rx_pkt_tlv_offset_get = 1207 hal_rx_pkt_tlv_offset_get_generic; 1208 #endif 1209 hal_soc->ops->hal_compute_reo_remap_ix2_ix3 = 1210 hal_compute_reo_remap_ix2_ix3_6290; 1211 hal_soc->ops->hal_setup_link_idle_list = 1212 hal_setup_link_idle_list_generic_li; 1213 }; 1214 1215 struct hal_hw_srng_config hw_srng_table_6290[] = { 1216 /* TODO: max_rings can populated by querying HW capabilities */ 1217 { /* REO_DST */ 1218 .start_ring_id = HAL_SRNG_REO2SW1, 1219 .max_rings = 4, 1220 .entry_size = sizeof(struct reo_destination_ring) >> 2, 1221 .lmac_ring = FALSE, 1222 .ring_dir = HAL_SRNG_DST_RING, 1223 .reg_start = { 1224 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR( 1225 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1226 HWIO_REO_R2_REO2SW1_RING_HP_ADDR( 1227 SEQ_WCSS_UMAC_REO_REG_OFFSET) 1228 }, 1229 .reg_size = { 1230 HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(0) - 1231 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(0), 1232 HWIO_REO_R2_REO2SW2_RING_HP_ADDR(0) - 1233 HWIO_REO_R2_REO2SW1_RING_HP_ADDR(0), 1234 }, 1235 .max_size = HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_BMSK >> 1236 HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_SHFT, 1237 }, 1238 { /* REO_EXCEPTION */ 1239 /* Designating REO2TCL ring as exception ring. This ring is 1240 * similar to other REO2SW rings though it is named as REO2TCL. 1241 * Any of theREO2SW rings can be used as exception ring. 1242 */ 1243 .start_ring_id = HAL_SRNG_REO2TCL, 1244 .max_rings = 1, 1245 .entry_size = sizeof(struct reo_destination_ring) >> 2, 1246 .lmac_ring = FALSE, 1247 .ring_dir = HAL_SRNG_DST_RING, 1248 .reg_start = { 1249 HWIO_REO_R0_REO2TCL_RING_BASE_LSB_ADDR( 1250 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1251 HWIO_REO_R2_REO2TCL_RING_HP_ADDR( 1252 SEQ_WCSS_UMAC_REO_REG_OFFSET) 1253 }, 1254 /* Single ring - provide ring size if multiple rings of this 1255 * type are supported 1256 */ 1257 .reg_size = {}, 1258 .max_size = HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_BMSK >> 1259 HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_SHFT, 1260 }, 1261 { /* REO_REINJECT */ 1262 .start_ring_id = HAL_SRNG_SW2REO, 1263 .max_rings = 1, 1264 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 1265 .lmac_ring = FALSE, 1266 .ring_dir = HAL_SRNG_SRC_RING, 1267 .reg_start = { 1268 HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR( 1269 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1270 HWIO_REO_R2_SW2REO_RING_HP_ADDR( 1271 SEQ_WCSS_UMAC_REO_REG_OFFSET) 1272 }, 1273 /* Single ring - provide ring size if multiple rings of this 1274 * type are supported 1275 */ 1276 .reg_size = {}, 1277 .max_size = HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_BMSK >> 1278 HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_SHFT, 1279 }, 1280 { /* REO_CMD */ 1281 .start_ring_id = HAL_SRNG_REO_CMD, 1282 .max_rings = 1, 1283 .entry_size = (sizeof(struct tlv_32_hdr) + 1284 sizeof(struct reo_get_queue_stats)) >> 2, 1285 .lmac_ring = FALSE, 1286 .ring_dir = HAL_SRNG_SRC_RING, 1287 .reg_start = { 1288 HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR( 1289 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1290 HWIO_REO_R2_REO_CMD_RING_HP_ADDR( 1291 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1292 }, 1293 /* Single ring - provide ring size if multiple rings of this 1294 * type are supported 1295 */ 1296 .reg_size = {}, 1297 .max_size = HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_BMSK >> 1298 HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_SHFT, 1299 }, 1300 { /* REO_STATUS */ 1301 .start_ring_id = HAL_SRNG_REO_STATUS, 1302 .max_rings = 1, 1303 .entry_size = (sizeof(struct tlv_32_hdr) + 1304 sizeof(struct reo_get_queue_stats_status)) >> 2, 1305 .lmac_ring = FALSE, 1306 .ring_dir = HAL_SRNG_DST_RING, 1307 .reg_start = { 1308 HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR( 1309 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1310 HWIO_REO_R2_REO_STATUS_RING_HP_ADDR( 1311 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1312 }, 1313 /* Single ring - provide ring size if multiple rings of this 1314 * type are supported 1315 */ 1316 .reg_size = {}, 1317 .max_size = 1318 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> 1319 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, 1320 }, 1321 { /* TCL_DATA */ 1322 .start_ring_id = HAL_SRNG_SW2TCL1, 1323 .max_rings = 3, 1324 .entry_size = (sizeof(struct tlv_32_hdr) + 1325 sizeof(struct tcl_data_cmd)) >> 2, 1326 .lmac_ring = FALSE, 1327 .ring_dir = HAL_SRNG_SRC_RING, 1328 .reg_start = { 1329 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR( 1330 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1331 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR( 1332 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1333 }, 1334 .reg_size = { 1335 HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(0) - 1336 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(0), 1337 HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(0) - 1338 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(0), 1339 }, 1340 .max_size = HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK >> 1341 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT, 1342 }, 1343 { /* TCL_CMD */ 1344 .start_ring_id = HAL_SRNG_SW2TCL_CMD, 1345 .max_rings = 1, 1346 .entry_size = (sizeof(struct tlv_32_hdr) + 1347 sizeof(struct tcl_gse_cmd)) >> 2, 1348 .lmac_ring = FALSE, 1349 .ring_dir = HAL_SRNG_SRC_RING, 1350 .reg_start = { 1351 HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_ADDR( 1352 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1353 HWIO_TCL_R2_SW2TCL_CMD_RING_HP_ADDR( 1354 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1355 }, 1356 /* Single ring - provide ring size if multiple rings of this 1357 * type are supported 1358 */ 1359 .reg_size = {}, 1360 .max_size = 1361 HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RING_SIZE_BMSK >> 1362 HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RING_SIZE_SHFT, 1363 }, 1364 { /* TCL_STATUS */ 1365 .start_ring_id = HAL_SRNG_TCL_STATUS, 1366 .max_rings = 1, 1367 .entry_size = (sizeof(struct tlv_32_hdr) + 1368 sizeof(struct tcl_status_ring)) >> 2, 1369 .lmac_ring = FALSE, 1370 .ring_dir = HAL_SRNG_DST_RING, 1371 .reg_start = { 1372 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR( 1373 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1374 HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR( 1375 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1376 }, 1377 /* Single ring - provide ring size if multiple rings of this 1378 * type are supported 1379 */ 1380 .reg_size = {}, 1381 .max_size = 1382 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_BMSK >> 1383 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_SHFT, 1384 }, 1385 { /* CE_SRC */ 1386 .start_ring_id = HAL_SRNG_CE_0_SRC, 1387 .max_rings = 12, 1388 .entry_size = sizeof(struct ce_src_desc) >> 2, 1389 .lmac_ring = FALSE, 1390 .ring_dir = HAL_SRNG_SRC_RING, 1391 .reg_start = { 1392 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR( 1393 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET), 1394 HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR( 1395 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET), 1396 }, 1397 .reg_size = { 1398 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET - 1399 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET, 1400 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET - 1401 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET, 1402 }, 1403 .max_size = 1404 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >> 1405 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT, 1406 }, 1407 { /* CE_DST */ 1408 .start_ring_id = HAL_SRNG_CE_0_DST, 1409 .max_rings = 12, 1410 .entry_size = 8 >> 2, 1411 /*TODO: entry_size above should actually be 1412 * sizeof(struct ce_dst_desc) >> 2, but couldn't find definition 1413 * of struct ce_dst_desc in HW header files 1414 */ 1415 .lmac_ring = FALSE, 1416 .ring_dir = HAL_SRNG_SRC_RING, 1417 .reg_start = { 1418 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR( 1419 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 1420 HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR( 1421 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 1422 }, 1423 .reg_size = { 1424 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 1425 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 1426 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 1427 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 1428 }, 1429 .max_size = 1430 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >> 1431 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT, 1432 }, 1433 { /* CE_DST_STATUS */ 1434 .start_ring_id = HAL_SRNG_CE_0_DST_STATUS, 1435 .max_rings = 12, 1436 .entry_size = sizeof(struct ce_stat_desc) >> 2, 1437 .lmac_ring = FALSE, 1438 .ring_dir = HAL_SRNG_DST_RING, 1439 .reg_start = { 1440 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR( 1441 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 1442 HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR( 1443 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 1444 }, 1445 /* TODO: check destination status ring registers */ 1446 .reg_size = { 1447 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 1448 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 1449 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 1450 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 1451 }, 1452 .max_size = 1453 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> 1454 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, 1455 }, 1456 { /* WBM_IDLE_LINK */ 1457 .start_ring_id = HAL_SRNG_WBM_IDLE_LINK, 1458 .max_rings = 1, 1459 .entry_size = sizeof(struct wbm_link_descriptor_ring) >> 2, 1460 .lmac_ring = FALSE, 1461 .ring_dir = HAL_SRNG_SRC_RING, 1462 .reg_start = { 1463 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1464 HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1465 }, 1466 /* Single ring - provide ring size if multiple rings of this 1467 * type are supported 1468 */ 1469 .reg_size = {}, 1470 .max_size = 1471 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_BMSK >> 1472 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_SHFT, 1473 }, 1474 { /* SW2WBM_RELEASE */ 1475 .start_ring_id = HAL_SRNG_WBM_SW_RELEASE, 1476 .max_rings = 1, 1477 .entry_size = sizeof(struct wbm_release_ring) >> 2, 1478 .lmac_ring = FALSE, 1479 .ring_dir = HAL_SRNG_SRC_RING, 1480 .reg_start = { 1481 HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1482 HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1483 }, 1484 /* Single ring - provide ring size if multiple rings of this 1485 * type are supported 1486 */ 1487 .reg_size = {}, 1488 .max_size = 1489 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> 1490 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, 1491 }, 1492 { /* WBM2SW_RELEASE */ 1493 .start_ring_id = HAL_SRNG_WBM2SW0_RELEASE, 1494 .max_rings = 4, 1495 .entry_size = sizeof(struct wbm_release_ring) >> 2, 1496 .lmac_ring = FALSE, 1497 .ring_dir = HAL_SRNG_DST_RING, 1498 .reg_start = { 1499 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1500 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1501 }, 1502 .reg_size = { 1503 HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) - 1504 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1505 HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) - 1506 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1507 }, 1508 .max_size = 1509 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> 1510 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, 1511 }, 1512 { /* RXDMA_BUF */ 1513 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA0_BUF0, 1514 #ifdef IPA_OFFLOAD 1515 .max_rings = 3, 1516 #else 1517 .max_rings = 2, 1518 #endif 1519 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 1520 .lmac_ring = TRUE, 1521 .ring_dir = HAL_SRNG_SRC_RING, 1522 /* reg_start is not set because LMAC rings are not accessed 1523 * from host 1524 */ 1525 .reg_start = {}, 1526 .reg_size = {}, 1527 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1528 }, 1529 { /* RXDMA_DST */ 1530 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW0, 1531 .max_rings = 1, 1532 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 1533 .lmac_ring = TRUE, 1534 .ring_dir = HAL_SRNG_DST_RING, 1535 /* reg_start is not set because LMAC rings are not accessed 1536 * from host 1537 */ 1538 .reg_start = {}, 1539 .reg_size = {}, 1540 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1541 }, 1542 { /* RXDMA_MONITOR_BUF */ 1543 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA2_BUF, 1544 .max_rings = 1, 1545 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 1546 .lmac_ring = TRUE, 1547 .ring_dir = HAL_SRNG_SRC_RING, 1548 /* reg_start is not set because LMAC rings are not accessed 1549 * from host 1550 */ 1551 .reg_start = {}, 1552 .reg_size = {}, 1553 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1554 }, 1555 { /* RXDMA_MONITOR_STATUS */ 1556 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_STATBUF, 1557 .max_rings = 1, 1558 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 1559 .lmac_ring = TRUE, 1560 .ring_dir = HAL_SRNG_SRC_RING, 1561 /* reg_start is not set because LMAC rings are not accessed 1562 * from host 1563 */ 1564 .reg_start = {}, 1565 .reg_size = {}, 1566 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1567 }, 1568 { /* RXDMA_MONITOR_DST */ 1569 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW1, 1570 .max_rings = 1, 1571 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 1572 .lmac_ring = TRUE, 1573 .ring_dir = HAL_SRNG_DST_RING, 1574 /* reg_start is not set because LMAC rings are not accessed 1575 * from host 1576 */ 1577 .reg_start = {}, 1578 .reg_size = {}, 1579 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1580 }, 1581 { /* RXDMA_MONITOR_DESC */ 1582 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_DESC, 1583 .max_rings = 1, 1584 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 1585 .lmac_ring = TRUE, 1586 .ring_dir = HAL_SRNG_SRC_RING, 1587 /* reg_start is not set because LMAC rings are not accessed 1588 * from host 1589 */ 1590 .reg_start = {}, 1591 .reg_size = {}, 1592 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1593 }, 1594 { /* DIR_BUF_RX_DMA_SRC */ 1595 .start_ring_id = HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING, 1596 .max_rings = 1, 1597 .entry_size = 2, 1598 .lmac_ring = TRUE, 1599 .ring_dir = HAL_SRNG_SRC_RING, 1600 /* reg_start is not set because LMAC rings are not accessed 1601 * from host 1602 */ 1603 .reg_start = {}, 1604 .reg_size = {}, 1605 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1606 }, 1607 #ifdef WLAN_FEATURE_CIF_CFR 1608 { /* WIFI_POS_SRC */ 1609 .start_ring_id = HAL_SRNG_WIFI_POS_SRC_DMA_RING, 1610 .max_rings = 1, 1611 .entry_size = sizeof(wmi_oem_dma_buf_release_entry) >> 2, 1612 .lmac_ring = TRUE, 1613 .ring_dir = HAL_SRNG_SRC_RING, 1614 /* reg_start is not set because LMAC rings are not accessed 1615 * from host 1616 */ 1617 .reg_start = {}, 1618 .reg_size = {}, 1619 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1620 }, 1621 #endif 1622 { /* REO2PPE */ 0}, 1623 { /* PPE2TCL */ 0}, 1624 { /* PPE_RELEASE */ 0}, 1625 { /* TX_MONITOR_BUF */ 0}, 1626 { /* TX_MONITOR_DST */ 0}, 1627 { /* SW2RXDMA_NEW */ 0}, 1628 }; 1629 1630 /** 1631 * hal_qca6290_attach() - Attach 6290 target specific hal_soc ops, 1632 * offset and srng table 1633 */ 1634 void hal_qca6290_attach(struct hal_soc *hal_soc) 1635 { 1636 hal_soc->hw_srng_table = hw_srng_table_6290; 1637 hal_srng_hw_reg_offset_init_generic(hal_soc); 1638 1639 hal_hw_txrx_default_ops_attach_li(hal_soc); 1640 hal_hw_txrx_ops_attach_6290(hal_soc); 1641 } 1642